A two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer and a preparation method thereof

Abstract

The present invention discloses a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer and a preparation method thereof, including a plurality of heterojunction units constituting the array. The heterojunction unit is a vertical heterojunction of a two-dimensional material / silicon, and the array is a planar array of heterojunction units. The preparation method is to form a patterned top silicon strip on a silicon substrate on an insulating layer by etching the top silicon, and then sequentially deposit an insulating layer, make electrodes, etch out silicon windows and silicon contact holes, and then transfer the two-dimensional material to the silicon window and pattern it. The present invention broadens the absorption band and enhances light absorption through a vertical heterojunction of a two-dimensional material and silicon. In the heterojunction array of the present invention, each column / row of heterojunctions shares the same top silicon strip, and the two-dimensional material contact electrodes of each row / column of heterojunctions are interconnected to form a top electrode wiring of the row / column. The present invention realizes the array production of two-dimensional material / silicon heterojunction devices, and provides a solution for large-scale integration of two-dimensional materials and silicon.

Description

Technical Field

[0001] The invention belongs to the technical field of photoelectric detection, and relates to a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer and a preparation method thereof. Background Art

[0002] Photoelectric detection technology has a wide range of applications in food testing, material identification, medical research, biochemical testing, environmental security, wireless communications and other fields. The process of preparing large-area high-quality single-crystal silicon is already very mature. In the visible light field, silicon photoelectric detectors have been used in various fields. However, in ultraviolet, infrared and high-speed scenarios, it is difficult to meet the needs by relying solely on silicon photoelectric detectors.

[0003] The introduction of two-dimensional materials such as graphene has provided new ideas for pure silicon-based photodetectors. Due to the quantum confinement effect, new two-dimensional materials have excellent and unique optical and electrical properties and are considered to be promising photodetection materials, which may be used in the next generation of micro-nanoelectronic devices. For example, graphene has ultra-high carrier mobility and a wide absorption spectrum; transition metal sulfides have strong light-matter interactions. As a layered material formed by the van der Waals force between atomic layers, two-dimensional materials have formed an extremely rich material system and have important application potential in the fields of photonics and optoelectronics, especially with outstanding advantages such as optional spectral range and no lattice mismatch. By forming a heterojunction between two-dimensional materials and silicon, it is expected to achieve comprehensive high-performance photodetectors such as responsiveness, bandwidth and sensitivity. In addition, two-dimensional material devices face challenges in preparation uniformity, reliability, arraying, and scale, and breakthroughs are still needed in array, integration, and high-reliability preparation technology and processes. Summary of the invention

[0004] The purpose of the present invention is to provide a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer and a preparation method thereof in view of the deficiencies of the prior art. The invention provides a two-dimensional material / silicon heterojunction optoelectronic device structure, solves the problem of two-dimensional material / silicon device array manufacturing, and provides a solution for large-scale integration of two-dimensional materials and silicon.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] The present invention provides a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer, comprising a plurality of heterojunction units constituting the array, wherein the heterojunction units are vertical heterojunctions of the two-dimensional material and silicon; the array is a planar array of heterojunction units;

[0007] The array comprises a silicon substrate on an insulating layer, wherein the silicon substrate on an insulating layer is an SOI substrate in which top silicon is patterned into a plurality of top silicon strips, and an insulating layer is further provided on the substrate, wherein a silicon window array and silicon contact holes are engraved in the insulating layer;

[0008] A two-dimensional material contact electrode is provided around the periphery of each silicon window of the silicon window array, and the two-dimensional material contact electrodes around the silicon windows of each row / column are interconnected and led out as a common top electrode of the row / column; the two-dimensional material contact electrode is covered with a two-dimensional material, and the two-dimensional material contacts the top silicon strip through the silicon window to form a heterojunction; each column / row of heterojunctions in the array shares the same top silicon strip, and each top silicon strip is connected to a silicon contact electrode through the silicon contact hole, and each row / column of heterojunctions is made on a different top silicon strip.

[0009] Furthermore, the two-dimensional material is a single-layer or multi-layer two-dimensional thin film material, including single-layer or multi-layer graphene, macroscopically assembled graphene, thin-layer graphite, single-layer or multi-layer transition metal sulfide, single-layer or multi-layer transition metal selenide, single-layer or multi-layer black phosphorus.

[0010] Furthermore, the heterojunction region formed by the contact between the two-dimensional material and silicon is a photosensitive region arranged in an array structure.

[0011] Furthermore, the top electrode including the two-dimensional material contact electrode and the silicon contact electrode are made of conductive metal.

[0012] The present invention provides a method for preparing a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer, comprising the following steps:

[0013] (1) using photolithography technology to form a stripe array mask on the top silicon surface of the silicon-on-insulator substrate, and etching the top silicon not protected by the mask to form a silicon-on-insulator substrate having a top silicon shape of a plurality of top silicon strips;

[0014] (2) thermally oxidizing the surface of the silicon substrate on the patterned insulating layer, and then depositing an insulating material to isolate adjacent top silicon strips and fill gaps between adjacent silicon strips;

[0015] (3) planarizing by CMP method, grinding and polishing the upper surface of the deposited insulating material to form an insulating layer 3;

[0016] (4) photolithography of a silicon contact hole pattern on the polished insulating layer, and wet or dry etching the insulating layer to form a silicon contact hole, and ion implantation is performed in the silicon contact hole region to form a good ohmic contact between the silicon contact electrode and the silicon;

[0017] (5) using photolithography to make an electrode pattern mask on the upper surface of the insulating layer, depositing electrode materials, and then peeling them off in a degumming solution to form a top electrode and a silicon contact electrode; or first depositing electrode materials and then using photolithography and etching techniques to pattern the electrodes to form a top electrode and a silicon contact electrode;

[0018] (6) photolithography a pattern of a silicon window array on the upper surface of the insulating layer, and wet or dry etching the insulating layer to form the silicon window array;

[0019] (7) Transferring the two-dimensional material to the silicon window array;

[0020] (8) Use photolithography and etching techniques to pattern the two-dimensional material, leaving behind the two-dimensional material in the area where the heterojunction array is located.

[0021] The present invention also provides a method for preparing a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer, comprising the following steps:

[0022] (1) using photolithography technology to form a stripe array mask on the top silicon surface of the silicon-on-insulator substrate, and etching the top silicon not protected by the mask to form a silicon-on-insulator substrate having a top silicon shape of a plurality of top silicon strips;

[0023] (2) a silicon window array mask and a silicon contact hole mask are formed on the upper surface of the silicon substrate on the patterned insulating layer, and then an insulating material is deposited and placed in a degumming solution for stripping, leaving an insulating layer with silicon windows and silicon contact holes; or the insulating material can be deposited first, and then the insulating layer is patterned by photolithography and etching techniques to form an insulating layer with silicon windows and silicon contact holes;

[0024] (3) Using photolithography technology to make an electrode pattern mask on the upper surface of the insulating layer, depositing electrode materials, and then peeling them off in a degumming solution to form a top electrode and a silicon contact electrode; or first depositing electrode materials, and then using photolithography and etching technology to pattern the electrodes to form a top electrode and a silicon contact electrode;

[0025] (4) Transferring the two-dimensional material to the silicon window array;

[0026] (5) Use photolithography and etching techniques to pattern the two-dimensional material, leaving behind the two-dimensional material in the area where the heterojunction array is located.

[0027] The working principle of the two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer proposed in the present invention is:

[0028] (1) In the vertical heterojunction of two-dimensional material / silicon in the present invention, due to the different work functions of two-dimensional material and silicon, electrons will flow from the material with high Fermi level to the material with low Fermi level, thereby forming a potential barrier and a depletion region. A certain reverse bias is applied between the two-dimensional material contact electrode and the silicon contact electrode, and the two-dimensional material / silicon heterojunction is in a reverse cutoff state, with only a very low dark current; for the incidence of visible light, when the incident light is incident on the heterojunction device, the incident light enters the depletion region of the semiconductor substrate, and will excite electron-hole pairs in the depletion region. The electrons and holes are separated under the action of the electric field and collected by the two-dimensional material and the silicon substrate, respectively, to form a large photocurrent; for the detection of ultraviolet light, a wide-bandgap two-dimensional material and silicon are used to form a heterojunction, and the absorption of ultraviolet light is achieved by relying on the large bandgap width of the two-dimensional material; for the detection of infrared light, the internal photoemission effect (IPE) and the photothermal electron emission effect (PTI) are used to make electrons cross the potential barrier to achieve light response. The information of the incident light is reflected by detecting the size of the photocurrent.

[0029] (2) In the two-dimensional material / silicon heterojunction array of the present invention, each column / row of heterojunctions shares the same top silicon strip, and the two-dimensional material contact electrodes of each row / column of heterojunctions share the same top electrode wiring. The information of each heterojunction unit is read out in sequence using a gated readout method, that is, a negative bias is applied to the top electrode of each row / column in turn, and parallel current reading is performed at the silicon contact electrode of each column / row. The current readout method generally uses an operational amplifier with a resistor or capacitor feedback with the positive end grounded to achieve voltage output.

[0030] The beneficial effects of the present invention are as follows:

[0031] 1. The present invention broadens the absorption band and enhances light absorption through the vertical heterojunction of two-dimensional materials and silicon. Photogenerated carriers will be separated under the action of the electric field and effectively collected by the two-dimensional material; two-dimensional materials are a very rich material system, and suitable two-dimensional materials can be selected to realize light detection in various bands.

[0032] 2. The two-dimensional material / silicon heterojunction array provided by the present invention has a simple structure and preparation process, can be prepared on a large scale, has a high yield, and is compatible with CMOS technology.

[0033] 3. The two-dimensional material / silicon heterojunction array provided by the present invention has separate substrates for heterojunction units in different columns / rows, and is naturally isolated from each other, effectively avoiding crosstalk between pixels. By means of row / column gating, the information of each heterojunction unit in the array can be read out accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a three-dimensional structural diagram of a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer provided by an embodiment of the present invention;

[0035] Figure 2 is a cross-sectional view of a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer provided by an embodiment of the present invention;

[0036] In the figure: silicon substrate 1 on the insulating layer, top silicon strip 2, insulating layer 3, two-dimensional material contact electrode 4, two-dimensional material 5, silicon contact electrode 6, and silicon window array 7. DETAILED DESCRIPTION

[0037] The following is a complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] Example 1

[0039] like Figure 1 , 2 As shown, the two-dimensional material / silicon heterojunction array based on the silicon substrate on the insulating layer provided in the embodiment of the present invention includes several heterojunction devices constituting the array, wherein the heterojunction array is to deposit an insulating layer 3 on the patterned top silicon strip 2 and polish it, and etch a silicon contact hole on the insulating layer 3 on each top silicon strip and ion implant it, then make a top electrode including a two-dimensional material contact electrode 4 and a silicon contact electrode 6, finally etch a silicon window in the middle of the two-dimensional material contact electrode 4, transfer the two-dimensional material 5 and pattern it. In this embodiment, the top silicon of the silicon substrate on the insulating layer is n-type lightly doped silicon, with a resistivity of 1 to 10Ω·cm and a thickness of 1.5μm±5%, the insulating layer 3 is made of silicon dioxide, and the two-dimensional material 5 is made of a single layer of graphene.

[0040] The method for preparing the above-mentioned two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer comprises the following steps:

[0041] (1) A silicon substrate on an insulating layer is used, wherein the top silicon is n-type lightly doped silicon with a resistivity of 1 to 10 Ω·cm and a thickness of 1.5 μm±5%.

[0042] (2) A strip array mask is made on the top silicon surface of the silicon substrate on the insulating layer using photolithography technology, and the top silicon not protected by the mask is etched using an inductively coupled plasma dry etching system (ICP) to make top silicon strips.

[0043] (3) Afterwards, the surface is thermally oxidized, and a silicon dioxide insulating layer is deposited using a plasma enhanced chemical vapor deposition system (PECVD) to isolate adjacent silicon strips and fill the gaps between adjacent silicon strips. The filled silicon dioxide insulating layer is polished using a chemical mechanical polishing (CMP) method.

[0044] (4) Using photolithography technology to make a silicon contact hole pattern on the polished upper surface of the insulating layer, and using wet or dry etching of the insulating layer to form silicon contact holes, and using ion implantation technology to heavily dope the top silicon in the contact hole area.

[0045] (5) A mask is made on the surface of the silicon dioxide insulating layer using photolithography technology, and 10 nm titanium and 60 nm gold are grown as electrodes using magnetron sputtering technology. The electrodes are then peeled off in a degumming solution to form a top electrode and a silicon contact electrode.

[0046] (6) Photolithography of a silicon window array pattern, etching the silicon dioxide insulating layer using a buffered oxide etchant (BOE); wherein the buffered oxide etchant is composed of HF, NH4F and water, HF: NH4F: H2O = 30 ml: 60 g: 100 ml (HF concentration is 48%).

[0047] (7) Covering the silicon window array with a single-layer graphene film; transferring the graphene using a wet transfer method: evenly spin-coating a layer of polymethyl methacrylate (PMMA) film on the surface of the single-layer graphene, immersing it in a copper etching solution for about 3 hours to etch away the copper foil, leaving a single-layer graphene film supported by PMMA; washing the PMMA-supported graphene film with deionized water and then transferring and covering the silicon window array; finally, immersing the sample in acetone and isopropanol to remove PMMA; wherein the etching solution is composed of CuSO4, HCl and water, CuSO4:HCl:H2O=10g:45ml:50ml.

[0048] (8) Use photolithography technology to cover the area of ​​the desired single-layer graphene pattern with photoresist. Then use oxygen plasma reactive ion etching technology (Oxygen plasma) to etch away the excess graphene, with a power and etching time of 60 watts and 2 minutes respectively. After etching, use acetone and isopropanol to clean and remove the residual photoresist.

[0049] (9) The device is subjected to rapid annealing treatment at a temperature of 400 degrees Celsius for 5 minutes.

[0050] Example 2

[0051] like Figure 1 , 2As shown, the two-dimensional material / silicon heterojunction array based on the silicon substrate on the insulating layer provided in the embodiment of the present invention includes a plurality of heterojunction devices constituting the array, wherein the heterojunction device is manufactured by depositing an insulating layer 3 on the patterned top silicon 2, and manufacturing a top electrode including a two-dimensional material contact electrode 4 on the insulating layer 3, and finally etching a silicon window in the middle of the two-dimensional material contact electrode 4, transferring the two-dimensional material 5 and patterning. In this embodiment, the top silicon of the silicon substrate on the insulating layer is n-type lightly doped silicon with a resistivity of 1 to 10Ω·cm, the insulating layer 3 is made of silicon dioxide, and the two-dimensional material 5 is made of a single layer of graphene.

[0052] The method for preparing the above-mentioned two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer comprises the following steps:

[0053] (1) A silicon substrate on an insulating layer is used, wherein the top silicon is n-type lightly doped silicon with a resistivity of 1 to 10 Ω·cm and a thickness of 1.5 μm±5%.

[0054] (2) A strip array mask is made on the top silicon surface of the silicon substrate on the insulating layer using photolithography technology, and the top silicon not protected by the mask is etched using an inductively coupled plasma dry etching system (ICP) to make top silicon strips.

[0055] (3) a silicon window array mask and a silicon contact hole mask are formed on the upper surface of the patterned insulating layer on the silicon substrate 1, and then 200 nanometers of silicon dioxide is sputtered as an insulating layer material and placed in a degumming solution for stripping, leaving an insulating layer with silicon windows and silicon contact holes;

[0056] (4) using photolithography technology to make a mask on the surface of the silicon dioxide insulating layer, using magnetron sputtering technology to grow 10 nm titanium and 60 nm gold as electrodes, and then peeling them in a degumming solution to form a top electrode and a silicon contact electrode;

[0057] (5) Covering the silicon window array with a single-layer graphene film; transferring the graphene using a wet transfer method: evenly spin-coating a layer of polymethyl methacrylate (PMMA) film on the surface of the single-layer graphene, immersing it in a copper etching solution for about 3 hours to etch away the copper foil, leaving a single-layer graphene film supported by PMMA; washing the PMMA-supported graphene film with deionized water, transferring it to cover the silicon window array; finally, immersing the sample in acetone and isopropanol to remove PMMA; wherein the etching solution is composed of CuSO4, HCl and water, CuSO4:HCl:H2O=10g:45ml:50ml.

[0058] (6) Use photolithography technology to cover the area of ​​the required single-layer graphene pattern with photoresist. Then use oxygen plasma reactive ion etching technology (Oxygen plasma) to etch away the excess graphene, with a power and etching time of 60 watts and 2 minutes respectively. After etching, use acetone and isopropanol to clean and remove the residual photoresist.

[0059] (7) The device is subjected to rapid annealing treatment at a temperature of 400 degrees Celsius for 5 minutes.

[0060] The invention provides an optoelectronic device structure using a two-dimensional material / silicon heterojunction, and proposes a method for making a large-scale two-dimensional material / silicon heterojunction array. In the heterojunction array of the present invention, each column / row of heterojunctions shares the same top silicon strip, and the two-dimensional material contact electrodes of each row / column of heterojunctions are interconnected to form a top electrode wiring of the row / column. The information of each heterojunction unit in the array is read out in sequence by gating. The present invention realizes the array production of two-dimensional material / silicon heterojunction devices and provides a solution for the large-scale integration of two-dimensional materials and silicon.

[0061] The above is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the above disclosed methods and technical contents without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer, comprising a plurality of heterojunction units constituting the array, characterized in that: The heterojunction unit is a vertical heterojunction of a two-dimensional material and silicon; the array is a planar array of heterojunction units; The array comprises a silicon substrate on an insulating layer (1), wherein the silicon substrate on an insulating layer (1) is a silicon substrate on an insulating layer in which top silicon is patterned into a plurality of top silicon strips (2), an insulating layer (3) is also provided on the silicon substrate on an insulating layer (1), and a silicon window array (7) and silicon contact holes are engraved in the insulating layer (3); A two-dimensional material contact electrode (4) is provided at the periphery of each silicon window of the silicon window array (7); the two-dimensional material contact electrodes (4) at the periphery of each row / column of silicon windows are interconnected and led out as a common top electrode of the row / column; the two-dimensional material contact electrode (4) is covered with a two-dimensional material (5), and the two-dimensional material (5) contacts the top silicon strip (2) through the silicon window to form a heterojunction; each column / row of heterojunctions in the array shares the same top silicon strip (2), and each top silicon strip (2) is connected to a silicon contact electrode (6) through the silicon contact hole.

2. The two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer according to claim 1, characterized in that: The two-dimensional material (5) is a single-layer or multi-layer thin film material, including single-layer graphene, multi-layer graphene, macroscopically assembled graphene, thin-layer graphite, single-layer or multi-layer transition metal sulfide, single-layer or multi-layer transition metal selenide, single-layer or multi-layer black phosphorus.

3. The two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer according to claim 1, characterized in that: The heterojunction region formed by the contact between the two-dimensional material (5) and silicon is a photosensitive region arranged in an array structure.

4. The two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer according to claim 1, characterized in that: The two-dimensional material contact electrode (4) and the silicon contact electrode (6) are made of conductive metal.

5. A method for preparing a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer according to any one of claims 1 to 4, characterized in that: The steps include: (1) using photolithography technology to form a stripe array mask on the top silicon surface of the silicon substrate on an insulating layer, and etching the top silicon not protected by the mask to form a silicon substrate on an insulating layer (1) having a top silicon shape of a plurality of top silicon strips (2); (2) subjecting the surface of the silicon substrate (1) on the patterned insulating layer to thermal oxidation treatment, and then depositing an insulating material to isolate adjacent silicon top silicon strips (2) and fill gaps between adjacent silicon top silicon strips (2); (3) flattening the upper surface of the deposited insulating material by polishing to form an insulating layer (3); (4) photolithography of a silicon contact hole pattern on the upper surface of the polished insulating layer (3), and etching the insulating layer by wet or dry method to form a silicon contact hole, and ion implantation in the silicon contact hole region to form a good ohmic contact between the silicon contact electrode (6) and the top silicon strip (2); (5) using photolithography technology to make an electrode pattern mask on the upper surface of the insulating layer (3), depositing electrode materials, and then peeling them off in a degumming solution to form a top electrode and a silicon contact electrode (6); or alternatively, first depositing electrode materials, and then using photolithography and etching technology to pattern the electrodes to form the top electrode and the silicon contact electrode (6); (6) photolithography a pattern of a silicon window array on the upper surface of the insulating layer (3), and etching the insulating layer (3) by a wet method or a dry method to form a silicon window array (7); (7) transferring the two-dimensional material (5) onto the silicon window array (7); (8) The two-dimensional material (5) is patterned using photolithography and etching techniques, leaving the two-dimensional material (5) in the area where the heterojunction array is located.

6. A method for preparing a two-dimensional material / silicon heterojunction array based on a silicon substrate on an insulating layer according to any one of claims 1 to 4, characterized in that: The steps include: (1) using photolithography technology to form a stripe array mask on the top silicon surface of the silicon substrate on an insulating layer, and etching the top silicon not protected by the mask to form a silicon substrate on an insulating layer (1) having a top silicon shape of a plurality of top silicon strips (2); (2) forming a silicon window array mask and a silicon contact hole mask on the upper surface of the silicon substrate (1) on the patterned insulating layer, then depositing an insulating material and placing it in a degumming solution for stripping, leaving an insulating layer with silicon windows and silicon contact holes; or first depositing an insulating material, then patterning the insulating layer using photolithography and etching techniques to form an insulating layer with silicon windows and silicon contact holes; (3) using photolithography technology to make an electrode pattern mask on the upper surface of the insulating layer (3), depositing electrode materials, and then peeling them off in a degumming solution to form a top electrode and a silicon contact electrode (6); or alternatively, first depositing electrode materials, and then using photolithography and etching technology to pattern the electrodes to form the top electrode and the silicon contact electrode (6); (4) transferring the two-dimensional material (5) onto the silicon window array (7); (5) Using photolithography and etching techniques to pattern the two-dimensional material (5), leaving the two-dimensional material (5) in the area where the heterojunction array is located.

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