A dual-gate ferroelectric transistor, a preparation method and a data erase and readout method

Abstract

The application belongs to the technical field of transistors, and discloses a double-gate ferroelectric transistor, a preparation method and a data erasing and reading method, which comprise a substrate and a channel, the channel is arranged above the substrate and located at the middle part of the substrate, source and drain regions are arranged on the two sides of the channel respectively, a source electrode is arranged on the source region, a drain electrode is arranged on the drain region, and an insulating layer, a lower gate electrode, a ferroelectric gate dielectric layer and an upper gate electrode are sequentially arranged above the channel from bottom to top. The double-gate ferroelectric field effect transistor can realize the erasing and writing process by adding a pulse between the upper gate electrode and the lower gate electrode, so that the voltage is prevented from falling on the insulating layer; in turn, the breakdown of the insulating layer caused by an excessively large electric field on the insulating layer is avoided, the fatigue resistance of the transistor is improved, and the programming and erasing voltage and the working voltage of the ferroelectric field effect transistor are reduced.

Description

Technical Field

[0001] This invention relates to the field of transistor technology, and in particular to a dual-gate ferroelectric transistor, its fabrication method, and a data erasure and readout method. Background Technology

[0002] Semiconductor memories, as devices for storing information in electronic systems, are core components ensuring the normal operation of the system. Requirements for them include high storage density, fast write speed, low power consumption, a high number of erase / write cycles, and stable storage state. Among ferroelectric memories, ferroelectric field-effect transistors (FeFETs) have many significant advantages, including non-volatile data storage, programming / erasing times in the nanosecond range, low operating voltage, virtually unlimited endurance, and lossless readout.

[0003] However, the fatigue resistance of ferroelectric field-effect transistors based on HfO2 thin films is significantly different from that of traditional perovskite ferroelectric materials, and cannot meet the application requirements of high-performance devices.

[0004] Traditional data erasure / reading methods involve applying erasure / reading pulses to the source, drain, and gate. As a result, the insulating layer, due to its low dielectric constant, experiences a high electric field during pulse erasure / reading, which can lead to breakdown. Consequently, ferroelectric transistors based on HfO2 thin films have a limited number of fatigue cycles and poor fatigue resistance. Summary of the Invention

[0005] The purpose of this invention is to improve existing ferroelectric transistors and enhance their fatigue resistance.

[0006] To achieve the above objectives, the present invention provides a dual-gate ferroelectric transistor, comprising a substrate and a channel, wherein the channel is disposed above the substrate and located in the middle of the substrate, and a source region and a drain region are respectively disposed on both sides of the channel; a source electrode is disposed on the source region, and a drain electrode is disposed on the drain region; an insulating layer, a lower gate electrode, a ferroelectric gate dielectric layer and an upper gate electrode are disposed sequentially from bottom to top above the channel.

[0007] Furthermore, the ferroelectric gate dielectric layer is an HfZrOx thin film.

[0008] Furthermore, the ratio of the length of the upper gate electrode to the length of the lower gate electrode is greater than zero and less than one.

[0009] Furthermore, the substrate material is Ge or Si0.55Ge0.45 or Si.

[0010] Furthermore, the upper gate electrode and the lower gate electrode are annular gates or fin-shaped gates.

[0011] This invention also discloses a method for fabricating a dual-gate ferroelectric transistor, comprising:

[0012] The substrate is cleaned, and a SiO2 insulating layer is grown on the substrate using a dry oxygen process.

[0013] TaN was deposited on the SiO2 insulating layer using a magnetron sputtering process to form the lower gate electrode;

[0014] A HfZrOx thin film is deposited on the lower gate electrode to form a ferroelectric gate dielectric layer;

[0015] TaN was deposited on the ferroelectric gate dielectric layer using a magnetron sputtering process to form the upper gate electrode;

[0016] The upper gate electrode region is marked on the upper gate electrode using photolithography.

[0017] Using an etching process, the excess portion around the upper gate electrode area is etched to the surface of the lower gate electrode.

[0018] The source region, lower gate region, and drain region are marked on the lower gate electrode using photolithography.

[0019] Using an etching process, the excess portions around the source and drain regions are etched to the substrate surface, and the source and drain regions on both sides of the lower gate region are etched to the substrate surface.

[0020] Ion implantation is performed on the substrate of the etched source and drain regions to form source and drain regions. The substrate at the same horizontal height between the source and drain regions, where no ions are implanted, forms the channel.

[0021] The source and drain regions are activated using an annealing process;

[0022] Using electron beam technology, metal is deposited on the upper surfaces of the activated source and drain regions to form source and drain electrodes, thus obtaining a ferroelectric field-effect transistor with an MFMIS structure.

[0023] Furthermore, the deposition of a HfZrOx thin film on the lower gate electrode to form a ferroelectric gate dielectric layer specifically involves:

[0024] Using TDMAHf and TDMAZr as hafnium and zirconium sources, HfZrOx thin films are deposited on the insulating layer by atomic layer deposition, magnetron sputtering or pulsed laser deposition to form a ferroelectric gate dielectric layer.

[0025] Furthermore, the magnetron sputtering process specifically involves growing TaN under nitrogen and argon atmospheres, using solid Ta as the sputtering target, and at a pressure of 1×10⁻⁷–1.5×10⁻⁷ Pa.

[0026] Furthermore, the thickness of the TaN is 5-100 nm.

[0027] This invention also discloses a data erasing and reading method, which utilizes the aforementioned dual-gate ferroelectric transistor.

[0028] When writing data: a positive pulse voltage is applied between the upper gate electrode and the lower gate electrode, the source electrode is grounded, and the potentials of the drain electrode and the lower gate electrode are kept consistent. At this time, the upper gate electrode is at a high level, and the drain electrode and the lower gate electrode are at a low level, thus realizing data writing.

[0029] When erasing data: a negative pulse voltage is applied between the upper gate electrode and the lower gate electrode, the source electrode is grounded, and the drain electrode and the lower gate electrode are kept at the same potential. At this time, the upper gate electrode is at a low level, the lower gate electrode is at a high level, and the drain electrode is at a high level, thus realizing data erasure.

[0030] When reading data, the lower gate electrode is left floating, and the current is read through the upper gate electrode, source, and drain. At this time, the upper gate electrode is at a high level, the drain electrode is at a high level, and the source electrode is grounded. The source and drain currents are read to determine the storage status.

[0031] Compared with the prior art, the dual-gate ferroelectric transistor, its fabrication method, and its data erasure and readout method of this invention have the following advantages: The dual-gate ferroelectric transistor of this invention achieves the erasure and write process by applying a pulse between the upper gate electrode and the lower gate electrode, avoiding voltage falling on the insulating layer; thus, it avoids excessive electric field on the insulating layer leading to insulation layer breakdown, improving the transistor's fatigue resistance; it also avoids voltage division in the insulating layer, thereby reducing the programming and erasure voltage and the operating voltage of the ferroelectric transistor. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a dual-gate ferroelectric transistor according to the present invention;

[0033] Figure 2 This is a voltage waveform diagram during the data erasure, writing, and reading process of a dual-gate ferroelectric transistor according to the present invention.

[0034] Figure 3 This is a schematic diagram of the fabrication process of a dual-gate ferroelectric transistor according to the present invention.

[0035] In the figure, 1 is the substrate; 2 is the source region; 3 is the drain region; 4 is the channel; 5 is the insulating layer; 6 is the lower gate electrode; 7 is the ferroelectric gate dielectric layer; 8 is the upper gate electrode; 9 is the drain electrode; and 10 is the source electrode. Detailed Implementation

[0036] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0037] Example 1:

[0038] like Figure 1 As shown, the present invention discloses a dual-gate ferroelectric transistor, including a substrate 1 and a channel 4. The channel 4 is disposed above the substrate and located in the middle of the substrate. A source region 2 and a drain region 3 are respectively disposed on both sides of the channel 4. A source electrode 10 is disposed on the source region 2, and a drain electrode 9 is disposed on the drain region 3. An insulating layer 5, a lower gate electrode 6, a ferroelectric gate dielectric layer 7, and an upper gate electrode 8 are disposed sequentially from bottom to top above the channel 4.

[0039] Figure 1 The dual-gate ferroelectric transistor can be obtained according to the fabrication method of Embodiment 2. Those skilled in the art can also obtain it using other methods, such as... Figure 1 The structure is a dual-gate ferroelectric transistor. In conventional techniques, the insulating layer 5 carries a high voltage, making it prone to breakdown. Furthermore, the requirement of voltage on the insulating layer 5 for writing and erasing further increases the risk of breakdown and reduces the transistor's fatigue resistance.

[0040] The inventiveness of the dual-gate ferroelectric transistor of the present invention lies in the fact that a source region 2 and a drain region 3 are provided on both sides of the channel 4, and an insulating layer 5, a lower gate electrode 6, a ferroelectric gate dielectric layer 7 and an upper gate electrode 8 are sequentially provided above the channel 4 from bottom to top.

[0041] Reference Figure 2 Using the transistor of this invention, when writing data: a positive pulse voltage is applied between the upper gate electrode 8 and the lower gate electrode 6, the source electrode 10 is grounded, and the drain electrode 9 and the lower gate electrode 6 have the same potential. At this time, the upper gate electrode 8 is at a high level, and the drain electrode 9 and the lower gate electrode 6 are at a low level, thus realizing data writing. When erasing data: a negative pulse voltage is applied between the upper gate electrode 8 and the lower gate electrode 6, the source electrode 10 is grounded, and the drain electrode 9 and the lower gate electrode 6 have the same potential. At this time, the upper gate electrode 8 is at a low level, the lower gate electrode 6 is at a high level, and the drain electrode 9 is at a high level, thus realizing data erasure. When reading data: the lower gate electrode 6 is left floating, and the current is read through the upper gate electrode 8, the source electrode, and the drain electrode. At this time, the upper gate electrode 8 is at a high level, the drain electrode 9 is at a high level, the source electrode 10 is grounded, and the source and drain currents are read to determine the storage state. It can be seen that the insulating layer 5 does not carry voltage, there is no risk of breakdown, and the voltage during erasure, writing, and reading is low.

[0042] In this embodiment, the channel 4 is located in the middle of the substrate. This can be understood as the channel 4 being located at the center of the substrate, and the substrate and the channel 4 forming a symmetrical structure. However, the center of the channel 4 is not necessarily exactly as described above; it may be offset to a certain extent. The channel 4 covering the center line of the substrate 1 should still be understood as the channel 4 being located in the middle of the substrate.

[0043] In this embodiment, the ferroelectric gate dielectric layer 7 is an HfZrOx thin film. The specific method for preparing the HfZrOx thin film is as follows:

[0044] Using TDMAHf and TDMAZr as hafnium and zirconium sources, HfZrOx thin films are deposited on insulating layer 5 by atomic layer deposition, magnetron sputtering or pulsed laser deposition to form ferroelectric grid dielectric layer 7.

[0045] In this embodiment, the ratio of the length of the upper gate electrode 8 to the length of the lower gate electrode 6 is greater than zero and less than one.

[0046] In this embodiment, the ferroelectric gate dielectric layer 7 and the upper gate electrode 8 have the same width.

[0047] In this embodiment, the insulating layer 5 and the lower gate electrode 6 have the same width.

[0048] In this embodiment, the substrate 1 is made of Ge or Si0.55Ge0.45 or Si.

[0049] In this embodiment, the upper gate electrode 8 and the lower gate electrode 6 may also be different gate structures such as annular gates or fin gates. The aforementioned electrodes and the lower gate electrode 6 have the same shape.

[0050] In this embodiment, multiple gate groups can be disposed above the channel 4. Each gate group consists of an insulating layer 5, a lower gate electrode 6, a ferroelectric gate dielectric layer 7, and an upper gate electrode 8, from bottom to top. Those skilled in the art can dispose of several gate groups on the channel 4 according to the content disclosed in this embodiment. Each gate group has the same function and structure, and multiple gate groups can expand the information storage capacity.

[0051] Implementation 2:

[0052] See Figure 3 This invention discloses a method for fabricating a dual-gate ferroelectric transistor, comprising:

[0053] After cleaning substrate 1, a SiO2 insulating layer 5 is grown on substrate 1 using a dry oxygen process, as shown in the figure. Figure 3 (a)(b);

[0054] TaN was deposited on the SiO2 insulating layer 5 using a magnetron sputtering process to form the lower gate electrode 6, see [link to documentation]. Figure 3 (c);

[0055] A thin film of HfZrOx is deposited on the lower gate electrode 6 to form the ferroelectric gate dielectric layer 7. Figure 3 (d);

[0056] TaN is deposited on the ferroelectric gate dielectric layer 7 using a magnetron sputtering process to form the upper gate electrode 8, see [link to documentation]. Figure 3 (e);

[0057] The area of ​​the upper gate electrode 8 is marked on the upper gate electrode 8 using photolithography.

[0058] Using an etching process, the excess portion around the upper gate electrode 8 region is etched to the surface of the lower gate electrode 6, as shown in the figure. Figure 3 (f);

[0059] Using photolithography, the source region, lower gate region, and drain region are marked on the lower gate electrode 6;

[0060] Using an etching process, the excess portions around the source and drain regions are etched onto the surface of substrate 1, and the source and drain regions on both sides of the lower gate region are etched onto the surface of substrate 1. (See...) Figure 3 (h);

[0061] Ion implantation is performed on substrate 1 after etching the source and drain regions to form source region 2 and drain region 3. The un-ion-implanted region of substrate 1 at the same horizontal level between source region 2 and drain region 3 forms channel 4. (See...) Figure 3 (i);

[0062] The source region 2 and drain region 3 are activated using an annealing process;

[0063] Using electron beam processing, metal is deposited on the surface of the activated source region 2 and drain region 3 to form source electrode 10 and drain electrode 9, thus obtaining a ferroelectric field-effect transistor with an MFMIS structure. (See...) Figure 3 (j).

[0064] In this embodiment, cleaning the substrate 1 can remove residual organic impurities, metal ions, and intrinsic oxide layers from its surface, avoiding any impact on subsequent processes and device performance. The cleaned substrate 1 can then better form the insulating layer 5.

[0065] In this embodiment, the material of the generated lower gate electrode 6 is preferably TaN, and the thickness of TaN is 5-100 nm. The thickness value includes the endpoint value. It can be five nanometers or one hundred nanometers. Those skilled in the art can select an appropriate thickness for the lower gate electrode 6 as needed.

[0066] In this embodiment, the thickness of the lower gate electrode 6 is further preferably 10 nm.

[0067] In this embodiment, the deposition of a HfZrOx thin film on the lower gate electrode 6 to form a ferroelectric gate dielectric layer 7 specifically involves:

[0068] Using TDMAHf and TDMAZr as hafnium and zirconium sources, HfZrOx thin films are deposited on insulating layer 5 by atomic layer deposition, magnetron sputtering or pulsed laser deposition to form ferroelectric grid dielectric layer 7.

[0069] In this embodiment, the upper gate electrode 8 is manufactured using the same process as the lower gate electrode 6, but their lengths differ. In this embodiment, the ratio of the length of the upper gate electrode 8 to the length of the lower gate electrode 6 is greater than or equal to 0.05 and less than or equal to 0.95. The thickness of the upper gate electrode 8 is 5-100 nm, and can be taken from the endpoint values, but is more preferably 10 nm.

[0070] In this embodiment, the magnetron sputtering process specifically involves growing TaN under a nitrogen and argon atmosphere, using solid Ta as the sputtering target, and a pressure of 1×10⁻⁷–1.5×10⁻⁷ Pa.

[0071] In this embodiment, the photolithography process is a prior art and will not be described in detail.

[0072] In this embodiment, the etching process specifically involves using chlorine radicals as an etchant, performed under the masking effect of photoresist.

[0073] In this embodiment, the ion implantation process is as follows: implantation energy of 20-30 keV and ion dose of 1×10¹⁵-2×10¹⁵ cm⁻³. The ions implanted are: BF²⁺ ions implanted in the fabrication of P-type transistors and P⁺ ions implanted in the fabrication of N-type transistors.

[0074] In this embodiment, the annealing process is as follows: the source and drain electrodes are thermally annealed at 400-900℃ for 2-5 minutes.

[0075] In this embodiment, the deposition of metal on the upper surfaces of source region 2 and drain region 3 specifically involves: using solid Ni as the source, depositing Ni on the upper surfaces of source region 2 and drain region 3. The thickness of the deposited metal (Ni) is 5-100 nm; more preferably, the thickness is 10 nm. The thickness includes the endpoints.

[0076] Those skilled in the art can fabricate dual-gate ferroelectric transistors using the method disclosed in this invention, and simple feature substitutions based on the above method also fall within the scope of protection of this invention.

[0077] Based on the above-described process and procedure, the dual-gate ferroelectric transistor described in Example 1 can be obtained. This dual-gate ferroelectric transistor can not only complete data erasure and reading, but also achieve the erasure and writing process by applying a pulse between the upper gate electrode 8 and the lower gate electrode 6, thus avoiding voltage falling on the insulating layer 5. This prevents the insulating layer 5 from being broken down due to excessive electric field, thereby improving the transistor's fatigue resistance. It can also avoid voltage division in the insulating layer 5, thereby reducing the programming and erasure voltage and the operating voltage of the ferroelectric transistor.

[0078] Example 3:

[0079] The switching electrode type data erase / write / read method of the present invention is implemented based on the dual-gate ferroelectric field-effect transistor of Embodiment 1. The timing diagram of the voltage variation during erase / write and read operations over time is shown below. Figure 2 As shown, the voltage waveform of the upper gate electrode 8 corresponds to G1, the voltage waveform of the lower gate electrode 6 corresponds to G2, the voltage waveform of the source electrode 10 corresponds to S, and the voltage waveform of the drain electrode 9 corresponds to D.

[0080] This invention discloses a data erasure, writing, and reading method, which applies the dual-gate ferroelectric transistor described in Example 1.

[0081] When writing data: a positive pulse voltage is applied between the upper gate electrode 8 and the lower gate electrode 6, the source electrode 10 is grounded, and the potentials of the drain electrode 9 and the lower gate electrode 6 are kept consistent. At this time, the upper gate electrode 8 is at a high level, and the drain electrode 9 and the lower gate electrode 6 are at a low level, thus realizing data writing.

[0082] In this embodiment, a positive pulse voltage is applied between the upper and lower gate electrodes 6 to perform the "write" operation, at which time the binary information "1" is stored in the ferroelectric thin film.

[0083] When erasing data: a negative pulse voltage is applied between the upper gate electrode 8 and the lower gate electrode 6, the source electrode 10 is grounded, and the drain electrode 9 is at the same potential as the lower gate electrode 6. At this time, the upper gate electrode 8 is at a low level, the lower gate electrode 6 is at a high level, and the drain electrode 9 is at a high level, thus realizing data erasure.

[0084] In this embodiment, when performing the "erasure" operation, a negative pulse voltage is applied between the upper and lower gate electrodes 6, at which time binary information "0" is stored in the ferroelectric thin film.

[0085] When reading data, the lower gate electrode 6 is left floating, and the current is read through the upper gate electrode 8, the source, and the drain. At this time, the upper gate electrode 8 is at a high level, the drain electrode 9 is at a high level, and the source electrode 10 is grounded. The source and drain currents are read to determine the storage status.

[0086] In summary, the dual-gate ferroelectric transistor, its fabrication method, and its data erasure and readout method provided by the embodiments of the present invention have the following advantages compared with the prior art: The dual-gate ferroelectric transistor of the present invention achieves the erasure and write process by applying a pulse between the upper gate electrode 8 and the lower gate electrode 6, avoiding voltage falling on the insulating layer 5; thereby avoiding excessive electric field on the insulating layer 5 leading to breakdown of the insulating layer 5, improving the fatigue resistance of the transistor; it can also avoid voltage division in the insulating layer 5, thereby reducing the programming and erasure voltage and the operating voltage of the ferroelectric effect transistor.

[0087] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A dual-gate ferroelectric transistor, characterized in that, The device includes a substrate and a channel. The channel is disposed above the substrate and in the middle of the substrate. A source region and a drain region are respectively disposed on both sides of the channel. A source electrode is disposed on the source region and a drain electrode is disposed on the drain region. An insulating layer, a lower gate electrode, a ferroelectric gate dielectric layer and an upper gate electrode are disposed sequentially from bottom to top above the channel. The upper gate electrode and the lower gate electrode are annular gates or fin-shaped gates, and the ratio of the length of the upper gate electrode to the length of the lower gate electrode is greater than zero and less than one. The substrate material is Ge, Si0.55Ge0.45, or Si; The dual-gate ferroelectric transistor is used to perform a data erasure and readout method, including: When the dual-gate ferroelectric transistor performs data writing: a positive pulse voltage is applied between the upper gate electrode and the lower gate electrode, the source electrode is grounded, and the potentials of the drain electrode and the lower gate electrode are kept consistent. At this time, the upper gate electrode is at a high level, and the drain electrode and the lower gate electrode are at a low level, thereby realizing data writing. When the dual-gate ferroelectric transistor erases data, a negative pulse voltage is applied between the upper gate electrode and the lower gate electrode, the source electrode is grounded, and the drain electrode and the lower gate electrode have the same potential. At this time, the upper gate electrode is at a low level, the lower gate electrode is at a high level, and the drain electrode is at a high level, thereby realizing data erasure. When the dual-gate ferroelectric transistor reads data, the lower gate electrode is left floating, and the current is read through the upper gate electrode, source, and drain. At this time, the upper gate electrode is at a high level, the drain electrode is at a high level, and the source electrode is grounded. The source and drain currents are read to determine the storage status. The insulating layer is a SiO2 insulating layer, and the upper and lower gate electrodes are made of TaN. The TaN is sputtered by magnetron sputtering in a nitrogen and argon atmosphere, using solid Ta as the sputtering target, at a density of 1×10⁻⁶. -7 -1.5×10 -7 Grown under Pa pressure, with a thickness of 5-100 nm.

2. A method for fabricating a dual-gate ferroelectric transistor, characterized in that, Applied to a dual-gate ferroelectric transistor as described in claim 1, comprising: The substrate is cleaned, and a SiO2 insulating layer is grown on the substrate using a dry oxygen process. TaN was deposited on the SiO2 insulating layer using a magnetron sputtering process to form the lower gate electrode; A HfZrOx thin film is deposited on the lower gate electrode to form a ferroelectric gate dielectric layer; TaN was deposited on the ferroelectric gate dielectric layer using a magnetron sputtering process to form the upper gate electrode; The upper gate electrode region is marked on the upper gate electrode using photolithography. Using an etching process, the excess portion around the upper gate electrode area is etched to the surface of the lower gate electrode. The source region, lower gate region, and drain region are marked on the lower gate electrode using photolithography. Using an etching process, the excess portions around the source and drain regions are etched to the substrate surface, and the source and drain regions on both sides of the lower gate region are etched to the substrate surface. Ion implantation is performed on the substrate of the etched source and drain regions to form source and drain regions. The substrate at the same horizontal height between the source and drain regions, where no ions are implanted, forms the channel. The source and drain regions are activated using an annealing process; Using electron beam technology, metal is deposited on the upper surfaces of the activated source and drain regions to form source and drain electrodes, thus obtaining a ferroelectric field-effect transistor with an MFMIS structure.

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