A delay circuit with low process angle deviation

Abstract

The present invention provides a low process angle deviation delay circuit, including a low process angle deviation current mirror circuit and a delay module. The low process angle deviation current mirror circuit generates two currents according to its own input voltage, and adjusts its own device parameters so that the two currents are opposite to the process angle variation coefficient, inputs the two currents into the delay module, and controls the delay module to start. The delay module generates a fixed time delay signal through its own charging and discharging process. The present invention greatly reduces the large delay changes caused by the process angle change by the mutual cancellation of the two currents relative to the process angle variation coefficient, so that the delay module can generate a delay signal with a set time and is not affected by the process angle deviation. The delay signal of the present invention has high accuracy and can be widely used in structures that require a delay circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a low process angle deviation delay circuit. Background Art

[0002] The delay circuit is an indispensable basic building block in integrated circuits and is widely used in protection circuits, oscillators, and high-voltage drive circuits. Its function is to provide a set delay time T for the signal. Since the delay time generated by the current delay circuit is based on the size of the capacitor and the size of the charging current of the capacitor, the reference current provided by the reference circuit will change greatly under different process angles, resulting in a large difference in the delay time.

[0003] A common processing method in the prior art is to improve the reference current accuracy provided by the reference circuit under different process angles by increasing the design requirements for the reference circuit. However, this method has the following disadvantages: first, the reference circuit design is more complicated, which increases the design difficulty; second, the other parameters in the circuit also change with the process angle, resulting in this method not being able to effectively reduce the delay time deviation.

[0004] Therefore, for circuits requiring high precision in process angle variation deviation, the existing delay circuits generate long delay times, which will have a significant impact on the normal operation of subsequent circuits. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a low process angle deviation delay circuit. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] A low process angle deviation delay circuit provided by the present invention comprises:

[0007] A low process angle deviation current mirror circuit and a delay module, wherein the low process angle deviation current mirror circuit comprises a current mirror and a switch structure circuit;

[0008] A low process angle deviation current mirror circuit is used to generate two currents according to its own input voltage, and adjust its own device parameters so that the two currents are opposite to the process angle variation coefficient, input the two currents to the delay module, and control the start-up of the delay module;

[0009] The delay module is used to generate a fixed-time delay signal through its own charging and discharging process at startup.

[0010] Optionally, the low process angle deviation current mirror circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, and an eighth MOS tube M8;

[0011] The gate of the first MOS transistor M1 and the gate of the seventh MOS transistor M7 are both connected to the first input power terminal V BIASP The source of the first MOS tube (M1), the source of the fifth MOS tube (M5), the source of the sixth MOS tube (M6) and the source of the seventh MOS tube (M7) are all connected to the fourth input power supply terminal VDD; the gate of the second MOS tube M2 and the gate of the eighth MOS tube M8 are all connected to the second input power supply terminal V IN ; The drain of the first MOS tube M1 is connected to the source of the second MOS tube M2; the drain of the second MOS tube M2 is connected to the gate of the third MOS tube M3, the gate of the fourth MOS tube M4 and the drain of the third MOS tube M3; the source of the third MOS tube (M3) and the source of the fourth MOS tube (M4) are both connected to the ground terminal; the drain of the fourth MOS tube M4 is connected to the drain of the fifth MOS tube M5, the gate of the fifth MOS tube M5 and the gate of the sixth MOS tube M6; the drain of the seventh MOS tube M7 is connected to the source of the eighth MOS tube M8; the drain of the sixth MOS tube M6 outputs a first current to the delay module, and the drain of the eighth MOS tube M8 outputs a second current to the delay module.

[0012] Optionally, the delay module includes a first capacitor C1, a ninth MOS tube M9 and a tenth MOS tube M10;

[0013] The gate of the ninth MOS tube M9 is connected to the gate of the eighth MOS tube M8, the drain of the ninth MOS tube M9 is connected to one end of the first capacitor C1, the source of the ninth MOS tube M9 is connected to the drain of the tenth MOS tube M10, and the gate of the tenth MOS tube M10 is connected to the third input power supply terminal V BIASN The source of the tenth MOS tube M10 and the other end of the first capacitor C1 are connected to the ground terminal, and the drain of the ninth MOS tube M9 is the output terminal of the delay circuit (V LCC-OUT ), output a delayed signal of a fixed time.

[0014] Optionally, the first MOS transistor M1 is a long-channel MOS transistor, and the seventh MOS transistor M7 is a short-channel MOS transistor.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The present embodiment provides a low process angle deviation delay circuit, including a low process angle deviation current mirror circuit and a delay module. The low process angle deviation current mirror circuit generates two currents according to its own input voltage, and adjusts its own device parameters so that the two currents are opposite to the process angle variation coefficient, inputs the two currents into the delay module, and controls the delay module to start. The delay module generates a fixed time delay signal through its own charging and discharging process. The present invention greatly reduces the large delay changes caused by the process angle change by the mutual cancellation of the two currents relative to the process angle variation coefficient, so that the delay module can generate a delay signal with a set time and is not affected by the process angle deviation. The delay signal of the present invention has high accuracy and can be widely used in structures that require a delay circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An overall circuit diagram of a low process angle deviation delay circuit provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram showing how the delay time T of the low process angle deviation delay circuit provided in an embodiment of the present invention varies with the process angle. DETAILED DESCRIPTION

[0019] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0020] See also Figure 1 , Figure 1 A schematic diagram of a low process angle deviation delay circuit structure provided by an embodiment of the present invention, a low process angle deviation delay circuit of the present invention comprises:

[0021] A low process angle deviation current mirror circuit and a delay module, wherein the low process angle deviation current mirror circuit comprises a current mirror and a switch structure circuit;

[0022] A low process angle deviation current mirror circuit is used to generate two currents according to its own input voltage, and adjust its own device parameters so that the two currents are opposite to the process angle variation coefficient, input the two currents to the delay module, and control the start-up of the delay module;

[0023] The delay module is used to generate a fixed-time delay signal through its own charging and discharging process at startup.

[0024] The low process angle deviation current mirror circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, and an eighth MOS tube M8;

[0025] The gate of the first MOS transistor M1 and the gate of the seventh MOS transistor M7 are both connected to the first input power terminal V BIASP The source of the first MOS tube (M1), the source of the fifth MOS tube (M5), the source of the sixth MOS tube (M6) and the source of the seventh MOS tube (M7) are all connected to the fourth input power supply terminal VDD; the gate of the second MOS tube M2 and the gate of the eighth MOS tube M8 are all connected to the second input power supply terminal V IN ; The drain of the first MOS tube M1 is connected to the source of the second MOS tube M2; the drain of the second MOS tube M2 is connected to the gate of the third MOS tube M3, the gate of the fourth MOS tube M4 and the drain of the third MOS tube M3; the source of the third MOS tube (M3) and the source of the fourth MOS tube (M4) are both connected to the ground terminal; the drain of the fourth MOS tube M4 is connected to the drain of the fifth MOS tube M5, the gate of the fifth MOS tube M5 and the gate of the sixth MOS tube M6; the drain of the seventh MOS tube M7 is connected to the source of the eighth MOS tube M8; the drain of the sixth MOS tube M6 outputs a first current to the delay module, and the drain of the eighth MOS tube M8 outputs a second current to the delay module.

[0026] Wherein, the delay module includes a first capacitor C1, a ninth MOS tube M9 and a tenth MOS tube M10;

[0027] The gate of the ninth MOS tube M9 is connected to the gate of the eighth MOS tube M8, the drain of the ninth MOS tube M9 is connected to one end of the first capacitor C1, the source of the ninth MOS tube M9 is connected to the drain of the tenth MOS tube M10, and the gate of the tenth MOS tube M10 is connected to the third input power supply terminal V BIASN The source of the tenth MOS tube M10 and the other end of the first capacitor C1 are connected to the ground terminal, and the drain of the ninth MOS tube M9 is the output terminal of the delay circuit (V LCC-OUT ), outputs a delayed signal of a fixed time. The first MOS transistor M1 is a long-channel MOS transistor, and the seventh MOS transistor M7 is a short-channel MOS transistor.

[0028] The overall principle of the low process angle deviation delay circuit of the present invention is described below:

[0029] M1 and M7 are related to the input voltage V BIASP A current mirror is formed, and M1 is a long-channel MOS tube, and M7 is a short-channel MOS tube, which can ensure that the current replication multiple of the M1 tube is positively correlated with the process angle change, and the current replication multiple of the M7 tube is independent of the process angle change.

[0030] M2 and M8 are used as switch structures. When the input V INWhen it is low, M2 and M8 are turned on, M1 and M7 start to work as a current mirror, copying the previous current, M1 to C1 generates one current, M7 to C1 generates a second current, and the delay circuit starts to work.

[0031] The bandgap reference current of the previous stage is copied through the current mirror M1, flows through the open switch tube M2, and then is copied to M4 through the current mirror composed of M3 and M4. The current on M4 flows through M5, and then is copied to M6 through the current mirror composed of M5 and M6. The current on M6 charges the capacitor C1 to form one current. The bandgap reference current of the previous stage is copied through the current mirror M7, and charges the capacitor C1 through the open switch tube M8 to form two currents.

[0032] M3, M4, M5 and M6 form a current mirror circuit. By changing their width-to-length ratio, the current I copied by M1 can be adjusted. M1 When the process angle changes, if the reference current provided by the bandgap reference circuit decreases, due to I M1 Is the current that is positively correlated with the process angle change, I M1 Increases, and at the same time the current I M7 The current replication multiple has nothing to do with the process angle change, so I M7 As the reference current decreases, it decreases. Properly adjusting the width-to-length ratio of M3, M4, M5, and M6 can make I M1 with I M7 The summed current I M The coefficient of change relative to the process angle is A.

[0033] C1, M9 and M10 are used as delay modules. The coefficient of C1 changing with the process angle is B. By adjusting the width-to-length ratio of M3, M4, M5 and M6 so that A=B, the current I can be offset. M The deviation of the charging time T of capacitor C1 to the process angle change. M9 and M10 form a discharge path. When V IN When it is low, the discharge path is closed. IN When it is high, the charge on C1 is quickly discharged and the delay circuit is closed to wait for the next operation.

[0034] See also Figure 2 , Figure 2 Schematic diagram of the delay time T of the low process angle deviation delay circuit provided by the embodiment of the present invention at different process angles. The experimental condition is to set V DD The voltage range is 2.6-5.3V, T=1.35ms. After simulation under three process angles FF, SS, and TT, it can be seen that within a given voltage range, when the bandgap reference current source current is offset by 30% under different process angles, the deviation of T is less than 2%. The delay time of the delay circuit is less affected by the process angle deviation.

[0035] The present embodiment provides a low process angle deviation delay circuit, including a low process angle deviation current mirror circuit and a delay module. The low process angle deviation current mirror circuit generates two currents according to its own input voltage, and adjusts its own device parameters so that the two currents are opposite to the process angle variation coefficient, inputs the two currents into the delay module, and controls the delay module to start. The delay module generates a fixed time delay signal through its own charging and discharging process. The present invention greatly reduces the large delay changes caused by the process angle change by the mutual cancellation of the two currents relative to the process angle variation coefficient, so that the delay module can generate a delay signal with a set time and is not affected by the process angle deviation. The delay signal of the present invention has high accuracy and can be widely used in structures that require a delay circuit.

[0036] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A low process angle deviation delay circuit, characterized in that: include: A low process angle deviation current mirror circuit and a delay module, wherein the low process angle deviation current mirror circuit comprises a current mirror and a switch structure circuit; The low process angle deviation current mirror circuit is used to generate two currents according to its own input voltage, and adjust its own device parameters so that the two currents are opposite to the process angle variation coefficient, input the two currents to the delay module, and control the delay module to start; The delay module is used to generate a fixed time delay signal through its own charging and discharging process at startup; The low process angle deviation current mirror circuit comprises a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3), a fourth MOS tube (M4), a fifth MOS tube (M5), a sixth MOS tube (M6), a seventh MOS tube (M7), and an eighth MOS tube (M8); The gate of the first MOS transistor (M1) and the gate of the seventh MOS transistor (M7) are both connected to the first input power supply terminal (V BIASP The source of the first MOS tube (M1), the source of the fifth MOS tube (M5), the source of the sixth MOS tube (M6) and the source of the seventh MOS tube (M7) are all connected to the fourth input power supply terminal (VDD); the gate of the second MOS tube (M2) and the gate of the eighth MOS tube (M8) are all connected to the second input power supply terminal (V IN The drain of the first MOS tube (M1) is connected to the source of the second MOS tube (M2); the drain of the second MOS tube (M2) is connected to the gate of the third MOS tube (M3), the gate of the fourth MOS tube (M4) and the drain of the third MOS tube (M3); the source of the third MOS tube (M3) and the source of the fourth MOS tube (M4) are both connected to the ground terminal; the drain of the fourth MOS tube (M4) is connected to the drain of the fifth MOS tube (M5), the gate of the fifth MOS tube (M5) and the gate of the sixth MOS tube (M6); the drain of the seventh MOS tube (M7) is connected to the source of the eighth MOS tube (M8); the drain of the sixth MOS tube (M6) outputs a first current to the delay module, and the drain of the eighth MOS tube (M8) outputs a second current to the delay module.

2. The low process angle deviation delay circuit according to claim 1, characterized in that: The delay module comprises a first capacitor (C1), a ninth MOS tube (M9) and a tenth MOS tube (M10); The gate of the ninth MOS tube (M9) is connected to the gate of the eighth MOS tube (M8), the drain of the ninth MOS tube (M9) is connected to one end of the first capacitor (C1), the source of the ninth MOS tube (M9) is connected to the drain of the tenth MOS tube (M10), and the gate of the tenth MOS tube (M10) is connected to the third input power supply terminal (V BIASN The source of the tenth MOS tube (M10) and the other end of the first capacitor (C1) are connected to the ground terminal, and the drain of the ninth MOS tube (M9) is the output end of the delay circuit (V LCC-OUT ), outputting a delayed signal of a fixed time; one end of the first capacitor (C1) is connected to the drain of the sixth MOS tube (M6).

3. The low process angle deviation delay circuit according to claim 1, characterized in that: The first MOS transistor (M1) is a long-channel MOS transistor, and the seventh MOS transistor (M7) is a short-channel MOS transistor.

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