A bus loopback test structure and method

Abstract

The application discloses a bus loopback test structure and method, which comprises a register configuration module, a time generation module, a clock synchronization module, a data sending module, a data receiving module, a loopback time generation module and a loopback data sending module; the time generation module and the loopback time generation module generate independent periods and time slot information respectively; when loopback is enabled, the output TX_LP of the loopback data sending module is subjected to AND operation with the output TX of the data sending module, and is connected with RX. The loopback test of the time-triggered bus can be completed, and the test efficiency of the bus is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit design, in particular to a bus loopback test structure and method. BACKGROUND

[0002] In recent years, time-triggered bus has been widely used in industrial control, aerospace, ship weapon and other fields due to its good clock synchronization accuracy.

[0003] Due to the increasing complexity of the control of data transmission and reception of various buses, there are great difficulties in debugging of each node. In addition, compared with event-triggered bus, a large number of time-related parameters need to be configured before the time-triggered bus works, which makes its debugging more complex than event-triggered bus.

[0004] Therefore, loopback test has become an important test method in bus debugging process. In the process of debugging and circuit test, when the receiving and sending of the bus are problematic, loopback test can effectively assist the designer in problem judgment and positioning.

[0005] Event-triggered bus usually supports loopback mode. For time-triggered bus, if the method of event-triggered bus is adopted, the TX end is directly connected with the RX end. Since time-triggered bus needs at least 2 nodes to build their own time network, effective time information cannot be obtained, which leads to the failure of time synchronization of the bus, and further leads to the failure of normal work of the bus, so that it cannot support loopback mode. SUMMARY

[0006] In order to solve the problems in the prior art, the present application provides a bus loopback test structure and method, which can complete the loopback test of time-triggered bus and improve the test efficiency of the bus.

[0007] To achieve the above purpose, the present application provides the following technical solutions:

[0008] A bus loopback test structure, comprising a register configuration module, a time generation module, a clock synchronization module, a data sending module, a data receiving module, a loopback time generation module and a loopback data sending module.

[0009] The register configuration module is used to configure the time parameters of the bus and the time slots of data sending and data receiving.

[0010] The time generation module is used to generate the period and time slot information of the bus according to the parameters configured by the register configuration module.

[0011] The clock synchronization module is used for sampling time information of each synchronization frame and calculating a correction value for clock synchronization.

[0012] The data sending module is used for generating a synchronization frame and a data frame according to cycle and time slot information of the time generation module and sending the frame through a TX end.

[0013] The data receiving module is used for decoding and storing data received by the RX end.

[0014] The loopback time generation module generates cycle and time slot information of the bus according to configured parameters.

[0015] The loopback data sending module generates a synchronization frame and a data frame according to cycle and time slot information of the loopback time generation module and sends the frame through a TX_LP end.

[0016] The time generation module and the loopback time generation module each generate independent cycle and time slot information.

[0017] When loopback is enabled, the output TX_LP of the loopback data sending module is ANDed with the output TX of the data sending module and connected to the RX.

[0018] Preferably, the application further comprises a storage control module used for storing sent and received data.

[0019] Preferably, when loopback is enabled, the output TX of the data sending module is ANDed with the TX_LP of the loopback data sending module and connected to the RX end; when loopback is not enabled, the TX end of the data sending module is output to the outside and the TX_O end input from the outside is connected to the RX end.

[0020] Preferably, the clock synchronization module comprises a deviation value sampling module, a deviation value calculation 1 module and a deviation value calculation 2 module.

[0021] The deviation value sampling module samples deviation value information of the node according to time information carried by each synchronization frame, calculates a correction value through the deviation value calculation 1 module and takes the correction value as input of the time generation module; meanwhile, the deviation value is inverted and a correction value is obtained through the deviation value calculation 2 module and taken as input of the loopback time generation module.

[0022] A bus loopback test method, comprising the following steps,

[0023] Step 1: configuring a loopback test enable register in a register configuration module to make the circuit in a loopback mode;

[0024] Step 2: configuring parameters of a time triggered bus in a time generation module;

[0025] Step 3, configuring loopback synchronization frame SYNC_ID1 and normal synchronization frame SYNC_ID2 in the clock synchronization module;

[0026] Step 4, configuring the loopback test sending module for the data frame ID and corresponding sending data for sending;

[0027] Step 5, configuring the data receiving module for the ID for receiving;

[0028] Step 6, configuring the bus start synchronization;

[0029] Step 7, judging whether the bus is successfully synchronized, if the synchronization is successfully completed, comparing the loopback sending data received by the data receiving module and the received data, if the two are equal, indicating that the loopback test is correct.

[0030] Preferably, in step 2, the parameters of the time triggered bus include the time slot length, the time slot number and the cycle length.

[0031] Preferably, in step 3, the loopback synchronization frame SYNC_ID1 is smaller than the normal synchronization frame SYNC_ID2.

[0032] Compared with the prior art, the application has the following beneficial technical effects:

[0033] The bus loopback test structure of the application performs loopback test through the loopback data sending module and the loopback time generating module, without additional nodes or devices, and by comparing the sending data and the received data, if the two are equal, indicating that the loopback test is successful, otherwise the loopback test fails, facilitating the loopback test. The loopback test structure and the test method of the time triggered bus designed by the application can be used for debugging diagnosis in complex debugging environment, and can be used for circuit automatic test and aging test, which can effectively save resources and improve test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 It is a schematic diagram of the loopback test structure of the application;

[0035] Figure 2 It is a schematic diagram of the connection of the sending port and the receiving port;

[0036] Figure 3 It is a schematic diagram of the structure of the clock synchronization module;

[0037] Figure 4 It is a flow chart of the loopback test method. DETAILED DESCRIPTION

[0038] The application will be further described in detail below in combination with specific embodiments, which are the explanation of the application but not the limitation.

[0039] The bus structure and method for bus loopback test of the present application comprises the following modules: register configuration module, time generation module, clock synchronization module, storage control module, data transmission module, data reception module, loopback time generation module, loopback data transmission module, all of which are interconnected through internal bus.

[0040] The register configuration module configures time parameters of the bus, and configures time slots for data transmission and data reception.

[0041] The time generation module generates information such as period and time slot of the bus according to the configured parameters.

[0042] The clock synchronization module samples time information of each synchronization frame, and calculates and generates a correction value for clock synchronization.

[0043] The storage control module stores transmitted and received data.

[0044] The data transmission module generates synchronization frames and data frames according to period and time slot information of the time generation module, and transmits through TX end.

[0045] The data reception module decodes and stores data received by RX end.

[0046] The loopback time generation module generates information such as period and time slot of the bus according to the configured parameters.

[0047] The loopback data transmission module transmits synchronization frames and data frames according to period and time slot information of the loopback time generation module, and transmits through TX_LP end.

[0048] The time generation module and the loopback time generation module each generate independent period and time slot information.

[0049] In the structure, when loopback is enabled, the output TX_LP of the loopback transmission module and the output TX of the data transmission module are subjected to AND operation, and are connected with RX.

[0050] The loopback test method of the present application comprises the following steps:

[0051] Step 1: configure loopback test enable register, so that the circuit is in loopback mode.

[0052] Step 2: configure parameters of time triggered bus, including time slot length, time slot number and period length, etc.

[0053] Step 3: configure loopback synchronization frame ID, SYNC_ID1 and normal synchronization frame ID, SYNC_ID2; further, it is required that SYNC_ID1<SYNC_ID2.

[0054] Step 4, configure the frame ID and corresponding sending data of the loopback test sending module for sending;

[0055] Step 5, configure the ID for receiving of the receiving module;

[0056] Step 6, configure bus start synchronization;

[0057] Step 7, judge whether the bus is successfully synchronized, if the synchronization is successfully completed, compare the loopback sending data and the received data, if the two are equal, it indicates that the loopback test is correct.

[0058] Figure 1 is the loopback test structure schematic diagram of the application, containing data sending module, data receiving module, clock synchronization module, time generation module, register configuration module and storage control module, loopback time generation module and loopback sending module;

[0059] The register configuration module configures the time parameters of the bus, and configures the time slots of data sending and data receiving;

[0060] The time generation module generates the period and time slot information of the bus according to the configured parameters;

[0061] The clock synchronization module samples the time information of each synchronization frame, and calculates and generates the correction value for clock synchronization;

[0062] The storage control module stores the sending and receiving data;

[0063] The data sending module generates synchronization frames and data frames according to the period and time slot information of the time generation module, and sends through the TX end;

[0064] The data receiving module decodes and stores the data received by the RX end;

[0065] The loopback time generation module generates the period and time slot information of the bus according to the configured parameters;

[0066] The loopback data sending module sends synchronization frames and data frames according to the period and time slot information of the loopback time generation module, and sends through the TX_LP end;

[0067] In the application, the loopback time generation module structure reuses the structure of the time generation module, and the loopback data sending module reuses the structure of the data sending module, which simplifies the design.

[0068] Figure 2is a connection diagram of a sending port and a receiving port. When the loopback is enabled, the output of the data sending module is connected to the RX port by performing an AND operation between the TX of the data sending module and the TX_LP of the loopback data sending module. In the normal mode, the output of the data sending module is connected to the outside, and the TX_O input from the outside is connected to the RX port.

[0069] Figure 3 is a structure diagram of a clock synchronization module, which comprises a deviation value sampling module, a deviation value calculation 1 module and a deviation value calculation 2 module. The deviation value sampling module samples the deviation value information of the node according to the time information carried by each synchronization frame, and calculates the deviation correction value through the deviation value calculation 1 module, which is used as the input of the time generation module. Meanwhile, the deviation value is inverted and input into the deviation value calculation 2 module, which is used as the input of the loopback time generation module. The time-triggered bus usually needs to extract time information from the received information for synchronization, so as to avoid the deviation from becoming larger and larger and thus causing the synchronization to be impossible. The deviation correction value is the information used for correction, which is calculated according to the extracted time information.

[0070] In the flow of the loopback test, the loopback synchronization frame SYNC_ID1<normal synchronization frame ID SYNC_ID2, the loopback time generation module is used as the leading node, which firstly generates time information such as time slot and period. When the loopback synchronization frame ID matches the current time slot, the loopback sending module starts to send the synchronization frame.

[0071] The time generation module is used as the accompanying node, which receives the synchronization frame SYNC_ID1 of the loopback sending module, and generates time information according to the time parameter configuration, including time slot and period. After receiving the time information of the time generation module, the data sending module judges whether the time slot matches the synchronization frame SYNC_ID2, and starts to send the synchronization frame SYNC_ID2.

[0072] The clock synchronization module obtains the deviation value information of each node according to the time information carried by the synchronization frame of each node in each period, and calculates the deviation correction value of the time generation module and the loopback time generation module respectively, which are input into the time generation module and the loopback time generation module respectively for clock synchronization and correction.

[0073] When the clock synchronization is successful, the loopback sending module judges whether the time slot matches the data sending frame ID, and starts to send the data frame. The receiving module decodes and receives the data on the bus. If the sending data and the receiving data are equal, it indicates that the loopback test is successful, otherwise, the loopback test fails.

[0074] The loopback test structure and the test method can be used for debugging under a complex topology, and can be used in automatic circuit testing and burn-in testing, thereby effectively saving resources and improving test efficiency. The application has been applied to multiple SoCs.

Claims

1. A bus loopback test structure, characterized in that, It includes a register configuration module, a time generation module, a clock synchronization module, a data transmission module, a data reception module, a loopback time generation module, and a loopback data transmission module; The register configuration module is used to configure the bus timing parameters and the time slots for data transmission and reception. The time generation module is used to generate the bus period and time slot information according to the parameters configured by the register configuration module; The clock synchronization module is used to sample the time information of each synchronization frame and calculate and generate the correction value for clock synchronization. The clock synchronization module includes a deviation value sampling module, a deviation value calculation 1 module, and a deviation value calculation 2 module; The deviation value sampling module samples the deviation value information of this node based on the time information carried by each synchronization frame, and calculates the correction value through the correction value calculation module 1, which is used as the input of the time generation module; at the same time, the deviation value is inverted and the correction value is obtained through the correction value calculation module 2, which is used as the input of the loopback time generation module. The data transmission module is used to generate synchronization frames and data frames based on the period and time slot information of the time generation module, and send them through the TX terminal; The data receiving module is used to decode and store the data received by the RX terminal; The loopback time generation module generates the bus period and time slot information according to the configured parameters; The loopback data transmission module generates synchronization frames and data frames based on the period and time slot information of the loopback time generation module, and sends them through the TX_LP terminal. The time generation module and the loopback time generation module each generate independent period and time slot information; When loopback is enabled, the output TX_LP of the loopback data transmission module is ANDed with the output TX of the data transmission module and connected to RX.

2. The bus loopback test structure according to claim 1, characterized in that, It also includes a storage control module, which is used to store the data sent and received.

3. The bus loopback test structure according to claim 1, characterized in that, When loopback enable LB_EN is active, the TX output of the data transmission module is ANDed with the TX_LP of the loopback data transmission module and connected to the RX terminal; when loopback is disabled, i.e., in normal mode, the TX terminal of the data transmission module is output to the outside, and the external input TX_O terminal is connected to the RX terminal.

4. A bus loopback test method, characterized in that, Based on the bus loopback test structure described in claims 1-3 Includes the following steps, Step 1: Configure the loopback test enable register in the register configuration module to put the circuit in loopback mode; Step 2: Configure the parameters of the time trigger bus in the time generation module; Step 3: Configure the loopback synchronization frame SYNC_ID1 and the normal synchronization frame SYNC_ID2 in the clock synchronization module; The clock synchronization module includes a deviation value sampling module, a deviation value calculation 1 module, and a deviation value calculation 2 module; The deviation value sampling module samples the deviation value information of this node based on the time information carried by each synchronization frame, and calculates the correction value through the correction value calculation module 1, which is used as the input of the time generation module; at the same time, the deviation value is inverted and the correction value is obtained through the correction value calculation module 2, which is used as the input of the loopback time generation module. Step 4: Configure the loopback test sending module to send data frame IDs and corresponding data; Step 5: Configure the ID that the data receiving module will receive; Step 6, configure bus startup synchronization; Step 7: Determine if the bus synchronization is successful. If synchronization is successful, compare the loopback data received by the data receiving module with the received data. If they are equal, the loopback test is correct.

5. The bus loopback test method according to claim 4, characterized in that, In step 2, the parameters of the time-triggered bus include the time slot length, the number of time slots, and the period length.

6. The bus loopback test method according to claim 4, characterized in that, In step 3, the loopback synchronization frame SYNC_ID1 is smaller than the normal synchronization frame SYNC_ID2.

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