Display panel and display device

Abstract

The present invention discloses a display panel and display device. By ensuring that the orthographic projections of each effective light-emitting area on a substrate overlap with the orthographic projections of signal traces on the substrate, and that the first overlapping region is non-linear, light emitted from the effective light-emitting area can form optical interference through the signal traces in the first overlapping region. Consequently, when the display panel is used in a 3D display device, moiré patterns can be reduced, enhancing the display quality.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, the field of 3D display has rapidly developed. Among them, lenticular 3D display devices have attracted much attention due to their advantages such as simple manufacturing process and low crosstalk. Typically, a lenticular 3D display device includes a display panel and a grating. The viewer's left and right eyes receive the left and right eye views displayed by the display panel through the grating, respectively, to form a 3D display image. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device to improve display effects.

[0004] A display panel provided by an embodiment of the present invention includes: a base substrate, the base substrate including a plurality of sub-pixels and a plurality of signal lines; wherein each of the sub-pixels includes an effective light-emitting area;

[0005] The orthographic projection of each effective light emitting area on the base substrate and the orthographic projection of the signal trace on the base substrate have a first overlapping area; and the shape of the first overlapping area is non-linear.

[0006] In some examples, the shape of the first overlapping region is a broken line, and a bending angle of the first overlapping region is greater than or equal to 70° and less than 180°.

[0007] In some examples, the plurality of signal lines include a plurality of data lines; one data line is correspondingly provided for one column of sub-pixels;

[0008] Each of the data lines includes a first sub-data line and a second sub-data line electrically connected to each other;

[0009] The orthographic projection of the first sub-data line on the base substrate and the orthographic projection of the effective light-emitting area of ​​the corresponding sub-pixel on the base substrate form the first overlapping area;

[0010] The orthographic projection of the second sub-data line on the base substrate does not overlap with the orthographic projection of each effective light-emitting area on the base substrate.

[0011] In some examples, the display panel further includes: a first insulating layer located between the data line and the base substrate, and a plurality of auxiliary lines located between the first insulating layer and the base substrate; wherein the auxiliary lines extend along a column direction of the sub-pixels; and each sub-pixel corresponds to one auxiliary line;

[0012] The orthographic projection of the auxiliary line on the base substrate does not overlap with the orthographic projection of the effective light-emitting area on the base substrate;

[0013] For the same sub-pixel, the orthographic projection of the auxiliary line on the base substrate and the orthographic projection of the first sub-data line on the base substrate form a triangle; the bending angle is the angle between the first overlapping area and the side facing the auxiliary line.

[0014] In some examples, the display panel further includes: a second insulating layer located on a side of the data line facing away from the base substrate, and a transparent pixel electrode layer located on a side of the second insulating layer facing away from the base substrate;

[0015] The transparent pixel electrode layer includes a plurality of pixel electrodes spaced apart from each other; wherein one sub-pixel includes one pixel electrode.

[0016] In some examples, the pixel electrode includes: a first sub-pixel electrode, a second sub-pixel electrode, and an electrode connecting portion; wherein the first sub-pixel electrode and the second sub-pixel electrode are spaced apart from each other, and the first sub-pixel electrode and the second sub-pixel electrode in the same pixel electrode are electrically connected via the electrode connecting portion;

[0017] The orthographic projection of each data line on the base substrate does not overlap with the orthographic projection of each first sub-pixel electrode and each second sub-pixel electrode on the base substrate.

[0018] In some examples, the display panel further includes: a common electrode layer and a third insulating layer;

[0019] The common electrode layer is located between the second insulating layer and the transparent pixel electrode layer, and the third insulating layer is located between the common electrode layer and the transparent pixel electrode layer; or,

[0020] The common electrode layer is located between the layer where the auxiliary lines are located and the base substrate, and the third insulating layer is located between the common electrode layer and the layer where the auxiliary lines are located.

[0021] In some examples, the plurality of data lines include a plurality of first-type data lines and a plurality of second-type data lines; the first-type data lines and the second-type data lines are alternately arranged along a row direction of the sub-pixels;

[0022] Two adjacent columns of sub-pixels form a column group, and each two adjacent column groups correspond to one first-category data line; wherein, the odd-numbered rows of sub-pixels in the first column group of each two adjacent column groups are all electrically connected to the corresponding first-category data lines, and the even-numbered rows of sub-pixels in the second column group are all electrically connected to the corresponding first-category data lines.

[0023] In some examples, the common electrode layer includes a plurality of common electrode portions spaced apart from each other;

[0024] The orthographic projection of the common electrode portion on the base substrate does not overlap with the orthographic projection of the first-type data line on the base substrate; and / or,

[0025] The orthographic projection of the common electrode portion on the base substrate does not overlap with the orthographic projection of the scanning line on the base substrate; and / or,

[0026] An orthographic projection of the common electrode portion on the base substrate overlaps with an orthographic projection of the second-type data line on the base substrate.

[0027] In some examples, one column group corresponds to one second data line, and one second data line corresponds to one column of common electrode portions;

[0028] When the common electrode layer is located between the second insulating layer and the transparent pixel electrode layer, the second-type data line is electrically connected to the corresponding common electrode portion through a second via hole penetrating the second insulating layer.

[0029] In some examples, the display panel further includes a common electrode connection line that is in the same layer as the scan line and is spaced apart from the scan line; wherein the common electrode connection line extends along the row direction of the sub-pixels, and an orthographic projection of the common electrode connection line on the base substrate does not overlap with an orthographic projection of the effective light-emitting area on the base substrate;

[0030] The common electrode connection line is electrically connected to each of the second-type data lines through a first via hole penetrating the first insulating layer.

[0031] In some examples, one column group corresponds to one second data line, and one second data line corresponds to one column of common electrode portions;

[0032] When the common electrode layer is located between the layer where the auxiliary lines are located and the base substrate, the second-type data lines are electrically connected to the corresponding common electrode parts through third via holes penetrating the first insulating layer and the third insulating layer.

[0033] In some examples, the display panel further includes a common electrode connection line that is in the same layer as the scan line and is spaced apart from the scan line; wherein the common electrode connection line extends along the row direction of the sub-pixels, and an orthographic projection of the common electrode connection line on the base substrate does not overlap with an orthographic projection of the effective light-emitting area on the base substrate;

[0034] The third via hole includes a third transfer hole and a third conductive hole; wherein the third transfer hole passes through the first insulating layer, and the third conductive hole passes through the third insulating layer;

[0035] The second-type data line is electrically connected to the common electrode connection line through the third transfer hole, and the common electrode connection line is electrically connected to the common electrode portion through the third conductive hole.

[0036] A display device provided by an embodiment of the present invention includes the above-mentioned display panel.

[0037] In some examples, the further included is a grating located on the light-emitting side of the display panel.

[0038] The beneficial effects of the present invention are as follows:

[0039] The display panel and display device provided by embodiments of the present invention utilize a non-linear first overlapping region between the orthographic projection of each effective light-emitting area on the substrate and the orthographic projection of the signal trace on the substrate. This allows light emitted from the effective light-emitting area to interfere with the signal trace in the first overlapping region. Consequently, when the display panel is used in a 3D display device, moiré patterns can be reduced, enhancing display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic structural diagram of a display panel in an embodiment of the present invention;

[0041] Figure 2 Schematic diagrams of some specific structures of display panels in embodiments of the present invention;

[0042] Figure 3a Schematic diagrams of some structures of the layer where the scan lines of the display panel are located in an embodiment of the present invention;

[0043] Figure 3b Schematic diagrams of some structures of the layer where the data lines of the display panel are located in an embodiment of the present invention;

[0044] Figure 3c Schematic diagrams of some structures of the common electrode layer of the display panel in the embodiment of the present invention;

[0045] Figure 3d Schematic diagrams of some structures of a transparent pixel electrode layer of a display panel in an embodiment of the present invention;

[0046] Figure 4a Schematic diagrams of some structures of a layer where scan lines and a layer where data lines are located in a display panel according to an embodiment of the present invention;

[0047] Figure 4b Schematic diagrams of some structures of a scan line layer, a data line layer, and a common electrode layer of a display panel in an embodiment of the present invention;

[0048] Figure 5Schematic diagrams of some specific structures of the display panel in the embodiment of the present invention;

[0049] Figure 6a Schematic diagrams of some structures of the layer where the scan lines of the display panel are located in the embodiment of the present invention;

[0050] Figure 6b are some further structural diagrams of the layer where the data lines of the display panel are located in the embodiment of the present invention;

[0051] Figure 6c are further structural schematic diagrams of the common electrode layer of the display panel in the embodiment of the present invention;

[0052] Figure 6d Schematic diagrams of some further structures of the transparent pixel electrode layer of the display panel in the embodiment of the present invention;

[0053] Figure 7a Schematic diagrams of some structures of a layer where scan lines and a layer where data lines are located in a display panel according to an embodiment of the present invention;

[0054] Figure 7b Schematic diagrams of some structures of a layer where scan lines are located, a layer where data lines are located, and a common electrode layer of a display panel in an embodiment of the present invention;

[0055] Figure 8 Schematic diagrams of the structures of the transparent pixel electrode layer and the layer where the data lines are located of the display panel in the embodiment of the present invention;

[0056] Figure 9 Schematic diagrams of some further structures of the transparent pixel electrode layer of the display panel in the embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0059] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0060] When using a lenticular 3D display device, due to the manufacturing process of the display panel or other factors, the resulting 3D display image may produce moiré patterns, thereby affecting the 3D display effect.

[0061] An embodiment of the present invention provides a display panel, such as Figures 1 to 7b As shown, it may include: a base substrate 100, the base substrate 100 includes a plurality of sub-pixels spx and a plurality of signal traces 110; wherein each sub-pixel spx includes an effective light-emitting area FG; the orthographic projection of each effective light-emitting area FG on the base substrate 100 and the orthographic projection of the signal trace 110 on the base substrate 100 have a first overlapping area DB1; and the shape of the first overlapping area DB1 is non-linear.

[0062] In the display panel provided by the embodiments of the present invention, the orthographic projections of each effective light-emitting area on the substrate and the orthographic projections of the signal traces on the substrate have a first overlapping region, and the shape of the first overlapping region is non-linear. This allows light emitted from the effective light-emitting area to form optical interference through the signal traces in the first overlapping region. Consequently, when the display panel is used in a 3D display device, moiré patterns can be reduced, enhancing the display quality.

[0063] In a specific implementation, in an embodiment of the present invention, the display panel may include: a display area, and the display area may include a plurality of pixel units arranged in an array. Each pixel unit includes a plurality of sub-pixels spx. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0064] In specific implementation, in the embodiment of the present invention, as Figures 2 to 7b As shown, the shape of the first overlapping region DB1 may be a broken line, and the bending angle β of the first overlapping region DB1 may be greater than or equal to 70° and less than 180°. Figure 2 As shown, the bending angle β of the first overlapping region DB1 can be set to 70°, and an included angle θ1 between the first zigzag overlapping region DB1 and the column direction F1 of the sub-pixel spx can be set to 20°, and another included angle θ2 between the first zigzag overlapping region DB1 and the column direction F1 of the sub-pixel spx can be set to 90°. In this way, the first overlapping region DB1 and the column direction F1 form a right triangle.

[0065] For example, Figure 5 As shown, the bending angle β of the first overlapping region DB1 can be set to an angle greater than 90° and less than 180°. For example, β can be set to 114°, and an included angle θ1 between the first zigzag overlapping region DB1 and the column direction F1 of the sub-pixel spx can be set to 22°, and another included angle θ2 between the first zigzag overlapping region DB1 and the column direction F1 of the sub-pixel spx can be set to 22°. In this way, the first overlapping region DB1 and the column direction F1 form an isosceles triangle.

[0066] Of course, in practical applications, the specific values ​​of β, θ1 and θ2 can be designed according to the needs of the practical application and are not limited here.

[0067] Liquid crystal display (LCD) panels have features such as a thin and light appearance, energy saving, and no radiation, and are widely used. The working principle of the LCD panel is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference across the liquid crystal layer, thereby changing the light transmittance of the liquid crystal layer to display images. In a specific implementation, the display panel in the embodiment of the present invention can be a liquid crystal display panel. For example, the display panel may include an opposing substrate arranged opposite to the base substrate 100, and a liquid crystal layer encapsulated between the base substrate 100 and the opposing substrate. A color resist layer located in each sub-pixel spx may be provided on the opposing substrate, and the color of the color resist layer is consistent with the luminous color of the sub-pixel spx. In addition, the sub-pixel spx may include a pixel electrode located on the base substrate 100 and a thin film transistor electrically connected to the pixel electrode. Of course, the base substrate 100 is also provided with a scan line for transmitting a gate scan signal and a data line for transmitting a data signal. In this way, a gate scan signal is input to the TFT through the scan line to control the conduction of the TFT, thereby inputting the data signal transmitted on the data line into the pixel electrode, inputting a voltage to the pixel electrode, and inputting a common voltage to the common electrode to drive the liquid crystal molecules to rotate to display an image.

[0068] In specific implementation, in the embodiment of the present invention, as Figures 2 to 7b As shown, the display panel may further include: a first insulating layer located between the data lines (e.g., D1 and D2) and the base substrate 100; a plurality of auxiliary lines FS located between the first insulating layer and the base substrate 100; and a plurality of scan lines (e.g., GA1 and GA2) located on the same layer as the auxiliary lines FS and spaced apart; a second insulating layer located on the side of the data lines (e.g., D1 and D2) facing away from the base substrate 100; a common electrode layer 210 located on the side of the second insulating layer facing away from the base substrate 100; a third insulating layer located on the side of the common electrode layer 210 facing away from the base substrate 100; and a transparent pixel electrode layer 220 located on the side of the third insulating layer facing away from the base substrate 100. That is, the common electrode layer 210 is located between the second insulating layer and the transparent pixel electrode layer 220, and the third insulating layer is located between the common electrode layer 210 and the transparent pixel electrode layer 220.

[0069] In specific implementation, in the embodiment of the present invention, as Figures 1 to 7bAs shown, the multiple signal lines 110 may include multiple data lines (e.g., D1 and D2); one data line is provided for each column of sub-pixels spx. Furthermore, each data line includes a first sub-data line D01 and a second sub-data line D02 that are electrically connected to each other. The orthographic projection of the first sub-data line D01 on the substrate 100 and the orthographic projection of the effective light-emitting area FG of the corresponding sub-pixel spx on the substrate 100 form a first overlapping region DB1. The orthographic projection of the second sub-data line D02 on the substrate 100 does not overlap with the orthographic projections of each effective light-emitting area FG on the substrate 100. Exemplarily, the orthographic projection of the second sub-data line D02 on the substrate 100 is located between the orthographic projections of adjacent effective light-emitting areas FG on the substrate 100. In this way, data lines can be reused as signal lines 110 that form light interference, which can reduce the difficulty of process manufacturing and the thickness of the display panel.

[0070] In specific implementation, in the embodiment of the present invention, as Figures 2 to 7b As shown, the auxiliary line FS extends along the column direction F1 of the sub-pixel spx; one sub-pixel spx corresponds to one auxiliary line FS. The orthographic projection of the auxiliary line FS on the substrate 100 does not overlap with the orthographic projection of the effective light-emitting area FG on the substrate 100. Moreover, for the same sub-pixel spx, the orthographic projection of the auxiliary line FS on the substrate 100 and the orthographic projection of the first sub-data line D01 on the substrate 100 form a triangle; the bending angle is the angle between the first overlapping area DB1 and the side facing the auxiliary line FS. For example, as Figure 2 and Figure 4a As shown, the triangle formed by the orthographic projection of the auxiliary line FS on the base substrate 100 and the orthographic projection of the first sub-data line D01 on the base substrate 100 is a right triangle. Figure 5 and Figure 7a As shown, the triangle formed by the orthographic projection of the auxiliary line FS on the base substrate 100 and the orthographic projection of the first sub-data line D01 on the base substrate 100 is an isosceles triangle.

[0071] In specific implementation, in the embodiment of the present invention, as Figures 2 to 7bAs shown, the scan lines extend along the row direction F2 of the sub-pixels spx; one row of sub-pixels spx corresponds to two scan lines (such as GA1 and GA2). Moreover, between the orthographic projections of the scan lines corresponding to two adjacent rows of sub-pixels spx on the substrate substrate 100, an orthographic projection of the auxiliary lines FS corresponding to one row of sub-pixels spx on the substrate substrate 100 is provided. Exemplarily, the orthographic projections of the scan lines on the substrate substrate 100 are located between the orthographic projections of the effective light-emitting areas FG of the two adjacent rows of sub-pixels spx on the substrate substrate 100. Furthermore, the two scan lines corresponding to the sub-pixels spx in the same row are respectively located on both sides of the sub-pixels spx in the corresponding row. For example, one scan line (such as GA1) of the two scan lines corresponding to the sub-pixels spx in the same row is electrically connected to the thin film transistors in the odd-numbered columns of the sub-pixels spx in the row, and the other scan line (such as GA2) is electrically connected to the thin film transistors in the even-numbered columns of the sub-pixels spx in the row. The scan line (such as GA1) electrically connected to the thin film transistors in the odd-numbered sub-pixels spx in the row can be set above the row, and the scan line (such as GA2) electrically connected to the thin film transistors in the even-numbered sub-pixels spx in the row can be set below the row.

[0072] In specific implementation, in the embodiment of the present invention, as Figures 1 to 7b As shown, the plurality of data lines may include a plurality of first-category data lines D1 and a plurality of second-category data lines D2; the first-category data lines D1 and the second-category data lines D2 are alternately arranged along the row direction F2 of the sub-pixels spx. The first-category data lines D1 are electrically connected to the thin-film transistors TF in the sub-pixels spx, while the second-category data lines D2 are not electrically connected to the thin-film transistors TF in the sub-pixels spx. For example, the first-category data lines D1 may be provided for the sub-pixels spx in odd-numbered columns, and the second-category data lines D2 may be provided for the sub-pixels spx in even-numbered columns. Alternatively, the second-category data lines D2 may be provided for the sub-pixels spx in odd-numbered columns, and the first-category data lines D1 may be provided for the sub-pixels spx in even-numbered columns.

[0073] In specific implementation, in the embodiment of the present invention, as Figures 1 to 7b As shown, two adjacent columns of sub-pixels spx are formed into a column group, each two adjacent column groups correspond to a first-type data line D1, and one column group corresponds to a second data line; wherein, the odd-numbered rows of sub-pixels spx of the first column group in each two adjacent column groups are all electrically connected to the corresponding first-type data line D1, and the even-numbered rows of sub-pixels spx of the second column group are all electrically connected to the corresponding first-type data line D1.

[0074] Exemplarily, the first column of sub-pixels spx and the second column of sub-pixels spx form a column group LZ1, the third column of sub-pixels spx and the fourth column of sub-pixels spx form a column group LZ2, and the fifth column of sub-pixels spx and the sixth column of sub-pixels spx form a column group LZ3. Column group LZ1 corresponds to the first second-category data line D2, column group LZ2 corresponds to the second second-category data line D2, and column group LZ3 corresponds to the third second-category data line D2. Adjacent column groups LZ1 and LZ2 correspond to the first first-category data line D1, and adjacent column groups LZ2 and LZ3 correspond to the second first-category data line D1. In adjacent column groups LZ1 and LZ2, column group LZ1 serves as the first column group and column group LZ2 serves as the second column group. The odd-numbered sub-pixels spx in column group LZ1 are all electrically connected to the corresponding first-category data line D1, and the even-numbered sub-pixels spx in column group LZ2 are all electrically connected to the corresponding first-category data line D1. In adjacent column groups LZ2 and LZ3, column group LZ2 serves as the first column group and column group LZ3 serves as the second column group. Sub-pixels spx in odd-numbered rows of column group LZ2 are all electrically connected to corresponding first-type data lines D1, while sub-pixels spx in even-numbered rows of column group LZ3 are all electrically connected to corresponding first-type data lines D1. The rest of the process is similar and can be deduced by analogy, which is not further elaborated here.

[0075] Since the first type data line D1 is electrically connected to the thin film transistor TF in the sub-pixel spx, and the first type data line D1 can transmit data signals, in order to avoid the first type data line D1 and the common electrode layer 210 from interfering with each other and causing display abnormality, in a specific implementation, in an embodiment of the present invention, as shown in FIG. Figures 1 to 7b As shown, the common electrode layer 210 may include a plurality of common electrode portions 211 spaced apart from one another. The orthographic projections of the common electrode portions 211 on the base substrate 100 may not overlap with the orthographic projections of the first-type data lines D1 on the base substrate 100. This minimizes the amount of facing area between the first-type data lines D1 and the common electrode layer 210, thereby preventing the formation of coupling capacitance between the first-type data lines D1 and the common electrode layer 210 and signal interference.

[0076] Since the scan line is electrically connected to the thin film transistor in the sub-pixel spx, and the scan line can transmit the gate scan signal, in order to avoid the scan line and the common electrode layer 210 from interfering with each other and causing display abnormality, in the embodiment of the present invention, Figures 1 to 7b As shown, the orthographic projection of the common electrode portion 211 on the base substrate 100 and the orthographic projection of the scan line on the base substrate 100 can be made not to overlap. This can minimize the amount of facing area between the scan line and the common electrode layer 210, thereby preventing the formation of coupling capacitance between the scan line and the common electrode layer 210 and causing signal interference.

[0077] Since the second type data line D2 is not electrically connected to the thin film transistor in the sub-pixel spx, in order to make the area of ​​the common electrode portion 211 as large as possible, in the specific implementation, in the embodiment of the present invention, as shown in FIG. Figures 1 to 7b As shown, the orthographic projection of the common electrode portion 211 on the base substrate 100 can overlap with the orthographic projection of the second-type data line D2 on the base substrate 100. Furthermore, the orthographic projection of the common electrode portion 211 on the base substrate 100 can overlap with the orthographic projection of the first sub-data line D01 in the second-type data line D2 on the base substrate 100.

[0078] In specific implementation, in the embodiment of the present invention, as Figures 1 to 7b As shown, one second-type data line can correspond to one column of common electrode portions 211. Furthermore, when the common electrode layer 210 is located between the second insulating layer and the transparent pixel electrode layer 220, the second-type data line D2 is electrically connected to the corresponding common electrode portion 211 via a second via hole penetrating the second insulating layer. In this manner, the second-type data line D2 can electrically connect the spaced common electrode portions 211, and a common voltage can be transmitted to the electrically connected common electrode portions 211 via the second-type data line D2. Because the second-type data line D2 and the common electrode portion 211 transmit the same voltage, signal interference between the second-type data line D2 and the common electrode portion 211 can be avoided.

[0079] In specific implementation, in the embodiment of the present invention, as Figures 1 to 7b As shown, the display panel may further include a plurality of common electrode connection lines GS disposed in the same layer as the scan lines and spaced apart from each other. The common electrode connection lines GS extend along the row direction F2 of the sub-pixels spx, and the orthographic projections of the common electrode connection lines GS on the base substrate 100 do not overlap with the orthographic projections of the effective light-emitting areas FG on the base substrate 100. The common electrode connection lines GS are electrically connected to each of the second-type data lines D2 via first vias penetrating the first insulating layer. This allows the common electrode connection lines GS, the second-type data lines D2, and the common electrode portion 211 to be electrically connected in parallel, thereby further reducing resistance.

[0080] Exemplarily, a row of sub-pixels spx corresponds to a common electrode connection line GS, and the common electrode connection line GS is located between the corresponding row of sub-pixels spx and the scan line arranged below the row of sub-pixels spx. Further, a common electrode connection line GS corresponds to a row of common electrode portions 211.

[0081] For example, the orthographic projection of the second via on the base substrate 100 may be located inside the orthographic projection of the first via on the base substrate 100. Alternatively, the orthographic projection of the first via on the base substrate 100 may be located inside the orthographic projection of the second via on the base substrate 100. Alternatively, the orthographic projection of the second via on the base substrate 100 may only partially overlap with the orthographic projection of the first via on the base substrate 100. Alternatively, the orthographic projection of the second via on the base substrate 100 may not overlap with the orthographic projection of the first via on the base substrate 100.

[0082] In specific implementation, in the embodiment of the present invention, as Figures 1 to 7b As shown, the transparent pixel electrode layer 220 includes a plurality of pixel electrodes 221 spaced apart from each other; wherein, each sub-pixel spx includes one pixel electrode 221. The orthographic projection of the pixel electrode 221 on the substrate 100 overlaps with the orthographic projection of the common electrode layer 210 on the substrate 100. For example, the pixel electrode 221 has a hollow region, and the orthographic projection of the pixel electrode 221 on the substrate 100 overlaps with the orthographic projection of the common electrode layer 210 on the substrate 100. In this way, an electric field can be formed by the pixel electrodes and the common electrode layer 210 to drive the deflection of the liquid crystal molecules.

[0083] It should be noted that a gate insulating layer may be provided between the layer where the scan lines are located and the base substrate, and an active layer of a thin film transistor may be provided between the gate insulating layer and the base substrate.

[0084] The embodiment of the present invention provides some display panels, the structural diagram of which is as follows: Figure 8 and Figure 9 As shown, the embodiment described above is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0085] In a specific implementation, in an embodiment of the present invention, the common electrode layer 210 is located between the layer where the auxiliary lines FS are located and the base substrate 100, and a third insulating layer is located between the common electrode layer 210 and the layer where the auxiliary lines FS are located. Specifically, the display panel may include: a first insulating layer located between the data lines and the base substrate 100; a plurality of auxiliary lines FS located between the first insulating layer and the base substrate 100; and a plurality of scan lines spaced apart from each other and located on the same layer as the auxiliary lines FS; the common electrode layer 210 located between the layer where the auxiliary lines FS are located and the base substrate 100; a third insulating layer located between the common electrode layer 210 and the layer where the auxiliary lines FS are located; a second insulating layer located on the side of the data lines facing away from the base substrate 100; and a transparent pixel electrode layer 220 located on the side of the second insulating layer facing away from the base substrate 100.

[0086] In specific implementation, in an embodiment of the present invention, when the common electrode layer 210 is located between the layer where the auxiliary line FS is located and the base substrate 100, the second-type data line D2 is electrically connected to the corresponding common electrode portion 211 through a third via hole penetrating the first insulating layer and the third insulating layer.

[0087] In a specific implementation, in an embodiment of the present invention, the third via hole may include a third transfer hole and a third conductive hole; wherein the third transfer hole passes through the first insulating layer, and the third conductive hole passes through the third insulating layer. The second-type data line D2 is electrically connected to the common electrode connection line GS through the third transfer hole, and the common electrode connection line GS is electrically connected to the common electrode portion 211 through the third conductive hole.

[0088] For example, the orthographic projection of the third transfer hole on the base substrate 100 may be located inside the orthographic projection of the third conductive via on the base substrate 100. Alternatively, the orthographic projection of the third conductive via on the base substrate 100 may be located inside the orthographic projection of the third transfer hole on the base substrate 100. Alternatively, the orthographic projection of the third transfer hole on the base substrate 100 may only partially overlap with the orthographic projection of the third conductive via on the base substrate 100. Alternatively, the orthographic projection of the third transfer hole on the base substrate 100 may not overlap with the orthographic projection of the third conductive via on the base substrate 100.

[0089] Since there is only one second insulating layer between the layer where the data line is located and the transparent pixel electrode layer 220, the data line will cause signal interference to the pixel electrode in the transparent pixel electrode layer 220. In order to reduce signal interference, in the specific implementation, in the embodiment of the present invention, Figure 8 and Figure 9 As shown, the pixel electrode 221 may include: a first sub-pixel electrode 2211, a second sub-pixel electrode 2212, and an electrode connecting portion 2213; wherein the first sub-pixel electrode 2211 and the second sub-pixel electrode 2212 are spaced apart from each other, and the first sub-pixel electrode 2211 and the second sub-pixel electrode 2212 in the same pixel electrode 221 are electrically connected via the electrode connecting portion 2213. In addition, each data line (for example, D1, D2, Figure 8 The orthographic projection of D1 on the substrate 100 does not overlap with the orthographic projections of the first sub-pixel electrodes 2211 and the second sub-pixel electrodes 2212 on the substrate 100. This minimizes the facing area between the data line and the pixel electrode, thereby reducing coupling capacitance and signal interference, thereby improving display quality.

[0090] It should be noted that a first gate insulating layer may be provided between the common electrode layer and the layer where the scan line is located, an active layer of a thin film transistor may be provided between the first gate insulating layer and the layer where the scan line is located, and a second gate insulating layer may be provided between the active layer of the thin film transistor and the layer where the scan line is located.

[0091] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel described above. The principles of this display device are similar to those of the aforementioned display panel, and thus the implementation of this display device can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated here.

[0092] In specific implementation, in an embodiment of the present invention, the display device may further include: a grating located on the light-emitting side of the display panel, wherein the grating is used to enable the display device to achieve a 3D display effect, thereby enabling the display device in the embodiment of the present invention to achieve a 3D display effect.

[0093] The display panel and display device provided by embodiments of the present invention utilize a non-linear first overlapping region between the orthographic projection of each effective light-emitting area on the substrate and the orthographic projection of the signal trace on the substrate. This allows light emitted from the effective light-emitting area to interfere with the signal trace in the first overlapping region. Consequently, when the display panel is used in a 3D display device, moiré patterns can be reduced, enhancing display quality.

[0094] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, characterized in that: include: A base substrate, the base substrate comprising a plurality of sub-pixels and a plurality of signal traces; wherein each of the sub-pixels comprises an effective light-emitting area; The orthographic projection of each effective light-emitting area on the base substrate and the orthographic projection of the signal trace on the base substrate have a first overlapping area; and the shape of the first overlapping area is non-linear; The pixel electrode includes: a first sub-pixel electrode, a second sub-pixel electrode, and an electrode connecting portion; wherein the first sub-pixel electrode and the second sub-pixel electrode are spaced apart from each other, and the first sub-pixel electrode and the second sub-pixel electrode in the same pixel electrode are electrically connected via the electrode connecting portion, and an orthographic projection of each data line on a base substrate does not overlap with an orthographic projection of each first sub-pixel electrode and each second sub-pixel electrode on the base substrate; The second sub-pixel electrode includes a first edge and a second edge close to the data line, the first sub-pixel electrode includes a third edge and a fourth edge close to the data line, the data line includes a first sub-data line, the first sub-data line includes a first data line portion and a second data line portion, the extension direction of the first data line portion is the same as that of the first edge and the third edge, the extension direction of the second data line portion is the same as that of the second edge and the fourth edge, and the first sub-data line is in a zigzag shape.

2. The display panel according to claim 1, wherein The first overlapping area is in a broken line shape, and a bending angle of the first overlapping area is greater than or equal to 70° and less than 180°.

3. The display panel according to claim 2, wherein: The plurality of signal lines include a plurality of data lines; one data line is correspondingly provided for one column of sub-pixels; Each of the data lines includes a first sub-data line and a second sub-data line electrically connected to each other; The orthographic projection of the first sub-data line on the base substrate and the orthographic projection of the effective light-emitting area of ​​the corresponding sub-pixel on the base substrate form the first overlapping area; The orthographic projection of the second sub-data line on the base substrate does not overlap with the orthographic projection of each effective light-emitting area on the base substrate.

4. The display panel according to claim 3, wherein: The display panel further includes: a first insulating layer located between the data line and the base substrate, and a plurality of auxiliary lines located between the first insulating layer and the base substrate; wherein the auxiliary lines extend along a column direction of the sub-pixels; and each sub-pixel corresponds to one auxiliary line; The orthographic projection of the auxiliary line on the base substrate does not overlap with the orthographic projection of the effective light-emitting area on the base substrate; For the same sub-pixel, the orthographic projection of the auxiliary line on the base substrate and the orthographic projection of the first sub-data line on the base substrate form a triangle; the bending angle is the angle between the first overlapping area and the side facing the auxiliary line.

5. The display panel according to claim 4, wherein: The display panel further includes: a second insulating layer located on a side of the data line facing away from the base substrate, and a transparent pixel electrode layer located on a side of the second insulating layer facing away from the base substrate; The transparent pixel electrode layer includes a plurality of pixel electrodes spaced apart from each other; wherein one sub-pixel includes one pixel electrode.

6. The display panel according to claim 5, wherein: The display panel further includes: a common electrode layer and a third insulating layer; The common electrode layer is located between the second insulating layer and the transparent pixel electrode layer, and the third insulating layer is located between the common electrode layer and the transparent pixel electrode layer; or, The common electrode layer is located between the layer where the auxiliary lines are located and the base substrate, and the third insulating layer is located between the common electrode layer and the layer where the auxiliary lines are located.

7. The display panel according to claim 6, wherein: The plurality of data lines include a plurality of first-type data lines and a plurality of second-type data lines; the first-type data lines and the second-type data lines are alternately arranged along a row direction of the sub-pixels; Two adjacent columns of sub-pixels form a column group, and each two adjacent column groups correspond to one first-category data line; wherein, the odd-numbered rows of sub-pixels in the first column group of each two adjacent column groups are all electrically connected to the corresponding first-category data lines, and the even-numbered rows of sub-pixels in the second column group are all electrically connected to the corresponding first-category data lines.

8. The display panel according to claim 7, wherein: The common electrode layer includes a plurality of common electrode portions spaced apart from each other; The orthographic projection of the common electrode portion on the base substrate does not overlap with the orthographic projection of the first type of data line on the base substrate; and / or, The orthographic projection of the common electrode portion on the base substrate does not overlap with the orthographic projection of the scanning line on the base substrate; and / or, An orthographic projection of the common electrode portion on the base substrate overlaps with an orthographic projection of the second-type data line on the base substrate.

9. The display panel according to claim 8, wherein: One column group corresponds to one second data line, and one second data line corresponds to one column of common electrode portions; When the common electrode layer is located between the second insulating layer and the transparent pixel electrode layer, the second-type data line is electrically connected to the corresponding common electrode portion through a second via hole penetrating the second insulating layer.

10. The display panel according to claim 9, wherein: The display panel further includes a common electrode connection line that is in the same layer as the scan line and is spaced apart from the scan line; wherein the common electrode connection line extends along the row direction of the sub-pixels, and an orthographic projection of the common electrode connection line on the base substrate does not overlap with an orthographic projection of the effective light-emitting area on the base substrate; The common electrode connection line is electrically connected to each of the second-type data lines through a first via hole penetrating the first insulating layer.

11. The display panel according to claim 8, wherein One column group corresponds to one second data line, and one second data line corresponds to one column of common electrode portions; When the common electrode layer is located between the layer where the auxiliary lines are located and the base substrate, the second-type data lines are electrically connected to the corresponding common electrode parts through third via holes penetrating the first insulating layer and the third insulating layer.

12. The display panel according to claim 11, wherein: The display panel further includes a common electrode connection line that is in the same layer as the scan line and is spaced apart from the scan line; wherein the common electrode connection line extends along the row direction of the sub-pixels, and an orthographic projection of the common electrode connection line on the base substrate does not overlap with an orthographic projection of the effective light-emitting area on the base substrate; The third via hole includes a third transfer hole and a third conductive hole; wherein the third transfer hole passes through the first insulating layer, and the third conductive hole passes through the third insulating layer; The second-type data line is electrically connected to the common electrode connection line through the third transfer hole, and the common electrode connection line is electrically connected to the common electrode portion through the third conductive hole.

13. A display device, characterized in that: The device comprises a display panel as claimed in any one of claims 1 to 12.

14. The display device according to claim 13, wherein Also includes: A grating is located on the light-emitting side of the display panel.

Images