A reliability optimization system and method for a floating point processing unit

Abstract

The present invention provides a reliability optimization system and method for a floating-point processing unit. Two operands are preprocessed before an exponent detection prediction module. When performing addition and multiplication operations, the sign bit of the addend or multiplicand remains unchanged. When performing a subtraction operation, the sign of the minuend is inverted. Then, the operation code and the sign bit, the exponent part, and the mantissa part of the operand are respectively sent to the exponent detection prediction module, and the exponent prediction is performed through the module. The exponent detection module outputs the smaller of the two possible exponents to an error detection unit. The error detection unit compares the output result of the exponent detection prediction module and the output result incremented by +1 with the exponent of the floating-point processing unit operation result at the same time. Only when both comparisons fail will a signal indicating an error in the operation result be output. The method for detecting and predicting floating-point exponents of the present invention can not only detect transient errors in a larger range, but also has a very low overhead.

Description

Technical Field

[0001] The present invention relates to the field of reliability of floating point processing units supporting addition, subtraction and multiplication operations, and more specifically, to a novel floating point processing unit error detection method, which can effectively improve the floating point unit operation reliability problem. Background Art

[0002] As the performance of floating-point processing units (FPUs) improves, the size of related integrated circuits decreases, the power supply voltage decreases and the frequency increases, FPUs become more sensitive to various noise interferences such as electromagnetic interference, crosstalk and various radiations. Therefore, these interferences are very likely to cause the FPU circuit to operate incorrectly, greatly reducing the reliability of the FPU. In the scope of digital integrated circuits to which FPUs belong, the impact of single-particle effects on circuit reliability is particularly important. The main errors caused by single-particle effects are soft errors and hard errors. Hard errors are caused by irrecoverable faults in circuit units and are permanent errors; while soft errors are transient errors caused by noise interference or high-energy particle impacts and are recoverable errors. When particles bombard integrated circuits, electron / hole pairs are formed on the path they pass through. These electron / hole pairs drift and diffuse under the action of electric field forces, and are eventually collected by electrodes, generating transient currents and forming voltage pulses at the bombardment nodes, which may cause soft errors. Studies have shown that 80-90% of failures in computer systems are caused by transient faults, which means that the main faults in FPUs are caused by soft errors. Therefore, reducing the sensitivity to soft errors in digital circuits and protecting circuits from faults have become research hotspots.

[0003] At present, there are further studies on error detection / correction on the FPU data path. Common methods include replication, triple module redundancy (TMR) technology, etc. Although the method of replicating the floating point processing unit is simple and applicable to all designs, the >100% area overhead and the additional delay caused by the method make this method not very attractive. Triple module redundancy (TMR) has the same properties as replication. Although triple module redundancy (TMR) also has the advantage of error correction, the >200% area overhead is also daunting. Therefore, these methods have great limitations when designing commercial floating point processing units. Summary of the invention

[0004] In view of this, the problem to be solved by the present invention is the limitations caused by the large area overhead, inflexible application and other reasons of the existing floating point processing unit error detection and correction method.

[0005] Based on the above purpose, the present invention proposes a reliability optimization system for a floating point processing unit, comprising:

[0006] Data preprocessing module, index detection prediction module and error detection unit;

[0007] The data preprocessing module is used to simultaneously receive the data input into the floating point processing unit and perform preprocessing;

[0008] The index detection and prediction module is used to receive the preprocessing result and perform index prediction;

[0009] The error detection unit is used to receive the result of the index prediction and the FPU calculation index obtained by the floating point processing unit operation, and compare the result of the index prediction with the FPU calculation index to determine whether the operation result of the floating point processing unit is wrong.

[0010] Furthermore, the data input into the floating point processing unit includes two operands and an operation code.

[0011] Furthermore, the pre-processing process includes:

[0012] When two operands are added or multiplied, the sign bit of the addend or multiplicand remains unchanged. During the subtraction operation, the sign of the minuend is inverted to convert the subtraction operation into an addition operation. The operation code and the sign bit, exponent part and mantissa part of the operand are respectively input into the exponent detection prediction module.

[0013] Furthermore, the exponent detection prediction module transmits the smaller of the two possible exponents as output to the error detection unit.

[0014] Furthermore, the error detection unit compares the output result of the exponential detection prediction module and the result of the output result incremented by one with the exponent of the floating-point processing unit operation result at the same time, and outputs a signal indicating that the operation result of the floating-point operation unit is wrong when both comparisons fail, otherwise, does not output a signal indicating that the operation result of the floating-point operation unit is wrong.

[0015] Furthermore, in the multiplication operation of the exponent detection prediction module, an addition operation is performed on the exponent parts of the two input operands;

[0016] In the addition and subtraction operations of the exponent detection and prediction module, when the signs of the two input operands are the same, the exponent takes the maximum exponent value or the maximum exponent value plus 1; when the signs of the two input operands are different, if the exponents are the same or the exponents differ by 1, a copy method is used for prediction; if the larger exponent and the smaller exponent differ by >1, the output exponent is the larger exponent itself or the larger exponent minus one.

[0017] Furthermore, the index detection and prediction module further includes three data selectors, wherein:

[0018] A first data selector, used for selecting the exponent result of the addition and subtraction operation according to the result of the XOR of the two operand signs as a control signal;

[0019] A second data selector is used to select the above-mentioned multiplication operation and addition and subtraction operation according to the operation code;

[0020] The third data selector is used to determine the final output result according to the special value judgment result.

[0021] Based on the above purpose, the present invention also proposes a reliability optimization method for a floating point processing unit, comprising:

[0022] receiving data input into the floating point processing unit and performing preprocessing;

[0023] Receiving the preprocessing result and performing index prediction;

[0024] The result of the index prediction and the FPU calculation index obtained by the floating point processing unit operation are received, and the result of the index prediction and the FPU calculation index are compared to determine whether the operation result of the floating point processing unit is wrong.

[0025] In general, the advantages of the present invention and the experience it brings to users are:

[0026] 1. A method for predicting the exponential part of the output result of a floating-point processing unit is proposed. The reliability of the floating-point processing unit is optimized by comparing the predicted exponent with the exponent of the actual floating-point processing unit output result.

[0027] 2. The exponential detection prediction module provided by the present invention is parallel to the floating-point processing unit and will not affect the operation of the floating-point processing unit in terms of delay and other aspects.

[0028] 3. The method provided by the present invention is simple to operate, has a fast calculation speed, and has a very low area cost, thus overcoming the cost problem in commercial design and being applicable to production. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present invention and should not be regarded as limiting the scope of the present invention.

[0030] Figure 1 It is a schematic diagram of the overall structure of the reliability optimization design of the floating point processing unit (FPU) according to an embodiment of the present invention.

[0031] Figure 2It is a structural schematic diagram of a data preprocessing module of a reliability optimization design according to an embodiment of the present invention.

[0032] Figure 3 It is a structural diagram of an index detection prediction module of a reliability optimization design according to an embodiment of the present invention.

[0033] Figure 4 It is a structural schematic diagram of an error detection unit module of a reliability optimization design according to an embodiment of the present invention.

[0034] Figure 5 The present invention is a flowchart of a reliability optimization method for a floating-point processing unit according to an embodiment of the present invention.

[0035] Figure 6 A schematic diagram showing the structure of an electronic device provided by an embodiment of the present invention is shown;

[0036] Figure 7 A schematic diagram of a storage medium provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0038] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] To achieve the above object, the present invention provides a design scheme for detecting and predicting the exponential part to improve reliability, using a parallel structure, such as Figure 1 As shown, it includes three parts: a data preprocessing module, an exponent detection and prediction module, and an error detection unit. While the floating-point processing unit is inputting data Opcode, Opa, and Opb, the data Opcode, Opa, and Opb are also sent to the data preprocessing module, and after processing, the data is sent to the exponent detection and prediction module, and the exponent prediction is performed by the module. The predicted index is compared with the exponent calculated by the floating-point processing unit in the error detection unit. The present invention is applicable to both single-precision and double-precision floating-point processing units, and the present invention is described by taking a double-precision floating-point processing unit as an example.

[0040] A. Data preprocessing module: Figure 2As shown, the data Opcode, Opa, and Opb are preprocessed. When performing addition and multiplication operations, the sign bit of the addend or the multiplicand remains unchanged. During the subtraction operation, the sign of the minuend is inverted, and the subtraction operation is converted into an addition operation. Then, the sign bits Signa and Signb of the opcode and the operand, the exponent parts Expa and Expb, and the mantissa parts Mana and Manb are respectively sent to the exponent detection prediction module.

[0041] B. Figure 3 As shown, in the index detection prediction module, the following situations are considered:

[0042] 1. Multiplication operation:

[0043] Performs addition operation on the exponent parts of the two input operands Expa and Expb.

[0044] 2. Addition / subtraction operations:

[0045] Since preprocessing has been performed before the data is input into the index detection prediction module, the situations discussed below are all performed when the two input operands are regarded as addition operations.

[0046] 1. When the signs of the two input operands are the same, the exponent may take the maximum exponent value (the maximum exponent is selected by the exponent comparator), or the maximum exponent value may be increased by 1, such as:

[0047] operand Decimal representation Sign bit index mantissa A 5.5 0 11’b100 0000 0001 52’b0110 0000....0000 B 1.875 0 11’b011 1111 1111 52’b1110 0000....0000 C 7.875 0 11’b100 0000 0001 52’b1111 1000....0000 D 7.375 0 11’b100 0000 0001 52’b1101 1000....0000 E 9.75 0 11’b100 0000 0010 52’b0011 1000....0000

[0048] ① In the case of A+B=D, the exponent of the output result D is the larger exponent of A and B because the mantissa does not overflow.

[0049] ② In the case of B+C=E, the exponent of the output result E is the larger exponent between the two input exponents A and B + 1 due to the overflow of the mantissa.

[0050] 2. When the two symbols are different:

[0051] (1) When the indices are the same or the difference between the indices is 1, a replication method is used for prediction. The replication method here can use the prior art mentioned in the background technology, which will not be described in detail here.

[0052] (2) When the difference between the larger exponent and the smaller exponent is greater than 1, the output exponent may be the larger exponent itself or the larger exponent minus 1, such as:

[0053] operand Decimal representation Sign bit index mantissa A 5.5 0 11’b100 0000 0001 52’b0110 0000....0000 B -1.875 1 11’b011 1111 1111 52’b1110 0000....0000 C -0.125 1 11’b011 1111 1100 52’b0000 0000....0000 D 3.625 0 11’b100 0000 0000 52’b1101 0000....0000 E 5.375 0 11’b100 0000 0001 52’b0101 1100....0000

[0054] ①A+B=D. The exponent of D is the larger exponent of A and B (here the exponent of A) - 1.

[0055] ②A+C=E. The exponent of E is the larger exponent of A and B (here it is the exponent of A).

[0056] Mux1: selects the exponential results of 1. and 2. above based on the result of XOR of the two operands as a control signal.

[0057] Mux2: selects between the above two cases (a) and (b) according to the operation code Opcode.

[0058] Mux3: Determine the final output result based on the special value judgment result.

[0059] C. In the error detection unit, such as Figure 4 As shown, the FPU calculated exponent result is compared with the result of the exponent detection prediction module. Since the predicted exponent may differ by 1, the exponent detection prediction module selects the smaller of the two possible exponent results. Therefore, in this module, the FPU output exponent result should be compared with the exponent detection prediction exponent result + 1. Only when the output results of comparator 1 and comparator 2 are both incorrect, the FPU output result will be judged to be incorrect.

[0060] Therefore, the present invention improves the reliability of the floating-point processing unit by detecting the exponent part of the input operand, including an exponent detection prediction module and an error detection unit, and supports the reliability optimization of the addition, subtraction and multiplication operations of the floating-point unit. Before the exponent detection prediction module, the two operands are preprocessed, and when performing addition and multiplication operations, the sign bit of the addend or the multiplicand remains unchanged. When performing subtraction operations, the sign of the minuend is inverted, and the subtraction operations are converted into addition operations. Then, the operation code and the sign bit, the exponent part and the mantissa part of the operand are respectively sent to the exponent detection prediction module, and the exponent prediction is performed through the module. The exponent detection prediction module outputs the smaller of the two possible exponents as an output to the error detection unit, and the error detection unit compares the input of the exponent detection prediction module with the exponent of the floating-point processing unit operation result, and in order to ensure the correctness of the error detection unit, the floating-point processing unit (FPU) operation result is also compared with the incremented +1 result of the detection prediction module output result, and only when both comparisons fail will the signal of the operation result error be output. The method for detecting and predicting floating-point exponents of the present invention can not only detect transient errors in a larger range, but also has a very low overhead.

[0061] like Figure 5 As shown, the present invention also provides a reliability optimization method for a floating point processing unit, such as Figure 5 As shown, the method includes:

[0062] S101, receiving data input into the floating point processing unit and performing preprocessing;

[0063] S102, receiving the preprocessing result and performing index prediction;

[0064] S103, receiving the result of the index prediction and the FPU calculation index obtained by the floating point processing unit operation, and comparing the result of the index prediction with the FPU calculation index to determine whether the operation result of the floating point processing unit is wrong.

[0065] The reliability optimization system for a floating-point processing unit provided by the above-mentioned embodiment of the present invention and the reliability optimization method for a floating-point processing unit provided by the embodiment of the present invention are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0066] The embodiment of the present invention further provides an electronic device corresponding to the reliability optimization method of a floating point processing unit provided in the above embodiment, so as to execute the reliability optimization method of a floating point processing unit.

[0067] Please refer to Figure 6 , which shows a schematic diagram of an electronic device provided by some embodiments of the present invention. Figure 6 As shown, the electronic device 2 includes: a processor 200, a memory 201, a bus 202 and a communication interface 203, wherein the processor 200, the communication interface 203 and the memory 201 are connected via the bus 202; the memory 201 stores a computer program that can be run on the processor 200, and when the processor 200 runs the computer program, the reliability optimization method of the floating-point processing unit provided in any of the aforementioned embodiments of the present invention is executed.

[0068] The memory 201 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 203 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0069] The bus 202 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs, and the processor 200 executes the programs after receiving execution instructions. The reliability optimization method of the floating-point processing unit disclosed in any implementation of the above-mentioned embodiment of the present invention may be applied to the processor 200, or implemented by the processor 200.

[0070] The processor 200 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 200 or the instruction in the form of software. The above processor 200 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiment of the present invention can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor can be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201 and completes the steps of the above method in combination with its hardware.

[0071] The electronic device provided by the embodiment of the present invention and the reliability optimization method of the floating-point processing unit provided by the embodiment of the present invention are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented therein.

[0072] The embodiment of the present invention also provides a computer-readable storage medium corresponding to the reliability optimization method of the floating-point processing unit provided in the above embodiment, please refer to Figure 7 The computer-readable storage medium shown is a CD 30 on which a computer program (ie, a program product) is stored. When the computer program is run by a processor, the reliability optimization method of the floating-point processing unit provided in any of the aforementioned embodiments will be executed.

[0073] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0074] The computer-readable storage medium provided by the above-mentioned embodiment of the present invention and the reliability optimization method of the floating-point processing unit provided by the embodiment of the present invention are based on the same inventive concept and have the same beneficial effects as the method adopted, run or implemented by the application program stored therein.

[0075] It should be noted that:

[0076] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems may also be used together with the teachings based thereon. According to the above description, it is apparent that the structure required for constructing such systems is not intended for any particular programming language. In addition, the present invention is not intended for any particular programming language either. It should be understood that various programming languages ​​may be utilized to implement the content of the present invention described herein, and the description of the particular language above is intended to disclose the best mode of the present invention.

[0077] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0078] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0079] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0080] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0081] The various component embodiments of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all functions of some or all components in the creation system of a virtual machine according to an embodiment of the present invention. The present invention can also be implemented as a device or system program (e.g., a computer program and a computer program product) for executing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0082] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim listing a number of systems, several of these systems may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0083] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A reliability optimization system for a floating point processing unit, characterized in that: include: Data preprocessing module, index detection prediction module and error detection unit; The data preprocessing module is used to simultaneously receive the data input into the floating point processing unit and perform preprocessing; The index detection and prediction module is used to receive the preprocessing result and perform index prediction; The error detection unit is used to receive the result of the index prediction and the FPU calculation index obtained by the floating point processing unit, and compare the result of the index prediction with the FPU calculation index to determine whether the calculation result of the floating point processing unit is wrong; The data input into the floating point processing unit includes two operands and an operation code; The pre-treatment process includes: When two operands are added or multiplied, the sign bit of the addend or multiplicand remains unchanged, and when a subtraction operation is performed, the sign of the minuend is inverted, and the subtraction operation is converted into an addition operation, and then the operation code and the sign bit, exponent part and mantissa part of the operand are respectively input into the exponent detection prediction module; The exponent detection prediction module outputs the smaller of the two possible exponents to the error detection unit.

2. A reliability optimization system for a floating point processing unit according to claim 1, characterized in that: The error detection unit compares the output result of the exponential detection prediction module and the result of the output result incremented by one with the exponent of the floating-point processing unit operation result at the same time, and outputs a signal indicating that the operation result of the floating-point processing unit is wrong when both comparisons fail, otherwise, no signal indicating that the operation result of the floating-point processing unit is wrong is output.

3. The reliability optimization system of a floating point processing unit according to claim 1, characterized in that: In the multiplication operation of the exponent detection prediction module, an addition operation is performed on the exponent parts of the two input operands; In the addition and subtraction operations of the exponent detection and prediction module, when the signs of the two input operands are the same, the exponent takes the maximum exponent value or the maximum exponent value plus 1; when the signs of the two input operands are different, if the exponents are the same or the exponents differ by 1, a copy method is used for prediction; if the larger exponent and the smaller exponent differ by >1, the output exponent is the larger exponent itself or the larger exponent minus one.

4. A reliability optimization system for a floating point processing unit according to claim 3, characterized in that: The index detection and prediction module further includes three data selectors, wherein: A first data selector, used for selecting the exponent result of the addition and subtraction operation according to the result of the XOR of the two operand signs as a control signal; A second data selector is used to select the above-mentioned multiplication operation and addition and subtraction operation according to the operation code; The third data selector is used to determine the final output result according to the special value judgment result.

5. A reliability optimization method for a floating point processing unit, used in the system according to any one of claims 1 to 4, characterized in that: include: receiving data input into the floating point processing unit and performing preprocessing; Receiving the preprocessing result and performing index prediction; The result of the index prediction and the FPU calculation index obtained by the floating point processing unit operation are received, and the result of the index prediction and the FPU calculation index are compared to determine whether the operation result of the floating point processing unit is wrong.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes the computer program to implement the method according to claim 5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the method according to claim 5.

Images