A Timing Margin Monitoring and Compression Method and Circuit for Deep Pipeline Circuits

Abstract

The present invention relates to a method and circuit for timing margin monitoring and compression in a deep pipelined circuit. By detecting time borrowing in some critical paths and near-critical paths on the pipeline through a time borrowing detection module, the real-time timing margin of the hardware circuit at the current operating frequency is inferred, and the redundant timing margin is compressed by dynamically adjusting the clock frequency and maintained near a preset target value. Compared with the prior art, the present invention effectively compresses the redundant timing margin with a small hardware overhead, thereby improving the performance and energy efficiency of the hardware circuit during operation.

Description

Technical Field

[0001] The present invention relates to the field of deep pipelined circuits, and more particularly to a method and circuit for monitoring and compressing timing margins for deep pipelined circuits. Background Art

[0002] Process, voltage, and temperature (PVT) variations can cause timing fluctuations between different wafers of an integrated circuit and at different times on the same wafer, resulting in circuit malfunction. To ensure that an integrated circuit chip can operate correctly under all PVT conditions, sufficient timing margins are typically reserved according to the worst PVT case in traditional designs. Since the worst PVT case of the chip rarely occurs, there is a large amount of timing redundancy in the reserved timing margins for most chips operating under normal conditions, which limits their runtime performance and energy efficiency.

[0003] To address the above problems, error detection and correction (EDAC) technology can detect and correct circuit errors in a timely manner when timing errors occur, enabling the circuit to operate at the critical point of the timing error, effectively eliminating the redundant timing margins reserved in the circuit under normal PVT conditions, thereby improving the circuit performance and energy efficiency. However, when applying EDAC technology to deep pipeline circuits, there are problems such as a large number of critical paths, relatively balanced path delays between adjacent pipeline stages, and the possibility of multiple-stage paths failing simultaneously, resulting in significant increases in the number of EDACs that need to be inserted into the circuit and unaffordable error correction costs, severely restricting the improvement of circuit performance and energy efficiency.

[0004] In addition, the critical path replication technology has also received attention. However, due to the differences in process, voltage, and temperature between the replicated critical path and the critical path of the actual circuit, a large amount of timing margin needs to be reserved for this technology itself to ensure that the replicated critical path always experiences timing errors earlier than the critical path of the actual circuit, which is not conducive to improving circuit performance and energy efficiency. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defect that various integrated circuit chips based on deep pipelining need to set a large amount of timing margins for fluctuations in process, voltage, temperature, etc. in the prior art, and provide a method and circuit for monitoring and compressing timing margins for deep pipelined circuits to accurately infer the current timing margin of the deep pipeline circuit and perform real-time compression on the redundant timing margins, thereby effectively improving the performance and energy efficiency of the circuit during operation.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A timing margin monitoring and compression method for a deep pipelined circuit, comprising: monitoring some critical paths in the deep pipelined circuit, determining whether a time borrowing event occurs, counting the number of time borrowing events detected within a period of time, thereby inferring the current timing margin of the deep pipelined circuit, comparing the current timing margin with a preset target timing margin, and adaptively and real-time adjusting the clock frequency of the deep pipelined circuit according to the comparison result.

[0008] Further, select the critical paths in the deep pipelined circuit with the highest trigger frequency and reaching a preset first quantity for monitoring.

[0009] Further, selecting the critical paths in the deep pipelined circuit with the highest trigger frequency and reaching a preset first quantity for monitoring specifically includes:

[0010] Determine all critical paths of the pipeline stage to be monitored in the deep pipelined circuit according to the static timing of the deep pipelined circuit;

[0011] Apply real input excitation to the deep pipelined circuit for dynamic simulation, count the triggering probabilities of all critical paths, select the critical paths with the highest triggering probability and reaching the first quantity for monitoring, and the first quantity of critical paths satisfies: the number of time borrowing events detected has a monotonically decreasing relationship with the timing margin of the deep pipelined circuit.

[0012] Further, select the critical paths of the last pipeline stage of three to five consecutive pipeline stages in the deep pipelined circuit for monitoring.

[0013] Further, the inference process of the current timing margin of the deep pipelined circuit is specifically as follows:

[0014] Count the number of time borrowing events detected within a period of time, and then compare with the corresponding relationship between the timing margin and the number of time borrowing events within the corresponding monitoring time configured in advance to obtain the current timing margin;

[0015] The monitoring time is one or more clock cycles of the deep pipelined circuit.

[0016] Further, if the deep pipelined circuit is set in a non-fault-tolerant application scenario, the value range of the target timing margin is within 0 to 2.5%; if the deep pipelined circuit is set in a fault-tolerant application scenario, the value range of the target timing margin is within -15% to 2.5%.

[0017] Further, by adaptively and real - time adjusting the clock frequency of the deep - pipelined circuit, the current timing margin of the deep - pipelined circuit is maintained at a specific value, thereby controlling the error rate of the deep - pipelined circuit.

[0018] Further, comparing the current timing margin with a preset target timing margin, and adaptively and real - time adjusting the clock frequency of the deep - pipelined circuit according to the comparison result, specifically:

[0019] If the current timing margin is greater than the target timing margin, increase the clock frequency of the deep - pipelined circuit by one adjustment step;

[0020] If the current timing margin is less than the target timing margin, decrease the clock frequency of the deep - pipelined circuit by one adjustment step;

[0021] If the current timing margin is equal to the target timing margin, do not adjust the clock frequency of the deep - pipelined circuit.

[0022] Further, obtain a reference clock signal, and sequentially generate a plurality of clock signals with sequentially delayed phases according to the reference clock signal by equal - amount delay;

[0023] The step of increasing the clock frequency of the deep - pipelined circuit by one adjustment step is specifically:

[0024] Starting from the reference clock signal, when the signal is about to jump from low level to high level each time, sequentially switch and select from the generated plurality of clock signals from front to back to obtain a clock signal with an extended clock period;

[0025] The step of decreasing the clock frequency of the deep - pipelined circuit by one adjustment step is specifically:

[0026] Starting from the last generated clock signal, when the signal is about to jump from high level to low level each time, sequentially switch and select from the generated plurality of clock signals from back to front to obtain a clock signal with a shortened clock period.

[0027] The present invention also provides a timing margin monitoring and compression circuit for a deep - pipelined circuit, including: a clock borrowing detection module, a timing margin inference module, and a timing margin compression module that are connected in sequence;

[0028] The clock borrowing detection module includes a plurality of time borrowing detection units, and each time borrowing detection unit includes a shadow register connected to the master register in the deep - pipelined circuit and an exclusive - OR gate. The inputs of the master register and the shadow register both include the clock signal of the master register and the input of the master register, and the outputs of the master register and the shadow register generate a time borrowing detection result after passing through the exclusive - OR gate;

[0029] The multiple time borrowing detection units are installed on multiple critical paths in a deep pipeline circuit;

[0030] The timing margin inference module includes an adder, an accumulator, a timing margin lookup table, and a comparator connected in sequence. The input of the adder is the outputs of all time borrowing detection units, and the output is the number of time borrowing events detected in the current clock cycle. The accumulator accumulates the number of time borrowing events detected in one or more clock cycles to obtain the number of time borrowing events detected during a certain monitoring period. The timing margin lookup table is pre-configured with the corresponding relationship between the timing margin and the number of time borrowing events during the corresponding monitoring period, and outputs the current timing margin. The comparator compares the current timing margin with a preset target timing margin to generate comparison results of redundancy, deficiency, and sufficiency;

[0031] The timing margin compression module includes a local oscillator loop, a phase generator, and a phase selector connected in sequence. The local oscillator loop generates a reference clock signal. The phase generator sequentially performs equal-delay according to the reference clock signal to generate multiple clock signals with sequentially delayed phases. The phase selector performs switching selection according to the comparison result between the current timing margin and the preset target timing margin. Specifically, if the comparison result is redundancy, the clock frequency of the deep pipeline circuit is increased by one adjustment step; if the comparison result is deficiency, the clock frequency of the deep pipeline circuit is decreased by one adjustment step; if the comparison result is sufficiency, no adjustment is made to the clock frequency of the deep pipeline circuit.

[0032] Compared with the prior art, for a deep pipeline circuit, this timing margin monitoring and compression technology of the present invention effectively compresses redundant timing margins with a small hardware overhead, thereby improving the performance and energy efficiency during the operation of the hardware circuit; specifically, it has the following advantages:

[0033] (1) By monitoring some critical paths and approximate critical paths of the deep pipeline circuit, and using the number of time borrowing events detected to reflect the current timing margin, the actual current timing margin of the circuit can be accurately inferred;

[0034] (2) This technology only monitors some of the most frequently triggered critical paths and approximate critical paths in the deep pipeline circuit of the deep pipeline, and inserts detection units to detect the number of time borrowing events occurring, thereby effectively reducing the number of required time borrowing detection units and hardware overhead;

[0035] (3) This technology only monitors one level among multiple adjacent pipeline stages of the deep pipeline, removing redundant time borrowing event detection information caused by path correlation between adjacent pipeline stages, thereby effectively reducing the number of required time borrowing detection units and hardware overhead;

[0036] (4) This technology can set different target timing margins for different application scenarios. For application scenarios without fault tolerance, the target timing margin can be configured within the range of 0 to 2.5%, and for application scenarios with certain fault tolerance, the target timing margin can be configured within the range of -15% to 2.5%, so as to improve circuit performance and energy efficiency under certain computational accuracy requirements;

[0037] (5) The computational error rate of this technology for deep pipeline circuits is controllable. By maintaining the timing margin at a specific value, the operating error rate of the hardware circuit can be controlled within a specific range;

[0038] (6) This technology maintains the timing margin at a specific value by adaptively adjusting the clock frequency, thereby dynamically compressing redundant timing margins and improving circuit performance and energy efficiency. Brief Description of the Drawings

[0039] Figure 1 It is a schematic diagram of the principle of a timing margin monitoring and compression circuit for a deep pipeline circuit provided in an embodiment of the present invention;

[0040] Figure 2 It is a schematic diagram of the structure of a time borrowing detection unit based on double sampling provided in an embodiment of the present invention;

[0041] Figure 3 It is a timing waveform diagram of a time borrowing detection unit provided in an embodiment of the present invention;

[0042] Figure 4 It is a structural diagram of a timing margin inference module provided in an embodiment of the present invention;

[0043] Figure 5 It is a structural diagram of a timing margin compression module provided in an embodiment of the present invention;

[0044] Figure 6 It is a schematic diagram of the phase selection process of a timing margin compression module provided in an embodiment of the present invention;

[0045] Figure 7 It is a technical schematic diagram taking a 64-stage deep pipeline SHA256 hardware accelerator as an example provided in an embodiment of the present invention. Detailed Embodiment

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention usually described and illustrated in the drawings herein can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0048] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0049] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the inventive product is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0050] It should be noted that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.

[0051] Embodiment 1

[0052] This embodiment provides a method for monitoring and compressing the timing margin of a deep pipelined circuit, including:

[0053] A time borrowing detection step: monitoring multiple critical paths in the deep pipelined circuit to determine whether a time borrowing event occurs;

[0054] A timing margin inference step: counting the number of time borrowing events detected within a period of time, thereby inferring the current timing margin of the deep pipelined circuit, and comparing the current timing margin with a preset target timing margin;

[0055] Timing margin compression step: adaptively and real-timely adjust the clock frequency of the deep pipelined circuit according to the comparison result.

[0056] As Figure 1 As shown, this embodiment also provides a timing margin monitoring and compression circuit for a deep pipelined circuit, which is used to implement the steps of the above method. The timing margin monitoring and compression circuit includes a clock borrowing detection module, a timing margin inference module, and a timing margin compression module, which are connected in sequence. The clock borrowing detection module is used to execute the above time borrowing detection step; the timing margin inference module is used to execute the above timing margin inference step; and the timing margin compression module is used to execute the above timing margin compression step.

[0057] The following is a specific description of each step:

[0058] I. Time borrowing detection

[0059] The time borrowing detection module includes n time borrowing detection units, whose function is to detect whether time borrowing events occur on n critical paths and approximate critical paths (i.e., critical paths) of the deep pipelined circuit. Specifically, for a deep pipelined circuit based on high-level transparent latches, it is to detect whether the endpoints of these n critical paths and approximate critical paths change after the arrival of the rising edge of the clock.

[0060] As Figure 2 As shown is the structure of a time borrowing detection unit based on double sampling. It double-samples the input of the main register (high-level transparent latch) in the deep pipelined circuit with a shadow register (low-level transparent latch). The inputs of both the main register and the shadow register include the clock signal clk of the main register and the input din of the main register. The output dout of the main register and the output Qs of the shadow register generate a time borrowing detection result, that is, the output signal tb, after passing through an exclusive-OR gate DFF. Its timing waveform is as Figure 3 As shown, in clock cycle 2, if the input of the main register flips during the high level of the main register clock signal, then the outputs of the main register and the shadow register are high after passing through an exclusive-OR gate, that is, the output signal tb of the time borrowing detection unit is high, indicating that a time borrowing event has occurred on the monitored path; in clock cycle 1, if the input of the main register does not flip during the high level, then tb is low, indicating that no time borrowing event has occurred on the monitored path. As the timing margin decreases, the number of critical paths and approximate critical paths in the deep pipelined circuit where time borrowing events may occur increases. Therefore, the number of time borrowing events Ntb detected by the n time borrowing detection units also increases. In one clock cycle, the minimum possible value of Ntb is 0, and the maximum possible value is n. Therefore, the number of time borrowing events Ntb can reflect the current timing margin of the circuit.

[0061] As a preferred embodiment, the time borrowing detection module does not need to monitor all critical paths and approximate critical paths, that is, n is less than the total number of all critical paths and approximate critical paths of the deep pipeline circuit. The number of required time borrowing detection units n only needs to satisfy that the number of time borrowing events Ntb detected by n time borrowing detection units and the timing margin of the deep pipeline circuit satisfy a monotonically decreasing relationship.

[0062] That is, select the critical paths with the highest trigger frequency and reaching a preset first quantity in the deep pipeline circuit for monitoring. Specifically:

[0063] Determine all critical paths of the pipeline stage to be monitored in the deep pipeline circuit according to the static timing of the deep pipeline circuit;

[0064] Apply a real input excitation to the deep pipeline circuit for dynamic simulation, count the triggering probabilities of all critical paths, and select the critical paths with the highest triggering probability and reaching the first quantity for monitoring. The first quantity of critical paths satisfies that the number of time borrowing events detected and the timing margin of the deep pipeline circuit satisfy a monotonically decreasing relationship.

[0065] The monotonically decreasing relationship here can be explained as follows: for timing margins ts1 and ts2, where ts1 < ts2, for the timing margin ts1, the number of time borrowing events Ntb_ts1 detected by n time borrowing detection units, and for the timing margin ts2, the number of time borrowing events Ntb_ts2 detected by n time borrowing detection units, then Ntb_ts1 and Ntb_ts2 need to satisfy Ntb_ts1 > Ntb_ts2.

[0066] Correspondingly, the n critical paths and approximate critical paths to be monitored are determined by combining static timing analysis and dynamic timing analysis. Specifically, first, all critical paths and approximate critical paths of the pipeline stage to be monitored are determined according to static timing analysis; then, by applying real input stimuli, dynamic simulation is performed to count the triggering probabilities of all critical paths and approximate critical paths, and these critical paths and approximate critical paths are sorted in descending order according to the triggering probabilities; next, the critical paths and approximate critical paths are sequentially added to the set of paths to be monitored, and it is determined whether the number of time borrowing events Ntb that can be detected by the current set of paths to be monitored can accurately reflect the current timing margin, that is, whether the number of detected time borrowing events Ntb has a monotonically decreasing relationship with the timing margin. If the number of time borrowing events Ntb that can be detected by the current set of paths to be monitored can accurately reflect the current timing margin, adding new critical paths or approximate critical paths to the set of paths to be monitored can be stopped. At this time, the total number of paths in the set of paths to be monitored is n, and n time borrowing detection units are required to monitor these n critical paths and approximate critical paths. Therefore, the present invention effectively reduces the number of required time borrowing detection units and the hardware overhead.

[0067] As a preferred embodiment, the critical paths of the last pipeline stage of three to five consecutive pipeline stages in the deep pipeline circuit are selected for monitoring. The specific advantages are as follows:

[0068] Due to the path correlation between adjacent pipeline stages, the number of time borrowing events detected between adjacent pipeline stages contains redundant information. Therefore, the time borrowing detection module of the present invention does not need to monitor the critical paths and approximate critical paths of all pipeline stages. Specifically, for K consecutive pipeline stages, the monitored critical paths and approximate critical paths are only distributed in the last pipeline stage of the K pipeline stages. Taking the first pipeline stage, the second pipeline stage to the Kth pipeline stage as an example, due to the path correlation between adjacent pipeline stages, the paths that have time borrowing time events in the first pipeline stage to the (K - 1)th pipeline stage are very likely to accumulate their timing fluctuations to the Kth pipeline stage and be detected by the time borrowing detection unit of the Kth pipeline stage; if the timing fluctuations of the paths that have time borrowing events in the first pipeline stage to the (K - 1)th pipeline stage do not accumulate to the Kth pipeline stage, it means that the timing fluctuations of the paths in the first to the (K - 1)th pipeline stages have healed themselves through the time borrowing ability of the latch pipeline, and the timing margin is sufficient. Therefore, the time borrowing detection module only needs to monitor the last stage of every K consecutive pipeline stages.

[0069] II. Timing Margin Inference

[0070] The inference process of the current timing margin of the deep pipeline circuit is specifically as follows:

[0071] Count the number of time borrowing events detected within a period of time, and then compare it with the pre-configured correspondence between the timing margin and the number of time borrowing events within the corresponding monitoring time to obtain the current timing margin;

[0072] The monitored time is the clock cycle of one or more deep pipelined circuits.

[0073] As Figure 4 shown, the timing margin inference module includes an adder, an accumulator, a timing margin lookup table, and a comparator connected in sequence. The input of the adder is the output of all time borrowing detection units, and the output is the number of time borrowing events detected in the current clock cycle; the accumulator accumulates the number of time borrowing events detected in one or more clock cycles to obtain the number of time borrowing events detected in a certain monitoring time; the timing margin lookup table is pre-configured with the correspondence between the timing margin and the number of time borrowing events within the corresponding monitoring time, and outputs the current timing margin; the comparator compares the current timing margin with the preset target timing margin to generate comparison results of redundancy, insufficiency, and adequacy.

[0074] Specifically, the adder adds the 1-bit outputs of n time borrowing detection units in the time borrowing detection module to obtain the number of time borrowing events Ntb detected in the current clock cycle. The minimum possible value of Ntb is 0, and the maximum possible value is n. The accumulator accumulates the number of time borrowing events within Tob clock cycles to obtain the total number of time borrowing events Ntb_tot detected within Tob clock cycles. When Tob is 1, Ntb_tot is equal to Ntb. Compared with Ntb_tot obtained when Tob = 1, that is, Ntb, Ntb_tot obtained when Tob is greater than 1 can eliminate the fluctuation of Ntb caused by different input excitations and obtain a more stable Ntb_tot value. In the timing margin inference module, Tob is adjustable. For different target timing margins, different Tob values can be selected. Specifically, when the target timing margin is large, the number of critical paths and approximate critical paths where time borrowing events occur is small, and the value of Ntb is more affected by the fluctuation caused by different input excitations. At this time, a longer accumulation period, that is, a larger Tob, can be selected to make the total accumulated number of time borrowing events Ntb_tot more stable. When the target timing margin is small, the number of critical paths and approximate critical paths where time borrowing events occur is large, and the value of Ntb is less affected by the fluctuation caused by different input excitations. At this time, a shorter accumulation period, that is, a smaller Tob, can be selected. The timing margin look-up table stores the pre-configured correspondence between the timing margin and the number of time borrowing events within Tob clock cycles. According to Ntb_tot output by the accumulator and the corresponding accumulation period Tob, the look-up table can find the corresponding current timing margin (ts_cur). The comparator compares the current timing margin ts_cur output by the look-up table with the target timing margin ts_tag, indicates whether the current timing margin is redundant (ts_cur > ts_tag), insufficient (ts_cur < ts_tag), or appropriate (ts_cur = ts_tag) compared with the target timing margin, and converts these three situations into a 2-bit judgment signal ts_state and outputs it to the timing margin compression module.

[0075] As a preferred implementation manner, if the deep pipeline circuit is set in a non-fault-tolerant application scenario, the value range of the target timing margin is within the range of 0 to 2.5%; if the deep pipeline circuit is set in a fault-tolerant application scenario, the value range of the target timing margin is within the range of -15% to 2.5%. The specific advantages are as follows:

[0076] The target timing margin is configurable. For different application scenarios, different target timing margins can be configured to maximize the performance and energy efficiency benefits under a certain computational accuracy requirement. For application scenarios without fault tolerance, the target timing margin should be configured to be slightly greater than 0, that is, within the range of 0 to 2.5%; for application scenarios with certain fault tolerance, such as neural network acceleration, image processing, etc., the target timing margin can be configured within the range of -15% to 2.5% to obtain higher performance and energy efficiency benefits. In particular, the target timing margin has a monotonic relationship with the error rate of the calculation results of the deep pipeline circuit. Specifically, for timing margins ts1 and ts2, where ts1 < ts2 < 0, for the timing margin ts1, the error rate of the calculation results of the deep pipeline circuit is ERR1, and for the timing margin ts2, the error rate of the calculation results of the deep pipeline circuit is ERR2, then ERR1 and ERR2 satisfy ERR1 > ERR2. Therefore, by maintaining the timing margin of the deep pipeline circuit at a certain specific value, the error rate of the deep pipeline circuit can be maintained within a certain controllable range.

[0077] III. Timing Margin Compression

[0078] In the timing margin compression step, the current timing margin is compared with the preset target timing margin, and the clock frequency of the deep pipeline circuit is adaptively and real-time adjusted according to the comparison result. Specifically:

[0079] If the current timing margin is greater than the target timing margin, the clock frequency of the deep pipeline circuit is increased by one adjustment step;

[0080] If the current timing margin is less than the target timing margin, the clock frequency of the deep pipeline circuit is decreased by one adjustment step;

[0081] If the current timing margin is equal to the target timing margin, the clock frequency of the deep pipeline circuit is not adjusted.

[0082] The timing margin compression module includes a local oscillator loop, a phase generator, and a phase selector connected in sequence. The local oscillator loop generates a reference clock signal, and the phase generator generates multiple clock signals with sequentially delayed phases according to the reference clock signal by equal delays; the phase selector makes a switching selection according to the comparison result. Specifically: If the comparison result is redundant, the clock frequency of the deep pipeline circuit is increased by one adjustment step; if the comparison result is insufficient, the clock frequency of the deep pipeline circuit is decreased by one adjustment step; if the comparison result is appropriate, the clock frequency of the deep pipeline circuit is not adjusted.

[0083] As a preferred embodiment, the timing margin compression step includes: obtaining a reference clock signal, and sequentially generating a plurality of clock signals with sequentially delayed phases by performing equal delays according to the reference clock signal;

[0084] Specifically, increasing the clock frequency of the deep pipeline circuit by one adjustment step is as follows:

[0085] Starting from the reference clock signal, each time the signal is about to jump from low level to high level, sequentially perform switching selection from the front to the back among the generated multiple clock signals to obtain a clock signal with an extended clock cycle;

[0086] Specifically, decreasing the clock frequency of the deep pipeline circuit by one adjustment step is as follows:

[0087] Starting from the last generated clock signal, each time the signal is about to jump from high level to low level, sequentially perform switching selection from the back to the front among the generated multiple clock signals to obtain a clock signal with a shortened clock cycle.

[0088] Equivalently, the timing margin compression module adaptively and real-time adjusts the clock frequency of the circuit according to the 2-bit judgment signal ts_state output by the timing margin inference module. As Figure 5 shown in the structural diagram of the timing margin compression module, it includes a local oscillator loop, a phase generator and a phase selector. The local oscillator loop generates a reference clock signal clk_ref, and clk_ref generates M clock signals with different phases through a phase generator composed of a delay chain. The phase selector selects a suitable clock phase according to the current timing margin inferred by the timing margin inference module. Specifically, if the timing margin inference module indicates that there is redundancy in the current timing margin (ts_cur>ts_tag), the timing margin compression module increases the clock frequency by one step; if the timing margin inference module indicates that the current timing margin is insufficient (ts_cur<ts_tag), the timing margin compression module decreases the clock frequency by one step; if the timing margin inference module indicates that the current timing margin is appropriate (ts_cur = ts_tag), the timing margin compression module does not adjust the clock frequency. As Figure 6The waveform shown corresponds to the case where the current timing margin is insufficient (ts_cur < ts_tag). At this time, the phase selector will sequentially select phase 1 (φ1), phase 2 (φ2), phase 3 (φ3),... at the beginning of each clock cycle. The clock period of the adjusted clock clk_tuned obtained thereby is increased by ΔT compared to the clock period T of the reference clock clk_ref. The value of ΔT is the delay difference between two adjacent clock phases generated by the phase generator. The clock clk_tuned after clock frequency adjustment will be output to the deep pipeline circuit as its working clock. Therefore, the timing margin compression module can maintain the working frequency of the deep pipeline circuit in real time at the working frequency corresponding to the appropriate state of the timing margin of the deep pipeline circuit, effectively compressing the redundant timing margin.

[0089] The following provides a specific implementation of the solution of the present invention in a 64-stage deep pipeline SHA256 hardware accelerator. This 64-stage deep pipeline circuit adopts a pipeline design based on high-level transparent three-phase non-overlapping latches and has a certain time borrowing ability. The arithmetic functions of each stage of the pipeline are the same, both are two hash iteration calculations, and the pipeline is highly balanced.

[0090] In this specific implementation example, the monitored critical paths and approximate critical paths are distributed in the last stage of every adjacent three pipeline stages, that is, 21 pipeline stages such as the 3rd pipeline stage, the 6th pipeline stage, and the 9th pipeline stage. Taking the 1st pipeline stage, the 2nd pipeline stage, and the 3rd pipeline stage as an example, due to the path correlation between adjacent pipeline stages, the paths with time borrowing time in the 1st pipeline stage and the 2nd pipeline stage are very likely to accumulate their timing fluctuations to the 3rd pipeline stage and be detected by the time borrowing detection unit of the 3rd pipeline stage; if the timing fluctuations of the paths with time borrowing time in the 1st pipeline stage and the 2nd pipeline stage do not accumulate to the 3rd pipeline stage, it means that the timing fluctuations of the paths in the 1st pipeline stage and the 2nd pipeline stage have been self-healed through the time borrowing ability of the latch pipeline and the timing margin is sufficient. Therefore, for the 1st pipeline stage, the 2nd pipeline stage, and the 3rd pipeline stage, the time borrowing detection module only needs to monitor the 3rd pipeline stage.

[0091] The time borrowing detection module in this embodiment contains 294 time borrowing detection units, which are used to monitor whether time borrowing events occur on 294 critical paths and near-critical paths. The monitored critical paths and near-critical paths only account for 3.1% of all critical paths and near-critical paths, and the number of time borrowing detection units only accounts for 0.59% of the total number of pipeline latches, with extremely low hardware overhead. The above-mentioned 294 monitored critical paths and near-critical paths are selected by combining static timing analysis and dynamic timing analysis. Specifically, first, all critical paths and near-critical paths of 21 pipeline stages to be monitored are determined according to static timing analysis; then, by applying real input stimuli and performing dynamic simulation, the triggering probabilities of all critical paths and near-critical paths are statistically analyzed, and these critical paths and near-critical paths are sorted in descending order according to the triggering probabilities; next, the critical paths and near-critical paths are sequentially added to the monitored path set, and it is judged whether the number of time borrowing events Ntb that can be detected by the current monitored path set within a period of time can accurately reflect the current timing margin, that is, whether the total number of detected time borrowings Ntb has a monotonically decreasing relationship with the timing margin. If the total number of time borrowings Ntb that can be monitored by the current monitored path set can accurately reflect the current timing margin, the addition of new critical paths or near-critical paths to the monitored path set can be stopped, and the final monitored path set is obtained. For this embodiment, each pipeline stage to be monitored contains 14 time borrowing detection units, which continuously monitor 14 most frequently triggered critical paths and near-critical paths in this pipeline stage.

[0092] The timing margin detection module in this embodiment includes an adder, an accumulator, a timing margin lookup table, and a comparator. The adder adds the outputs of 294 time borrowing detection units in the time borrowing detection module to obtain the number of time borrowings Ntb detected in the current clock cycle. The minimum possible value of Ntb is 0, and the maximum possible value is 294. The accumulator accumulates the total number of time borrowing situations within Tob clock cycles to obtain the total number of time borrowings Ntb_tot within Tob clock cycles.

[0093] Tob in this embodiment is adjustable. For different target timing margins ts_tag, different Tob values can be selected. Specifically, when the target timing margin is large, such as when ts_tag is 2.5% of the clock cycle, the number of critical paths and near-critical paths where time borrowing events occur is small, and the value of Ntb fluctuates greatly due to different input stimuli. At this time, this embodiment selects a longer accumulation period Tob = 1000, so that the total number of time borrowing times Ntb_tot obtained by accumulation is more stable. When the target timing margin is small, such as when ts_tag is -5% of the clock cycle, the number of critical paths and near-critical paths where time borrowing events occur is large, and the value of Ntb fluctuates less due to different input stimuli. At this time, this embodiment selects a shorter accumulation period Tob = 250. Particularly, a ts_tag less than 0 corresponds to a certain calculation error rate of the deep pipeline circuit. In this embodiment, ts_tag = -5% can control the calculation error rate of the deep pipeline circuit below 1E-5%.

[0094] The timing margin lookup table stores the pre-configured correspondence between the timing margin and the total number of time borrowing events within Tob clock cycles. According to Ntb_tot output by the accumulator and the corresponding accumulation period Tob, the lookup table can find the corresponding current timing margin ts_cur. Particularly, the target timing margin is configurable. For different application scenario requirements, different target timing margins can be configured to maximize the performance and energy efficiency benefits under certain calculation accuracy requirements. For this embodiment, the timing margin can be configured as -15%, -12.5%, -10%, -7.5%, -5%, -2.5%, 0, 2.5%, corresponding to different cases where the calculation error rates are 1%, 0.1%, 0.01%, 0.001%, 0.0001%, 0.00001%, 0, and with a 2.5% redundant timing margin respectively.

[0095] The comparator compares the current timing margin ts_cur output by the lookup table with the target timing margin ts_tag, indicates whether the current timing margin is redundant (ts_cur > ts_tag), insufficient (ts_cur < ts_tag) or appropriate (ts_cur = ts_tag) compared with the target timing margin, and converts these three cases into a 2-bit judgment signal ts_state and outputs it to the timing margin compression module.

[0096] In this embodiment, the timing margin compression module adaptively and real-time adjusts the clock frequency of the circuit according to the output ts_state of the timing margin inference module, so as to achieve the compression effect on the redundant timing margin. The timing margin compression module includes a local oscillator loop, a phase generator, and a phase selector. The local oscillator loop generates a reference clock signal clk_ref, and clk_ref generates 64 clock signals with different phases through a phase generator composed of a delay chain. The phase selector selects a suitable clock phase according to the current timing margin inferred by the timing margin inference module. Specifically, if the timing margin inference module indicates that the current timing margin is redundant (ts_cur>ts_tag), the timing margin compression module will increase the clock frequency by an adjustment step; if the timing margin detection module indicates that the current timing margin is insufficient (ts_cur<ts_tag), the timing margin correction module will decrease the clock frequency by an adjustment step; if the timing margin detection module indicates that the current timing margin is appropriate (ts_cur = ts_tag), the timing margin correction module will not adjust the clock frequency. The clock clk_tuned after the clock frequency adjustment will be output to the SHA256 hardware accelerator as its working clock. Therefore, the timing margin compression module can maintain the current timing margin near the target timing margin ts_tag, thereby dynamically and real-time compressing the redundant timing margin and improving the performance and energy efficiency of the circuit.

[0097] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations according to the concept of the present invention without creative labor. Therefore, all technical solutions that can be obtained by those skilled in the art in the technical field based on the concept of the present invention through logical analysis, reasoning, or limited experiments on the basis of the prior art should be within the protection scope determined by the claims.

Claims

1. A timing margin monitoring and compression method for a deep pipelined circuit, characterized in that Including: Monitoring some critical paths in the deep pipelined circuit, determining whether a time borrowing event occurs, counting the number of time borrowing events detected within a period of time, thereby inferring the current timing margin of the deep pipelined circuit, comparing the current timing margin with a preset target timing margin, and adaptively and real-timely adjusting the clock frequency of the deep pipelined circuit according to the comparison result; Selecting the critical paths with the highest trigger frequency and reaching a preset first quantity in the deep pipelined circuit for monitoring; specifically: Determining all critical paths of the pipeline stage to be monitored in the deep pipelined circuit according to the static timing of the deep pipelined circuit; Applying a real input excitation to the deep pipelined circuit for dynamic simulation, counting the triggering probabilities of all critical paths, selecting the critical paths with the highest triggering probability and reaching the first quantity for monitoring, and the first quantity of critical paths satisfies: the number of time borrowing events detected has a monotonically decreasing relationship with the timing margin of the deep pipelined circuit; Comparing the current timing margin with a preset target timing margin, and adaptively and real-timely adjusting the clock frequency of the deep pipelined circuit according to the comparison result, specifically: If the current timing margin is greater than the target timing margin, increasing the clock frequency of the deep pipelined circuit by one adjustment step; If the current timing margin is less than the target timing margin, decreasing the clock frequency of the deep pipelined circuit by one adjustment step; If the current timing margin is equal to the target timing margin, no adjustment is made to the clock frequency of the deep pipelined circuit.

2. The timing margin monitoring and compression method for a deep pipelined circuit according to claim 1, wherein Selecting the critical paths of the last pipeline stage of three to five consecutive pipeline stages in the deep pipelined circuit for monitoring.

3. A timing margin monitoring and compression method for a deep pipelined circuit according to claim 1, wherein The inference process of the current timing margin of the deep pipelined circuit is specifically: Counting the number of time borrowing events detected within a period of time, and then comparing with the corresponding relationship between the timing margin and the number of time borrowing events within the corresponding monitoring time configured in advance to obtain the current timing margin; The monitoring time is one or more clock cycles of the deep pipelined circuit.

4. A timing margin monitoring and compression method for a deep pipeline circuit according to claim 1, characterized in that If the deep pipelined circuit is set in a non-fault-tolerant application scenario, the value range of the target timing margin is within 0 to 2.5%; if the deep pipelined circuit is set in a fault-tolerant application scenario, the value range of the target timing margin is within -15% to 2.5%.

5. A timing margin monitoring and compression method for a deep pipelined circuit according to claim 1, characterized in that, By adaptively and real-timely adjusting the clock frequency of the deep pipelined circuit, maintaining the current timing margin of the deep pipelined circuit at a certain specific value, thereby controlling the error rate of the deep pipeline circuit.

6. A timing margin monitoring and compression method for a deep pipelined circuit according to claim 1, wherein Obtaining a reference clock signal, and sequentially generating a plurality of clock signals with sequentially delayed phases according to the reference clock signal with equal delays; The specific operation of increasing the clock frequency of the deep pipelined circuit by one adjustment step is: Starting from the reference clock signal, when the signal is about to jump from low level to high level each time, sequentially switching and selecting from the generated plurality of clock signals from front to back to obtain a clock signal with an extended clock period; The specific operation of decreasing the clock frequency of the deep pipelined circuit by one adjustment step is: Starting from the last generated clock signal, each time the signal is about to jump from high level to low level, switching selection is sequentially performed from back to front among the generated multiple clock signals to obtain a clock signal with a shortened clock cycle.

7. A timing margin monitoring and compression circuit for a deep pipeline circuit that implements a timing margin monitoring and compression method for a deep pipeline circuit as described in any one of claims 1-6, characterized in that, Including: A clock borrowing detection module, a timing margin inference module, and a timing margin compression module connected in sequence; The clock borrowing detection module includes multiple time borrowing detection units. Each time borrowing detection unit includes a shadow register and an exclusive OR gate connected to the master register in the deep pipeline circuit. The inputs of the master register and the shadow register both include the clock signal of the master register and the input of the master register. The outputs of the master register and the shadow register generate a time borrowing detection result after passing through the exclusive OR gate; The multiple time borrowing detection units are installed on multiple critical paths in the deep pipeline circuit; The timing margin inference module includes an adder, an accumulator, a timing margin look-up table, and a comparator connected in sequence. The input of the adder is the output of all time borrowing detection units, and the output is the number of time borrowing events detected in the current clock cycle; The accumulator accumulates the number of time borrowing events detected in one or more clock cycles to obtain the number of time borrowing events detected in a certain monitoring time period; the timing margin look-up table is pre-configured with the corresponding relationship between the timing margin and the number of time borrowing events in the corresponding monitoring time period, and outputs the current timing margin; the comparator compares the current timing margin with a preset target timing margin to generate comparison results of redundancy, insufficiency, and adequacy; The timing margin compression module includes a local oscillator loop, a phase generator, and a phase selector connected in sequence. The local oscillator loop generates a reference clock signal. The phase generator sequentially generates multiple clock signals with sequentially delayed phases according to the reference clock signal; the phase selector performs switching selection according to the comparison result between the current timing margin and the preset target timing margin. Specifically, if the comparison result is redundancy, the clock frequency of the deep pipeline circuit is increased by an adjustment step; if the comparison result is insufficiency, the clock frequency of the deep pipeline circuit is decreased by an adjustment step; if the comparison result is adequacy, the clock frequency of the deep pipeline circuit is not adjusted.

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