Separate cache for address mapping data

Abstract

This application is directed to a split cache for address mapping data. A memory system can include a cache (e.g., including a first portion and a second portion) for storing data indicating mappings between logical addresses associated with a host system and physical addresses of the memory system. The memory system can store data (e.g., the address mapping data) in the first portion of the cache. Additionally, the memory system can store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. If a subset of the data is used for access operations during the duration, the memory system can transfer the subset of the data to the second portion of the cache.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 953,075, filed November 19, 2020, entitled “SPLIT CACHE FOR ADDRESS MAPPING DATA”, by Colella et al., which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to a separate cache for address-mapped data. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to different states. For example, a binary memory cell can be programmed to typically correspond to one of two supported states, either logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of those possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time even in the absence of an external power supply. Summary of the Invention

[0006] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions executable by a processor to: store data indicating a mapping between logical addresses associated with a host system and physical addresses of a memory system in a first portion of a cache of the memory system; identify a first subset of data for one or more access operations of the memory system during the duration the data is stored in the first portion of the cache; and transfer the first subset of data from the first portion of the cache to a second portion of the cache, at least in part based on the identification.

[0007] A memory system is described. The memory system may include: a memory device; a cache configured to store data indicating a mapping between logical addresses associated with a host system and physical addresses of the memory device, the cache including a first portion configured to store data according to a first granularity and a second portion configured to store data according to a second granularity smaller than the first granularity; and a controller coupled to the memory device and the cache and configured to: transfer data from the memory device to the first portion of the cache; and transfer a first subset of data from the first portion of the cache to the second portion of the cache, at least in part, based on a first subset of data used for one or more access operations of the memory system during the duration during which the data is stored in the first portion of the cache.

[0008] Describe an apparatus. The apparatus may include: a memory array; and a controller coupled to the memory array and configured such that the apparatus: stores data indicating a mapping between logical addresses associated with a host system and physical addresses of the memory system in a first portion of a cache of the memory system; identifies a first subset of data for one or more access operations of the memory system during the duration the data is stored in the first portion of the cache; and transfers the first subset of data from the first portion of the cache to a second portion of the cache, at least in part based on the identification. Attached Figure Description

[0009] Figure 1 This describes an instance of a system that supports a separate cache for address-mapped data, based on examples disclosed herein.

[0010] Figure 2 This describes an instance of a system that supports a separate cache for address-mapped data, based on examples disclosed herein.

[0011] Figure 3 This document describes an example of a flowchart supporting a separate cache for address-mapped data, based on examples disclosed herein.

[0012] Figure 4 A block diagram of a memory system supporting a separate cache for address-mapped data, based on examples disclosed herein, is shown.

[0013] Figure 5 A flowchart illustrating one or more methods for supporting separate caches for address-mapped data, based on examples disclosed herein. Detailed Implementation

[0014] A memory system can be coupled to a host system, which can transmit access commands to the memory system for execution. In some cases, the host system may utilize a set of logical addresses for the access command, while the memory system may utilize a set of physical addresses (e.g., different from the logical addresses) to execute the access command. Here, the memory system may rely on address mapping data to determine the mapping between logical and physical addresses. The memory system may store the address mapping data within its memory devices (e.g., using a logical-physical address (L2P) table or a physical address table (PPT)). When the memory system receives an access command, it may access the address mapping data associated with the access command to execute the access command. Therefore, the amount of time associated with accessing the address mapping data can affect the latency of the memory system. That is, if the memory system accesses the address mapping data quickly, then the latency of the memory system can be reduced compared to a memory system that accesses the address mapping data less quickly.

[0015] Some memory systems can utilize caches to store a subset of address-mapped data to reduce the amount of latency associated with accessing some address-mapped data. That is, accessing address-mapped data stored in a cache can be associated with less latency compared to accessing address-mapped data stored in the memory devices of the memory system. However, a cache may not be large enough to store all the address-mapped data associated with the memory system. A cache hit can occur when the memory system receives an access command associated with address-mapped data stored in the cache. Alternatively, a cache miss can occur when the memory system receives an access command associated with address-mapped data not stored in the cache. In some cases, increasing the frequency of cache hits can reduce the latency associated with the memory system executing the access command. When the memory system receives an access command associated with address-mapped data not yet stored in the cache (e.g., new address-mapped data associated with a cache miss), the memory system can store the new address-mapped data in the cache. In some cases (e.g., when the cache is full of other address-mapped data), the memory system may evict some address-mapped data previously stored in the cache to make room for new address-mapped data. For example, the memory system may evict address-mapped data that is not yet associated with as many access commands as other address-mapped data stored in the cache.

[0016] In some memory systems, caches may store address-mapped data in a single granularity (e.g., 4 kilobytes (KB)). In other memory systems, caches may store address-mapped data in more than one granularity. For example, a cache may contain a first portion associated with a first granularity (e.g., 4 KB) and a second portion associated with a second granularity smaller than the first granularity (e.g., 1 KB). Here, the memory system may initially store address-mapped data in the first portion of the cache according to the first granularity. When the first portion of the cache is full and the memory system receives an access command associated with new address-mapped data, the memory system may identify a set of address-mapped data that is not associated with as many access commands as other sets of address-mapped data within the cache. The memory system may then transfer one or more subsets of the identified address-mapped data already associated with one or more access commands to the second portion of the cache (e.g., when stored in the first portion of the cache). The memory system may additionally evict the remaining one or more subsets of the identified address-mapped data from the cache. By storing a subset of the address-mapped data associated with a larger number of access commands in a cache (e.g., without evicting the subset), the memory system can increase the frequency of cache hits, thus reducing the latency associated with executing access commands. Furthermore, because the cache contains a second portion associated with address-mapped data at a smaller granularity than the first portion of the cache, the density of address-mapped data used for access commands can be higher than in a cache that stores data only according to a first, larger granularity.

[0017] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figure 3 Features of this disclosure are described within the context of the flowcharts described. These and other features of this disclosure are further illustrated by and described with reference to device diagrams and flowcharts relating to, as referenced Figure 4 and 5 The described separate cache for address-mapped data.

[0018] Figure 1 This describes an instance of system 100 that supports a separate cache for address-mapped data, as disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any computing device that includes memory and processing means.

[0021] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations according to the instances described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to host system 105 or included in host system 150), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and to read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise conveying control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, peripheral component interconnect high speed (PCIe) interfaces, USB interfaces, Fibre Channel, small computer system interface (SCSI), Serial Attached SCSI (SAS), dual data rate (DDR), dual in-line memory module (DIMM) interfaces (e.g., DDR-enabled DIMM socket interfaces), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR). In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 or memory device 140 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 or memory device 140 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., non-volatile memory cell type), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., volatile memory cell type). Although in Figure 1 The example shows a memory device 130 and a memory device 140, but it should be understood that the memory system 110 may contain any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may be missing either memory device 130 or memory device 140.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with memory device 130 or memory device 140 to perform operations such as reading data, writing data, erasing data, or refreshing data at memory device 130 or memory device 140, and other such operations generally referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or memory device 140 to execute such commands (e.g., at a memory array within one or more memory devices 130 or memory device 140). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to enable desired access to memory device 130 or memory device 140. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 or memory device 140 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with memory device 130 or memory device 140 into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with memory device 130 or memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 130 or memory device 140.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein that pertain to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that may store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, when data is read from or written to memory device 130 or memory device 140, the data may be stored in local memory 120 and may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updates) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130 or memory device 140).

[0028] The memory system controller 115 may additionally include a cache 180. For example, the memory system controller 115 may include a 1024KB SRAM cache. In some cases, the cache 180 may be contained within local memory 120. In some cases, the cache 180 may be part of local memory 120. In some cases, the cache 180 may contain the entire local memory 120. The cache 180 may be configured to store data indicating a mapping between logical addresses associated with host system 105 and physical addresses (e.g., address mapping data) in memory system 110. Memory system 110 may store the entire L2P table (e.g., containing address mapping data) at one or more locations in memory devices 130 and 140. Additionally, memory system 110 may store a subset of the address mapping data within cache 180. In some cases, accessing address mapping data stored in cache 180 may be associated with less latency compared to accessing address mapping data stored in memory devices 130 or 140. A cache hit can occur when memory system 110 receives an access command associated with address-mapped data stored in cache 180. Alternatively, a cache miss can occur when memory system 110 receives an access command associated with address-mapped data not stored in cache 180. In some cases, increasing the frequency of cache hits can reduce the latency associated with memory system 110 executing access commands.

[0029] When memory system 110 receives an access command associated with address-mapped data not yet stored in cache 180 (e.g., new address-mapped data associated with a cache miss), memory system 110 may store the new address-mapped data in cache 180. In some cases (e.g., when cache 180 is full of other address-mapped data), memory system 110 may evict some address-mapped data previously stored in cache 180 to store the new address-mapped data in cache 180. For example, memory system 110 may additionally store an indication associated with each set of address-mapped data indicating whether the address-mapped data was associated with any access command when stored in cache 180. Here, memory system 110 may evict address-mapped data associated with an indication indicating that the address-mapped data was not associated with any access command when stored in cache 180. Alternatively or additionally, the indication may indicate the number of access operations associated with the set of address-mapped data when stored in cache 180. Here, memory system 110 may evict address-mapped data that has been used for fewer access operations when stored in cache 180, compared to the number of access commands associated with other address-mapped data stored in cache 180. In either case, evictming address-mapped data from cache 180 allows memory system 110 to store new address-mapped data in cache 180.

[0030] Cache 180 may include a first portion 185 configured to store address-mapped data according to a first granularity (e.g., 2KB, 4KB, 8KB, 16KB). Memory system controller 115 may transfer address-mapped data from memory device 130 or 140 to the first portion 185 of cache 180 according to the first granularity. In some cases, each set of address-mapped data (e.g., containing address-mapped data of the first granularity) may contain address-mapped information for a defined number of physical addresses of memory device 130 or 140. For example, each set of 4KB address-mapped data may contain address-mapped information for the address space of memory device 130 or 140 configured to store 1 megabyte (MB) of data.

[0031] In some cases, an access command received from host system 105 may indicate only a subset of 1MB of data associated with address-mapped data. In other cases, an access command received from host system 105 may indicate data associated with a set of non-contiguous physical addresses (e.g., via a set of logical addresses). Here, memory system 110 may access multiple sets of address-mapped data to identify the mapping between the logical and physical addresses of the access command. In either case, memory system 110 may transfer address-mapped data to cache 180 according to granularity (e.g., 4KB), and one or more subsets of the address-mapped data may not be associated with an access command. In an instance where cache 180 stores data only according to a first granularity, cache 180 may contain address-mapped data used infrequently for access operations. For example, to ensure that a 1KB subset of address-mapped data remains in cache 180, cache 180 may be configured to store a 4KB set of address-mapped data containing the 1KB subset of address-mapped data. Here, cache 180 can store 3KB of address mapping data that is rarely used for access operations.

[0032] In an example of memory system 110, cache 180 may include a second portion 190 configured to store data at a second granularity smaller than the first granularity. Therefore, before evicting a set of address-mapped data from the first portion 185 of cache 180, memory system 110 may transfer a subset of the address-mapped data for access operations from the first portion 185 of cache 180 to the second portion 190 of cache 180. For example, for each subset of address-mapped data, memory system 110 may store (e.g., in the first portion 185 of cache 180) an indication of whether the subset of address-mapped data was used for an access operation while the address-mapped data was stored in the first portion 185 of cache 180. Therefore, when a set of address-mapped data is evicted from the first portion 185 of cache 180 (e.g., caused by the first portion 185 of cache 180 becoming full), memory system 110 may first transfer one or more subsets of the set of address-mapped data to the second portion 190 of cache 180 based on one or more subsets indicated for access operations when stored in the first portion 185 of cache 180. This can increase the density of address-mapped data used for access operations, which in turn can increase the frequency of cache hits and reduce the frequency of cache misses associated with cache 180. In some cases, this can reduce the latency associated with the execution of access operations at memory system 110.

[0033] Although Figure 1The example of memory system 110 has been described as including memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or may perform the functions belonging to memory system controller 115 herein, which may be located within memory device 130 or memory device 140, respectively. Generally, one or more functions belonging to memory system controller 115 herein may, in some cases, be performed by host system 105, local controller 135, or local controller 145, or any combination thereof.

[0034] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells. In some instances, memory device 140 may support random access operations with reduced latency relative to memory device 130 (e.g., via host system 105), or may provide one or more other performance differences relative to memory device 130.

[0035] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0036] In some instances, memory device 130 or memory device 140 may each include (e.g., on the same die or within the same package) a local controller 135 or local controller 145, which can perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. In some cases, memory device 130 or memory device 140 including local controller 135 or local controller 145 may be referred to as a managed memory device and may include a memory array and associated circuitry combined with a local (e.g., on-die or within-package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0037] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0038] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information; these memory cells may be referred to as single-level cells (SLCs). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If each cell is configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if each cell is configured to store three bits of information, it may be referred to as a three-level cell (TLC); if each cell is configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide higher storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write tolerances or higher complexity for supporting circuitry.

[0039] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are located in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0040] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0041] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but can be erased at a second-level granularity (e.g., at the block level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0042] In some cases, L2P tables can be maintained, and data can be marked as valid or invalid at the page level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated because the latest or newest version of the data is stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as the logical address referenced by host system 105. Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or erased.

[0043] System 100 may include any number of non-transitory computer-readable media supporting separate caches for address-mapped data. For example, host system 105, memory system controller 115, memory device 130, or memory device 140 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing functions belonging to host system 105, memory system controller 115, memory device 130, or memory device 140 herein. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, memory device 130 (e.g., by local controller 135), or memory device 140 (e.g., by local controller 145), may cause host system 105, memory system controller 115, memory device 130, or memory device 140 to perform one or more associated functions as described herein.

[0044] Figure 2 This describes an instance of system 200 that supports a separate cache for address-mapped data, based on examples disclosed herein. System 200 may implement aspects of system 100. For example, system 200 may include cache 280, a first portion 285, and a second portion 290, which may be respectively as described in reference... Figure 1 Examples of the described cache 180, first part 185, and second part 190.

[0045] The first portion 285 can be configured to store data 205 according to a first granularity. For example, the first portion 285 can be configured to store data 205 according to a 4KB granularity. Here, each set of data 205 can contain 4KB of data. Additionally, data 205-a can be as referenced. Figure 1 The described address mapping data. That is, each set of data 205 (e.g., data 205-a, data 205-b, data 205-c, and data 205-d) can indicate a mapping between logical addresses associated with the host system and physical addresses in the memory system. Additionally, each set of data 205 can indicate a mapping between sets of logical addresses and physical addresses spanning an address space based on the size of data 205. For example, if data 205 contains 4KB of data, then data 205 can indicate a mapping between logical addresses and physical addresses spanning a 1MB address space. That is, the logical and physical addresses associated with data 205 can be configured to store 1MB of data.

[0046] Each set of data 205 may additionally contain more than one subset of data 210. In an instance of system 200, each set of data 205 contains four subsets of data 210. In other instances, each set of data 205 may contain more or fewer than four subsets of data 210. Each subset of data 210 may correspond to a subset of the address space associated with data 205. For example, if a set of data 205-a is associated with a 1MB address space, then each subset of data 210-a, 210-b, 210-c, and 210-d may span 256KB. Cache 280 may additionally include a second portion 290 configured to store data 205 with a second granularity smaller than the first granularity (e.g., associated with the first portion 285 of cache 280) and equal to the size of each subset of data 210. For example, if each subset of data 210 contains 1KB of data, then the granularity of the second portion 290 of cache 280 may be 1KB. In another instance, if each set of data 205 contains 4KB of data and each of the two subsets of data 210 contains 2KB of data, then the granularity of the second portion 290 of cache 280 can be 2KB. In some cases, cache 280 can be configured to store 1MB of data 205. For example, the first portion 285 of cache 280 can be configured to store 768KB of data 205, and the second portion 290 of cache 280 can be configured to store 256KB of data.

[0047] The memory system may additionally store an indicator 215 (e.g., a hit flag) associated with each set of data 205. For example, indicator 215-a may be associated with data 205-a. Additionally, indicator 215-b may be associated with data 205-b. Each indicator 215 stored within the first portion 285 of cache 280 may indicate whether data 205 is used for an access operation during the duration data 205 is stored within the first portion 285 of cache 280. Furthermore, each indicator 215 may contain bits associated with each subset of data 210. For example, indicator 215-c may contain four bits, each of which is associated with one of the four subsets of data 210 within data 205-c. That is, the first '0' in indicator 215-c can be associated with a subset 210-i of data; the second '0' in indicator 215-c can be associated with a subset 210-j of data; the third '1' in indicator 215-c can be associated with a subset 210-k of data; and the fourth '1' in indicator 215-c can be associated with a subset 210-l of data. Therefore, each indicator 215 can indicate whether each subset of data 210 has been used for access operations during the duration during which the subset of data 210 is stored in the first part 285 of cache 280. In some cases, a logical value '0' in indicator 215 may indicate that a subset of data 210 is not used for access operations when the subset of data 210 is stored in the first part 285 of cache 280, while a logical value '1' in indicator 215 may indicate that the subset of data 210 has been used for access operations when the subset of data 210 is stored in the first part 285 of cache 280.

[0048] When the memory system (e.g., as reference) Figure 1 When the memory system receives an access command, it can determine whether the set of logical addresses indicated by the access command is associated with data 205 in cache 280. If cache 280 does indeed contain data 205 associated with the access command, the memory controller (e.g., as described in reference) can determine whether the set of logical addresses indicated by the access command is associated with data 205 in cache 280. Figure 1The physical addresses associated with one or more logical addresses can be identified based on the mapping indicated by data 205 stored in cache 280. If data 205 used by an access operation is stored in the first portion 285 of cache 280, the memory system can then update the value of the indicator 215 associated with data 205 to indicate that data 205 is used for the access operation. For example, if the memory system receives an access command associated with each subset of data 210 of data 205-a, the memory system can set each bit in indicator 215-a to the logical value '1'. In another instance, if the memory system receives an access command associated with subsets 210-o and 210-p of data 205-d, the memory system can update the bits in indicator 215-d associated with subsets 210-o and 210-p of data 210-d to the logical value '1'. In another case where the data 205 used for access operations is a subset of the data 210 stored in the second portion 290 of cache 280, the memory system may not update any indicator 215 associated with the subset of data 210. That is, the memory system may not store the indicator associated with the subset of data 210 stored in the second portion 290 of cache 280 in cache 280.

[0049] In the absence of data 205 associated with access commands in cache 280, the memory controller may base its decisions on data not stored in cache 280 (and alternatively, data stored as referenced in [reference]). Figure 1 The data 205 in the memory device of the described memory system is mapped to identify one or more physical addresses associated with one or more logical addresses. The memory system can then transfer the data 205 associated with the access command from the memory device to the first portion 285 according to a first granularity. For example, if the memory system receives an access command using data 205-b and the memory system determines that cache 280 does not contain data 205-b, then the memory system can store data 205-b in the first portion 285 of cache 180. In addition, the memory system can set the indicator 215 associated with data 205 to indicate that data 205 is not used by an access operation while data 205 is stored in the first portion 285 of cache 280 (e.g., by setting each bit of indicator 215 to the logical value '0').

[0050] In some cases, the memory system may need to evict data 205 from the first portion 285 of cache 280 before storing new data 205 in cache 280. For example, cache 280 may be full of data 205, and the memory system may receive an access command for data 205 that is not currently stored in cache 280. Here, the memory system may identify data 205 that was evicted from cache 280 before storing new data 205 in the first portion 285 of cache 280. When identifying data 205 in the first portion 285 of cache 280, the memory system may identify a smaller subset of data 205 for access operations compared to other sets of data 205 in the first portion 285 of cache 280. For example, the memory system can identify that data 205-c and 205-d have only two subsets of data 210 used for access operations during the duration during which data 205-c and 205-d are stored in the first part 285 of cache 280, respectively, data 205-c and 205-d being smaller than both data 205-a and 205-b, data 205-a and 205-b having four and three subsets of data 210, respectively, which are used for access operations during the duration during which data 205-a and 205-b are stored in the first part 285 of cache 280.

[0051] After identifying one or more sets of data 205 to be evicted from the first portion 285 of cache 280, the memory system may then identify any subset of data 210 within data 205 that has been used for access operations during the duration that data 205 is stored in the first portion 285 of cache 280. For example, the memory system may determine subsets 210-k and 210-l of data 205-c used for access operations while data 205-c is stored in the first portion 285 of cache 280 (e.g., based on bits of indicator 215-c associated with subsets 210-k and 210-l of data having a logic value of '1'). The memory system may then transfer these subsets of data 210 to be stored in the second portion 290 of cache 280 from the first portion 285 of cache 280. For example, the memory system may transfer subsets 210-k and 210-l of data to the second portion 290 of cache 280. In another example, the memory system may determine subsets 210-m and 210-n of the data 205-d used for access operations when the data 205-d is stored in the first portion 285 of the cache 280 (e.g., based on the bits of indicator 215-d associated with subsets 210-m and 210-n of the data having a logic value of '1'). Here, the memory system may transfer subsets 210-m and 210-n of the data to the second portion 290 of the cache 280.

[0052] After transferring one or more subsets of data 210 to the second portion 290 of cache 280, the memory system can evict the associated data 205 from the first portion 285 of cache 280. For example, after the memory system transfers subsets 210-m and 210-n of data to the second portion 290 of cache 280, the memory system can evict data 205-d from cache 280. In another example, after the memory system transfers subsets 210-k and 210-l of data to the second portion 290 of cache 280, the memory system can evict data 205-c from cache 280. After evicting data 205 from cache 280, the memory system can store new data 205 in cache 280. In some cases, a subset of data 210 stored in the second portion 290 of cache 280 may remain in cache 280 for a longer period of time than data 205 stored in the first portion 285 of cache 280. That is, data 205 may be evicted from the first portion of cache 280 at a higher frequency than a subset of data 210 may be evicted from the second portion 290 of cache 280.

[0053] By transferring a subset of data 210 associated with an access command to the second portion 290 of cache 280 and evicting a subset of data 210 not associated with an access command from cache 280, the density of the subset of data 210 stored within cache 280 for access operations can be greater than that of cache 280 not configured to store subsets of data 210 according to the second granularity. Therefore, the frequency of cache hits associated with cache 280 can be greater than that of cache 280 not containing the second portion 290. This reduces the latency associated with access commands executed by memory systems containing caches similar to cache 280 compared to memory systems that do not contain caches similar to cache 280.

[0054] Figure 3 This document describes an example of a flowchart 300 supporting a separate cache for address-mapped data, based on examples disclosed herein. In some instances, flowchart 300 may implement aspects of systems 100 and 200. For example, flowchart 300 may be provided by reference to... Figure 1 The described memory system controller 115 executes the instructions. Additionally, flowchart 300 can be implemented as instructions stored in the memory system controller 115 (e.g., firmware stored in local memory 120). For example, the instructions are executed by the controller (e.g., as referenced in...). Figure 1 When the memory system controller 115 described is executed, it enables the controller to perform the operations of flowchart 300.

[0055] At point 305, data (e.g., address-mapped data) can be stored in a first portion of the cache. For example, the memory system may receive an access command using address-mapped data that is not currently stored in the cache. Therefore, the memory system can store the data used by the access operation in the first portion of the cache. The cache may additionally include a second portion. Here, the first portion of the cache may be configured to store data according to a first granularity, and the second portion of the cache may be configured to store data according to a second granularity smaller than the first granularity.

[0056] At point 310, the indicator associated with the data can be updated based on the access operation associated with the data. That is, the memory system can receive access commands from the host system indicating one or more logical addresses associated with the data. For example, one or more subsets of the data can indicate the mapping between one or more logical addresses indicated by the access command and one or more physical addresses associated with the memory system. Here, the memory system can update each bit in the indicator associated with the subset of data used for the access operation to store the logical value '1'. If the subset of data is not used for an access operation, the associated bit in the indicator can retain the logical value '0'.

[0057] At point 315, a determination can be made regarding whether to evict data from the cache. For example, the memory system can determine whether to evict data from the cache based on the number of subsets of data used for access operations when the data was stored in the first part of the cache. For example, if the data contains a subset of four data, then the indicator may contain four bits. If each of the four bits is a logic value '1', then the memory system can determine that the data contains a subset of the four data used for access operations when the data was stored in the first part of the cache. Alternatively, if one of the four bits is a logic value '1' and three of the four bits are logic values ​​'0', then the memory system can determine that the data contains a subset of one data used for access operations when the data was stored in the first part of the cache (and a subset of three data not used for access operations). If the data contains a smaller subset of data used for access operations compared to other data stored in the first part of the cache, the memory system can proceed to point 320. If the data contains a larger subset of data for access operations compared to any other data stored in the first subset of the cache, the memory system can continue 330.

[0058] At 320, one or more subsets of the data may optionally be transferred to the second part of the cache. For example, if any subset of the data was used for access operations while the data was stored in the first part of the cache (e.g., indicated by a logical value '1' as a bit associated with the subset), then the memory system may transfer those subsets to the second part of the cache. Alternatively, if none of the subsets of the data was used for access operations while the data was stored in the first part of the cache (e.g., indicated by an indicator including a bit with a logical value '0'), then the memory system may avoid transferring any subset of the data to the second part of the cache.

[0059] At 325, the memory system can evict data from the first part of the cache. Therefore, a subset of data used for access operations only when the data is stored in the first part of the cache can be stored in the cache (e.g., in the second part of the cache), while a subset of data not used for access operations when the data is stored in the first part of the cache can be entirely evicted from the cache.

[0060] At position 330, data can be retained in the first part of the cache. For example, the memory system can avoid evicting data from the first part of the cache.

[0061] Figure 4A block diagram 400 illustrates a memory system 405 supporting a separate cache for address-mapped data, based on examples disclosed herein. The memory system 405 may be as described in the references... Figures 1 to 3 Examples of aspects of the described memory system. Memory system 405 may include a data storage manager 410, an access operation manager 415, a data transfer component 420, an indicator manager 425, and a data egress component 430. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0062] The data storage manager 410 may store data indicating the mapping between logical addresses associated with the host system and physical addresses of the memory system in a first part of the memory system's cache. In some instances, the data storage device manager 410 may store second data indicating the mapping between a second logical address associated with the host system and a second physical address of the memory system in the first part of the memory system's cache based on evicted data. In some cases, the data contains 4KB of data.

[0063] Access operation manager 415 can identify a first subset of data for one or more access operations of the memory system during a duration during which the data is stored in a first portion of the cache. In some cases, the duration may be less than a second duration during which the first subset is stored in a second portion of the cache. In some instances, the first subset of data contains less than 4KB of data. In some instances, access operation manager 415 can perform access operations using the first subset of data based on the storage of data in the first portion of the cache. In some cases, access operation manager 415 can receive commands from the memory system controller indicating one or more logical addresses associated with the access operation for performing the access operation.

[0064] Data transfer component 420 may transfer a first subset of data from a first portion of the cache to a second portion of the cache based on identification. In some instances, data transfer component 420 may transfer the first subset of data based on the first portion of the cache used to store information. In some cases, data transfer component 420 may avoid transferring any subset of second data to the second portion of the cache, wherein the second data is stored in the first portion of the cache, based on identification that a first number of data subsets used for access operations during the duration is less than a second number of second data subsets used for access operations during the duration.

[0065] Indicator manager 425 may update an indicator used to indicate whether data was used for one or more access operations during a duration based on identification, wherein the first subset of data transferred is based on updating the indicator. In some instances, indicator manager 425 may set a bit associated with the first subset of data within an indicator associated with data to a value indicating that the first subset of data was used for one or more access operations during a duration based on the execution of an access operation, wherein identification is based on setting the bit. In some cases, indicator manager 425 may identify one or more physical addresses associated with one or more logical addresses based on a mapping indicated by the first subset of data stored in a first part of a cache.

[0066] In some cases, the indicator manager 425 may update an indicator indicating whether data was used for one or more access operations during a duration based on a mapping indicated by a first subset of data to identify one or more physical addresses. In some instances, the indicator manager 425 may identify a first number of subsets of data used for access operations during the duration that is less than a second number of subsets of data used for access operations during the duration, wherein the second data is stored in a first portion of a cache. In some cases, the indicator contains a set of bits, each associated with a subset of data. In some cases, each bit in the set of bits indicates whether the associated subset of data was used for one or more access operations during the duration.

[0067] Data eviction component 430 may evict data from a first portion of the cache based on a first subset of the transmitted data. In some instances, data eviction component 430 may identify the absence of access operations associated with a second subset of the data during a duration based on the value of an indicator associated with the data, wherein data eviction is based on identifying the absence of access operations.

[0068] Figure 5 A flowchart illustrating one or more methods 500 for supporting separate caches for address-mapped data, based on examples disclosed herein. The operation of method 500 may be implemented by a memory system or its components as described herein. For example, the operation of method 500 may be implemented by, as referenced... Figure 4 The described memory system performs the function. In some instances, the memory system can execute a set of instructions to control the functional elements of the memory system to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0069] At 505, the memory system may store data indicating the mapping between logical addresses associated with the host system and physical addresses of the memory system in the first part of the memory system's cache. The operation of 505 can be performed according to the methods described herein. In some instances, aspects of the operation of 505 may be as described in the references... Figure 4 The described data storage manager is executed.

[0070] At 510, the memory system can identify a first subset of data used for one or more access operations of the memory system during the duration during which the data is stored in the first part of the cache. The operation at 510 can be performed according to the method described herein. In some instances, aspects of the operation at 510 can be derived from references... Figure 4 The described access operation manager is executed.

[0071] At point 515, the memory system can transfer a first subset of data from a first portion of the cache to a second portion of the cache based on identification. The operation of point 515 can be performed according to the method described herein. In some instances, aspects of the operation of point 515 can be derived from, as referenced... Figure 4 The described data transmission component is executed.

[0072] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, methods, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing data indicating a mapping between logical addresses associated with a host system and physical addresses of a memory system in a first portion of a cache of the memory system; identifying a first subset of data for one or more access operations of the memory system during the duration the data is stored in the first portion of the cache; and transferring the first subset of data from the first portion of the cache to a second portion of the cache based on the identification.

[0073] Some instances of the method 500 and device described herein may further include features, methods, or instructions for updating an indicator based on identification to indicate whether data is available for one or more access operations during a duration, wherein a first subset of the data to be transferred may be based on updating the indicator.

[0074] In some cases of the methods 500 and devices described herein, the indicator contains a set of bits, each associated with a subset of data, and each bit in the set of bits indicates whether the associated subset of data is available for one or more access operations during a duration.

[0075] Some examples of the methods 500 and devices described herein may further include operations, features, methods, or instructions for: performing an access operation using a first subset of data based on storing data in a first part of a cache; and setting a bit associated with the first subset of data within an indicator associated with the data to a value indicating that the first subset of data is available for one or more access operations during a duration, wherein the identification may be based on the set bit.

[0076] Some examples of the methods 500 and devices described herein may further include operations, features, methods, or instructions for performing: receiving from a controller of a memory system a command indicating an access operation for performing an access operation on one or more logical addresses associated with the access operation; identifying one or more physical addresses associated with the one or more logical addresses based on a mapping indicated by a first subset of data stored in a first portion of a cache; and updating an indicator indicating whether data is available for one or more access operations during a duration based on the identification of one or more physical addresses, the identification of the one or more physical addresses being based on a mapping indicated by the first subset of data.

[0077] Some aspects of the method 500 and device described herein may further include operations, features, methods, or instructions for evicting data from a first portion of a cache based on a first subset of the transmitted data.

[0078] Some examples of the method 500 and device described herein may further include operations, features, methods, or instructions that perform the following: storing second data, based on evicted data, indicating a mapping between a second logical address associated with the host system and a second physical address of the memory system, in a first portion of a cache of the memory system.

[0079] Some instances of the method 500 and device described herein may further include operations, features, methods, or instructions that identify the absence of an access operation associated with a second subset of the data during a duration based on the value of an indicator associated with the data, wherein data eviction may be based on the identification of the absence of the access operation.

[0080] Some aspects of the method 500 and apparatus described herein may further include operations, features, methods, or instructions that perform the following: identifying a first number of a subset of data used for access operations during a duration that may be less than a second number of a subset of second data used for access operations during a duration, wherein the second data may be stored in a first portion of a cache; and avoiding transferring any subset of the second data to the second portion of the cache based on the identification.

[0081] Some examples of the methods 500 and devices described herein may further include operations, features, methods, or instructions that can transfer a first subset of data based on a first portion of a cache used for storing information.

[0082] In some instances of the method 500 and device described herein, the duration may be less than the second duration in the second part of the first subset that may be stored in the cache.

[0083] In some cases of the method 500 and device described herein, the data contains 4KB of data, and a first subset of the data contains less than 4KB of data.

[0084] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0085] Describe an apparatus. The apparatus may include: a memory device; a cache configured to store data indicating a mapping between logical addresses associated with a host system and physical addresses of the memory device, the cache including a first portion configured to store data according to a first granularity and a second portion configured to store data according to a second granularity smaller than the first granularity; and a controller coupled to the memory device and the cache and configured to: transfer data from the memory device to the first portion of the cache, and transfer a first subset of data from the first portion of the cache to the second portion of the cache at least in part based on a first subset of data used for one or more access operations of the memory system during the duration during which the data is stored in the first portion of the cache.

[0086] In some instances, the first part of the cache may be further configured to store indicators that indicate whether data is available for one or more access operations during a duration.

[0087] In some cases, the indicator contains a set of bits, each associated with a subset of the data, and each bit in the set of bits indicates whether the associated subset of the data is available for one or more access operations during the duration.

[0088] In some cases, the controller may be further configured to: identify commands indicating the execution of one or more logical address access operations associated with the access operations; identify one or more physical addresses associated with the one or more logical addresses based on a mapping indicated by a first subset of data stored in a first part of the cache; and update an indicator indicating whether data is available for one or more access operations during a duration based on the identification of one or more physical addresses, the mapping indicated by the first subset of data.

[0089] In some instances, the controller may be further configured to evict data from the first part of the cache based on sending a first subset of the data to the second part of the cache.

[0090] In some cases, the controller may be further configured to transfer second data from the memory device to the first part of the cache based on the evicted data.

[0091] In some cases, the controller may be further configured to identify the absence of access operations associated with a second subset of the data during the duration based on the value of an indicator associated with the data, wherein data eviction may be based on identifying the absence of access operations.

[0092] In some instances, the memory device includes NAND memory cells.

[0093] Describe an apparatus. The apparatus may include: a memory array; and a controller coupled to the memory array and configured such that the apparatus: stores data indicating a mapping between logical addresses associated with a host system and physical addresses of the memory system in a first portion of a cache of the memory system; identifies a first subset of data for one or more access operations of the memory system during the duration the data is stored in the first portion of the cache; and transfers the first subset of data from the first portion of the cache to a second portion of the cache based on the identification.

[0094] In some instances, the controller may be further configured to update an indicator that indicates whether data is available for one or more access operations during a duration based on identification, wherein a first subset of the data to be transferred may be based on updating the indicator.

[0095] In some cases, the indicator contains a set of bits, each associated with a subset of the data, and each bit in the set of bits indicates whether the associated subset of the data is available for one or more access operations during the duration.

[0096] In some cases, the controller may be further configured to: perform an access operation using a first subset of data based on storing the data in a first part of a cache; and may set a bit associated with the first subset of data in an indicator that can be associated with the data to a value indicating that the first subset of data is used for one or more access operations during a duration, wherein the identification may be based on the set bit.

[0097] In some instances, the controller may be further configured to: receive a command indicating to perform an access operation for one or more logical addresses associated with the access operation; identify one or more physical addresses associated with the one or more logical addresses based on a mapping indicated by a first subset of data stored in a first part of a cache; and update an indicator indicating whether data is available for one or more access operations during a duration based on the identification of one or more physical addresses, the identification of the one or more physical addresses being based on a mapping indicated by the first subset of data.

[0098] The information and signals disclosed herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and code slices that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0099] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that can enable the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the flow of signals between connected components for a period of time.

[0100] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0101] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0102] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. During the initial formation or growth of the substrate, doping can be performed by ion implantation or by any other doping method.

[0103] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor is "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor is "turned off" or "deactivated."

[0104] The descriptions herein, illustrated in conjunction with the accompanying drawings, depict exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed descriptions contain specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0105] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0106] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0107] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0108] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items preceded by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of A, B, or C means A or B or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0109] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The combinations described above also fall within the scope of computer-readable media.

[0110] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A non-transitory computer-readable medium storing code comprising instructions executable by a processor to: store data indicative of mappings between logical addresses associated with a host system and physical addresses of a memory system in a first portion of a cache of the memory system; identify, during a duration that the data is stored in the first portion of the cache, a first subset of the data used for one or more access operations of the memory system; and transfer the first subset of the data from the first portion of the cache to a second portion of the cache based at least in part on the identifying, wherein the first portion of the cache is configured to store data according to a first granularity and the second portion of the cache is configured to store data according to a second granularity that is less than the first granularity.

2. The non-transitory computer-readable medium of claim 1, wherein the instructions are further executable by the processor to: update, based at least in part on the identifying, an indicator to indicate whether the data was used for the one or more access operations during the duration, wherein transferring the first subset of the data is based at least in part on updating the indicator.

3. The non-transitory computer-readable medium of claim 2, wherein: the indicator comprises a set of bits each associated with a respective subset of the data; and each bit of the set of bits indicates whether the respective subset of the data was used for the one or more access operations during the duration.

4. The non-transitory computer-readable medium of claim 1, wherein the instructions are further executable by the processor to: perform an access operation using the first subset of the data based at least in part on storing the data in the first portion of the cache; and set, based at least in part on performing the access operation, a bit associated with the first subset of the data within an indicator associated with the data to a value indicating that the first subset of the data was used for the one or more access operations during the duration, wherein the identifying is based at least in part on setting the bit.

5. The non-transitory computer-readable medium of claim 1, wherein the instructions are further executable by the processor to: receive, from a controller of the memory system, a command to perform an access operation indicating one or more logical addresses associated with the access operation; identify one or more physical addresses associated with the one or more logical addresses based at least in part on the mappings indicated by the first subset of the data stored in the first portion of the cache; and update, based at least in part on identifying the one or more physical addresses, an indicator to indicate whether the data was used for the one or more access operations during the duration, the identifying the one or more physical addresses based at least in part on the mappings indicated by the first subset of the data.

6. The non-transitory computer-readable medium of claim 1, wherein the instructions are further executable by the processor to: evict the data from the first portion of the cache based at least in part on transferring the first subset of the data.

7. The non-transitory computer-readable medium of claim 6, wherein the instructions are further executable by the processor to: store second data indicating mappings between second logical addresses associated with the host system and second physical addresses of the memory system in the first portion of the cache of the memory system based at least in part on evicting the data.

8. The non-transitory computer-readable medium of claim 6, wherein the instructions are further executable by the processor to: identify an absence of access operations associated with a second subset of the data during the duration of time based at least in part on a value of an indicator associated with the data, wherein evicting the data is based at least in part on identifying the absence of access operations.

9. The non-transitory computer-readable medium of claim 1, wherein the instructions are further executable by the processor to: identify that a first number of subsets of the data used for access operations during the duration of time is less than a second number of subsets of second data used for access operations during the duration of time, wherein the second data is stored in the first portion of the cache; and avoid transferring any subsets of the second data to the second portion of the cache based at least in part on the identification.

10. The non-transitory computer-readable medium of claim 1, wherein transferring the first subset of the data is based at least in part on the first portion of the cache for storing information.

11. The non-transitory computer-readable medium of claim 1, wherein the duration of time is less than a second duration of time in which the first subset is stored in the second portion of the cache.

12. The non-transitory computer-readable medium of claim 1, wherein: the data comprises 4 kilobyte (KB) data; and the first subset of the data comprises less than 4 KB of data.

13. A memory system, comprising: a memory device; a cache configured to store data indicating mappings between logical addresses associated with a host system and physical addresses of the memory device, the cache comprising a first portion configured to store data according to a first granularity and a second portion configured to store data according to a second granularity that is less than the first granularity; and a controller coupled with the memory device and the cache and configured to: transfer data from the memory device to the first portion of the cache; and evict the data from the first portion of the cache based at least in part on transferring the first subset of the data. transferring a first subset of the data from the first portion of the cache to the second portion of the cache based at least in part on the first subset of the data for one or more access operations for the memory system during a duration in which the data is stored in the first portion of the cache.

14. The memory system of claim 13, wherein the first portion of the cache is further configured to store an indicator to indicate whether the data is for the one or more access operations during the duration.

15. The memory system of claim 14, wherein: the indicator comprises a set of bits each associated with a subset of the data; and each bit of the set of bits indicates whether the subset associated with the data is for the one or more access operations during the duration.

16. The memory system of claim 13, wherein the controller is further configured to: identify a command to perform an access operation that indicates one or more logical addresses associated with the access operation; identify one or more physical addresses associated with the one or more logical addresses based at least in part on the mapping indicated by the first subset of the data stored in the first portion of the cache; and update an indicator to indicate whether the data is for the one or more access operations during the duration based at least in part on identifying the one or more physical addresses, the identifying the one or more physical addresses based at least in part on the mapping indicated by the first subset of the data.

17. The memory system of claim 13, wherein the controller is further configured to: evict the data from the first portion of the cache based at least in part on transferring the first subset of the data to the second portion of the cache.

18. The memory system of claim 17, wherein the controller is further configured to: transfer second data from the memory device to the first portion of the cache based at least in part on evicting the data.

19. The memory system of claim 17, wherein the controller is further configured to: identify an absence of an access operation associated with a second subset of the data during the duration based at least in part on a value of an indicator associated with the data, wherein evicting the data is based at least in part on identifying the absence of an access operation.

20. The memory system of claim 13, wherein the memory device comprises NAND memory cells.

21. A memory device, comprising: a memory array; and a controller coupled with the memory array and configured to cause the memory device to: store data indicating a mapping between logical addresses associated with a host system and physical addresses of a memory system in a first portion of a cache of the memory system; evict the data from the first portion of the cache based at least in part on transferring a first subset of the data to a second portion of the cache, the first subset of the data for one or more access operations for the memory system during a duration in which the data is stored in the first portion of the cache.

22. The memory device of claim 21, wherein the controller is further configured to: identify a command to perform an access operation that indicates one or more logical addresses associated with the access operation; identify one or more physical addresses associated with the one or more logical addresses based at least in part on the mapping indicated by the first subset of the data stored in the first portion of the cache; and update an indicator to indicate whether the data is for the one or more access operations during the duration based at least in part on identifying the one or more physical addresses, the identifying the one or more physical addresses based at least in part on the mapping indicated by the first subset of the data.

23. The memory device of claim 21, wherein the controller is further configured to: evict the data from the first portion of the cache based at least in part on transferring the first subset of the data to the second portion of the cache.

24. The memory device of claim 23, wherein the controller is further configured to: transfer second data from the memory device to the first portion of the cache based at least in part on evicting the data.

25. The memory device of claim 23, wherein the controller is further configured to: identify an absence of an access operation associated with a second subset of the data during the duration based at least in part on a value of an indicator associated with the data, wherein evicting the data is based at least in part on identifying the absence of an access operation.

26. The memory device of claim 21, wherein the memory array comprises NAND memory cells. identifying a first subset of the data used for one or more access operations for the memory system during a duration that the data is stored in the first portion of the cache; and transferring the first subset of the data from the first portion of the cache to a second portion of the cache based at least in part on the identifying, wherein the first portion of the cache is configured to store data according to a first granularity and the second portion of the cache is configured to store data according to a second granularity that is less than the first granularity.

22. The memory device of claim 21, wherein the controller is further operable to cause the memory device to: update an indicator that indicates whether the data was used for the one or more access operations during the duration based at least in part on the identifying, wherein transferring the first subset of the data is based at least in part on updating the indicator.

23. The memory device of claim 22, wherein: the indicator comprises a set of bits that are each associated with a subset of the data; and each bit of the set of bits indicates whether the subset associated with the data was used for the one or more access operations during the duration.

24. The memory device of claim 21, wherein the controller is further operable to cause the memory device to: perform an access operation using the first subset of the data based at least in part on storing the data in the first portion of the cache; and set a bit associated with the first subset of the data to a value that indicates that the first subset of the data was used for the one or more access operations during the duration within an indicator associated with the data based at least in part on performing the access operation, wherein the identifying is based at least in part on setting the bit.

25. The memory device of claim 21, wherein the controller is further operable to cause the memory device to: receive a command to perform an access operation that indicates one or more logical addresses associated with the access operation; identify one or more physical addresses associated with the one or more logical addresses based at least in part on the mapping indicated by the first subset of the data stored in the first portion of the cache; and update an indicator that indicates whether the data was used for the one or more access operations during the duration based at least in part on identifying the one or more physical addresses, the identifying the one or more physical addresses being based at least in part on the mapping indicated by the first subset of the data.

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