High voltage isolation device for semiconductor devices

Abstract

This document discloses a high-voltage isolation device and associated system for a semiconductor device. The isolation device can support the operation of a 3D NAND memory array of the semiconductor device. In some embodiments, during high-voltage operation (e.g., erase operation), the isolation device can provide a high voltage to the memory array while isolating other circuitry supporting low-voltage operation of the memory array from the high voltage. The isolation device may include a set of narrow active regions separating the low-voltage circuitry from the high voltage, and a gate over the narrow active regions. In another embodiment, the isolation device includes interdigitated narrow active regions and a common gate over the interdigitated narrow active regions for reducing the area occupied by the isolation device.

Description

Technical Field

[0001] This technology generally relates to semiconductor devices, and more specifically, to high-voltage isolation devices for semiconductor devices. Background Technology

[0002] Semiconductor devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of memory cells. Various types of semiconductor memory devices exist, such as non-volatile memory devices (e.g., NOR flash memory devices, 3D NAND flash memory devices, etc.) and volatile memory devices (e.g., dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), etc.).

[0003] Improving memory devices can broadly include increasing memory cell density, increasing read / write speeds or otherwise reducing operational latency, improving reliability, increasing data retention, reducing power consumption, reducing the area occupied by the integrated circuit system, or reducing manufacturing costs, among other metrics. One way to reduce manufacturing costs is to improve the manufacturing process to increase the margin of successful device manufacturing. Manufacturers can improve the manufacturing margin by implementing processes such as increasing the consistency or tolerance of manufacturing steps (e.g., material removal or deposition), scaling up manufacturing, and reducing the variability between memory cells. Summary of the Invention

[0004] On one hand, this disclosure relates to a semiconductor device comprising: an active region including an intermediate region having one or more source contacts and an outer region having a single bit line contact; a plurality of interdigitated active channels comprising: 1) a plurality of first active channels connected to an edge of the outer region, wherein each of the first active channels is aligned with a corresponding bit line contact and extends in a first direction orthogonal to the single bit line contact; and 2) a plurality of second active channels spaced apart from the edge of the outer region, wherein the second active channels are parallel to the first active channels such that individual first active channels alternate with individual second active channels; and a common gate over the plurality of interdigitated active channels, the common gate extending in a second direction parallel to the single bit line contact and configured to couple with the plurality of interdigitated active channels.

[0005] In another aspect, this disclosure relates to a semiconductor device comprising: an active region including a central region having a row of source contacts and an outer region having a row of bit line contacts; a first gate over the active region, the first gate comprising: 1) a straight portion positioned between the row of source contacts and the bit line contacts; and 2) a plurality of protruding segments connected to the straight portion, wherein individual protruding segments extend through an edge of the outer region in a first direction orthogonal to the row of bit line contacts and are positioned between two adjacent bit line contacts; a plurality of first active channels connected to the edge of the outer region, wherein each of the first active channels is aligned with a corresponding bit line contact and extends in the first direction; and a second gate over the plurality of first active channels, the second gate extending in a second direction parallel to the row of bit line contacts.

[0006] In another aspect, this disclosure relates to a semiconductor device comprising: a first active region including a first intermediate region and a first outer region having a single row of first bit line contacts; a plurality of first active channels connected to an edge of the first outer region, wherein each of the first active channels is aligned with a corresponding first bit line contact and extends in a first direction orthogonal to the single row of first bit line contacts; a second active region including a second intermediate region and a second outer region having a single row of second bit line contacts; a plurality of second active channels connected to an edge of the second outer region, wherein each of the second active channels is aligned with a corresponding second bit line contact and extends in the first direction, and wherein: the first outer region faces the second outer region; and the plurality of first active channels and the plurality of second active channels form a plurality of interdigitated active channels such that individual first active channels alternate with individual second active channels; and a common gate over the plurality of interdigitated active channels, the common gate extending in a second direction parallel to the single row of first bit line contacts and configured to couple with the plurality of interdigitated active channels. Attached Figure Description

[0007] The accompanying drawings provide a better understanding of many aspects of this technology. The components in the drawings are not necessarily drawn to scale; rather, the focus is on clearly illustrating the principles of this technology.

[0008] Figures 1A to 1C This is the layout of the isolation device according to an embodiment of the present technology.

[0009] Figures 2A to 2C This refers to the layout options of the isolation device according to embodiments of the present technology.

[0010] Figure 3 This is a schematic diagram of a system including a memory device with an isolation device according to an embodiment of the present technology. Detailed Implementation

[0011] Embodiments of this technology include isolation devices for semiconductor devices, such as 3D NAND memory devices. During specific operations of the memory device (e.g., erase operations), the isolation device couples a relatively high voltage (HV) to the memory cells of the memory device while isolating other components of the memory device (e.g., page buffers) from the high voltage. During other operations of the memory device (e.g., read / write operations), the isolation device couples the memory cells to other components of the memory device (e.g., page buffers) operating at a relatively low voltage (LV). Therefore, such isolation devices may be referred to as LV-HV isolation devices or high-voltage isolation devices.

[0012] In some embodiments, the isolation device includes narrow active regions configured to couple a subset of memory cells to (or decouple a subset of memory cells from) a corresponding page buffer. For this purpose, the isolation device includes a gate coupled to the narrow active region to control the conductivity of the narrow active region via a gate dielectric material. Furthermore, the isolation devices may be placed adjacent to each other (e.g., side-by-side), such that a first group of narrow active regions of a first isolation device may be positioned adjacent to a second group of narrow active regions of a second isolation device. Therefore, a first gate of the first isolation device disposed over the narrow active regions of the first group may be positioned adjacent to a second gate of the second isolation device disposed over the narrow active regions of the second group.

[0013] As described in more detail herein, the length of the isolation device can be determined by the configuration of the memory array of the memory device. For example, the number of narrow active regions along the length of the isolation device corresponds to the number of bit lines of the memory array supported by the isolation device. However, the width of the isolation device can be scaled proportionally independently of the memory array configuration, thereby reducing the area occupied by the isolation device. For example, the narrow active regions of the first and second groups can be interdigitated so that the individual narrow active regions of the first group alternate with the individual narrow active regions of the second group. Furthermore, the first and second gates can be combined over a common gate on the interdigitated active regions so that the common gate can be shared by the narrow active regions of the first and second groups. Because the first and second gates are biased to the same voltage simultaneously during isolation device operation, sharing of the common gate is feasible.

[0014] Alternatively, the widths of the first and second narrow active regions can be reduced (e.g., reduced to the minimum feature size of the memory device) to facilitate interleaving of the first and second narrow active regions. Furthermore, the widths of the first and second gates over the first and second narrow active regions can be reduced so that the first and second isolation devices can be brought closer together. In this way, the area occupied by the isolation devices can be reduced to support the increasing number of memory cells built into a unit area of ​​the memory device and / or reduce the area occupied by the isolation devices (e.g., the overlay area).

[0015] Numerous specific details are disclosed herein to provide a thorough and possible description of embodiments of the present technology. Furthermore, the present technology may have additional embodiments, and may be described without further reference. Figures 1A to 2C The described embodiments are practiced in several details. For example, some details of semiconductor devices well known in the art have been omitted so as not to obscure the technology. Generally, it should be understood that various other devices and systems are within the scope of this technology, in addition to the specific embodiments disclosed herein.

[0016] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” can refer to the relative orientation or position of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “top” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations, such as reversed or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right may depend on orientation interchange.

[0017] Those skilled in the art will recognize that appropriate stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending on the context in which it is used, the term "substrate" can refer to a wafer-level substrate or a single-cut die-level substrate. Furthermore, unless the context otherwise indicates, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques. Those skilled in the art will also understand that this technique may have additional embodiments, and that this technique may be described without further reference. Figures 1A to 2C The described embodiments are practiced in several details.

[0018] Figure 1A The various features of a high-voltage isolation device according to embodiments of the present technology are described. Furthermore, the operating principle of the isolation device is referenced. Figure 1A To describe. Figure 1B and 1C This describes aspects of isolation devices included in a semiconductor device to support the operation of the memory array of the semiconductor device. Figures 2A to 2C This section describes layout options for isolation devices with interdigitated narrow active channels and a common gate above the active channel to reduce the coverage area of ​​the isolation device. The layout options illustrate various modifications for interdigitated narrow active channels and common gates. Furthermore, it references the trade-off between the coverage area of ​​the isolation device and the risk associated with leakage current during high-voltage operation. Figures 2A to 2C To describe.

[0019] Figure 1A This is a layout of a portion of an isolation device 110 according to an embodiment of the present technology. In some embodiments, the isolation device 110 is part of a memory device (e.g., a 3D NAND memory device). Furthermore, the isolation device 110 may be positioned under a memory array (e.g., a 3D NAND memory cell array) to support operations of the memory device for the memory array, such as erase operations and read / write operations. The isolation device 110 includes active regions (e.g., active region 115, active region 120 (also individually identified as 120a to f)), gates (e.g., first gate 125 (also individually identified as 125a / b)), second gate 130 (also individually identified as 130a / b)) and contacts to the active regions and gates. The contacts to the active regions include a source contact 135, a bit line contact 140 (also individually identified as 140a / b), and a contact 145 (also individually identified as 145a / b) at the end of active region 120. The contacts to the gate include contacts 150 (also individually identified as 150a / b) to the first gate 125 and contacts 155 (also individually identified as 155a / b) to the second gate 130. Additionally, the isolation device 110 includes other features (e.g., interconnects in the dielectric layer, not shown) and can be coupled to other integrated circuit systems and / or components of the memory device (e.g., control circuitry driving the isolation device 110, memory array, page buffer, etc.).

[0020] Active regions 115 and 120 correspond to regions of a substrate (e.g., a silicon substrate in which a memory device is fabricated) surrounded by a dielectric material (e.g., a dielectric material in a shallow trench isolation (STI) feature of the substrate, which may be referred to as a field region) that provides electrical isolation between the active regions of the substrate. Furthermore, active regions 115 and 120 may contain one or more dopant species that modify the electrical and / or material properties of the active regions. Thus, active regions 115 and 120 may be referred to as diffusion regions and / or diffusion areas. For example, active regions 115 and 120 can form the source, channel, drain, and / or lightly doped drain (LDD) regions of a field-effect transistor (FET) by selectively introducing one or more dopant species into various portions of the active regions. Additionally, the active regions of the substrate may contain other components of the memory device, such as diffusion resistors, wells, ground nodes, or the like.

[0021] The first and second gates 125 and 130 may comprise polysilicon (poly-Si), metallic elements (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.), metallic silicides (e.g., WSix), or combinations thereof. During operation of the isolation device 110, the first and second gates 125 and 130 may be capacitively coupled to the underlying active region (e.g., FET channel) via a dielectric material to control (e.g., determine, modify) the conductivity of the active region. The dielectric material positioned between the active region and the first and second gates 125 and 130 may be referred to as the gate dielectric. The gate dielectric may comprise silicon oxide, silicon nitride, oxides containing high-k elements (e.g., hafnium (Hf), zirconium (Zr), lanthanum (La), etc.), metallic silicides containing high-k elements (e.g., Hf silicide, Zr silicide), or combinations thereof.

[0022] Contacts 135 to 155 comprise conductive material that couples the various nodes of isolation device 110 to other functional features or operating voltages of the memory device (e.g., control circuitry operating isolation device 110, memory array, page buffer, etc.). Contacts 135 to 155 may be filled with tungsten (W) and may be referred to as W0 contacts. W0 contacts (and / or metal traces connected thereto) may correspond to the lowest contacts and / or interconnects formed on active regions 115 and 120 and the first and second gates 125 and 130 (e.g., formed earlier than other conductive features in the process of manufacturing interconnects of the memory device).

[0023] In some embodiments, the active region 115 may be considered to include an intermediate region 116 (e.g., a central region) in which a column of source contacts 135 are located. Furthermore, the active region 115 includes an outer region 117 (also individually identified as 117a / b) in which a plurality of columns of bit line contacts 140 are located (e.g., a region surrounding the central region). Each bit line contact 140 may be coupled to a corresponding bit line of the memory array.

[0024] The isolation device 110 further includes a first gate 125 disposed over the active region 115. Each first gate 125 can be considered to have a straight portion 126 (also individually identified as 126a / b) between a row of source contacts 135 and a plurality of rows of bit line contacts 140a / b. Thus, the straight portion 126 of the first gate 125 can couple the source contacts 135 to the bit line contacts 140 (or decouple the source contacts 135 from the bit line contacts 140) based on a voltage applied to the first gate 125 through the contact 150. Furthermore, each first gate 125 includes a plurality of protruding segments 127 (also individually identified as 127a / b) extending through the edge 118 (also individually identified as 118a / b) of the outer region 117 in a first direction orthogonal to a row of bit line contacts 140. Individual protruding segments 127 of the first gate 125 are positioned between two adjacent bit line contacts 140, such that the protruding segments 127 can help isolate the adjacent bit line contacts 140 from each other.

[0025] Furthermore, the isolation device 110 includes a set of active channels 120 (e.g., narrow, elongated active regions forming channels) connected to the edge 118 of the outer region 117. In this respect, a single continuous active region may include both an active region 115 and a set of active channels 120. Each of the active channels 120 is aligned with a corresponding bit line contact 140. Additionally, each individual active channel extends in a first direction (e.g., orthogonal to a row of bit line contacts 140) and includes an end of the contact 145 located therein, away from the edge 118. Individual contacts 145 may be coupled to a corresponding page buffer of the memory device. In this way, the page buffer can be coupled to (or decoupled from) the corresponding bit line contact 140 during operation of the memory array via individual contacts (i.e., individual ends of the active channels containing the contact 145).

[0026] The isolation device 110 further includes a second gate 130 over a set of active channels 120, wherein the second gate 130 extends in a second direction orthogonal to the first direction (e.g., parallel to a row of bit line contacts 140). Furthermore, the second gate 130 is positioned between a row of bit line contacts 140 and contact 145. Thus, the second gate 130 can couple the bit line contacts 140 to contact 145 (and therefore, to the page buffer of contact 145) (or decouple the bit line contacts 140 from contact 145) based on a voltage applied to the second gate 130 through contact 155.

[0027] During a first operation of the memory device at a relatively low voltage (LV) (e.g., LV operation, read / write operation), the first gate 125 can be turned off (e.g., grounded, deactivated) to decouple the source contact 135 from the bit line contact 140. Furthermore, the second gate 130 can be turned on (e.g., activated) to couple the bit line contact 140 to the contact 145. In this way, individual bit lines of the memory array coupled to the bit line contact 140 can be coupled to corresponding page buffers to read data from the memory cell of the bit line to the page buffer or write data from the page buffer to the memory cell of the bit line. In some embodiments, the low voltage can vary between about 0.5V (e.g., 0.5V ± 5%, 0.5V ± 10%, or the like) and about 2.4V (e.g., 2.4V ± 5%, 2.4V ± 10%, or the like) to support various operations specified in the datasheet of the memory device. Under specific operating conditions (such as test operations), low voltages can be achieved at approximately 3.6V (e.g., 3.6V ± 5%, 3.6V ± 10%, or the like).

[0028] During a second operation (e.g., an HV operation, an erase operation) of the memory device at a relatively high voltage (HV), a high voltage (e.g., an erase voltage of about 15V to about 25V) may be applied to the source contact 135. A first gate 125 may be turned on to couple the source voltage (i.e., the voltage at which the intermediate region 116 of the source contact 135 is located) to the bit line contact 140, allowing the erase voltage to be delivered to the memory array. Furthermore, a second gate 130 may be turned off (e.g., grounded, deactivated) to decouple the bit line contact 140 from the contact 145 to isolate the high voltage from the contact 145 (and thus isolate the high voltage from the page buffer coupled to the contact 145). In some embodiments, the high voltage may vary between about 10V (e.g., 10V ± 5%, 10V ± 10%, or the like) and about 35V (e.g., 35V ± 5%, 35V ± 10%, or the like). Therefore, in some embodiments, the thickness of the gate dielectric material of the second gate 130 can be sufficiently thick to maintain a high voltage across the gate dielectric material, for example, the thickness ranges from about 35 nanometers (nm) to about 45 nm. In this way, individual bit lines of the memory array can be coupled to the erase voltage, while the page buffer is isolated from the erase voltage.

[0029] Figure 1BThis is a layout of an isolation device 110 according to an embodiment of the present technology. The isolation device 110 is depicted having a width W and a length L. Furthermore, the physical dimensions of the isolation device 110 can be determined by specific architectural aspects of the memory array, such as the length L defined by the length of the memory plane. For example, the length L of the isolation device 110 can be determined based on the number of bit lines of the memory array supported by the isolation device 110. In this regard, the number of narrow active regions 120 along the length of the isolation device 110 can correspond to the number of bit lines of the memory array. In some embodiments, the length L can vary between about 1,000 micrometers (μm) and about 10,000 μm. However, the width W of the isolation device 110 can be relatively independent of the memory array architecture. In some embodiments, the width W can vary between about 5 μm and about 8 μm. Thus, the width W can be as referenced... Figure 1C and 2A The reduction is described in more detail in 2C.

[0030] Figure 1C This describes the layout of a pair of isolation devices 110 (also individually identified as isolation devices 110a and 110b) according to an embodiment of the present technology. Isolation devices 110a and 110b are positioned side-by-side such that active channels 120a and 120b are adjacent to each other. Furthermore, isolation devices 110a and 110b can operate in pairs. For example, second gates 130a and 130b can be biased together during operation of isolation devices 110a and 110b. Therefore, second gates 130a and 130b can be combined to form a reference... Figures 2A to 2C A common gate is described. Furthermore, active channels 120a and 120b can be interdigitated so that individual active channels 120a and 120b alternate. In this way, isolation devices 110a and 110b can be closer to each other, such that the total width corresponding to isolation devices 110a and 110b (e.g., having interdigitated active channels and a common gate shared by the interdigitated active channels) can be less than the sum of the widths of the two individual isolation devices 110a and 110b (e.g., 2W).

[0031] In some embodiments, if the high voltage (e.g., erase voltage) coupled to bit line contact 140 during HV operation (e.g., erase operation) is distributed substantially across the LDD region 160 of the active channel 120, then the thickness of the gate dielectric material of the second gate 130 can be reduced. In other words, when the second gate 130 is deactivated (e.g., grounded) during HV operation, the electric field across the gate dielectric material can be reduced due to the voltage drop across the LDD region, allowing for a reduction in the thickness of the gate dielectric material. For example, the thickness of the gate dielectric material of the second gate 130 can be reduced to a thickness designed to support relatively low-voltage operation of the semiconductor device, for example, a thickness ranging from about 3.5 nm to about 7.5 nm, corresponding to 1.8 V to 3.3 V operations, respectively. The LDD region 160 refers to a portion of the active channel 120 between the bit line contact 140 (or the edge 118 of the outer region 117) and the edge of the second gate 130 facing the bit line contact 140.

[0032] In this respect, the width of the active channel 120 (in) Figure 1C The region denoted as Wch, which in some embodiments can vary between about 110 nm and about 150 nm, can be reduced (e.g., reduced to the minimum feature size of the memory device) to increase the resistance of the LDD region, thereby promoting a voltage drop across the LDD region. For example, the width of the active channel 120 can be reduced to about 100 nm (or less) corresponding to the minimum feature size of the active layer. Furthermore, reducing the gate oxide thickness promotes a reduction in the gate length of the second gate 130 (in... Figure 1C The active channel 120b, designated Lg, can vary between approximately 200 nm and approximately 500 nm in some embodiments, for example, without experiencing short-channel effects. Furthermore, the active channel 120b can be offset relative to the active channel 120a (e.g., shifted upwards or downwards) so that the active channels 120a and 120b can converge to form an interdigitated active channel. For example, the active channel 120b can be offset by the spacing between the active channels 120a and 120b (in... Figure 1C The reference numeral P (which in some embodiments may vary between approximately 400 nm and approximately 650 nm) represents half of this. Additionally, a common gate (e.g., a combination of second gates 130a and 130b) may be positioned above an interdigitated active channel, allowing active channels 120a and 120b to share a common gate, as shown in the reference. Figures 2A to 2C describe.

[0033] Figure 2A This describes the layouts 201 and 202 of a portion of the isolation device 210 according to an embodiment of the present technology. The isolation device 210 may be referenced. Figures 1A to 1C The described isolation device 110 is an example of or includes an aspect of the isolation device 110. Layouts 201 and 202 can be considered as Figure 1CRegion 170 of isolation devices 110a and 110b described herein has been modified to form interdigitated active channels and a common gate shared by the interdigitated active channels, thereby reducing the area occupied by isolation devices 110a and 110b. Layout 201 illustrates the active, gate, and contact layers that describe the various features of isolation device 210 having interdigitated active channels and a common gate. Layout 202 illustrates the implanted layers covering the active, gate, and contact layers of layout 201 to illustrate additional features of isolation device 210.

[0034] Layout 201 describes an active region 215 (also individually identified as 215a / b) comprising aspects of an active region 115, such as an intermediate region (not shown), an outer region 217 (also individually identified as 217a / b), and an edge 218 (also individually identified as 218a / b) of the outer region 217. The intermediate region of the active region 215 contains one or more source contacts (e.g., source contact 135, not shown in layout 201), and the outer region 217 contains bit line contacts 140 (also individually identified as 140a to e). The bit line contacts 140 can be considered as forming a plurality of columns of bit line contacts in the outer region 217.

[0035] Layout 201 also describes a set of interdigitated active channels including a set of first active channels 220a (one of which is identified as 220a1) and a set of second active channels 220b (one of which is identified as 220b1). The sets of first and second active channels 220a / b are respectively connected to the edge 218 of the outer region 217. Each of the first and second active channels 220a / b is aligned with a corresponding bit line contact 140 and extends in a first direction orthogonal to the sets of bit line contacts 140. As shown in layout 201, individual first active channels 220a and individual second active channels 220b alternate to form a set of interdigitated active channels between the outer regions 217a / b. In this respect, a set of second active channels 220b may have been offset by a distance relative to a set of first active channels 220a (e.g., shifted upwards or downwards in a direction orthogonal to the active channels 220), or vice versa. In some embodiments, the distance corresponds to half the spacing between the first active channels 220a (or the second active channels 220b). Figure 2A The denoted part is P, which in some embodiments may vary between about 400 nm and about 650 nm.

[0036] Furthermore, the first and second active channels 220a / b may have widths orthogonal to the first direction (in Figure 2AThe width, denoted as Wch, can vary between approximately 110 nm and approximately 150 nm in some embodiments. In some embodiments, the width corresponds to the minimum feature size of the semiconductor device, which may be based on the process technology node used to manufacture the semiconductor device. For example, the width may be approximately 100 nm (or less). As described above, an active channel 220 with a minimum width can facilitate the coupling of the LDD region distribution across the active channel 220 to the line contact 140 at high voltages (e.g., erase voltages), allowing the thickness of the gate dielectric material above the active channel 220a / b to be reduced, for example, to a thickness that supports relatively low-voltage operation of the semiconductor device.

[0037] The first and second active channels 220a / b include an end portion 221a / b for positioning contacts 145a / b. Contacts 145a / b may be coupled to a page buffer of a memory device. The end portion 221a / b is located away from the corresponding edge 218a / b of the outer region 217a / b and may have a dimension different from (e.g., larger than) the width (Wch) of the active channel. For example, the end portion 221a / b includes an active region end cap surrounding the contact 145a / b, such that the contact 145a / b is independent of statistical process variations (e.g., changes in the critical dimension (CD) of the contact 145a / b and / or the end portion 221a / b, registration fluctuations between the active layer and the contact layer) within the end cap of the end portion 221a / b.

[0038] Layout 201 illustrates a common gate 280 over a set of interdigitated active channels. The common gate 280 extends in a second direction parallel to a plurality of column bit line contacts 140 and is coupled to the set of interdigitated active channels via a gate dielectric material disposed between the common gate 280 and the interdigitated active channels. That is, the common gate 280 is shared by the first and second active channels 220a / b, for example, Figure 1C The two individual gates 130a / b depicted are combined to form a common gate 280. The common gate 280 is positioned between the two ends 221a and 221b of the opposing active channels 220a and 220b of the internal positioning contacts 145a / b.

[0039] Furthermore, the common gate 280 includes: a straight portion 281 having a width (in Figure 2A The designation Lw (which may vary between approximately 60 nm and approximately 200 nm in some embodiments); a set of first segments 282a extending from the first edge of the straight portion 281 parallel to the first direction by a distance (in Figure 2AThe first and second segments 282a / b are denoted by D (which may vary between approximately 200 nm and approximately 400 nm in some embodiments); and a set of second segments 282b extending parallel to the first direction from the second edge of the straight portion 281 by a distance (D), wherein the second edge is opposite to the first edge of the straight portion 281. Individual first and second segments 282a / b are positioned above corresponding first and second active channels 220a / b. The sum of the width Lw and the distance D determines the electrical channel length (denoted by Lg) of the first and second active channels 220a / b. As shown in layout 201, individual first segments 282a extend away from the edge 218a of the outer region 217a of the active region 215a (or extend towards the edge 218b of the outer region 217b of the active region 215b). Similarly, the individual second segments 282b extend away from the edge 218b of the outer region 217b of the active region 215b (or towards the edge 218a of the outer region 217a of the active region 215a). Thus, the common gate 280 can be viewed as a continuous gate feature with a "zigzag" or "zipper" pattern. In some embodiments, the width Lw of the straight portion 281 corresponds to the minimum feature size of the memory device. The width Lw at the minimum feature size (or larger) will provide a reliable bridge between the individual first and second segments 282a / b.

[0040] Layout 201 illustrates the gate 225 (also individually identified as 225a / b) above the active region 215. Gate 225 includes a reference... Figure 1A Aspects of the described gate 125. For example, gate 225a is positioned between one or more source contacts located in the middle region (not shown) of active region 215a and bit line contacts 140 (e.g., bit line contacts 140a to c) located in outer region 217a. Furthermore, gate 225 includes a plurality of protruding segments 227 (also individually identified as 227a / b) extending in a first direction through corresponding edges 218 of outer region 217. Individual protruding segments 227a / b are positioned between two adjacent bit line contacts 140 in the corresponding outer region; for example, bit line contacts 140a and 140b are separated by one of the protruding segments 227a, and bit line contacts 140d and 140e are separated by one of the protruding segments 227b. In this way, highlighting sections 227a / b can help electrically isolate individual bit line contacts 140 from adjacent bit line contacts 140 in the corresponding outer region 217 of the active region 215.

[0041] Layout 202 illustrates a first implantation layer 285 disposed on layout 201. The shielding region of the first implantation layer 285 corresponds to a photoresist material configured to block one or more dopant species during a first implantation process step. In some embodiments, the dopant species used for the first implantation step may comprise boron, indium, or other suitable p-type dopant, such as dopant exhibiting positive polarity upon ionization. In other embodiments, the dopant species used for the first implantation step may comprise phosphorus, arsenic, or other suitable n-type dopant, such as dopant exhibiting negative polarity upon ionization. Furthermore, the first implantation step can be implemented with an implantation capability sufficient to penetrate the gate (e.g., first gate 225, common gate 280) (if performed after gate formation) but insufficient to penetrate the photoresist material. Thus, areas of layout 202 not covered by the well implantation layer 285 will receive dopant species during the first implantation process step. Such uncovered areas include field regions (the white space corresponding to layout 202 of the STI isolation region), regions surrounding and including ends 221a / b (also including portions of segments 282a / b of the common gate 280 and portions of interdigitated active channels near segments 282a / b of the ends 221a / b, one of such regions being identified by box 286), and gate 225 including protruding segments 227 and portions of active regions 215 not covered by resist material (e.g., one of such portions of active regions 215 under the protruding segment 227 of gate 225 being identified by box 287).

[0042] The dopant species used in the first implantation step can be determined to increase the threshold voltage of the active region containing the dopant species. For example, a first implant in a portion of the interdigitated active channel near the ends 221a / b (and under segments 282a / b of the common gate 280) increases the threshold voltage of the common gate 280 (e.g., increases the local threshold voltage of the implanted portion), which in turn helps to avoid short-channel effects of the common gate 280. Similarly, a first implant in a portion of the active region 215 (e.g., the active region identified by block 287) under the protruding segment 227 of the gate 225 increases the threshold voltage of the protruding segment 227 of the gate 225, which in turn helps to electrically isolate bit line contacts (e.g., bit line contact 140b) from adjacent bit line contacts (e.g., bit line contacts 140a and / or 140c). In some embodiments, the first implantation step is performed with a p-type dopant species (e.g., boron, indium).

[0043] Furthermore, layout 202 illustrates the second implantation layer 290. Regions 290a and 290b correspond to regions without photoresist material during the second implantation process step, while most of region 290c is covered by photoresist material, except for the openings surrounding and including ends 221a / b; for example, one of such openings corresponds to block 286. The dopant species for the second implantation step includes species having the opposite polarity to the dopant species used in the first implantation step. The second implantation step can reduce the contact resistance between the active region open to the second implantation step and the contacts formed therein. For example, if the first implantation step is implemented with boron and / or indium atoms (e.g., p-type dopant), then the dopant species used in the second implantation step may include arsenic and / or phosphorus atoms (e.g., n-type dopant).

[0044] Layout 201 can be seen as being related to Figure 2B and 2C The layouts 203 and / or 205 described herein have a relatively high risk of current leakage compared to aggressively compact layouts. For example, the area occupied by layout 201 may be smaller than the area occupied by layouts 203 and / or 205. However, the risk associated with leakage current problems during HV operation may be greater for layout 201 than for layouts 203 and 205. In this regard, layout 201 illustrates two critical distances for leakage current (denoted as C1 and C1a). In some embodiments, C1a may vary between about 100 nm and about 400 nm, and C1 may vary between about 200 nm and about 500 nm.

[0045] During HV operation, bit line contacts (e.g., bit line contact 140e) are coupled to a high voltage (e.g., the erase voltage for a memory array) while contacts in the end 221a of the active channel 220a (e.g., contact 145a) remain at a low voltage (e.g., ground). Therefore, the shorter the critical distance C1, the higher the risk of leakage current associated with the high-voltage node (e.g., bit line contact 140 or the active region containing bit line contact 140) and the low-voltage node (e.g., contact 145 or the end 221a of the active channel).

[0046] Furthermore, since the low-voltage node is separated from the LDD region of the opposing active channel connected to the high-voltage node by a distance C1a, leakage current can occur between them. Additionally, the distance C1a can be less than the critical distance C1. However, as the high voltage of the bit line contact 140 decreases across the LDD region, the leakage current between the LDD region and the end of the opposing active channel is not as severe as the leakage current between the bit line contact 140 and the nearest contact 145 (although not zero in some cases).

[0047] Figure 2BThis describes layouts 203 and 204 of a portion of an isolation device 210 according to an embodiment of the present technology. Layouts 203 and 204 include references Figure 2A Various aspects of layouts 201 and 202 are described. Therefore, descriptions of common aspects between layouts 201 / 202 and 203 / 204 are omitted in layouts 203 / 204 to avoid repetition. Several aspects of layouts 203 and 204, different from layouts 201 and 202, include the overall shape of the common gate 280, the distance between the edges 218a / b of the active regions 225a / b, the critical distance between the high-voltage node and the low-voltage node (denoted as C2 in layout 203), the overall shape of the first implanted layer 285, and so on. For example, the distance between the edges 218a and 218b of layout 203 is greater than the distance between the edges of layout 201. Therefore, the critical distance C2 of layout 203 is greater than the critical distance C1 of layout 201. In some embodiments, C2 may vary between about 400 nm and about 600 nm, and C2a may vary between about 100 nm and about 400 nm.

[0048] The common gate 280 of layout 203 includes: a straight portion 281 having a width (in Figure 2B The designation Lw (which may vary between approximately 200 nm and approximately 400 nm in some embodiments); a set of first segments 282a extending from the first edge of the straight portion 281 parallel to the first direction by a distance (in Figure 2B The designation 203 is denoted by D (which may vary between approximately 50 nm and approximately 250 nm in some embodiments); and a set of second segments 282b extending parallel to the first direction from the second edge of the straight portion 281 by a distance (D), wherein the second edge is opposite to the first edge of the straight portion 281. The width Lw of the layout 203 may be greater than the width of the layout 201. For example, the width Lw of the layout 203 may be greater than the minimum feature size of the memory device. Furthermore, the distance D of the layout 203 may be less than the distance of the layout 201. The sum of the width Lw of the layout 203 and the distance D may be maintained the same as the sum of the width and distance of the layout 201.

[0049] Layout 203 can be considered as... Figure 2A and 2CThe layouts 201 and / or 205 described herein have a moderately compact layout with a moderate risk of current leakage compared to other layouts. For example, the area occupied by layout 203 may be larger than that occupied by layout 201, but smaller than that occupied by layout 205. Furthermore, the risk associated with leakage current during HV operation in layout 203 may be greater than that in layout 205, but less than that in layout 201. For example, the critical distance C2 is greater than the critical distance C1, such that the leakage current between the high-voltage nodes (e.g., bit line contact 140 or the active region containing bit line contact 140) and the low-voltage nodes (e.g., contact 145 or the end 221 of the opposing active channel) in layout 203 is expected to be less than that in layout 201. Moreover, although the distance C2a may be approximately equal to the distance C1a, the leakage current between the LDD region of layout 203 and the low-voltage nodes may be less than that in layout 201 because the high voltage of bit line contact 140 drops more across the LDD region due to the greater distance between the low-voltage and high-voltage nodes.

[0050] Figure 2C This describes layouts 205 and 206 of a portion of an isolation device 210 according to an embodiment of the present technology. Layouts 205 and 206 include references Figure 2A Various aspects of layouts 201 and 202 are described. Therefore, descriptions of common aspects between layouts 201 / 202 and 205 / 206 are omitted in layouts 205 / 206 to avoid repetition. Several aspects of layouts 205 and 206 that differ from layouts 201 and 202 include the overall shape of the common gate 280, the distance between the edges 218a / b of the active regions 225a / b, and the critical distance (in... Figure 2C The layout 205 is designated C3 (which may vary between approximately 450 nm and approximately 850 nm in some embodiments), the overall shape of the first implanted layer 285, etc. For example, the distance between edges 218a and 218b of layout 205 is greater than the distance between edges of layout 201 or layout 203. Therefore, the critical distance C3 of layout 205 is greater than the critical distance C1 of layout 201 or the critical distance C2 of layout 203.

[0051] The common gate 280 of layout 205 includes: a straight portion 281 having a width (in Figure 2C The designation Lw (which may vary between approximately 60 nm and approximately 400 nm in some embodiments); a set of first segments 282a extending from the first edge of the straight portion 281 parallel to the first direction by a distance (in Figure 2CThe first segment 282a extends towards the edge 218a of the outer region 217a of the active region 215a, and the second segment 282b extends from the second edge of the straight portion 281 parallel to the first direction by a distance (D), wherein the second edge is opposite to the first edge of the straight portion 281. Individual first segments 282a extend towards the edge 218a of the outer region 217a of the active region 215a, and individual second segments 282b extend towards the edge 218b of the outer region 217b of the active region 215b. Thus, the common gate 280 of layout 205 can be viewed as a continuous gate feature similar to the common gates of layouts 201 and 203 with a "zigzag" pattern, but in the opposite direction of the "zigzag" pattern. In some embodiments, the width Lw of layout 205 may be greater than the width of layout 201. In other embodiments, the width Lw of layout 205 may correspond to the minimum feature size of the memory device. The sum of the width Lw and the distance D of layout 205 can be kept the same as the sum of the width and distance of layout 201.

[0052] Layout 205 can be considered as... Figure 2A and 2B The layouts 201 and / or 203 described herein have a relatively low risk of current leakage compared to conservative, compact layouts. For example, the area occupied by layout 205 may be larger than that occupied by layout 201 or layout 203. However, the risk associated with leakage current during HV operation is less with layout 205 than with layout 201 or layout 203. For example, the critical distance C3 is greater than the critical distance C2 (or C1), such that the leakage current between the high-voltage nodes (e.g., bit line contact 140 or the active region containing bit line contact 140) and the low-voltage nodes (e.g., contact 145 or the end 221 of the opposing active channel) of layout 205 is expected to be less than that of layout 203 (or layout 201).

[0053] Furthermore, layout 205 depicts a contact (e.g., contact 145) grounded during HV operation positioned between two adjacent segments 282 of the common gate 280. Given the straight portion 281 of the common gate 280 near end 221, the low-voltage node (e.g., ground contact 145, end 221 containing ground contact 145) surrounds three sides, allowing for better isolation from the LDD region of adjacent active channels compared to layouts 201 and / or 203. Therefore, layout 205 is the least likely to have leakage current issues among layouts 201, 203, and 205.

[0054] The above references Figures 1A to 2C The memory device described in detail, or the package incorporating this memory device, can be incorporated into any of a variety of larger and / or more complex systems, a representative example of which is... Figure 3The system 380 is illustrated schematically. System 380 may include a processor 382, ​​memory 384 (e.g., SRAM, DRAM, flash, 3D NAND, 3D cross-connect, and / or other memory devices), input / output devices 386, and / or other subsystems or components 388. For example, memory 384 may include reference... Figures 1A to 2C The described isolation devices (e.g., isolation device 110, isolation device 210 with various modifications) are described. Thus, the memory device of memory 384 may include a high-voltage isolation device with an interdigitated active channel sharing a common gate. In some embodiments, the common gate is a continuous feature comprising a "zigzag" pattern. The memory device and / or a package incorporating such a memory device may be included in... Figure 3 Any of the elements shown in the document.

[0055] The resulting system 380 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 380 include (but are not limited to) computers and / or other data processors, such as desktop computers, laptop computers, internet devices, handheld devices (e.g., PDAs, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 380 include lights, cameras, vehicles, etc. Regarding these and other examples, system 380 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. Therefore, components of system 380 can include any of local and / or remote memory storage devices and various suitable computer-readable media.

[0056] It should be noted that the embodiments described above depict possible implementations, and various schemes for integrating the process steps and sequences of the embodiments may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more of the modified schemes may be combined. It should be understood from the foregoing that specific embodiments of the technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Additionally, although specific features or components have been shown to have specific arrangements or configurations in the illustrated embodiments, other arrangements and configurations are possible. Furthermore, certain aspects of the technology described in the context of specific embodiments may be combined with or eliminated from other embodiments.

[0057] Although isolation devices for semiconductor devices including 3D NAND flash memory have been described and illustrated in the foregoing exemplary embodiments, in other embodiments, the semiconductor device may have different types of memory arrays, such as 3D cross-point memory, DRAM, resistive memory, magnetic memory, ferroelectric memory, etc. Furthermore, this technique, which modifies the shape (design, layout) of various components (e.g., gate, active region, implantation layer) of the isolation device (or other integrated circuit system), can be applied to semiconductor devices other than memory devices to reduce the area occupied by the isolation device while mitigating the risks associated with leakage currents from compact and densely packed layouts.

[0058] The devices discussed herein (including semiconductor devices) can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, indium, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0059] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0060] As should be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Indeed, numerous specific details have been set forth in the foregoing description to provide a thorough and possible description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail so as not to obscure other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods, in addition to the specific embodiments disclosed herein, may also be within the scope of the present technology.

Claims

1. A semiconductor device comprising: an active region including an intermediate region having one or more source contacts and an outer region having a single column of bit line contacts; a plurality of interdigitated active channels including: 1) a plurality of first active channels connected to an edge of the outer region, wherein each of the first active channels is aligned with a corresponding bit line contact and extends in a first direction orthogonal to the single column of bit line contacts; and 2) a plurality of second active channels spaced apart from the edge of the outer region, wherein the second active channels are parallel to the first active channels such that individual first active channels alternate with individual second active channels; and a common gate over the plurality of interdigitated active channels, the common gate extending in a second direction parallel to the single column of bit line contacts and configured to couple with the plurality of interdigitated active channels.

2. The semiconductor device of claim 1, wherein the plurality of second active channels are offset from the plurality of first active channels in the second direction by a distance corresponding to half a pitch of the first active channels.

3. The semiconductor device of claim 1, wherein the first and second active channels have a width orthogonal to the first direction, the width corresponding to a minimum feature size of the semiconductor device.

4. The semiconductor device of claim 1, further comprising: a gate dielectric material between the common gate and the plurality of interdigitated active channels, a thickness of the gate dielectric material supporting a relatively low voltage operation of the semiconductor device.

5. The semiconductor device of claim 1, further comprising: a plurality of first contacts each positioned in a first end portion of the first active channels, the first end portions opposite the corresponding bit line contacts; and a plurality of second contacts each positioned in a second end portion of the second active channels, the second end portions proximate to the edge of the outer region.

6. The semiconductor device of claim 5, wherein: individual first contacts are connected to a corresponding first page buffer of the semiconductor device; and individual second contacts are connected to a corresponding second page buffer of the semiconductor device.

7. The semiconductor device of claim 5, wherein the common gate is positioned between the plurality of first contacts and the plurality of second contacts.

8. The semiconductor device of claim 5, wherein the common gate includes: a straight portion having a width orthogonal to the second direction; a plurality of first segments extending a distance parallel to the first direction from a first edge of the straight portion, wherein individual first segments are positioned over corresponding first active channels; and a plurality of second segments extending the distance parallel to the first direction from a second edge of the straight portion, the second edge opposite the first edge, wherein individual second segments are positioned over corresponding second active channels.

9. The semiconductor device of claim 8, wherein a combination of the distance and the width determines an electrical channel length of the first and second active channels.

10. The semiconductor device of claim 8, wherein: individual first segments extend away from the edges of the outer region of the active region; and individual second segments extend toward the edges of the outer region of the active region.

11. The semiconductor device of claim 8, wherein: individual first segments extend toward the edges of the outer region of the active region; and individual second segments extend away from the edges of the outer region of the active region.

12. The semiconductor device of claim 8, wherein: one or more first contacts are positioned between two adjacent second segments of the common gate; and one or more second contacts are positioned between two adjacent first segments of the common gate.

13. The semiconductor device of claim 8, wherein portions of the interdigitated active channels under the common gate include dopant atoms that increase a threshold voltage of the portions of the interdigitated active channels.

14. The semiconductor device of claim 1, further comprising: a gate over the active region and positioned between the one or more source contacts and the single column bit line contact, the gate extending in the second direction.

15. The semiconductor device of claim 14, wherein the gate comprises a plurality of protruding segments extending through the edges of the outer region in the first direction, individual protruding segments positioned between two adjacent bit line contacts.

16. The semiconductor device of claim 15, wherein portions of the outer region of the active region under the protruding segments of the gate include dopant atoms that increase a threshold voltage of the portions of the outer region.

17. A semiconductor device, comprising: an active region including a middle region with a column of source contacts and an outer region with a column of bit line contacts; a first gate over the active region, the first gate including: 1) a straight portion positioned between source contacts and bit line contacts of the column; and 2) a plurality of protruding segments connected to the straight portion, wherein individual protruding segments extend through edges of the outer region in a first direction orthogonal to the column bit line contacts and are positioned between two adjacent bit line contacts; a plurality of first active channels connected to the edges of the outer region, wherein each of the first active channels is aligned with a corresponding bit line contact and extends in the first direction; and a second gate over the plurality of first active channels, the second gate extending in a second direction parallel to the column bit line contacts.

18. The semiconductor device of claim 17, further comprising: a plurality of second active channels spaced apart from the edges of the outer region, each of the second active channels extending in the first direction, wherein: the plurality of first active channels and the plurality of second active channels form a plurality of interdigitated active channels such that individual first active channels alternate with individual second active channels; and the second gate is over the plurality of interdigitated active channels and is configured to couple with the plurality of interdigitated active channels.

19. A semiconductor device comprising: a first active region including a first intermediate region and a first outer region having a single column of first bit line contacts; a plurality of first active channels connected to edges of the first outer region, wherein each of the first active channels is aligned with a corresponding first bit line contact and extends in a first direction orthogonal to the single column of first bit line contacts; a second active region including a second intermediate region and a second outer region having a single column of second bit line contacts; a plurality of second active channels connected to edges of the second outer region, wherein each of the second active channels is aligned with a corresponding second bit line contact and extends in the first direction, and wherein: the first outer region faces the second outer region; and the plurality of first active channels and the plurality of second active channels form a plurality of interdigitated active channels such that individual first active channels alternate with individual second active channels; and a common gate over the plurality of interdigitated active channels, the common gate extending in a second direction parallel to the single column of first bit line contacts and configured to couple with the plurality of interdigitated active channels.

20. The semiconductor device of claim 19, wherein the first and second active channels have a width orthogonal to the first direction, the width corresponding to a minimum feature size of the semiconductor device.

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