Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate comprising a base and a device structure; a conductive layer located on the device structure; a composite layer located on the conductive layer, the composite layer comprising a first film layer; a dielectric layer located on the substrate, the dielectric layer having a first opening therein; a second opening located in the first film layer, the sidewalls of the second opening being recessed relative to the sidewalls of the first opening; and conductive plugs located within the first and second openings. By recessing the sidewalls of the second opening relative to the sidewalls of the first opening, the flow path of a planarization solution can be effectively increased during the planarization process to form the conductive plug, thereby reducing etching damage to the conductive layer caused by the planarization solution. Furthermore, the growth of the conductive plug within the second opening can be restricted, thereby making the structure formed by the conductive plug in the second opening more compact, further reducing damage caused by the planarization solution flowing into the conductive layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits, the circuit density inside the integrated circuits is getting higher and higher, and the number of components contained is also increasing. This development makes it impossible to provide enough area on the wafer surface to make the required interconnect lines.

[0003] To meet interconnect requirements as components shrink, multi-layer metal interconnects with two or more layers have become a common approach in very large-scale integrated circuit technology. Currently, conduction between different metal layers, or between a metal layer and a device in the substrate, is achieved through conductive plugs in dielectric layers between the metal layers or between the metal layer and the substrate.

[0004] Currently, the conductive plug manufactured by the selective tungsten growth process can effectively increase the volume of the conductive plug, thereby increasing the contact area at the bottom of the conductive plug, thereby achieving the purpose of reducing contact resistance.

[0005] However, the performance of the conductive plugs manufactured using the selective tungsten growth process in the prior art needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0007] To solve the above-mentioned problem, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a base and a device structure located on the substrate; a conductive layer located on the device structure; at least one composite layer located on the conductive layer, the composite layer comprising a first film layer located on the conductive layer; a dielectric layer located on the substrate, the dielectric layer covering the device structure and the composite layer, the dielectric layer having a first opening therein; a second opening located in the first film layer, the sidewalls of the second opening being recessed relative to the sidewalls of the first opening; and conductive plugs located in the first opening and the second opening.

[0008] Optionally, the composite layer further includes: a barrier layer located on the first film layer, the barrier layer having a third opening therein, a sidewall of the second opening being recessed relative to a sidewall of the third opening, and the conductive plug is also located in the third opening.

[0009] Optionally, the composite layer further includes: a second film layer located on the barrier layer, the second film layer having a fourth opening therein, a sidewall of the fourth opening being recessed relative to a sidewall of the third opening, and the conductive plug is also located in the fourth opening.

[0010] Optionally, the first film layer and the barrier layer are made of different materials; the second film layer and the barrier layer are made of different materials.

[0011] Optionally, the material of the first film layer includes aluminum nitride; the material of the second film layer includes aluminum nitride.

[0012] Optionally, the material of the barrier layer includes carbon-doped silicon nitride.

[0013] Optionally, the conductive plug is made of tungsten.

[0014] Optionally, the material of the conductive layer includes cobalt.

[0015] Optionally, the device structure includes a transistor structure.

[0016] Optionally, the transistor structure includes: a gate structure located on the substrate; and source-drain doped layers located in the substrate on both sides of the gate structure.

[0017] Optionally, the conductive layer is located on the source / drain doped layer or the gate structure.

[0018] Accordingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a base and a device structure located on the substrate; forming a conductive layer on the device structure; forming at least one composite layer on the conductive layer, the composite layer comprising a first film layer located on the conductive layer; forming a dielectric layer on the substrate, the dielectric layer covering the device structure and the composite layer, the dielectric layer having a first opening therein; forming a second opening in the first film layer, the sidewalls of the second opening being recessed relative to the sidewalls of the first opening; and forming conductive plugs in the first and second openings.

[0019] Optionally, the composite layer further includes: a barrier layer located on the first film layer, the barrier layer having a third opening therein, a sidewall of the second opening being recessed relative to a sidewall of the third opening, and the conductive plug is also located in the third opening.

[0020] Optionally, the composite layer further includes: a second film layer located on the barrier layer, the second film layer having a fourth opening therein, a sidewall of the fourth opening being recessed relative to a sidewall of the third opening, and the conductive plug is also located in the fourth opening.

[0021] Optionally, the first film layer and the barrier layer are made of different materials; the second film layer and the barrier layer are made of different materials.

[0022] Optionally, the material of the first film layer includes aluminum nitride; the material of the second film layer includes aluminum nitride.

[0023] Optionally, the material of the barrier layer includes carbon-doped silicon nitride.

[0024] Optionally, the process of forming the second opening includes an isotropic wet etching process.

[0025] Optionally, the process of forming the fourth opening includes an isotropic wet etching process.

[0026] Optionally, the process of forming the third opening includes an anisotropic dry etching process.

[0027] Optionally, the method for forming the conductive plug includes: forming an initial conductive plug in the first opening, the second opening, the third opening and the fourth opening, and on the top surface of the dielectric layer using a metal selective growth process; and flattening the initial conductive plug until the top surface of the dielectric layer is exposed to form the conductive plug.

[0028] Optionally, the conductive plug is made of tungsten.

[0029] Optionally, the planarization process includes a chemical mechanical polishing process.

[0030] Optionally, the material of the conductive layer includes cobalt.

[0031] Optionally, the device structure includes a transistor structure.

[0032] Optionally, the transistor structure includes: a gate structure located on the substrate; and source-drain doped layers located in the substrate on both sides of the gate structure.

[0033] Optionally, the conductive layer is located on the source / drain doped layer or the gate structure.

[0034] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0035] In the structure of the technical solution of the present invention, the sidewalls of the second opening located within the first film layer are recessed relative to the sidewalls of the first opening. This effectively increases the flow path of the planarization solution during the subsequent planarization process to form the conductive plug, thereby reducing etching damage to the conductive layer caused by the planarization solution. Furthermore, because the sidewalls of the second opening are recessed relative to the sidewalls of the first opening, the growth of the conductive plug within the second opening is restricted, thereby making the structure of the conductive plug formed in the second opening more compact, further reducing the flow of the planarization solution to the conductive layer and thereby reducing etching damage to the conductive layer caused by the planarization solution.

[0036] Furthermore, the composite layer further includes a barrier layer located on the first film layer, the barrier layer having a third opening therein, and the sidewalls of the second opening being recessed relative to the sidewalls of the third opening. The barrier layer further increases the flow path of the planarization solution, thereby reducing etching damage to the conductive layer caused by the planarization solution.

[0037] Furthermore, the composite layer also includes: a second film layer located on the barrier layer, the second film layer having a fourth opening, the sidewall of the fourth opening being recessed relative to the sidewall of the third opening, and the conductive plug being further located within the fourth opening. The second film layer further increases the flow path of the planarization solution, thereby reducing the etching damage to the conductive layer caused by the planarization solution. In addition, since the sidewall of the fourth opening is recessed relative to the sidewall of the third opening, the growth of the conductive plug within the fourth opening is restricted, thereby making the structure formed by the conductive plug in the fourth opening more compact, further reducing the flow of the planarization solution to the conductive layer, thereby reducing the etching damage to the conductive layer caused by the planarization solution.

[0038] In the formation method of the technical solution of the present invention, by forming a second opening in the first film layer, the sidewalls of the second opening are recessed relative to the sidewalls of the first opening. During the subsequent planarization process to form the conductive plug, the flow path of the planarization solution can be effectively increased, thereby reducing etching damage to the conductive layer caused by the planarization solution. In addition, because the sidewalls of the second opening are recessed relative to the sidewalls of the first opening, the growth of the conductive plug in the second opening is restricted, thereby making the structure of the conductive plug formed in the second opening more compact, further reducing the flow of the planarization solution to the conductive layer, and thus reducing etching damage to the conductive layer caused by the planarization solution.

[0039] Furthermore, the composite layer further includes a barrier layer located on the first film layer, the barrier layer having a third opening therein, and the sidewalls of the second opening being recessed relative to the sidewalls of the third opening. The barrier layer further increases the flow path of the planarization solution, thereby reducing etching damage to the conductive layer caused by the planarization solution.

[0040] Furthermore, the composite layer also includes: a second film layer located on the barrier layer, the second film layer having a fourth opening, the sidewall of the fourth opening being recessed relative to the sidewall of the third opening, and the conductive plug being further located within the fourth opening. The second film layer further increases the flow path of the planarization solution, thereby reducing the etching damage to the conductive layer caused by the planarization solution. In addition, since the sidewall of the fourth opening is recessed relative to the sidewall of the third opening, the growth of the conductive plug within the fourth opening is restricted, thereby making the structure formed by the conductive plug in the fourth opening more compact, further reducing the flow of the planarization solution to the conductive layer, thereby reducing the etching damage to the conductive layer caused by the planarization solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figures 1 to 2 It is a structural diagram of a semiconductor structure;

[0042] Figures 3 to 10 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0043] As described in the background art, the performance of conductive plugs manufactured using the selective tungsten growth process in the prior art needs to be improved, which will be described in detail below with reference to the accompanying drawings.

[0044] Please refer to Figure 1 , providing a substrate, the substrate including a base 100 and a device structure 101 located on the base 100; forming a conductive layer 102 on the device structure 101; forming a dielectric layer 103 on the substrate, the dielectric layer 103 covering the device structure 101 and the conductive layer 102; forming a conductive opening 104 in the dielectric layer 103, the conductive opening 104 exposing a portion of the top surface of the conductive layer 102.

[0045] Please refer to Figure 2 , forming an initial conductive plug (not shown) in the conductive opening 104 and on the top surface of the dielectric layer 103 ; and planarizing the initial conductive plug until the top surface of the dielectric layer 103 is exposed, thereby forming a conductive plug 105 .

[0046] In this embodiment, the initial conductive plug is formed by selective growth of metal tungsten. However, since tungsten can only grow on metal surfaces, the bonding between the initial conductive plug and the sidewalls of the conductive opening 104 is not very good, resulting in a gap between the initial conductive plug and the sidewalls of the conductive opening. During the process of planarizing the initial conductive plug using a chemical mechanical mask, the polishing alkaline solution used will flow along the sidewalls of the conductive opening 104 toward the conductive layer 102, thereby causing certain damage to the conductive layer 102, thereby reducing the contact between the conductive layer 102 and the conductive plug 105, and even causing the conductive plug 105 to completely lose contact with the conductive layer 102 (e.g., Figure 2 As shown in part A in FIG, the performance of the finally formed semiconductor structure is degraded.

[0047] On this basis, the present invention provides a semiconductor structure and a method for forming the same. By forming a second opening in the first film layer, the sidewalls of the second opening are recessed relative to the sidewalls of the first opening. During the subsequent planarization process to form the conductive plug, the flow path of the planarization solution can be effectively increased, thereby reducing etching damage to the conductive layer caused by the planarization solution. Furthermore, because the sidewalls of the second opening are recessed relative to the sidewalls of the first opening, the growth of the conductive plug within the second opening is restricted, thereby making the structure of the conductive plug formed in the second opening more compact, further reducing the flow of the planarization solution to the conductive layer, and thereby reducing etching damage to the conductive layer caused by the planarization solution.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] Figures 3 to 10 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0050] Please refer to Figure 3 , providing a substrate, the substrate including a base 200 and a device structure 201 located on the base 200.

[0051] In this embodiment, the substrate 200 has a plurality of mutually separated fins (not labeled), and an isolation layer (not labeled) covering a portion of the fins, wherein the top surface of the isolation layer is lower than the top surface of the fins. In other embodiments, the substrate may further have a plurality of active areas, with an isolation layer between adjacent active areas.

[0052] In this embodiment, the device structure 201 includes a transistor structure, which includes: a gate structure (not marked) located on the substrate, the gate structure spanning the fin and covering part of the sidewall and top surface of the fin; and a source-drain doping layer (not marked) located in the substrate on both sides of the gate structure.

[0053] Please refer to Figure 4 , forming a conductive layer 202 on the device structure 201 .

[0054] In this embodiment, the conductive layer 202 is located on the source-drain doped layer. In other embodiments, the conductive layer may also be located on the gate structure.

[0055] In this embodiment, the conductive layer 202 is made of cobalt.

[0056] Please refer to Figure 5 , at least one composite layer is formed on the conductive layer 202 , and the composite layer includes a first film layer 203 located on the conductive layer 202 .

[0057] In this embodiment, the composite layer further includes a barrier layer 204 located on the first film layer 203 .

[0058] In this embodiment, the composite layer further includes: a second film layer 205 located on the barrier layer 204 .

[0059] In this embodiment, the first film layer 203 and the barrier layer 204 are made of different materials; the second film layer 205 and the barrier layer 204 are made of different materials. By selecting different materials, the etching selectivity between the different film layers is increased during the subsequent etching process, thereby reducing damage to other film layers.

[0060] In this embodiment, the material of the first film layer 203 includes aluminum nitride; the material of the second film layer 205 includes aluminum nitride.

[0061] In this embodiment, the material of the barrier layer 204 includes carbon-doped silicon nitride.

[0062] Please refer to Figure 6 After the composite layer is formed, a dielectric layer 206 is formed on the substrate. The dielectric layer 206 covers the device structure 201 and the composite layer. The dielectric layer 206 has a first opening 207 therein.

[0063] In this embodiment, the method for forming the dielectric layer 206 includes: forming an initial dielectric layer (not shown) on the composite layer; forming a patterned layer (not shown) on the initial dielectric layer, wherein the patterned layer exposes a portion of the top surface of the initial dielectric layer; and etching the initial dielectric layer using the patterned layer as a mask until the top surface of the composite is exposed, thereby forming the dielectric layer 206.

[0064] In this embodiment, the material of the dielectric layer 206 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0065] After forming the dielectric layer 206, the process further includes: forming a second opening in the first film layer 203, wherein the sidewall of the second opening is recessed relative to the sidewall of the first opening 207; forming a third opening in the barrier layer 204, wherein the sidewall of the second opening is recessed relative to the sidewall of the third opening; and forming a fourth opening in the second film layer 205, wherein the sidewall of the fourth opening is recessed relative to the sidewall of the third opening. For the detailed formation process, please refer to Figures 7 to 9 .

[0066] Please refer to Figure 7 , the second film layer 205 is etched using the dielectric layer 206 as a mask to form the fourth opening 208 in the second film layer 205 .

[0067] In this embodiment, the fourth opening 208 is formed by an isotropic wet etching process.

[0068] Please refer to Figure 8 The barrier layer 204 is etched using the dielectric layer 206 and the second film layer 205 as masks to form the third opening 209 in the barrier layer 204 .

[0069] In this embodiment, the process of forming the third opening 209 includes an anisotropic dry etching process.

[0070] Please refer to Figure 9 The first film layer 203 is etched using the dielectric layer 206 , the second film layer 205 and the barrier layer 204 as masks to form the second opening 210 in the first film layer 203 .

[0071] In this embodiment, the second opening 210 is formed by an isotropic wet etching process.

[0072] In this embodiment, by forming the second opening 210 in the first film layer 203, the sidewalls of the second opening 210 are recessed relative to the sidewalls of the first opening 207. This effectively increases the flow path of the planarization solution during the subsequent planarization process to form the conductive plug, thereby reducing etching damage to the conductive layer caused by the planarization solution. Furthermore, because the sidewalls of the second opening 210 are recessed relative to the sidewalls of the first opening 207, the growth of the conductive plug within the second opening 210 is restricted, thereby making the structure of the conductive plug formed in the second opening 210 more compact, further reducing the flow of the planarization solution toward the conductive layer 202, and thereby reducing etching damage to the conductive layer 202 caused by the planarization solution.

[0073] The barrier layer 204 further increases the flow path of the planarization solution, thereby reducing the etching damage of the planarization solution to the conductive layer 202.

[0074] The second film layer 205 further increases the flow path of the planarization solution, thereby reducing etching damage to the conductive layer caused by the planarization solution. In addition, because the sidewalls of the fourth opening 208 are recessed relative to the sidewalls of the third opening 209, the growth of the conductive plug within the fourth opening 208 is restricted, thereby making the structure of the conductive plug formed in the fourth opening 208 more compact, further reducing the flow of the planarization solution to the conductive layer 202, and thus reducing etching damage to the conductive layer 202 caused by the planarization solution.

[0075] Please refer to Figure 10 , conductive plugs 211 are formed in the first opening 207 and the second opening 210 .

[0076] In this embodiment, the conductive plug 211 is also located in the third opening 209 and the fourth opening 208 .

[0077] In this embodiment, the method for forming the conductive plug 211 includes: forming an initial conductive plug (not shown) in the first opening 207, the second opening 210, the third opening 209, and the fourth opening 208, and on the top surface of the dielectric layer 206 using a metal selective growth process; and planarizing the initial conductive plug until the top surface of the dielectric layer 206 is exposed, thereby forming the conductive plug 211.

[0078] In this embodiment, the conductive plug 211 is made of tungsten.

[0079] In this embodiment, the planarization process includes a chemical mechanical polishing process.

[0080] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 10 , comprising: a substrate, the substrate comprising a base 200 and a device structure 201 located on the base 200; a conductive layer 202 located on the device structure 201; at least one composite layer located on the conductive layer 202, the composite layer comprising a first film layer 203 located on the conductive layer 202; a dielectric layer 206 located on the substrate, the dielectric layer 206 covering the device structure 201 and the composite layer, the dielectric layer 206 having a first opening 207 therein; a second opening 210 located in the first film layer 203, the sidewall of the second opening 210 being recessed relative to the sidewall of the first opening 207; and conductive plugs 211 located in the first opening 207 and the second opening 210.

[0081] In this embodiment, the sidewalls of the second opening 210 are recessed relative to the sidewalls of the first opening 207 through the second opening 210 located within the first film layer 203. This effectively increases the flow path of the planarization solution during the subsequent planarization process to form the conductive plug 211, thereby reducing etching damage to the conductive layer caused by the planarization solution. Furthermore, because the sidewalls of the second opening 210 are recessed relative to the sidewalls of the first opening 207, the growth of the conductive plug 211 within the second opening 210 is restricted, resulting in a denser structure of the conductive plug 211 within the second opening 210. This further reduces the flow of the planarization solution toward the conductive layer 202, thereby reducing etching damage to the conductive layer 202 caused by the planarization solution.

[0082] In this embodiment, the composite layer further includes a barrier layer 204 located on the first film layer 203. The barrier layer 204 defines a third opening 209. The sidewalls of the second opening 210 are recessed relative to the sidewalls of the third opening 209. The conductive plug 211 is also located within the third opening 209. The barrier layer 204 further increases the flow path of the planarization solution, thereby reducing etching damage to the conductive layer 202 caused by the planarization solution.

[0083] In this embodiment, the composite layer further includes a second film layer 205 positioned on the barrier layer 204. The second film layer 205 defines a fourth opening 208, with the sidewalls of the fourth opening 208 recessed relative to the sidewalls of the third opening 209. The conductive plug 211 is also positioned within the fourth opening 208. The second film layer 205 further increases the flow path of the planarization solution, thereby reducing etching damage to the conductive layer 202 caused by the planarization solution. Furthermore, because the sidewalls of the fourth opening 208 are recessed relative to the sidewalls of the third opening 209, the growth of the conductive plug 211 within the fourth opening 208 is restricted, resulting in a denser structure formed by the conductive plug 211 within the fourth opening 208. This further reduces the flow of the planarization solution toward the conductive layer 202, thereby reducing etching damage to the conductive layer 202 caused by the planarization solution.

[0084] In this embodiment, the first film layer 203 and the barrier layer 204 are made of different materials; the second film layer 205 and the barrier layer 204 are made of different materials.

[0085] In this embodiment, the material of the first film layer 203 includes aluminum nitride; the material of the second film layer 205 includes aluminum nitride.

[0086] In this embodiment, the material of the barrier layer 204 includes carbon-doped silicon nitride.

[0087] In this embodiment, the conductive plug 211 is made of tungsten.

[0088] In this embodiment, the material of the conductive layer 202 includes cobalt.

[0089] In this embodiment, the device structure 201 includes a transistor structure.

[0090] In this embodiment, the transistor structure includes: a gate structure located on the substrate 200; and source and drain doping layers located in the substrate on both sides of the gate structure.

[0091] In this embodiment, the conductive layer 202 is located on the source-drain doped layer. In other embodiments, the conductive layer may also be located on the gate structure.

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate, comprising a base and a device structure located on the base; a conductive layer located on the device structure; at least one composite layer located on the conductive layer, the composite layer comprising a first film layer located on the conductive layer; a dielectric layer located on the substrate, the dielectric layer covering the device structure and the composite layer, and having a first opening therein; a second opening located in the first film layer, wherein a sidewall of the second opening is recessed relative to a sidewall of the first opening; Conductive plugs located in the first opening and the second opening; wherein, The sidewall of the second opening is recessed relative to the sidewall of the first opening, so as to increase the flow path of the planarization solution and reduce etching damage of the planarization solution to the conductive layer during the process of forming the conductive plug by planarization.

2. The semiconductor structure according to claim 1, wherein: The composite layer further includes a barrier layer located on the first film layer, the barrier layer having a third opening therein, a sidewall of the second opening being recessed relative to a sidewall of the third opening, and the conductive plug is further located in the third opening.

3. The semiconductor structure according to claim 2, wherein: The composite layer further includes: a second film layer located on the barrier layer, the second film layer having a fourth opening therein, a sidewall of the fourth opening being recessed relative to a sidewall of the third opening, and the conductive plug is further located in the fourth opening.

4. The semiconductor structure according to claim 3, wherein: The first film layer and the barrier layer are made of different materials; the second film layer and the barrier layer are made of different materials.

5. The semiconductor structure according to claim 4, wherein: The material of the first film layer includes aluminum nitride; the material of the second film layer includes aluminum nitride.

6. The semiconductor structure according to claim 4, wherein: The material of the barrier layer includes carbon-doped silicon nitride.

7. The semiconductor structure according to claim 1, wherein: The conductive plug is made of tungsten.

8. The semiconductor structure according to claim 1, wherein: The conductive layer is made of cobalt.

9. The semiconductor structure according to claim 1, wherein: The device structure includes a transistor structure.

10. The semiconductor structure according to claim 9, wherein: The transistor structure includes: a gate structure located on the substrate; and source-drain doping layers located in the substrate on both sides of the gate structure.

11. The semiconductor structure according to claim 10, wherein: The conductive layer is located on the source / drain doped layer or the gate structure.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base and a device structure located on the base; forming a conductive layer on the device structure; forming at least one composite layer on the conductive layer, wherein the composite layer includes a first film layer located on the conductive layer; forming a dielectric layer on the substrate, the dielectric layer covering the device structure and the composite layer, and having a first opening in the dielectric layer; forming a second opening in the first film layer, wherein a sidewall of the second opening is recessed relative to a sidewall of the first opening; Conductive plugs are formed in the first opening and the second opening; wherein, The method for forming the conductive plug includes: forming an initial conductive plug in the first opening, the second opening, and on the top surface of the dielectric layer; performing a planarization process on the initial conductive plug until the top surface of the dielectric layer is exposed, thereby forming the conductive plug; The sidewall of the second opening is recessed relative to the sidewall of the first opening, so as to increase the flow path of the planarization solution and reduce etching damage of the planarization solution to the conductive layer during the process of forming the conductive plug by planarization.

13. The method for forming a semiconductor structure according to claim 12, wherein: The composite layer further includes a barrier layer located on the first film layer, the barrier layer having a third opening therein, a sidewall of the second opening being recessed relative to a sidewall of the third opening, and the conductive plug is further located in the third opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The composite layer further includes: a second film layer located on the barrier layer, the second film layer having a fourth opening therein, a sidewall of the fourth opening being recessed relative to a sidewall of the third opening, and the conductive plug is further located in the fourth opening.

15. The method for forming a semiconductor structure according to claim 14, wherein: The first film layer and the barrier layer are made of different materials; the second film layer and the barrier layer are made of different materials.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the first film layer includes aluminum nitride; the material of the second film layer includes aluminum nitride.

17. The method for forming a semiconductor structure according to claim 15, wherein: The material of the barrier layer includes carbon-doped silicon nitride.

18. The method for forming a semiconductor structure according to claim 12, wherein: The second opening is formed by an isotropic wet etching process.

19. The method for forming a semiconductor structure according to claim 14, wherein: The fourth opening is formed by an isotropic wet etching process.

20. The method for forming a semiconductor structure according to claim 13, wherein: The process of forming the third opening includes an anisotropic dry etching process.

21. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the conductive plug includes: forming an initial conductive plug in the first opening, the second opening, the third opening, and the fourth opening, and on the top surface of the dielectric layer using a metal selective growth process; and performing a planarization process on the initial conductive plug until the top surface of the dielectric layer is exposed, thereby forming the conductive plug.

22. The method for forming a semiconductor structure according to claim 12, wherein: The conductive plug is made of tungsten.

23. The method for forming a semiconductor structure according to claim 21, wherein: The planarization process includes a chemical mechanical polishing process.

24. The method for forming a semiconductor structure according to claim 12, wherein: The conductive layer is made of cobalt.

25. The method for forming a semiconductor structure according to claim 12, wherein: The device structure includes a transistor structure.

26. The method for forming a semiconductor structure according to claim 25, wherein: The transistor structure includes: a gate structure located on the substrate; and source-drain doping layers located in the substrate on both sides of the gate structure.

27. The method for forming a semiconductor structure according to claim 26, wherein: The conductive layer is located on the source / drain doped layer or the gate structure.

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