Electronic package and method of making the same

Abstract

An electronic package and a method of manufacturing the same includes at least one protective structure disposed between a first electronic element and a second electronic element on a carrier structure, so that stress generated inside the first electronic element and the second electronic element by a filler material formed on the carrier structure to cover the protective structure and contact the first and second electronic elements is reduced to avoid the first electronic element and the second electronic element from being broken, and the reliability of the electronic package is improved.

Description

Technical Field

[0001] This invention relates to an electronic package and its manufacturing method, and more particularly to an electronic package with a multi-chip package structure and its manufacturing method. Background Technology

[0002] With the evolution of technology, the demand trend for electronic products is moving towards heterogeneous integration, which has led to the rise of multi-chip package structures (MCM / MCP).

[0003] like Figure 1 The multi-chip package structure 1 shown herein is formed by bonding multiple semiconductor chips 11 to a package substrate 10 via multiple solder bumps 13, and then forming a package material 14 covering the multiple semiconductor chips 11. This encapsulates multiple semiconductor chips into a single chip, resulting in a higher I / O count, significantly increased processor processing power, and reduced signal transmission latency. This allows for applications in high-end products with high-density circuitry, high transmission speeds, high stack-up counts, and large-size designs.

[0004] However, in the existing multi-chip package structure 1, during packaging, the packaging material 14 may be formed at the corner of the semiconductor chip 11 or the edge of the non-functional surface 11b, and the packaging material 14 has a relatively large Young's modulus, which increases the internal stress of the semiconductor chip 11, causing stress concentration in the semiconductor chip 11, resulting in cracks in the packaging material 14 that extend to the semiconductor chip 11 and cause rupture, thus resulting in poor reliability of the multi-chip package structure 1.

[0005] Therefore, overcoming the problems of the existing technology has become an urgent issue that needs to be addressed. Summary of the Invention

[0006] In view of the various shortcomings of the prior art, the present invention provides an electronic package and its manufacturing method to improve the reliability of the electronic package.

[0007] The electronic package of the present invention includes: a carrier structure; a first electronic component and a second electronic component disposed at a distance on the carrier structure such that a space is formed between the first electronic component and the second electronic component; a protective structure disposed on the carrier structure and located between the first electronic component and the second electronic component; and a filler material formed on the carrier structure and in the space and covering the protective structure.

[0008] The present invention also provides a method for manufacturing an electronic package, comprising: disposing a first electronic component and a second electronic component at intervals on a carrier structure having a protective structure, wherein a space is formed between the first electronic component and the second electronic component, and the protective structure is located between the first electronic component and the second electronic component; and forming a filler material on the carrier structure such that the filler material covers the protective structure and is formed in the space.

[0009] In the aforementioned electronic package and its manufacturing method, the first electronic component and the second electronic component are electrically connected to the carrier structure.

[0010] In the aforementioned electronic packaging components and their manufacturing methods, the protective structure is a metal structure.

[0011] In the aforementioned electronic packaging components and their manufacturing methods, the protective structure is either mesh-like or baffle-like.

[0012] In the aforementioned electronic packaging component and its manufacturing method, the protective structure has at least one hollow portion that exposes the supporting structure.

[0013] In the aforementioned electronic package and its manufacturing method, the carrier structure has a plurality of electrical contact pads electrically connected to the first electronic component and / or the second electronic component, such that the height of the electrical contact pads relative to the surface of the carrier structure is greater than the height of the protective structure relative to the surface of the carrier structure.

[0014] In the aforementioned electronic package and its manufacturing method, the carrier structure defines a placement area and a peripheral area surrounding the placement area, such that the first electronic component and the second electronic component are located in the placement area, and the protective structure is also disposed on the peripheral area. For example, the area where the protective structure is disposed is larger than the area of ​​the first electronic component projected vertically onto the carrier structure and / or the area of ​​the second electronic component projected vertically onto the carrier structure.

[0015] The aforementioned electronic package and its manufacturing method further include forming a packaging layer on the carrier structure to cover the first electronic component and the second electronic component. For example, the first electronic component and / or the second electronic component are exposed in the packaging layer.

[0016] As can be seen from the above, in the electronic package and manufacturing method of the present invention, the protective structure is mainly disposed between the first electronic component and the second electronic component through the support structure to disperse the stress distribution, thereby reducing the stress generated by the filler material inside the first electronic component and the second electronic component. Therefore, compared with the prior art, the present invention can avoid the first electronic component and the second electronic component from cracking, thus improving the reliability of the electronic package. Attached Figure Description

[0017] Figure 1This is a cross-sectional schematic diagram of an existing multi-chip package structure.

[0018] Figures 2A to 2D This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of the present invention.

[0019] Figure 2A 'and Figure 2A "for Figure 2A Partial top view schematic diagrams of different embodiments.

[0020] Figure 2C 'and Figure 2C "for Figure 2C Enlarged cross-sectional views of different fields of view before the flip-chip reflow process.

[0021] Figure 2D 'for Figure 2D A cross-sectional schematic diagram of another embodiment.

[0022] Explanation of reference numerals in the attached figures

[0023] 1: Multi-chip package structure

[0024] 10: Packaging substrate

[0025] 11: Semiconductor chips

[0026] 11b, 21b, 22b: Non-acting surfaces

[0027] 13: Solder bumps

[0028] 14: Packaging materials

[0029] 2,2': Electronic package

[0030] 20: Load-bearing structure

[0031] 200: Electrical contact pad

[0032] 21: First electronic component

[0033] 21a, 22a: Surface of action

[0034] 21c,21c',22c,22c': Side view

[0035] 210, 220: Electrode pads

[0036] 211, 221: Conductive bumps

[0037] 22: Second electronic component

[0038] 23: Filler material

[0039] 24,24': Encapsulation layer

[0040] 25,25': Protective structure

[0041] 250: Openwork section

[0042] A: Crystal placement area

[0043] B: Outer Zone

[0044] D: Distance

[0045] h1, h2: Height

[0046] L: Width

[0047] S: Space

[0048] t: height difference. Detailed Implementation

[0049] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0050] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0051] Please see Figures 2A to 2D This is a cross-sectional schematic diagram of the manufacturing method of the electronic package 2 of the present invention.

[0052] like Figure 2A As shown, a load-bearing structure 20 is provided, and at least one protective structure 25, 25' is disposed on the load-bearing structure 20.

[0053] In this embodiment, the carrier structure 20 is a substrate with a core layer and a circuit structure, or a coreless circuit structure. For example, the circuit structure has at least one dielectric layer and a redistribution layer (RDL) formed on the dielectric layer. The redistribution layer can be made of copper, and the dielectric layer can be formed by coating with materials such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer, or other materials. However, in other embodiments, the carrier structure 20 can also be a semiconductor substrate with multiple through-silicon vias (TSVs) to serve as a through silicon interposer (TSI). It should be understood that the carrier structure 20 can also be other carrier units that can carry electronic components such as chips, such as lead frames, and is not limited to the above.

[0054] Furthermore, the carrier structure 20 defines a placement area A and a peripheral area B surrounding the placement area A. For example, the placement area A needs to be provided with the circuit redistribution layer, and the circuit redistribution layer forms a plurality of electrical contact pads 200 in the form of micropads (u-pads) on the surface of the placement area A, while the peripheral area B can be selectively configured with or without circuits as needed.

[0055] Furthermore, the protective structure 25 is disposed in the crystal placement area A, and the protective structure 25' can be configured on the peripheral area B as needed. For example, some of the protective structures 25' can be configured within the edge of the crystal placement area A. In other words, the protective structures 25, 25' can be installed on the supporting structure 20 except for the area where the circuit is laid, or the protective structures 25, 25' can be installed only in specific areas.

[0056] On the other hand, the protective structure 25, 25' is a metal structure, which can be as follows: Figure 2A The copper mesh shown is as follows. Figure 2A The image shows multiple copper blocks arranged at intervals (dams).

[0057] like Figure 2B As shown, at least one first electronic component 21 and at least one second electronic component 22 are disposed at intervals on the crystal placement area A of the support structure 20, and a space S is formed (defined) between the first electronic component 21 and the second electronic component 22, so that the protective structure 25 is located between the first electronic component 21 and the second electronic component 22.

[0058] In this embodiment, the first electronic component 21 is an active component, a passive component, a package structure, or a combination thereof. The active component is, for example, a semiconductor chip, while the passive component is, for example, a resistor, a capacitor, or an inductor. For example, the first electronic component 21 is a semiconductor chip having opposing active surfaces 21a and non-active surfaces 21b. The active surface 21a has a plurality of electrode pads 210, and conductive bumps 211 are formed on these electrode pads 210, so that the first electronic component 21 is connected and electrically connected to the electrical contact pads 200 of the carrier structure 20 via the conductive bumps 211 in a flip-chip manner.

[0059] Furthermore, the second electronic component 22 can be an active component, a passive component, a package structure, or a combination thereof, and the active component can be, for example, a semiconductor chip, while the passive component can be, for example, a resistor, capacitor, or inductor. For example, the second electronic component 22 is a semiconductor chip having opposing active surfaces 22a and non-active surfaces 22b. The active surface 22a has multiple electrode pads 220, and conductive bumps 221 are formed on these electrode pads 220, allowing the second electronic component 22 to be bonded and electrically connected to the electrical contact pads 200 of the carrier structure 20 via the conductive bumps 221 in a flip-chip manner. It should be understood that the first electronic component 21 and the second electronic component 22 are of the same type of electronic component (i.e., an active component), and their internal structures may be the same or different. Alternatively, the first electronic component 21 and the second electronic component 22 may also be of different types of electronic components. For example, the first electronic component 21 is a package structure, and the second electronic component 22 is an active component.

[0060] Furthermore, the protective structures 25, 25' can be arranged as needed between the working surface 21a of the first electronic component 21 and the supporting structure 20, and between the working surface 22a of the second electronic component 22 and the supporting structure 20. In other words, in addition to the supporting structure 20 being provided with the protective structure 25 in the space S, the first or second electronic component 21, 22 is also provided with the protective structure 25' between it and the supporting structure 20, and the supporting structure 20 is also provided in the peripheral area B.

[0061] like Figure 2C As shown, a filler 23 is formed between the support structure 20 and the first electronic component 21 and between the support structure 20 and the second electronic component 22, and the filler 23 covers the conductive bumps 211, 221 and the protective structure 25.

[0062] In this embodiment, the filler 23 is, for example, a primer, and it is also formed in the space S between the first electronic component 21 and the second electronic component 22. Specifically, the filler 23 extends to the side 21c of the first electronic component 21 corresponding to the space S and the side 22c of the second electronic component 22 corresponding to the space S due to capillary action. Therefore, the smaller the width L of the space S (i.e., the distance between the first electronic component 21 and the second electronic component 22) (or the smaller the distance), the more pronounced the capillary action of the filler 23 in the space S.

[0063] Furthermore, if the protective structure 25' is provided on the outer perimeter B, the filler material 23 can cover part of the protective structure 25' of the outer perimeter B.

[0064] In addition, such as Figure 2C As shown, the height h1 of the electrical contact pad 200 relative to the surface of the support structure 20 is greater than the height h2 of the protective structure 25' of the peripheral area B relative to the surface of the support structure 20, such as a height difference t of 3 micrometers (µm), to prevent the multiple conductive bumps 211, 221 near the peripheral area B from contacting the protective structure 25' and short-circuiting when combined with the electrical contact pad 200. It should be understood that the height h1 of the electrical contact pad 200 relative to the surface of the support structure 20 can also be greater than the height of the protective structure 25 corresponding to the location in the space S relative to the surface of the support structure 20.

[0065] like Figure 2D As shown, an encapsulation layer 24 is formed on the support structure 20 and in the space S to cover the first electronic component 21 and the second electronic component 22.

[0066] In this embodiment, the encapsulation layer 24 can fill the space S by lamination or molding. Specifically, the encapsulation layer 24 is first used to cover the non-functional surface 21b of the first electronic component 21 and the non-functional surface 22b of the second electronic component 22, and the encapsulation layer 24 is extended into the space S. Then, a portion of the material of the encapsulation layer 24 is removed by grinding or cutting (a portion of the material of the non-functional surface 21b of the first electronic component 21 and a portion of the material of the non-functional surface 22b of the second electronic component 22 can be removed as needed), so that the non-functional surface 21b of the first electronic component 21 and the non-functional surface 22b of the second electronic component 22 are flush with the upper surface of the encapsulation layer 24.

[0067] Furthermore, the Young's coefficient of the encapsulation layer 24 is smaller than that of the filler 23. For example, the encapsulation layer 24 is an insulating material, such as polyimide (PI), dry film, epoxy resin, molding compound, photoresist, or solder mask.

[0068] In another embodiment, such as Figure 2D As shown, the encapsulation layer 24 may also cover the non-functional surface 21b of the first electronic component 21 and the non-functional surface 22b of the second electronic component 22.

[0069] Therefore, the manufacturing method of the present invention uses the protective structure 25 disposed between the first electronic component 21 and the second electronic component 22 by the support structure 20 to avoid the problem of uneven stress distribution or stress concentration caused by the mismatch of the coefficient of thermal expansion (CTE) of the filler material 23. For example, the situation where the crack caused by excessive stress extends into the circuit redistribution layer of the support structure 20. Therefore, compared with the prior art, the present invention can avoid the electrical contact pad 200 from breaking and causing the electrical failure of the end product of the electronic package 2.

[0070] Furthermore, the protective structure 25, 25' has at least one openwork portion 250 that exposes the supporting structure 20 (e.g., Figure 2A The mesh shown is as follows: Figure 2A The gap shown in the figure facilitates the contact and bonding of the filler 23 with the support structure 20, thus preventing delamination between the protective structures 25, 25' and the support structure 20. It should be understood that because the filler 23 (base adhesive) has better adhesion to the dielectric layer (such as PI material) of the support structure 20, delamination between the protective structures 25, 25' and the dielectric layer (PI material) can be avoided.

[0071] Furthermore, by also deploying the protective structure 25' in the peripheral area B, the stress distribution can be more effectively dispersed (the stress is usually greatest at the corner of the chip), thus avoiding stress concentration at the corner of the placement area A (such as the first electronic component 21 and / or the second electronic component 22), thereby preventing the first electronic component 21 and / or the second electronic component 22 from breaking. For example, the distance D between the deployment area of ​​the protective structure 25' and the side 22c' of the second electronic component 22 corresponding to the peripheral area B (or the side 21c' of the first electronic component 21 corresponding to the peripheral area B) is at least 25 micrometers (µm), i.e., D ≥ 25 micrometers. Preferably, the area of ​​the protective structure 25, 25' (which is distributed in the crystal placement area A and the peripheral area B) is greater than the area of ​​the first electronic component 21 projected vertically onto the support structure 20 (such as the area of ​​the functional surface 21a, which is only distributed in the crystal placement area A) and / or the area of ​​the second electronic component 22 projected vertically onto the support structure 20 (such as the area of ​​the functional surface 22a, which is only distributed in the crystal placement area A).

[0072] The present invention also provides an electronic package 2,2', comprising: a carrier structure 20, a first electronic component 21 and a second electronic component 22, a protective structure 25 and a filler material 23.

[0073] The first electronic component 21 and the second electronic component 22 are spaced apart on the support structure 20, so that a space S is defined (formed) between the first electronic component 21 and the second electronic component 22.

[0074] The protective structure 25 is disposed on the supporting structure 20 and located between the first electronic component 21 and the second electronic component 22.

[0075] The filler material 23 is formed on the supporting structure 20 and in the space S and covers the protective structure 25.

[0076] In one embodiment, the first electronic component 21 and the second electronic component 22 are electrically connected to the support structure 20.

[0077] In one embodiment, the protective structure 25 is a metal structure.

[0078] In one embodiment, the protective structure 25 is mesh-like or block-like.

[0079] In one embodiment, the protective structure 25 has at least one openwork portion 250 that exposes the supporting structure 20.

[0080] In one embodiment, the support structure 20 has a plurality of electrical contact pads 200 electrically connected to the first electronic component 21 and / or the second electronic component 22, such that the height h1 of the electrical contact pads 200 relative to the surface of the support structure 20 is greater than the height h2 of the protective structures 25, 25' relative to the surface of the support structure 20.

[0081] In one embodiment, the support structure 20 defines a placement area A and a peripheral area B surrounding the placement area A, such that the first electronic component 21 and the second electronic component 22 are located in the placement area A, and the protective structure 25' is also disposed on the peripheral area B. For example, the area where the protective structures 25, 25' are arranged is larger than the area of ​​the first electronic component 21 projected vertically onto the support structure 20 and / or the area of ​​the second electronic component 22 projected vertically onto the support structure 20.

[0082] In one embodiment, the electronic package 2,2' further includes a packaging layer 24,24' formed on the carrier structure 20 to cover the first electronic component 21 and the second electronic component 22. For example, the first electronic component 21 and / or the second electronic component 22 are exposed in the packaging layer 24.

[0083] In summary, the electronic package and its manufacturing method of the present invention, by distributing the protective structure between the first electronic component and the second electronic component through the support structure, disperses the stress distribution, thereby reducing the stress generated by the filler material inside the first and second electronic components. Therefore, the present invention can prevent the first and second electronic components from cracking, thus improving the reliability of the electronic package.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. An electronic package, characterized in that, include: Load-bearing structure; The first electronic component and the second electronic component are disposed on the support structure at a distance, so that a space is formed between the first electronic component and the second electronic component; A protective structure is disposed on the supporting structure and located between the first electronic component and the second electronic component, and the protective structure has at least one open portion that exposes the supporting structure. as well as A filler material that is formed on the load-bearing structure and in the space and covers the protective structure.

2. The electronic package as described in claim 1, characterized in that, The first electronic component and the second electronic component are electrically connected to the support structure.

3. The electronic package as described in claim 1, characterized in that, The protective structure is made of metal.

4. The electronic package as described in claim 1, characterized in that, The protective structure is either mesh or block-shaped.

5. The electronic package as described in claim 1, characterized in that, The support structure has a plurality of electrical contact pads electrically connected to the first electronic component and / or the second electronic component, such that the height of the electrical contact pads relative to the surface of the support structure is greater than the height of the protective structure relative to the surface of the support structure.

6. The electronic package as claimed in claim 1, characterized in that, The support structure defines a crystal placement area and a peripheral area surrounding the crystal placement area, such that the first electronic component and the second electronic component are located in the crystal placement area, and the protective structure is also disposed on the peripheral area.

7. The electronic package as described in claim 6, characterized in that, The area covered by the protective structure is greater than the area of ​​the first electronic component projected vertically onto the supporting structure and / or the area of ​​the second electronic component projected vertically onto the supporting structure.

8. The electronic package as claimed in claim 1, characterized in that, The electronic package also includes an encapsulation layer formed on the carrier structure to cover the first electronic component and the second electronic component.

9. The electronic package as claimed in claim 8, characterized in that, The first electronic component and / or the second electronic component are exposed in the encapsulation layer.

10. A method for manufacturing an electronic package, characterized in that, include: A first electronic component and a second electronic component are spaced apart on a support structure with a protective structure, wherein a space is formed between the first electronic component and the second electronic component, and the protective structure is located between the first electronic component and the second electronic component and has at least one hollow portion that exposes the support structure. as well as A filler is formed on the load-bearing structure so that the filler covers the protective structure and is formed in the space.

11. The method for manufacturing an electronic package as described in claim 10, characterized in that, The first electronic component and the second electronic component are electrically connected to the support structure.

12. The method for manufacturing an electronic package as described in claim 10, characterized in that, The protective structure is made of metal.

13. The method for manufacturing an electronic package as described in claim 10, characterized in that, The protective structure is either mesh-like or block-like.

14. The method for manufacturing an electronic package as described in claim 10, characterized in that, The support structure has a plurality of electrical contact pads electrically connected to the first electronic component and / or the second electronic component, such that the height of the electrical contact pads relative to the surface of the support structure is greater than the height of the protective structure relative to the surface of the support structure.

15. The method for manufacturing an electronic package as described in claim 10, characterized in that, The support structure defines a crystal placement area and a peripheral area surrounding the crystal placement area, such that the first electronic component and the second electronic component are located in the crystal placement area, and the protective structure is also disposed on the peripheral area.

16. The method for manufacturing an electronic package as described in claim 15, characterized in that, The area covered by the protective structure is greater than the area of ​​the first electronic component projected vertically onto the supporting structure and / or the area of ​​the second electronic component projected vertically onto the supporting structure.

17. The method for manufacturing an electronic package as described in claim 10, characterized in that, The manufacturing process also includes forming an encapsulation layer on the carrier structure to cover the first electronic component and the second electronic component.

18. The method for manufacturing an electronic package as described in claim 17, characterized in that, The first electronic component and / or the second electronic component are exposed in the encapsulation layer.

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