Semiconductor components with hybrid fan-out and related methods and systems

Abstract

This application relates to semiconductor components with hybrid fan-out and related methods and systems. In one embodiment, at least one edge of a first semiconductor die is attached to a molding compound including a molded through-hole via (TMV). Conductive traces may be formed on a first side of the first semiconductor die, wherein the first side includes an integrated circuit system coupled to the conductive traces. Furthermore, conductive pads may be formed on a surface of the molding compound coplanar with the first side. The conductive pads are coupled to a first end of the TMV, wherein a second end of the TMV is coupled to a bonding wire connected to one or more second semiconductor dies carried by the first semiconductor die. Conductive bumps may be formed on the conductive traces and the conductive pads, thereby enabling the first semiconductor die and the molding compound attached thereto to be directly attached to a printed circuit board.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor components, and more specifically to hybrid fan-out for semiconductor components. Background Technology

[0002] Semiconductor packages typically include a semiconductor die (e.g., a memory chip, microprocessor chip, imager chip) mounted on a substrate and encased in a protective layer. The semiconductor die may include functional features, such as memory cells, processor circuitry, or imager devices, and bonding pads electrically connected to these functional features. The bonding pads can be electrically connected to corresponding conductive structures on the substrate, which can be coupled to terminals outside the protective layer, thereby enabling the semiconductor die to connect to higher-level circuitry.

[0003] Market pressures are increasingly driving semiconductor manufacturers to reduce the size of semiconductor packages to fit the space constraints of electronic devices. In some semiconductor packages, direct chip attachment methods (e.g., flip-chip bonding between the semiconductor die and substrate) can be used to reduce the package's footprint. Such direct chip attachment methods may include directly connecting multiple conductive pillars electrically coupled to the semiconductor die to corresponding conductive structures (e.g., conductive bumps) on the substrate. In some semiconductor packages, the thickness of the semiconductor die tends to be reduced to stack multiple dies without increasing the overall height of the semiconductor package. Summary of the Invention

[0004] In one aspect, this application relates to a semiconductor component comprising: a first semiconductor die including a first side having conductive traces and first conductive bumps connected to the conductive traces; a molding member attached to at least one edge of the first semiconductor die, the molding member including one or more molded through-vias (TMVs), wherein the molding member has a surface coplanar with the first side of the first semiconductor die, the surface having conductive pads connected to the one or more TMVs and second conductive bumps connected to the conductive pads; one or more second semiconductor dies attached to a second side of the first semiconductor die, the second side being opposite to the first side, wherein each second semiconductor die includes bonding pads; and bonding wires coupling the bonding pads of the one or more second semiconductor dies to the one or more TMVs.

[0005] In another aspect, this application relates to a method comprising: forming a molding material therein of a plurality of first semiconductor dies, wherein a first surface of the molding material is coplanar with a first side of the first semiconductor dies; forming conductive traces on the first side of the first semiconductor dies and forming conductive pads on the first surface of the molding material; removing a portion of the molding material to expose a second side of the first semiconductor dies, the second side being opposite to the first side, wherein the second surface of the molding material opposite to the first surface is coplanar with the second side due to the removal of the portion of the molding material; forming a molded through-hole (TMV) extending from the second surface, such that the TMV can be connected to the conductive pads formed on the first surface; and forming first conductive bumps on the conductive traces and forming second conductive bumps on the conductive pads connected to the TMVs.

[0006] On the other hand, this application relates to an apparatus comprising: a semiconductor die including a first side of an integrated circuit system having the semiconductor die, a conductive trace located on the first side and coupled to the integrated circuit system, and a first conductive bump connected to the conductive trace; and a molding member attached to at least one edge of the semiconductor die, the molding member including one or more molded through-holes (TMVs), wherein the molding member has a first surface coplanar with the first side of the first semiconductor die, a conductive lead pad located on the first surface and connected to a first end of the one or more TMVs, and a second conductive bump connected to the lead pad; wherein: the first conductive bump and the second conductive bump are configured to be directly coupled to a printed circuit board (PCB); and the one or more TMVs are configured to be coupled to a bonding wire at a second end of the TMV, the second end being opposite to the first end. Attached Figure Description

[0007] The following figures provide a better understanding of various aspects of this technology. The components in the figures are not necessarily drawn to scale. Rather, the focus is on clearly illustrating the principles of this technology.

[0008] Figure 1 This is a cross-sectional view of a semiconductor device assembly.

[0009] Figure 2 This is a cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology.

[0010] Figures 3A to 3I The illustration shows the stages of a process for forming a semiconductor device assembly according to an embodiment of the present technology.

[0011] Figure 4This is a schematic diagram illustrating a system including semiconductor device components constructed according to embodiments of the present technology.

[0012] Figure 5 This is a flowchart of a method for forming a semiconductor device assembly according to an embodiment of the present technology. Detailed Implementation

[0013] The following describes specific details of several embodiments of hybrid fan-out for semiconductor components and related systems and methods. Certain semiconductor packages may include multiple semiconductor dies (e.g., 3D NAND memory dies, DRAM dies, memory controllers, logic dies, etc.) within a specified physical dimension (e.g., footprint, height / thickness, which may be collectively referred to as form factor). In some embodiments, such a multi-die package (MDP) includes a package substrate on which the multiple semiconductor dies are attached. Furthermore, the MDP may include bonding wires connecting the semiconductor dies to the package substrate so that the semiconductor dies can communicate with higher-level circuitry by attaching the package substrate to conductive interconnects (e.g., ball grid arrays (BGAs)) on a printed circuit board (PCB).

[0014] Advanced semiconductor packaging technologies strive to increase memory capacity within a given form factor and / or provide a scalable (reduced) form factor without sacrificing memory capacity. In some embodiments, a greater number of memory dies can be attached to a package substrate to increase the memory capacity of a semiconductor assembly (also known as a semiconductor device assembly) while maintaining a certain form factor (e.g., assembly height). To this end, the thickness of the memory die can be reduced to facilitate the stacking of a greater number of memory dies. However, thinner semiconductor dies may fail to meet various physical and / or mechanical requirements (e.g., specifications for semiconductor die strength), leading to reliability and / or yield issues for the semiconductor assembly. Furthermore, given the increasing die size at advanced semiconductor technology nodes, thinning semiconductor dies is expected to become increasingly challenging.

[0015] This technology provides a semiconductor device without a packaging substrate, employing a hybrid fan-out scheme. Since the packaging substrate can occupy the majority of the total thickness of the semiconductor device, eliminating the packaging substrate allows for an increase in the thickness of the semiconductor die to meet physical and / or mechanical requirements, while maintaining a consistent thickness for the semiconductor device. Alternatively or additionally, eliminating the packaging substrate provides opportunities to scale the thickness of the semiconductor device. In other words, by eliminating the packaging substrate, its thickness can be appropriately allocated to strengthen the semiconductor die and / or reduce the overall thickness of the semiconductor device. Furthermore, by excluding third parties from designing and supplying the packaging substrate, eliminating the packaging substrate reduces manufacturing costs and simplifies the design of the semiconductor device.

[0016] As described in more detail herein, this technology provides a fan-out wafer-level packaging (WLP) integration scheme for attaching a molded part to at least one edge of a semiconductor die. Furthermore, conductive traces (e.g., redistribution layers (RDLs)) and conductive pads are formed on the active side of the semiconductor die (including one side of various integrated circuits and / or active features) and the corresponding side of the molded part, respectively. Subsequently, molded vias (TMVs) are formed in the molded part and connected to the conductive pads. In this way, the semiconductor die has a TMV (“fan-out TMV”) adjacent to at least one edge, thereby enabling the semiconductor die to replace the package substrate.

[0017] One or more semiconductor dies can be attached to the passive side (opposite to the active side) of a semiconductor die having a fan-out TMV. Each of these dies includes a bonding pad and is capable of forming bonding lines to couple the bonding pad to the fan-out TMV. Subsequently, the semiconductor die carrying one or more semiconductor dies and the molded component attached thereto can be attached to a PCB via conductive interconnects (e.g., BGAs) formed on conductive traces and conductive pads. Therefore, the semiconductor die (carrying one or more semiconductor dies) and the molded component (including the fan-out TMV) can be attached to a PCB without a package substrate. Furthermore, the semiconductor assembly can transmit and / or receive signals via the bonding lines and the fan-out TMV—thus realizing a hybrid fan-out scheme for semiconductor assemblies utilizing bonding lines and fan-out TMVs.

[0018] Figure 1This is a cross-sectional view of a semiconductor device assembly 100 mounted on a PCB 125. The semiconductor device assembly 100 includes a package substrate 105 attached to the PCB 125 via conductive structures 120 (e.g., BGA, solder balls). The package substrate 105 carries semiconductor dies 110 (e.g., four (4) semiconductor dies 110). The package substrate 105 further includes a plurality of substrate pads (one of which is described as substrate pad 107) coupled to bonding pads 112 of the semiconductor dies 110 via bonding lines 115. In this way, the semiconductor dies 110 transmit and / or receive signals via bonding lines 115. The package substrate 105 may include interconnects (not shown) coupling the substrate pads 107 to the conductive structures 120. In some embodiments, the package substrate 105 may be approximately 160 micrometers thick (T_ps = 160 μm), while the semiconductor dies 110 may be approximately 40 micrometers thick (T1 = 40 μm). Therefore, without considering the thickness of the conductive structure 120, the thickness of the semiconductor device assembly 100 is approximately 320 micrometers (T_PKG = 320 μm). In some embodiments, the 40 μm thick semiconductor die 110 may be an edge that meets die strength specifications but is subject to reliability and / or yield issues (e.g., due to semiconductor die breakage during packaging).

[0019] Figure 2 This is a cross-sectional view of a semiconductor device assembly 200 according to an embodiment of the present technology. The semiconductor device assembly 200 includes four semiconductor dies 210 stacked on top of each other (also individually identified as 210a-d). In some embodiments, the semiconductor dies 210 are structurally identical; for example, all four semiconductor dies 210 are structurally identical 3D NAND memory dies. However, the bottommost semiconductor die (semiconductor die 210a) is modified to include various structures that facilitate a hybrid fan-out scheme for the semiconductor device assembly 200. For example, semiconductor die 210a has conductive traces 235 formed on its first side 211. Furthermore, a molding compound 220 is attached to the edge of semiconductor die 210a, including one or more molded through-hole (TMV) 225. One end of the TMV is coupled to a conductive pad 230, and the opposite end is coupled to a bonding line 115. Furthermore, the semiconductor die 210a has conductive bumps 240 attached to conductive traces 235 (e.g., conductive bumps 240a) and conductive pads 230 (e.g., conductive bumps 240b), so that the semiconductor die 210a (and the molded part 220 attached thereto) can be directly attached to the PCB 125. Therefore, the semiconductor device assembly 200 does not include a packaging substrate (e.g., see reference 1). Figure 1 The described packaging substrate 105).

[0020] In some embodiments, the thickness of semiconductor die 210 is greater than the thickness of semiconductor die 110. For example, the thickness of semiconductor die 210 may be approximately 75 μm. Furthermore, in some embodiments, the thickness of conductive trace 235 and conductive pad 230 may be approximately 20 μm. Therefore, the thickness (T_PKG) of semiconductor device assembly 200 (excluding the thickness of conductive bump 240) can remain approximately the same as the thickness (T_PKG) of semiconductor device assembly 100, while the thickness of semiconductor die 210 is greater than the thickness of semiconductor die 110, for example, by approximately 35 μm (i.e., approximately 85%). Therefore, it is anticipated that semiconductor die 210 not only meets die strength specifications but also provides additional margin for those specifications.

[0021] Furthermore, as an example, if the thickness of semiconductor die 210 can be increased to approximately 60 μm to meet die strength specifications, the new thickness of semiconductor device assembly 200 will be reduced to approximately 260 μm, which is approximately 80% of the thickness (T_PKG) of semiconductor device assembly 100 (or semiconductor device assembly 200). In this way, the form factor of semiconductor device assembly 200 can be scaled compared to semiconductor device assembly 100 if needed. If the same form factor is maintained between semiconductor device assemblies 100 and 200, semiconductor device assembly 200 can accommodate five (5) semiconductor dies 210 instead of a stack of four (4) semiconductor dies 210, which in turn increases the memory capacity of semiconductor device assembly 200 by 25%.

[0022] In some embodiments, the semiconductor device assembly 200 includes a first semiconductor die (e.g., the bottommost semiconductor die 210a) having a first side 211 and a second side 212 opposite to the first side 211. The first side 211 may include conductive traces 235 (e.g., a redistribution layer (RDL) including copper) and first conductive bumps 240 (one of which is identified as 240a) connected to the conductive traces 235. Furthermore, the first side 211 of the first semiconductor die may include one or more integrated circuits (i.e., an integrated circuit system) of the first semiconductor die and may be referred to as the active side of the first semiconductor die. Similarly, the second side 212 may be referred to as the passive side of the first semiconductor die. Figure 2 As shown, the first semiconductor die is coupled to the PCB 125 via a conductive trace 235 and a first conductive bump 240 (e.g., conductive bump 240a), and the first side 211 of the first semiconductor die faces the PCB 125.

[0023] One or more edges of the first semiconductor die may be attached to the molding part 220 (e.g., as shown in the image). Figure 2 The molded parts 220 at the two edges shown (or connected thereto). Although in Figure 2 In a cross-sectional side view, the first semiconductor die is described as having two (2) molding elements 220, but the first semiconductor die may have one (1), three (3), or four (4) edges attached to the molding elements 220. In some embodiments, the first semiconductor die may be surrounded by the molding elements 220. Furthermore, the first semiconductor die and the molding elements 220 may have substantially the same thickness (e.g., within the range of ±3%, ±5%, or ±10%). Thus, the molding elements 220 have a first surface coplanar with a first side 211 of the first semiconductor die and a second surface coplanar with a second side 212 of the first semiconductor die. Each molding element 220 includes one or more TMVs 225 (e.g., fan-out TMVs), each TMV extending from the first surface of the molding element 220 to the second surface. Furthermore, the first surface of the molding element 220 has conductive pads 230 connected to the TMVs 225, which may also be referred to as landing pads of the TMVs 225. The conductive pad 230 is further connected to the second conductive bump 240 (one of which is identified as 240b).

[0024] The semiconductor device assembly 200 also includes one or more second semiconductor dies (e.g., semiconductor dies 210b-d) attached to a second side 212 of the first semiconductor die. Each individual second semiconductor die includes bonding pads 213 on its first side 211. The first side 211 of the second semiconductor die includes one or more integrated circuits coupled to the bonding pads 213. Figure 2 As described, the first side 211 of the second semiconductor die faces away from the first semiconductor die. The bonding pads 213 of the second semiconductor die are connected via bonding lines 115 (one of which is located in…). Figure 2 (As shown in the diagram) is coupled to TMV 225. In this way, the second semiconductor die can transmit and / or receive signals via a combination of bonding line 115 and TMV 225 – thus enabling hybrid fan-out of the semiconductor device assembly 200.

[0025] In some embodiments, the conductive trace 235 of the first semiconductor die is coupled to the conductive pad 230 of the molding compound 220. In this way, the first semiconductor die can send signals to / receive signals from other components attached to the PCB 125 via first and second conductive bumps (e.g., conductive bumps 240a and 240b). Similarly, the second semiconductor die can send signals to / receive signals from other components attached to the PCB 125 via first and second conductive bumps (e.g., conductive bumps 240a and 240b). Figure 2As shown, the first and second conductive bumps 240 (e.g., BGA, solder bumps, solder balls, etc.) are configured to directly couple the first semiconductor die (carrying the second semiconductor die) and the molding compound 220 to the PCB 125. Therefore, the packaging substrate 105 of the semiconductor device assembly 100 can be omitted in the semiconductor device assembly 200.

[0026] Although the semiconductor device assembly 200 is described and illustrated as comprising four (4) semiconductor dies in the foregoing exemplary embodiments, the present technology is not limited thereto. For example, the semiconductor device assembly 200 may include different numbers of semiconductor dies, such as two (2), three (3), five (5), eight (8), sixteen (16), or even more. Furthermore, the first semiconductor die (e.g., semiconductor die 210a) may be different from the second semiconductor die (e.g., semiconductor dies 210b-d). For example, the first semiconductor die may be a memory controller or logic die, while the second semiconductor die may be a 3D NAND memory die, or a DRAM die, etc.

[0027] Figures 3A to 3I The illustration shows the stages of a process for forming a semiconductor device assembly (e.g., semiconductor device assembly 200) according to an embodiment of the present technology. Figure 3A The figure illustrates a mold frame 350 with adhesive material 355. Furthermore, a first side 211 of the semiconductor die 210 (e.g., the bottommost die 210a of the semiconductor device assembly 200) can be attached to the mold frame 350 via adhesive material 355 (as indicated by arrows). In some embodiments, a portion of the semiconductor die 210 can be removed from a second side 212 (i.e., the passive side) before attaching the first side 211 of the semiconductor die 210 to the mold frame 350. For example, the thickness of the semiconductor die 210 can be reduced to a final thickness (e.g., T2 is 75 μm) or to an intermediate thickness greater than the final thickness (e.g., to reduce the risk of damaging the semiconductor die 210 during packaging), which can be achieved as shown in the reference... Figure 3E and 3F The subsequent process steps described further reduce the final thickness.

[0028] Figure 3B The illustration shows molding material 360 dispensed on a semiconductor die 210 attached to a mold frame 350. Furthermore, the molding material 360 is capable of curing under pressure (e.g., as in a wafer-level compression molding process), thereby enabling the molding material 360 to surround and attach to the semiconductor die 210.

[0029] Figure 3C The illustration shows cured molding material 360 separated from mold frame 350 (e.g., by dissolving adhesive material 355), in which semiconductor die 210 is located. Figure 3C In the middle, the molding material 360 of the semiconductor die 210 is relative to Figure 3B The molding material is flipped. Furthermore, the first surface 361 of the molding material 360 is coplanar with the first side 211 of the semiconductor die 210.

[0030] Figure 3D The figure shows the molding material 360 of the semiconductor die 210 after conductive traces 235 are formed on the first side 211 of the semiconductor die 210. Furthermore, conductive pads 230 have been formed on the first surface 361 of the molding material 360.

[0031] Figure 3E The diagram shows that the carrier substrate 365 has been attached to the conductive trace 235 and the conductive pad 230. Figure 3E In the middle, the molding material 360 of the semiconductor die 210 is relative to Figure 3D The molding material is flipped. Subsequently, a portion of the molding material 360 can be removed (e.g., using a back grinding process, chemical mechanical polishing (CMP) process, etc.), so that the molding material 360 and the semiconductor die 210 have approximately the same thickness (e.g., Figure 3F (as shown in the figure). In some embodiments, the thickness of the semiconductor die 210 is reduced to a final thickness (e.g., T1 = 75 μm).

[0032] Figure 3F This is a cross-sectional view of the molding material 360, including the semiconductor die 210, after a portion of the molding material 360 has been removed (and / or the thickness of the semiconductor die 210 has been reduced to its final thickness). As a result of removing a portion of the molding material 360, the second side 212 of the semiconductor die 210 is exposed. Furthermore, the second surface 362 of the molding material 360 is coplanar with the second side 212 of the semiconductor die 210. Figure 3F The illustration shows that a TMV 225 has been formed after a portion of the molding material 360 has been removed. In some embodiments, a laser drilling process can be used to form an opening extending from the second surface 362 to the first surface 361 of the molding material 360. The laser drilling process may terminate upon reaching a conductive pad 230 formed on the first surface 361 (which may also be referred to as a landing pad). The opening can then be filled with a conductive material (e.g., copper) to form the TMV. Alternatively or alternatively, a dry etching process can be used to form the opening in the molding material 360.

[0033] Figure 3G The figure illustrates the process after the carrier substrate 365 is separated (e.g., debonded), including... Figure 3F The molding material 360 of the semiconductor die 210 shown in the figure. Figure 3GIn the middle, the molding material 360 of the semiconductor die 210 is relative to Figure 3F The molding material was flipped over.

[0034] Figure 3H The diagram illustrates the process after the first conductive bumps (some of which are identified as 240a) have been formed on the conductive trace 235 (e.g., using a solder bump process). Figure 3G The molding material 360 of the semiconductor die 210. In addition, second conductive bumps (several of which are identified as 240b) have been formed on the conductive pads 230 connected to the TMV 225.

[0035] Figure 3I The illustration shows the process after the semiconductor die 210 has been singulated so that it can be used for further process steps to build a semiconductor device assembly 200, including... Figure 3H The molding material 360 of the semiconductor die 210. Various cutting techniques can be used to monomerize individual semiconductor dies 210, such as blade cutting, plasma cutting, or laser cutting. The monomerized first semiconductor die 210 includes at least one edge of a subset of portions having a TMV 225 attached to the molding material 360.

[0036] like Figure 3I As shown, a single semiconductor die 210 is monomerized to include a TMV 225 (“fan-out TMV”) in an attached molding material 220, which may be referred to as a monomerized fan-out TMV semiconductor die. The semiconductor die 210 includes a first side (e.g., first side 211) having an integrated circuit system of the semiconductor die 210, a conductive trace coupled to the integrated circuit system (e.g., conductive trace 235), and a first conductive bump (e.g., conductive bump 240a) connected to the conductive trace. At least one edge of the semiconductor die 210 is attached to a molding part (e.g., molding part 220) including one or more TMVs (e.g., TMV 225). Furthermore, the molding part has a first surface coplanar with the first side of the first semiconductor die 210, conductive pads (e.g., conductive pads 230) connected to the first ends of one or more TMVs, and second conductive bumps (e.g., conductive bump 240b) connected to the conductive pads. Furthermore, one or more TMVs are configured to be coupled to a bonding line (e.g., bonding line 115) at a second end of the TMV, the second end being opposite to the first end. First and second conductive bumps (e.g., conductive bumps 240a / b) are configured to be directly coupled to a printed circuit board (e.g., PCB 125), allowing the individualized fan-out TMV semiconductor die to be directly attached to the PCB.

[0037] Subsequently, one or more second semiconductor dies (e.g., reference) Figure 2The described semiconductor dies 210b-d can be attached to a second side 212 of the separate semiconductor die 210. One or more second semiconductor dies include bonding pads (e.g., bonding pads 213) on their active side, which faces away from the second side 212 of the separate semiconductor die 210. After the second semiconductor dies are attached to the semiconductor die 210, bonding lines (e.g., bonding lines 115) can be formed to couple the bonding pads of the second semiconductor dies to the TMV 225 of the molded part 220 attached to the separate semiconductor die 210. Thereafter, the separate semiconductor die 210 carrying one or more second semiconductor dies and the molded part 220 attached thereto can be attached to a PCB (e.g., PCB 125) via first and second conductive bumps (e.g., conductive bumps 240a / b).

[0038] Reference Figure 2-3I The described semiconductor die assembly 200 can be incorporated into any of a large number of larger and / or more complex systems, a representative example of which is... Figure 4 The system 470 is schematically illustrated. System 470 can include a semiconductor device assembly 200, a power supply 472, a driver 474, a processor 476, and / or other subsystems or components 478. Semiconductor device assembly 200 may include features substantially similar to the hybrid fan-out scheme described above. For example, the semiconductor die of semiconductor device assembly 200 may have increased thickness, which mitigates various problems limiting the yield and / or reliability of semiconductor device assembly 200, such as unreliability or inoperability of the semiconductor die due to failure to meet die strength specifications. Furthermore, semiconductor device assembly 200 may not include a packaging substrate. The resulting system 470 is capable of performing any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 470 may include, but are not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and electrical appliances. Components of system 470 may be housed in a single unit or distributed across multiple interconnected (e.g., via a communication network) units. Components of system 470 may also include remote devices and any of a variety of computer-readable media.

[0039] Figure 5 This is a flowchart 500 of a method for forming a semiconductor device assembly (e.g., semiconductor device assembly 200) according to an embodiment of the present technology. Flowchart 500 may include, as referenced... Figure 3A-3I The various aspects of the described method.

[0040] The method includes forming a molding material therein containing a plurality of first semiconductor dies, wherein a first surface of the molding material is coplanar with a first side of the first semiconductor dies (box 510). The method further includes forming conductive traces on the first side of the first semiconductor dies and forming conductive pads on the first surface of the molding material (box 515). The method further includes removing a portion of the molding material to expose a second side of the first semiconductor die, the second side being opposite to the first side, wherein the second surface of the molding material opposite to the first surface is coplanar with the second side due to the removal of a portion of the molding material (box 520). The method further includes forming molded vias (TMVs) extending from the second surface so that the TMVs can be connected to the conductive pads formed on the first surface (box 525). The method further includes forming first conductive bumps on the conductive traces and forming second conductive bumps on the conductive pads connected to the TMVs (box 530).

[0041] In some embodiments, the method may further include monomerizing individual first semiconductor dies from molding material such that each individual first semiconductor die includes at least one edge of a portion of the molding material attached to a subset of the TMV. In some embodiments, the method may further include attaching one or more second semiconductor dies to an exposed second side of an individual first semiconductor die, the one or more second semiconductor dies including bonding pads. In some embodiments, the method may further include forming bonding lines to couple the bonding pads to a subset of the TMV, thereby enabling one or more second semiconductor dies to transmit and / or receive signals via bonding lines coupled to a subset of the TMV. In some embodiments, the method may further include attaching a first semiconductor die carrying one or more second semiconductor dies to a printed circuit board (PCB) via first and second conductive bumps.

[0042] In some embodiments, forming the molding material therein of the first semiconductor die may further include attaching a first side of the first semiconductor die to a mold frame using an adhesive material, dispensing the molding material onto the first semiconductor die attached to the mold frame, curing the molding material while applying pressure to surround and attach the molding material to the first semiconductor die, and separating the cured molding material therein from the mold frame. In some embodiments, the method may further include removing a portion of the first semiconductor die from a second side of the first semiconductor die before attaching the first side of the first semiconductor die to the mold frame.

[0043] In some embodiments, removing a portion of the molding material may further include removing a portion of the first semiconductor die from a second side to reduce the thickness of the first semiconductor die to a predetermined thickness. In some embodiments, removing a portion of the molding material may further include attaching conductive traces on a first side of the first semiconductor die and conductive pads on a first surface of the molding material to a carrier substrate, and removing a portion of the molding material from a second surface of the molding material. In some embodiments, forming a TMV from the second surface of the molding material is performed when the first semiconductor die and the molding material are attached to the carrier substrate.

[0044] It should be noted that the methods described above depict possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods can be combined. It should also be understood that specific embodiments of the technology have been described herein for illustrative purposes, but various modifications can be made without departing from this disclosure.

[0045] The devices discussed herein, including semiconductor devices, can be formed on semiconductor substrates or dies, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping using various chemicals (including but not limited to phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0046] As used herein, the word "or," as used in the claims, or as in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of..."), indicates an inclusive list such that a list of, for example, at least one of A, B, or C, refers to A or B or C or AB or AC or BC or ABC (i.e., A and B as well as C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0047] Based on the foregoing, it should be understood that although specific embodiments of the invention have been described herein for illustrative purposes, various modifications can be made without departing from the scope of the invention. Rather, numerous specific details have been discussed in the preceding description to provide a thorough and feasible description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure can be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods besides the specific embodiments disclosed herein also fall within the scope of the present technology.

Claims

1. A semiconductor assembly comprising: a first semiconductor die including a first side having a conductive trace and a first conductive bump connected to the conductive trace; a mold member attached to at least one edge of the first semiconductor die, the mold member including one or more molded through vias (TMVs), wherein the mold member has a surface coplanar with the first side of the first semiconductor die, the surface having a conductive pad connected to the one or more TMVs and a second conductive bump connected to the conductive pad; one or more second semiconductor dies attached to a second side of the first semiconductor die, the second side opposite the first side, wherein an individual second semiconductor die includes a bond pad; and a bond wire directly coupling the bond pad of the one or more second semiconductor dies to the one or more TMVs.

2. The semiconductor assembly of claim 1, wherein the conductive trace is coupled to the conductive pad.

3. The semiconductor assembly of claim 1, wherein the first conductive bump and the second conductive bump are configured to be directly coupled to a printed circuit board (PCB) such that the first side of the first semiconductor die faces the PCB.

4. The semiconductor assembly of claim 1, wherein the bond pad of the second semiconductor die is located on a first side of the second semiconductor die that faces away from the first semiconductor die.

5. The semiconductor assembly of claim 1, wherein the one or more second semiconductor dies send and / or receive signals through a combination of the bond wire and the one or more TMVs.

6. The semiconductor assembly of claim 1, wherein: the first semiconductor die has a first thickness; and the mold member has a second thickness that is the same as the first thickness.

7. The semiconductor assembly of claim 1, wherein: the first semiconductor die has a first thickness; and the individual second semiconductor die has a second thickness that is the same as the first thickness.

8. The semiconductor assembly of claim 1, wherein the first semiconductor die is structurally identical to the one or more second semiconductor dies.

9. The semiconductor assembly of claim 1, wherein the first semiconductor die and the one or more second semiconductor dies are structurally identical 3-dimensional (3D) NAND memory dies.

10. A method of forming a semiconductor assembly comprising: forming a mold material in which a plurality of first semiconductor dies are located, wherein a first surface of the mold material is coplanar with a first side of the first semiconductor dies; forming a conductive trace on the first side of the first semiconductor dies and a conductive pad on the first surface of the mold material, respectively; removing a portion of the mold material to expose a second side of the first semiconductor dies, the second side opposite the first side, wherein a second surface of the mold material opposite the first surface is coplanar with the second side as a result of the removal of the portion of the mold material; forming a molded through via, TMV, extending from the second surface, enabling the TMV to be connected to the conductive pads formed on the first surface; forming a first conductive bump on the conductive traces and a second conductive bump on the conductive pads connected to the TMV, respectively; attaching one or more second semiconductor dies to the exposed second side of the individual first semiconductor dies, the one or more second semiconductor dies comprising bond pads; and forming bond wires to directly couple the bond pads with a subset of the TMVs, thereby enabling the one or more second semiconductor dies to send and / or receive signals through the bond wires coupled with the subset of the TMVs.

11. The method of claim 10, further comprising: singulating individual first semiconductor dies from the molded material, such that each individual first semiconductor die comprises at least one edge of a portion having the subset of the TMVs attached to the molded material.

12. The method of claim 11, further comprising: attaching the first semiconductor dies carrying the one or more second semiconductor dies to a printed circuit board, PCB, through the first conductive bumps and the second conductive bumps.

13. The method of claim 10, wherein forming the molded material in which the plurality of first semiconductor dies are located further comprises: attaching the first side of the first semiconductor dies to a mold frame through an adhesive material; dispensing the molded material on the first semiconductor dies attached to the mold frame; solidifying the molded material while applying pressure, such that the molded material surrounds and is attached on the first semiconductor dies; and separating the solidified molded material in which the first semiconductor dies are located from the mold frame.

14. The method of claim 13, further comprising: removing portions of the first semiconductor dies from the second side of the first semiconductor dies prior to attaching the first side of the first semiconductor dies to the mold frame.

15. The method of claim 10, wherein removing the portions of the molded material further comprises: removing portions of the first semiconductor dies from the second side of the first semiconductor dies to reduce a thickness of the first semiconductor dies to a predetermined thickness.

16. The method of claim 10, wherein removing the portions of the molded material further comprises: attaching the conductive traces on the first side of the first semiconductor dies and the conductive pads on the first surface of the molded material to a carrier substrate; and removing the portions of the molded material from the second surface of the molded material.

17. The method of claim 10, wherein forming the TMV from the second surface of the molded material is done while attaching the first semiconductor dies and the molded material to a carrier substrate.

18. A semiconductor assembly device comprising, wherein the device comprises: a first semiconductor die including a first side having integrated circuitry of the first semiconductor die, a conductive trace on the first side and coupled with the integrated circuitry, and a first conductive bump connected with the conductive trace; a mold member attached to at least one edge of the first semiconductor die, the mold member including one or more through-mold vias (TMVs), wherein the mold member has a first surface coplanar with the first side of the first semiconductor die, a conductive landing pad on the first surface and connected with a first end of the one or more TMVs, and a second conductive bump connected with the landing pad; and one or more second semiconductor dies attached to a second side of the first semiconductor die, the second side opposite the first side, wherein the individual second semiconductor dies include bond pads; wherein: the first conductive bump and the second conductive bump are configured to be directly coupled with a printed circuit board (PCB); and the one or more TMVs are configured to be directly coupled at a second end of the TMVs to the bond pads of the one or more second semiconductor dies by wire bonds, the second end opposite the first end.

Images