Layout structure

Abstract

The present invention provides a layout structure with extremely small additional parasitic value of capacitor and easy to integrate with other circuits. The layout structure is suitable for a signal format converter. The layout structure includes a first capacitor array and a second capacitor array. The first capacitor array is arranged on one side of a reference axis. The first capacitor array includes a plurality of first capacitor units. The plurality of first capacitor units form a plurality of first capacitors. The plurality of first capacitors respectively have a plurality of first capacitance values. The second capacitor array is arranged on the other side of the reference axis. The second capacitor array includes a plurality of second capacitor units. The plurality of second capacitor units form a plurality of second capacitors. The plurality of second capacitors respectively have a plurality of second capacitance values. The plurality of first capacitors respectively correspond to the plurality of second capacitors. Each first capacitor is symmetrical with each corresponding second capacitor on the reference axis or each first capacitor is symmetrical with each corresponding second capacitor on the reference axis. Each corresponding first capacitor has the same capacitance value as each second capacitor.

Description

Technical Field

[0001] The present invention relates to a layout structure, in particular to a layout structure with extremely small additional parasitic value of capacitance. Background Art

[0002] In today's semiconductor industry, capacitors are very important and basic components. Among them, the Metal-Oxide-Metal (MOM) capacitor structure is a common capacitor structure. Its basic design is to fill an insulating medium between the positive metal plate and the negative metal plate as two electrodes, so that the positive metal plate and the negative metal plate and the insulating medium therein can form a capacitor unit. Generally speaking, in the design of the capacitor structure, the unit capacitance value can be increased by reducing the thickness of the insulating medium between the electrodes or increasing the surface area of ​​the electrodes.

[0003] In addition, if a capacitor structure with parasitic capacitance is applied to an actual circuit, the parasitic capacitance formed by the metal plate will also affect the overall performance of the circuit. Therefore, how to reduce the parasitic capacitance that causes interference is also an important consideration in designing the capacitor structure. With the demand for semiconductor miniaturization, how to improve the capacitor structure under the existing process specifications to reduce the parasitic capacitance that causes interference has become an important research topic. In particular, for a circuit architecture composed of a large number of capacitors, parasitic capacitance directly affects the overall performance of the circuit.

[0004] For example, the architecture of a Successive Approximation Register (SAR) analog-to-digital converter (ADC) requires a capacitor array with a large number of capacitors. However, the design of the capacitor array often results in additional parasitic capacitance, which leads to capacitor mismatch of the SAR ADC, and thus makes the output result of the circuit unsatisfactory. In addition, when designing the capacitor array, the compact arrangement used to reduce the area used makes it difficult to integrate the capacitor array with other circuits. Summary of the invention

[0005] The present invention is directed to a layout structure, the additional parasitic value of the capacitance of the layout structure is extremely small.

[0006] According to an embodiment of the present invention, the layout structure is applicable to a signal format converter. The layout structure includes a first capacitor array and a second capacitor array. The first capacitor array is configured on one side of a reference axis. The first capacitor array includes a plurality of first capacitor units. The plurality of first capacitor units form a plurality of first capacitors. The plurality of first capacitors respectively have a plurality of first capacitance values. The second capacitor array is configured on the other side of the reference axis. The second capacitor array includes a plurality of second capacitor units. The plurality of second capacitor units form a plurality of second capacitors. The plurality of second capacitors respectively have a plurality of second capacitance values. The plurality of first capacitors respectively correspond to the plurality of second capacitors. Each first capacitor is symmetrical to each corresponding second capacitor with respect to the reference axis or each first capacitor is at the same distance from each corresponding second capacitor. Each corresponding first capacitor has the same capacitance value as each second capacitor.

[0007] According to the above, in the layout structure of the present invention, each first capacitor and each corresponding second capacitor are symmetrical about the reference axis or each first capacitor and each corresponding second capacitor are at the same distance, and each corresponding first capacitor and each second capacitor have the same capacitance value. Therefore, the layout structure of the present invention can match the capacitance of the SAR ADC, thereby making the circuit output an ideal result.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0010] Figure 1 A schematic diagram showing a layout structure of an embodiment of the present invention;

[0011] Figure 2 A schematic diagram showing a layout structure of an embodiment of the present invention;

[0012] Figure 3 A schematic diagram showing an implementation scheme of a layout structure of an embodiment of the present invention;

[0013] Figure 4 A schematic diagram showing an implementation scheme of a layout structure of an embodiment of the present invention;

[0014] Figure 5 A schematic diagram showing an implementation scheme of a layout structure of an embodiment of the present invention;

[0015] Figure 6 A schematic diagram showing a capacitor array according to an embodiment of the present invention;

[0016] Figure 7 A top view schematically shows a capacitor unit according to an embodiment of the present invention.

[0017] Description of Figure Numbers

[0018] 100, 200, 300, 400: layout structure;

[0019] 110, 210, 310, 410, 510: first capacitor array;

[0020] 111, 311, 411, 511: first capacitor;

[0021] 120, 220, 320, 420, 520: second capacitor array;

[0022] 121, 321, 421, 521: second capacitor;

[0023] 190, 290, 390, 490, 590: reference axis;

[0024] 231, 241: first side;

[0025] 232, 242: second side;

[0026] 233, 243, 333, 343, 433, 443, 533, 543: third side;

[0027] 234, 244: fourth side;

[0028] 271, 272, 273, 274, 275, 276: compensation capacitor block;

[0029] 280, 281, 282, 283, 284: redundant capacitor blocks;

[0030] 600: capacitor array;

[0031] B1, B2, B3, B4_1, B4_2, BC1, BC2, BD, BU1, BU2: lower electrodes;

[0032] C: capacitance value;

[0033] CC1: first compensation capacitor unit;

[0034] CC2: second compensation capacitor unit;

[0035] CD: redundant capacitor unit;

[0036] CU1: first capacitance unit;

[0037] CU2: second capacitance unit;

[0038] L1: first metal layer;

[0039] L2: second metal layer;

[0040] L3: The third metal layer;

[0041] L4: fourth metal layer;

[0042] STW: signal transmission wire;

[0043] T2, T3, T4, TC1, TC2, TD, TU1, TU2: upper electrode;

[0044] V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11: connecting through holes;

[0045] X, Y, Z: direction. DETAILED DESCRIPTION

[0046] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to indicate the same or similar parts. However, the present invention may be practiced in a variety of different forms and is not limited to the embodiments described below. In addition, the dimensions of the layers and components and the relative dimensions may be exaggerated in the drawings for clarity.

[0047] Please refer to Figure 1 , Figure 1 A schematic diagram of a layout structure of an embodiment of the present invention is shown. The layout structure 100 may include a first capacitor array 110 and a second capacitor array 120. Furthermore, the first capacitor array 110 may be configured on one side of a reference axis 190. Meanwhile, the second capacitor array 120 may be configured on the other side of the reference axis 190. Furthermore, the first capacitor array 110 may include a plurality of first capacitors 111, and the plurality of first capacitors 111 respectively have a plurality of different first capacitance values. Meanwhile, the second capacitor array 120 may include a plurality of second capacitors 121, and the plurality of second capacitors respectively have a plurality of different second capacitance values. In addition, each of the first capacitor 111 and the second capacitor 121 may be formed by a plurality of capacitor units (not shown). Regarding the implementation details of the capacitor units, see the following. Figure 6 and Figure 7 An example is provided for illustration, but the present invention is not limited thereto.

[0048] It should be noted that Figure 1 The first capacitor array 110 and the second capacitor array 120 may include three first capacitors and three second capacitors 121 respectively, but the number of the first capacitors 111 and the second capacitors 121 of the present invention is not limited thereto.

[0049] Furthermore, in the present embodiment, the plurality of first capacitors in the first capacitor array 110 are respectively opposite to the plurality of second capacitors in the second capacitor array 120. Each first capacitor 111 and each corresponding second capacitor 121 may be separated by the same distance L. Furthermore, each corresponding first capacitor 111 and each second capacitor 121 may have the same capacitance value. According to the design requirements, the shape of each first capacitor 111 may be a stepped shape, an L shape, a U shape or a rectangle, but the present invention is not limited thereto. Furthermore, the shape of each first capacitor 111 may be the same as the shape of each corresponding second capacitor 121.

[0050] In the layout operation, the designer may first complete the layout of the first capacitor array 110 on the first side of the reference axis 190 , and then layout the second capacitor array 120 on the second side of the reference axis 190 by duplicating and shifting the first capacitor array 110 .

[0051] It is worth noting that the first capacitor array 110 and the second capacitor array 120 can respectively form two rectangles of the same size. Specifically, the first capacitor array 110 is composed of a plurality of first capacitor units, and the second capacitor array 120 can be composed of a plurality of second capacitor units, and the first capacitor units and the second capacitor units here can be exactly the same. Moreover, the plurality of first capacitor units and the plurality of second capacitor units can respectively form a plurality of first capacitors 111 and a plurality of second capacitors 121. Finally, the plurality of first capacitors 111 can be arranged and combined into a rectangle, and the plurality of second capacitors 121 can be arranged and combined into another rectangle, and the two rectangles have the same size. For example, please refer to Figure 1 , a combination of the three first capacitors 111 can form a rectangle, and a combination of the three second capacitors 121 can form the same rectangle.

[0052] Incidentally, the plurality of first capacitance values ​​may form a first geometric progression. Meanwhile, the plurality of second capacitance values ​​may form a second geometric progression. Furthermore, the common ratio of the first geometric progression and the second geometric progression is the same. For example, the plurality of first capacitance values ​​and the second capacitance values ​​may be a geometric progression with a common ratio of 2, but the present invention is not limited thereto.

[0053] Please refer to the following Figure 2 , Figure 2 A schematic diagram showing a layout structure of an embodiment of the present invention. The layout structure 200 may include a first capacitor array 210, a second capacitor array 220, a compensation capacitor block 271, a compensation capacitor block 272, a compensation capacitor block 273, a compensation capacitor block 274, a compensation capacitor block 275, a compensation capacitor block 276, a redundant capacitor block 280, a redundant capacitor block 281, a redundant capacitor block 282, a redundant capacitor block 283, and a redundant capacitor block 284.

[0054] In this embodiment, the first capacitor array 210 may be disposed on one side of the reference axis 290. Meanwhile, the second capacitor array 220 may be disposed on the other side of the reference axis 290. Furthermore, the compensation capacitor block 271 may be disposed between the first side 231 of the first capacitor array 210 and the reference axis 290, wherein the first side 231 of the first capacitor array 210 may be adjacent to the reference axis 290. Meanwhile, the compensation capacitor block 272 may be disposed between the first side 241 of the second capacitor array 220 and the reference axis 290, wherein the first side 241 of the second capacitor array 220 may be adjacent to the reference axis 290.

[0055] Incidentally, the compensation capacitor block 271 may include a plurality of first compensation capacitor units (not shown), and the compensation capacitor block 272 may include a plurality of second compensation capacitor units (not shown). Moreover, each first compensation capacitor unit and each second compensation capacitor unit may have the same structure. In addition, in the present embodiment, each first compensation capacitor unit may also have the same structure as the capacitor units constituting the first capacitor array 210 and the second capacitor array 220.

[0056] In this embodiment, the redundant capacitor block 280 may be disposed between the compensation capacitor block 271 and the compensation capacitor block 272. Furthermore, the redundant capacitor block 280 may include a plurality of redundant capacitor units (not shown).

[0057] In the present embodiment, the compensation capacitor block 273, the redundant capacitor block 281, and the compensation capacitor block 274 are sequentially disposed outside the second side 232 of the first capacitor array 210, wherein the first side 231 of the first capacitor array 210 is opposite to the second side 232 of the first capacitor array 210. Meanwhile, the compensation capacitor block 275, the redundant capacitor block 282, and the compensation capacitor block 276 are sequentially disposed outside the second side 242 of the second capacitor array 220, wherein the first side 241 of the second capacitor array 220 is opposite to the second side 242 of the second capacitor array 220.

[0058] In the present embodiment, the redundant capacitor block 283 is disposed along the first direction (direction Y) outside the third side 233 of the first capacitor array 210 and the third side 243 of the second capacitor array 220, wherein the first direction (direction Y) is orthogonal to the extension direction (direction X) of the reference axis. Meanwhile, the redundant capacitor block 284 is disposed along the first direction (direction Y) outside the fourth side 234 of the first capacitor array 210 and the fourth side 244 of the second capacitor array 220, wherein the fourth sides 234 and 244 are opposite to the third sides 233 and 243, respectively.

[0059] It is worth noting that the redundant capacitor block 283 and the redundant capacitor block 284 are used to reduce the impact of uneven metal layer caused by etching on the layout. In addition, the above-mentioned compensation capacitor can be set according to design requirements. In other words, without setting the compensation capacitor, the redundant capacitor block 283 and the redundant capacitor block 284 can be independently set on the outside of the third side 233, 243 and the fourth side 234, 244 of the first capacitor array 210 and the second capacitor array 220.

[0060] Please refer to the following Figure 3 , Figure 3 A schematic diagram of an implementation scheme of a layout structure of an embodiment of the present invention is shown. The layout structure 300 may include a first capacitor array 310, a second capacitor array 320, and a signal transmission wire STW. In addition, the first capacitor array 310 may include a plurality of first capacitors 311, and the first capacitor array 310 composed of the plurality of first capacitors 311 forms a rectangle. At the same time, the second capacitor array 320 may include a plurality of second capacitors 321, and the second capacitor array 320 composed of the plurality of second capacitors 321 forms the same rectangle. In this embodiment, the second capacitor array 320 can be obtained by copying the first capacitor array 310. That is, the second capacitor array 320 can be completed by translating the plurality of first capacitors 311 in the first capacitor array 310 from one side of the reference axis 390 to the other side of the reference axis 390 by a fixed distance, and the second capacitor array 320 is located on the other side of the reference axis. In addition, the plurality of signal transmission wires STW can be coupled to the plurality of first capacitors 311 and the plurality of second capacitors 321 by the third side 333 of the first capacitor array and the third side 343 of the second capacitor array, respectively.

[0061] It is worth noting that the first capacitor array 310 and the second capacitor 320 can be applied to the capacitor array of a successive approximation register analog-to-digital converter (not shown). For example, the analog-to-digital converter includes a capacitor array for converting to a positive bit, and the analog-to-digital converter includes a capacitor array for converting to a negative bit. The first capacitor array 310 and the second capacitor 320 can be a capacitor array for converting to a positive bit and a capacitor array for converting to a negative bit in the successive approximation register analog-to-digital converter, respectively. In addition, since the plurality of signal transmission wires STW can be coupled to the plurality of first capacitors 311 and the plurality of second capacitors 321 by the third side 333 of the first capacitor array and the third side 343 of the second capacitor array, respectively, the additional parasitic value of the capacitor is extremely small. In other words, the additional parasitic value of the capacitor of the successive approximation register analog-to-digital converter is extremely small, and an ideal conversion result can be output.

[0062] It should be noted that the plurality of first capacitors 311 in the first capacitor array 310 and the plurality of second capacitors 321 in the second capacitor array 320 may correspond to different bits in the successive approximation register analog-to-digital converter, respectively. For example, the first capacitor 311 with the largest area may correspond to the most significant bit (MSB) in the positive bit, and the first capacitor 311 with the smallest area may correspond to the least significant bit (LSB) in the positive bit. At the same time, the corresponding second capacitors 321 in the second capacitor array 320 may correspond to the most significant bit and the least significant bit in the negative bit, respectively.

[0063] Incidentally, since the most significant bit is dominant in the SAR ADC, the influence of the least significant bit can be ignored. Therefore, each first capacitor 311 with a larger area and each corresponding second capacitor 321 can be at the same distance, and each corresponding first capacitor 311 and each second capacitor 321 have the same capacitance value. However, according to design requirements, each first capacitor 311 and each second capacitor 321 with a smaller area can be separately arranged to achieve a simple layout.

[0064] Please refer to the following Figure 4 , Figure 4 A schematic diagram showing the implementation of the layout structure of an embodiment of the present invention is shown. Figure 3 and Figure 4 , Figure 4 and Figure 3 The difference is that the first capacitor array 410 and the second capacitor array 420 in the layout structure 400 are respectively composed of different Figure 3 4. The first capacitor 411 and the second capacitor 421 of the plurality of first capacitors 311 and the plurality of second capacitors 321 are composed of a plurality of first capacitors 411 and a plurality of second capacitors 421. Furthermore, another difference is that each first capacitor 411 and each corresponding second capacitor 421 can be symmetrical to the reference axis 490 at the same time. It is worth noting that the first capacitor array 410 and the second capacitor array 420 respectively composed of the plurality of first capacitors 411 and the plurality of second capacitors 421 form the same rectangle. In addition, the plurality of signal transmission wires STW can be coupled to the plurality of first capacitors 411 and the plurality of second capacitors 421 by the third side 433 of the first capacitor array and the third side 443 of the second capacitor array, respectively.

[0065] Please refer to the following Figure 5 , Figure 5 A schematic diagram showing the implementation of the layout structure of an embodiment of the present invention is shown. Figure 3 , Figure 4 as well as Figure 5 , Figure 5 and Figure 3 as well as Figure 4 The difference is that the first capacitor 511 of the first capacitor array 510 and the second capacitor 521 of the second capacitor array 520 in the layout structure 500 can both be U-shaped. Figure 4 , each first capacitor 511 and each corresponding second capacitor 521 can be symmetrical to the reference axis 590 at the same time. Moreover, the first capacitor array 510 and the second capacitor array 520 respectively formed by the plurality of first capacitors 511 and the plurality of second capacitors 521 form the same rectangle. In addition, the plurality of signal transmission wires STW can be coupled to the plurality of first capacitors 511 and the plurality of second capacitors 521 respectively by the third side 533 of the first capacitor array and the third side 543 of the second capacitor array.

[0066] Please refer to the following Figure 6 , Figure 6 A schematic diagram of a capacitor array according to an embodiment of the present invention is shown. The capacitor array 600 may include a first capacitor unit CU1, a second capacitor unit CU2, a first compensation capacitor unit CC1, a second compensation capacitor unit CC2, and a redundant capacitor unit CD. The first capacitor unit CU1 includes an upper electrode TU1 and a lower electrode BU1, wherein the upper electrode TU1 is coupled to a signal transmission wire (not shown) and the lower electrode BU1 is coupled to a ground terminal. The second capacitor unit CU1 includes an upper electrode TU2 and a lower electrode BU2, wherein the upper electrode TU2 is coupled to a signal transmission wire and the lower electrode BU2 is coupled to a ground terminal. The first compensation capacitor unit CC1 includes an upper electrode TC1 and a lower electrode BC1, wherein the upper electrode TC1 and the lower electrode BC1 are both coupled to a ground terminal. The second compensation capacitor unit CC2 includes an upper electrode TC2 and a lower electrode BC2, wherein the upper electrode TC2 and the lower electrode BC2 are both coupled to a ground terminal. The redundant capacitor unit CD includes an upper electrode TD and a lower electrode BD, wherein the upper electrode TD is coupled to a reference voltage terminal (not shown) and the lower electrode BD is coupled to a ground terminal.

[0067] In this way, the equivalent parasitic capacitances on the left and right sides of the upper electrode TU1 of the first capacitor unit CU1 are the same, and the equivalent parasitic capacitances on the left and right sides of the upper electrode TU2 of the second capacitor unit C2 are also the same. In addition, the capacitance value C can be respectively provided between the lower electrode BU2 of the rightmost second capacitor unit CU2 and the lower electrode TC1 of the first compensation capacitor unit. Therefore, through the above-mentioned configuration, the capacitance additional parasitic value of the capacitor array 600 can be made extremely small.

[0068] Please refer to the following Figure 7 , Figure 7A top view schematic diagram of a capacitor unit according to an embodiment of the present invention is shown. The capacitor unit includes a first metal layer L1, a second metal layer L2, a third metal layer L3 and a fourth metal layer L4. The second metal layer L2, the third metal layer L3 and the fourth metal layer L4 form an upper electrode of the capacitor unit 700. The first metal layer L1, the second metal layer L2, the third metal layer L3 and the fourth metal layer L4 form a lower electrode of the capacitor unit 700. The upper electrode and the lower electrode are electrodes with different polarities in the capacitor unit 700, respectively. For example, the upper electrode and the lower electrode may be electrodes with positive charge and negative charge, respectively, but are not limited thereto.

[0069] In the present embodiment, the first metal layer L1, the second metal layer L2, the third metal layer L3 and the fourth metal layer L4 are stacked in parallel on a substrate (not shown) in sequence along the direction Z. The first metal layer L1, the second metal layer L2, the third metal layer L3 and the fourth metal layer L4 may be separated by a dielectric material. For example, the dielectric material may be a material having a high dielectric constant characteristic such as silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0070] In this embodiment, the first metal layer L1 includes a patterned metal portion B1 of the lower electrode and connecting vias V1 and V2. The second metal layer L2 includes a patterned metal portion T2 of the upper electrode, a patterned metal portion B2 of the lower electrode, and connecting vias V3, V4, V5, V6, and V7. The third metal layer L3 includes a patterned metal portion T3 of the upper electrode, a patterned metal portion B3 of the lower electrode, and connecting vias V8, V9, V10, V11, and V12. The fourth metal layer L4 includes a patterned metal portion T4 of the upper electrode and patterned metal portions B4_1 and B4_2 of the lower electrode.

[0071] In this embodiment, the patterned metal parts B1, B2, B3, and B4 of the lower electrode can be electrically connected via a plurality of connecting through holes V1, V2, V5, V6, V7, V11, and V12, respectively. The patterned metal parts T2, T3, and T4 of the upper electrode can be electrically connected via a plurality of connecting through holes V3, V4, V8, V9, and V10, respectively. In this way, a capacitor can be formed between the upper electrode and the lower electrode of the capacitor unit 700. Also, please refer to Figure 6 and Figure 7 , a capacitor can be formed between the lower electrode and the upper electrode of the capacitor unit. Therefore, through the above configuration, the additional parasitic value of the capacitor unit 700 can be made extremely small.

[0072] It is worth noting that in Figure 7 In the embodiment of FIG. 7 , the capacitor unit 700 includes four metal layers, but the present invention is not limited thereto. In consideration of increasing or decreasing the capacitance value, the number of metal layers may be increased or decreased accordingly.

[0073] According to the above, in the layout structure of the present invention, each first capacitor and each corresponding second capacitor are symmetrical about the reference axis or each first capacitor and each corresponding second capacitor are at the same distance, and each corresponding first capacitor and each second capacitor have the same capacitance value. In addition, the first capacitor array and the second capacitor array form the same rectangle. Furthermore, in one embodiment of the present invention, multiple signal transmission wires can be coupled to multiple first capacitors and multiple second capacitors from the sides of the first capacitor array and the second capacitor array on the same side. In addition, in one embodiment of the present invention, each capacitor can be composed of specially arranged capacitor units. In this way, the additional parasitic value of the capacitor of the layout structure is extremely small and easy to integrate with other circuits.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A layout structure, suitable for a signal format converter, comprising: A first capacitor array is arranged on one side of the reference axis, the first capacitor array includes a plurality of first capacitor units, the plurality of first capacitor units form a plurality of first capacitors, and the plurality of first capacitors respectively have a plurality of first capacitance values; A second capacitor array is arranged on the other side of the reference axis, the second capacitor array includes a plurality of second capacitor units, the plurality of second capacitor units form a plurality of second capacitors, and the plurality of second capacitors respectively have a plurality of second capacitance values. The plurality of first capacitors correspond to the plurality of second capacitors respectively, each of the first capacitors and each of the corresponding second capacitors are symmetrical to the reference axis or each of the first capacitors and each of the corresponding second capacitors are at the same distance, and each of the corresponding first capacitors and each of the second capacitors have the same capacitance value; A first compensation capacitor block, wherein a first side of the first capacitor array is adjacent to the reference axis, and the first compensation capacitor block is disposed between the first side of the first capacitor array and the reference axis; and a second compensation capacitor block, wherein the first side of the second capacitor array is adjacent to the reference axis, and the second compensation capacitor block is disposed between the first side of the second capacitor array and the reference axis, The first compensation capacitor block includes a plurality of first compensation capacitor units, the second compensation capacitor block includes a plurality of second compensation capacitor units, and each of the first compensation capacitor units and each of the second compensation capacitor units have the same structure. 2 . The layout structure according to claim 1 , wherein the first capacitor array and the second capacitor array form the same rectangle.

3. The layout structure as claimed in claim 1, wherein the plurality of first capacitance values ​​form a first geometric progression, the plurality of second capacitance values ​​form a second geometric progression, and the first geometric progression and the second geometric progression have the same common ratio. 4 . The layout structure as claimed in claim 1 , wherein each of the plurality of first capacitor units and the plurality of second capacitor units has the same structure. 5 . The layout structure as claimed in claim 1 , wherein a shape of each of the first capacitors is a step shape, an L shape, a U shape or a rectangle, and a shape of each of the first capacitors is the same as a shape of each of the corresponding second capacitors.

6. The layout structure of claim 1, further comprising: The redundant capacitor block is arranged between the first compensation capacitor block and the second compensation capacitor block, and includes a plurality of redundant capacitor units.

7. The layout structure of claim 1, further comprising: A third compensation capacitor block, a first redundant capacitor block, and a fourth compensation capacitor block are sequentially arranged outside the second side of the first capacitor array, wherein the first side of the first capacitor array is opposite to the second side of the first capacitor array; as well as The fifth compensation capacitor block, the second redundant capacitor block and the sixth compensation capacitor block are sequentially arranged outside the second side of the second capacitor array, and the first side of the second capacitor array is opposite to the second side of the second capacitor array.

8. The layout structure of claim 1, further comprising: A third redundant capacitor block is arranged outside a third side of the first capacitor array and the second capacitor array along a first direction, wherein the first direction is orthogonal to an extension direction of the reference axis; as well as The fourth redundant capacitor block is disposed outside a fourth side of the first capacitor array and the second capacitor array along the first direction, wherein the fourth side is opposite to the third side.

9. The layout structure of claim 8, further comprising: A plurality of signal transmission wires are coupled to the plurality of first capacitors and the plurality of second capacitors from the third sides of the first capacitor array and the second capacitor array.

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