Semiconductor devices and methods

Abstract

The present disclosure relates to semiconductor devices and methods. A method of forming a semiconductor device having an improved work function layer and a semiconductor device formed by the method are disclosed. In one embodiment, a method includes depositing a gate dielectric layer over a channel region on a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and depositing a second p-type work function metal on the first p-type work function metal after performing the oxygen treatment.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and method. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a first channel region; a second channel region; and a gate structure surrounding the first channel region and the second channel region, the gate structure comprising: a gate dielectric; a first p-type work function metal located on the gate dielectric, the first p-type work function metal comprising oxygen, wherein a first portion of the first p-type work function metal surrounds the first channel region, and wherein a second portion of the first p-type work function metal is separated from the first portion of the first p-type work function metal and surrounds the second channel region; a second p-type work function metal located on the first p-type work function metal, the second p-type work function metal having a lower oxygen concentration than the first p-type work function metal, wherein a third portion of the second p-type work function metal surrounds the first channel region, and wherein a fourth portion of the second p-type work function metal is connected to the third portion and surrounds the second channel region; and a fill layer located on the second p-type work function metal.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a channel region; an interface layer located on the channel region; a high-k gate dielectric layer located on the interface layer; a first work function structure located on the high-k gate dielectric layer, the first work function structure comprising a plurality of first work function layers, each of the first work function layers comprising a first p-type work function material and oxygen, wherein the oxygen concentration in the first work function structure decreases with increasing distance from the high-k gate dielectric layer; an adhesion layer located on the first work function structure; and a fill layer located on the adhesion layer.

[0006] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: depositing a gate dielectric layer on a channel region above a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and depositing a second p-type work function metal on the first p-type work function metal after performing the oxygen treatment. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 Examples of nanostructured field-effect transistors (nano-FETs) are shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 22A and Figure 22B This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments.

[0010] Figure 18C The diagram shows secondary ion mass spectrometry (SIMS) plots of the dielectric layer and work function layer in an example gate stack according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0013] Various embodiments provide gate electrodes with improved work function structures and methods for forming the same. The work function structure can be formed by depositing a work function layer, exposing the work function layer to an oxygen-containing environment, and repeating this process until a sufficient thickness is obtained. The work function structure can be deposited on top of a gate dielectric layer. Exposing the work function layer to an oxygen-containing environment allows oxygen to diffuse into the work function layer and accumulate at the interface between the gate dielectric layer and the work function structure. The increased oxygen concentration in the work function structure and at the interface between the gate dielectric layer and the work function structure increases the effective work function of the device including the work function structure, and increases its flat-band voltage (V). fb ), and reduced its threshold voltage (V t This improved the device speed and performance.

[0014] Some of the embodiments discussed herein are described in the context of dies including nano-FETs. However, various embodiments can be applied to dies that replace or are combined with nano-FETs to include other types of transistors (e.g., FinFETs, or planar transistors, etc.).

[0015] Figure 1 An example of a nano-FET (e.g., a nanowire FET, or a nanosheet FET, etc.) according to some embodiments is shown in a three-dimensional view. The nano-FET includes nanostructures 55 (e.g., nanosheets, or nanowires, etc.) situated above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 act as channel regions of the nano-FET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are provided between adjacent fins 66, allowing the fins 66 to protrude above the adjacent STI regions 68. Although the STI regions 68 are described / shown as separated from the substrate 50, as used herein, the term "substrate" may refer only to the semiconductor substrate or a combination of the semiconductor substrate and the STI regions. Furthermore, although the bottom portions of the fins 66 are shown as a single continuous material with the substrate 50, the bottom portions of the fins 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68.

[0016] The gate dielectric 100 extends along the top and side surfaces of the fin 66, and along the top, side, and bottom surfaces of the nanostructure 55. The gate electrode 105 is located on the gate dielectric 100. An epitaxial source / drain region 92 is disposed on the fin 66 and located on the opposite side of the gate dielectric 100 and the gate electrode 105.

[0017] Figure 1 Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 105 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FinFET. Cross section B-B' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nano-FETs. Cross section C-C' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nano-FET fin 66 and in the current direction, for example, between the epitaxial source / drain regions 92 of the nano-FET. For clarity, the following figures refer to these reference cross sections.

[0018] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments are envisioned for use with planar devices such as planar FETs, or FinFETs.

[0019] Figures 2 to 22B This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 19C , Figure 20A , Figure 20C , Figure 21A and Figure 22A It shows Figure 1 The reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12B , Figure 12E , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 19D , Figure 20B , Figure 20D , Figure 21B and Figure 22B It shows Figure 1 The reference section B-B' is shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 12C and Figure 12D It shows Figure 1 The reference section C-C' is shown in the figure.

[0020] exist Figure 2 The image shows a substrate 50. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations of the foregoing.

[0021] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region 50P can be used to form p-type devices such as PMOS transistors, e.g., p-type nano-FETs. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0022] In addition, Figure 2In this process, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layer 51 is removed, and the second semiconductor layer 53 is patterned to form a channel region for a nano-FET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region for a nano-FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nano-FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nano-FET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region for a nano-FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nano-FET in both the n-type region 50N and the p-type region 50P.

[0023] For illustrative purposes, the multilayer stack 64 is shown as comprising three layers each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material (e.g., silicon germanium), and the second semiconductor layer 53 may be formed of a second semiconductor material (e.g., silicon, silicon carbon, etc.). For illustrative purposes, the multilayer stack 64 is shown as having a bottom semiconductor layer formed of a first semiconductor material. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is formed of a second semiconductor material.

[0024] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity to each other. This allows the first semiconductor layer 51 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nano-FET. Similarly, in embodiments where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nano-FET.

[0025] According to some embodiments, in Figure 3 In this process, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination of the foregoing. The etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55.

[0026] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fins 66 and nanostructures 55. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with spacing, for example, smaller than that achievable using a single direct photolithography process. In some embodiments, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66 and nanostructures 55.

[0027] For illustrative purposes, Figure 3The fins 66 in the n-type region 50N and p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be larger or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is shown to have a consistently consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of the fins 66 and / or nanostructures 55 continuously increases toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0028] exist Figure 4 In the substrate 50, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. Subsequently, a filler material as discussed above can be formed on the liner.

[0029] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof, can be used. The planarization process exposes the nanostructure 55 so that, after the planarization process is completed, the top surface of the nanostructure 55 and the insulating material are flush.

[0030] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 and nanostructures 55 in the n-type regions 50N and p-type regions 50P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI regions 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fins 66 and nanostructures 55). For example, it can be removed using an oxide, such as diluted hydrofluoric acid (dHF).

[0031] The above text is about Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes relative to the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the epitaxial growth material can be doped in situ during growth, which can avoid prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0032] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are illustrated and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. In some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N or may be formed in a different order.

[0033] In addition, Figure 4In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P can be achieved using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can be used as a mask to prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, or antimony, etc., implanted into the region, with a concentration ranging from about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0034] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, or indium, etc., implanted into the region, with a concentration ranging from approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0035] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, but in-situ and implantation doping can be used together.

[0036] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and the dummy dielectric layer 70 can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized (e.g., by CMP). The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0037] Figures 6A to 22B Various additional steps in manufacturing the embodiment device are shown. Figures 6A to 22B The characteristics of either the n-type region 50N or the p-type region 50P are shown. Figures 6A to 6C In this process, acceptable photolithography and etching techniques can be used to process mask layer 74 (see...). Figure 5 The mask 78 is patterned to form a dummy gate layer 72 and a dummy dielectric layer 70. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy gate dielectric layer 70 to form the dummy gate 76 and the dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66 and a portion of the channel region of the second nanostructure 54. The pattern of the mask 78 can be used to separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may have a length direction perpendicular to the length direction of the corresponding fin 66.

[0038] exist Figures 7A to 7C In Figures 6A to 6C A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to act as spacers for forming self-aligned source / drain regions. Figures 7A to 7CIn this process, a first spacer layer 80 is formed on the top surface of the STI region 68; the side surfaces of the fin 66, the dummy gate dielectric 71, and the dummy gate 76; and the top and side surfaces of the nanostructure 55 and the mask 78. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, or silicon oxynitride using techniques such as thermal oxidation or deposition via CVD or ALD. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, or silicon oxynitride, and the second spacer layer 82 can be deposited via CVD or ALD. The first spacer layer 80 and the second spacer layer 82 can include low-k dielectric materials.

[0039] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation can be performed for the lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the above... Figure 4 The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P. An impurity of an appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and exposed nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type region 50P while exposing the n-type region 50N. An impurity of an appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and exposed nanostructures 52 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have a doping density of 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0040] exist Figures 8A to 8CIn this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83, respectively. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used for the self-aligned source / drain regions subsequently formed and for protecting the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. Suitable etching processes can be used to etch the first spacer layer 80 and the second spacer layer 82, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can be used as an etch stop layer when the second spacer layer 82 is patterned. The second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 serves as an etch stop layer. The remaining portion of the second spacer layer 82 forms the second spacer 83, such as Figure 8B and Figure 8C As shown. Then, when etching the exposed portion of the first spacer layer 80 to form the first spacer 81, the second spacer 83 acts as a mask, as... Figure 8B and Figure 8C As shown.

[0041] like Figure 8B As shown, a first spacer 81 and a second spacer 83 are disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In some embodiments, the top surfaces of the first spacer 81 and the second spacer 83 may be configured to be lower than the top surface of the mask 78. The top surfaces of the first spacer 81 and the second spacer 83 may be configured to be flush with or higher than the top surface of the mask 78. In some embodiments, the second spacer 83 can be removed from the first spacer 81 that is adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71. Figure 8C As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55.

[0042] Note that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), and / or additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0043] exist Figures 9A to 9CIn this process, a first recess 87 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first recess 87. The first recess 87 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. In some embodiments, the top surface of the STI region 68 may be flush with the bottom surface of the first recess 87. In some embodiments, the top surface of the STI region 68 may be higher or lower than the bottom surface of the first recess 87. The first recess 87 can be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process such as RIE or NBE. During the etching process for forming the first recess 87, a first spacer 81, a second spacer 83, and a mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single-pass etching process or a multi-pass etching process. A timed etching process can be used to stop etching after the first recess 87 reaches a desired depth.

[0044] exist Figure 10A and Figure 10B In the process, portions of the sidewalls of the layer formed by the first semiconductor material (e.g., the first nanostructure 52) exposed by the first recess 87 in the multilayer stack 64 are etched to form sidewall recesses 88. Although in Figure 10B In this embodiment, the sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are shown as straight, but these sidewalls can be concave or convex. Isotropic etching processes, such as wet etching, can be used to etch the sidewalls. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, an etching process utilizing tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH) can be used to etch the sidewalls of the first nanostructure 52.

[0045] exist Figures 11A to 11C In the middle, a first internal spacer 90 is formed in the sidewall recess 88. This can be achieved by... Figure 10A and Figure 10B An internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. As will be discussed in detail below, the source / drain regions will be formed in the first recess 87, and the first nanostructure 52 will be replaced by the gate structure.

[0046] The internal spacer layer can be deposited using a conformal deposition process such as CVD or ALD. The internal spacer layer comprises materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k-value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer wall of the first internal spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the first internal spacer 90 may extend beyond or be recessed relative to the sidewall of the second nanostructure 54.

[0047] Furthermore, despite Figure 11B In the diagram, the outer wall of the first inner spacer 90 is shown as straight, but the outer wall of the first inner spacer 90 can be concave or convex. As an example, Figure 11C An embodiment is shown where the sidewalls of the first nanostructure 52 are concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed relative to the sidewalls of the second nanostructure 54. The internal spacer layer can be etched using anisotropic etching processes such as RIE or NBE. The first internal spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes for forming gate structures) from affecting the subsequently formed source / drain regions (e.g., hereinafter regarding...). Figures 12A to 12E The destruction of the epitaxial source / drain region (92) under discussion.

[0048] exist Figures 12A to 12E In this configuration, an epitaxial source / drain region 92 is formed in the first recess 87. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54, thereby improving performance. Figure 12B As shown, an epitaxial source / drain region 92 is formed in the first recess 87, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 and a second spacer 83 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76 by an appropriate lateral distance, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the first nanostructure 52 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit the gate subsequently formed in the resulting nano-FET.

[0049] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 87 of the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, or silicon phosphide. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have facets.

[0050] The epitaxial source / drain region 92 in the p-type region 50P (e.g., PMOS region) can be formed by masking the n-type region 50N (e.g., NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 87 of the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which compressive strain is applied to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, or germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have a facet.

[0051] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain region can be approximately 1 × 10⁻⁶. 19 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0052] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 92 of the same nano-FinFET to merge, such as... Figure 12CAs shown. In some embodiments, after the epitaxial process is completed, adjacent source / drain regions 92 remain separated, as shown. Figure 12D As shown. In Figure 12C and Figure 12D In the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68 and may block epitaxial growth. In some embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55, thereby further blocking epitaxial growth. In some embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, thereby allowing the epitaxial source / drain region 92 to extend to the top surface of the STI region 68.

[0053] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0054] Figure 12E One embodiment is shown in which the sidewalls of the first nanostructure 52 are concave and the outer sidewalls of the first internal spacer 90 are concave. The first internal spacer 90 is concave relative to the sidewalls of the second nanostructure 54. Figure 12E As shown, the epitaxial source / drain region 92 can be formed to contact the first internal spacer 90. The epitaxial source / drain region 92 can extend beyond the sidewalls of the second nanostructure 54.

[0055] exist Figure 13A and Figure 13B In the middle, the first interlayer dielectric (ILD) 96 is deposited on Figure 12A and Figure 12BThe structure shown is above the first ILD 96. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material having an etch rate different from that of the overlying first ILD 96, such as silicon nitride, silicon oxide, or silicon oxynitride, etc.

[0056] exist Figure 14A and Figure 14B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76, as well as a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0057] exist Figure 15A and Figure 15B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form a second recess 98. A portion of the dummy gate dielectric 71 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than etching the first ILD 96, CESL 94, first spacer 81, second spacer 83, nanostructure 55, or STI region 68. Each second recess 98 exposes and / or covers portions of the nanostructure 55 that serve as channel regions in the subsequently completed nano-FET. The portions of the nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer as the dummy gate 76 is etched. Then the dummy gate dielectric 71 can be removed after the dummy gate 76 is removed.

[0058] exist Figure 16A and Figure 16B In this process, the first nanostructure 52 is removed to extend the second recess 98. The first nanostructure 52 can be removed by performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A-54C comprise, for example, Si or SiC, the first nanostructure 52 can be removed using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH).

[0059] Figures 17A to 20D The diagram shows the gate dielectric 100 and gate electrode 105 for forming a replacement gate. Figures 19A to 20D The various steps are shown in the figure. The gate electrode 105 and the gate dielectric 100 can be collectively referred to as the "gate stack". Figure 17A , Figure 18A , Figure 19A and Figure 20A It shows Figure 16A Detailed view of area 101. Figure 17B , Figure 18B , Figure 19B and Figure 20B It shows Figure 16B Detailed view of area 103. Figure 17A and Figure 17B Features of either p-type region 50P or n-type region 50N are shown. Figures 18A to 19D Features in the p-type region 50P are shown, and Figure 20A and Figure 20D Features in the n-type region 50N are shown. The gate dielectric 100 and the gate electrode 105 may each include one or more sublayers, which will be discussed in detail below.

[0060] exist Figure 17A and Figure 17BAn interface layer 100A and a first dielectric layer 100B are formed in the process. The interface layer 100A and the first dielectric layer 100B can be collectively referred to as the gate dielectric 100. The interface layer 100A can be conformally formed or deposited in the second recess 98, for example, on the top and side surfaces of the fin 66 and the top, side, and bottom surfaces of the second nanostructure 54. The interface layer 100A can also be deposited on: the top surfaces of the first ILD 96, CESL 94, the second spacer 83, and the STI region 68; the top and side surfaces of the first spacer 81; and the side surface of the first internal spacer 90. The interface layer 100A can include a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON). The interface layer 100A can be formed by chemical oxidation, thermal oxidation, ALD, or CVD. The interface layer 100A can have approximately To date The thickness.

[0061] A first dielectric layer 100B can be deposited on the interface layer 100A using a conformal process. The first dielectric layer 100B can be a high dielectric constant (high k) material (e.g., a material with a k value greater than 7.0), such as hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (LaO2), titanium dioxide (TiO2), zirconium oxide (HfZrO2), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), combinations of the foregoing, or multilayers of the foregoing. The first dielectric layer 100B can be formed by ALD or CVD, etc. In some embodiments, the interface layer 100A can be omitted, and the first dielectric layer 100B can be directly deposited on the fin 66 and the second nanostructure 54. The first dielectric layer 100B can have a thickness of about 1 nm to about 3 nm.

[0062] The formation of the interface layer 100A and the first dielectric layer 100B in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric 100 in each region is formed of the same material. In some embodiments, the gate dielectric 100 in each region can be formed using different processes, such that the gate dielectric 100 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0063] exist Figure 18A and Figure 18B In this configuration, a first work function structure 102 is deposited on the gate dielectric 100 in the p-type region 50P. Depositing the first work function structure 102 in the p-type region 50P can mask the n-type region 50N. In some embodiments, the first work function structure 102 may include a p-type work function structure. For example... Figure 18A and Figure 18B As shown, the first work function structure 102 may include a first work function layer 102A, a second work function layer 102B, and a third work function layer 102C. Although the first work function structure 102 is shown as including three work function layers 102A-102C, the first work function structure 102 may include more or fewer layers.

[0064] The first work function layer 102A can be deposited on the first dielectric layer 100B using processes such as ALD, CVD, or PVD. In some embodiments, the first work function layer 102A may include a p-type work function metal or material. The first work function layer 102A may include a transition metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), or vanadium nitride (VN). In embodiments where the first work function layer 102A includes titanium nitride, the first work function layer 102A can be deposited using a thermal ALD process, which includes a titanium chloride (TiCl4) precursor and an ammonia (NH3) precursor, and is performed at a temperature of about 200°C to about 500°C and a pressure of about 0.5 Torr to about 40 Torr. The first work function layer 102A can be deposited to have a thickness of about 0.5 nm to about 2.5 nm.

[0065] After the first work function layer 102A is deposited, an oxygen exposure process (also known as oxygen treatment) can be performed on the first work function layer 102A. The first work function layer 102A can be deposited in a sealed chamber, and vacuum destruction can occur after the deposition of the first work function layer 102A. In some embodiments, the substrate 50 can be removed from the chamber where the first work function layer 102A was deposited after vacuum destruction. In some embodiments, the oxygen exposure process can be performed by exposing the first work function layer 102A to an oxygen-containing ambient environment, which oxidizes the first work function layer 102A. The oxygen-containing ambient environment can include an oxygen concentration of about 1 atomic percentage (at.%) to about 99 at.%. The first work function layer 102A can be exposed to the oxygen-containing ambient environment for about 2 hours to about 8 hours at a temperature of about 25°C to about 600°C and a pressure of about 0.1 Torr to about 500 Torr.

[0066] In some embodiments, the oxygen exposure process may include exposing the first work function layer 102A to an ozone-containing (O3) environment. The ozone-containing environment may include ozone at a concentration of about 1 at.% to about 99 at.%. In some embodiments, the first work function layer 102A may be exposed to a source gas, which may include ozone gas supplied along with a carrier gas. The carrier gas may include an inert gas, such as argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), radon (Rn), or combinations thereof, and may be supplied at a flow rate of about 500 sccm to about 8000 sccm. The first work function layer 102A may be exposed to the ozone-containing environment for about 10 seconds to about 300 seconds at a temperature of about 25°C to about 600°C and a pressure of about 0.1 Torr to about 500 Torr.

[0067] Performing an oxygen exposure process on the first work function layer 102A increases the oxygen concentration of the first work function layer 102A. For example, after the oxygen exposure process, the oxygen concentration in the first work function layer 102A can be from about 15 at.% to about 75 at.%, or from about 50 at.% to about 60 at.%. The first work function layer 102A can have a gradient oxygen concentration, which is maximum near the first dielectric layer 100B and decreases with increasing distance from the first dielectric layer 100B. Furthermore, oxygen can diffuse through the first work function layer 102A to the interface between the first work function layer 102A and the first dielectric layer 100B. The oxygen concentration at the interface between the first work function layer 102A and the first dielectric layer 100B can be in the range of about 50 at.% to about 60 at.%. Increasing the oxygen concentration in the first work function layer 102A and at the interface between the first work function layer 102A and the first dielectric layer 100B to a specified value increases the effective work function in the p-type region 50P of the complete device and increases the flat-band voltage (V). FB (For example, about 30mV), and reduced the threshold voltage (V) t This increases device speed and improves the overall device performance. Performing the oxygen exposure process within the aforementioned duration range will adjust the threshold voltage of the resulting transistor by the desired amount. Performing the oxygen exposure process outside these duration ranges may not adequately adjust the threshold voltage of the resulting transistor, or may take excessive time, etc.

[0068] After the first work function layer 102A is deposited and an oxygen exposure process is performed on it, a second work function layer 102B can be deposited on top of the first work function layer 102A. The second work function layer 102B can be deposited using the same process as the first work function layer 102A, and an oxygen exposure process can be performed on it after its deposition. The second work function layer 102B can be deposited with a thickness of approximately 0.5 nm to approximately 2.5 nm. After the oxygen exposure process, the oxygen concentration in the second work function layer 102B can be approximately 15 at.% to approximately 75 at.%, or approximately 50 at.% to approximately 60 at.%. The second work function layer 102B can have a gradient oxygen concentration, which is maximized near the first work function layer 102A and decreases with increasing distance from the first work function layer 102A.

[0069] After the second work function layer 102B is deposited and an oxygen exposure process is performed on it, a third work function layer 102C can be deposited on top of the second work function layer 102B. The third work function layer 102C can be deposited using the same process as the first work function layer 102A. In some embodiments, an oxygen exposure process can be performed on the third work function layer 102C after its deposition. However, in some embodiments, the oxygen exposure process can be omitted for the third work function layer 102C, and a vacuum environment can be maintained in the deposition chamber where the third work function layer 102C is deposited. In embodiments where an oxygen exposure process is not performed on the third work function layer 102C, the third work function layer 102C may have a lower oxygen concentration than either the first work function layer 102A or the second work function layer 102B. The third work function layer 102C can be deposited with a thickness of about 0.5 nm to about 2.5 nm. The oxygen concentration in the third work function layer 102C can be from about 15 at.% to about 75 at.% or from about 50 at.% to about 60 at.%.

[0070] like Figure 18A As shown, portions of the third work function layer 102C deposited on adjacent fins 66 and the second nanostructure 54 can merge with each other. The third work function layer 102C can fill the space left between portions of the second work function layer 102B deposited on adjacent fins 66 and the second nanostructure 54 (e.g., in the inner sheet region). Although the first work function structure 102 is illustrated and described as comprising three work function layers, the first work function structure 102 can include any number of work function layers. The final layer of the first work function structure 102 can be a merged structure that fills the space between adjacent fins 66 and the second nanostructure 54 (e.g., in the inner sheet region).

[0071] Figure 18C Secondary ion mass spectrometry (SIMS) plots of interface layer 100A, first dielectric layer 100B, and first work function structure 102 are shown. In Example 200, an oxygen exposure process was performed on the first work function structure 102, while in Example 202, the first work function structure 102 was deposited without performing an oxygen exposure process. The y-axis provides the relative abundance of oxygen detected by SIMS, while the x-axis shows the relative positions of oxygen in interface layer 100A, first dielectric layer 100B, and first work function structure 102. Figure 18C As shown, in Example 200, the oxygen exposure process increases the oxygen concentration in the first work function structure 102 and at the interface between the first work function structure 102 and the first dielectric layer 100B compared to Example 202. The oxygen concentration in the first work function structure 102 can decrease with increasing distance from the first dielectric layer 100B. The oxygen concentration in the first dielectric layer 100B can increase from the interface with the first work function structure 102, reach a maximum at approximately half the thickness of the first dielectric layer 100B, and then decrease towards the interface with the interface layer 100A. The oxygen concentration in the interface layer 100A in Example 200 can be lower than that in Example 202, and can decrease with increasing distance from the first dielectric layer 100B.

[0072] The deposition and oxygen exposure process described above, which forms a first work function structure 102 in the p-type region 50P comprising a first work function layer 102A, a second work function layer 102B, and a third work function layer 102C, increases the oxygen concentration throughout the first work function structure 102 and at the interface between the first work function structure 102 and the first dielectric layer 100B. This increases the effective work function in the p-type region 50P of the complete device and increases the flat-band voltage (V). FB (For example, about 30mV), and reduced the threshold voltage (V t This increases device speed and improves the overall device performance.

[0073] exist Figures 19A to 19D In this process, an adhesion layer 104 and a filler material 106 are deposited on the first work function structure 102. The combination of the first work function structure 102 (including a first work function layer 102A, a second work function layer 102B, and a third work function layer 102C), the adhesion layer 104, and the filler material 106 forms the gate electrode 105 in the p-type region 50P.

[0074] An adhesion layer 104 can be conformally deposited on the first work function structure 102. The adhesion layer 104 can be formed of a conductive material such as titanium nitride or tantalum nitride, which can be deposited by CVD, ALD, PECVD, or PVD. The adhesion layer 104 can be referred to as an adhesive layer and can be used to improve the adhesion between the subsequently deposited filler material 106 and the first work function structure 102. The adhesion layer 104 can be optional and may be omitted in some embodiments. The adhesion layer 104 can be deposited to have a thickness of about 1 nm to about 15 nm. The adhesion layer 104 can be deposited on the third work function layer 102C in the same deposition chamber as the deposition chamber without disrupting the vacuum of the deposition chamber.

[0075] A filler material 106 is deposited on the adhesion layer 104. In some embodiments, the filler material 106 may be formed of a conductive material such as tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), or combinations thereof. The filler material 106 may be deposited by CVD, ALD, PECVD, or PVD. The filler material 106 fills the remaining portion of the second recess 98, for example, the portion of the second recess 98 that is not filled by the gate dielectric 100, the first work function structure 102, and the adhesion layer 104. Figure 19C and Figure 19D As shown, after the filler material 106 is deposited, a planarization process can be performed on the gate dielectric 100, the first work function structure 102, the adhesion layer 104, and the filler material 106, so that the top surface of the gate electrode 105 is flush with the top surfaces of the first ILD 96, CESL 94, the first spacer 81, and the second spacer 83. The planarization process can be chemical mechanical polishing (CMP), etch-back process, or a combination thereof.

[0076] exist Figures 20A to 20D In this process, a second work function structure 107, an adhesion layer 104, and a filler material 106 are formed in the n-type region 50N. When the second work function structure 107 is deposited in the n-type region 50N, the p-type region 50P can be masked. The combination of the second work function structure 107, the adhesion layer 104, and the filler material 106 forms the gate electrode 105 in the n-type region 50N.

[0077] A second work function structure 107 can be conformally deposited on the gate dielectric 100. In some embodiments, the second work function structure 107 may include an n-type work function metal. The second work function structure 107 may be formed of a conductive material such as aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum (TaAl), tantalum carbide (TaC), or a combination thereof, and may be deposited by CVD, ALD, PECVD, or PVD. The second work function structure 107 may be deposited to have a thickness of about 0.5 nm to about 2.5 nm.

[0078] The adhesive layer 104 in the n-type region 50N may comprise the same or similar material as the adhesive layer 104 in the p-type region 50P, and can be deposited using the same or similar process as the adhesive layer 104 in the p-type region 50P. The filler material 106 in the n-type region 50N may comprise the same or similar material as the filler material 106 in the p-type region 50P, and can be deposited using the same or similar process as the filler material 106 in the p-type region 50P. In some embodiments, the adhesive layer 104 and / or filler material 106 in both the n-type region 50N and the p-type region 50P may be deposited simultaneously; however, the adhesive layer 104 and filler material 106 may be deposited separately in the n-type region 50N and the p-type region 50P, and the adhesive layer 104 and filler material 106 may be deposited in any order. Figure 20C and Figure 20D As shown, after the filler material 106 is deposited, a planarization process can be performed on the gate dielectric 100, the second work function structure 107, the adhesion layer 104, and the filler material 106, so that the top surface of the gate electrode 105 is flush with the top surfaces of the first ILD 96, CESL 94, the first spacer 81, and the second spacer 83. The planarization process can be chemical mechanical polishing (CMP), etch-back process, or a combination thereof.

[0079] exist Figure 21A and Figure 21BIn this process, a second ILD 110 is deposited over the first ILD 96. In some embodiments, the second ILD 110 is a flowable film formed by FCVD. In some embodiments, the second ILD 110 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD or PECVD. In some embodiments, prior to forming the second ILD 110, the gate stack (including gate dielectric 100 and corresponding overlying gate electrode 105) is recessed, thereby forming a recess between the gate stack directly above and the opposing portion of the first spacer 81. The recess is filled with a gate mask 108 comprising one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride, etc.), followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. The gate contacts subsequently formed (e.g., referred to below) Figure 22A and Figure 22B The gate contact 114 discussed passes through the gate mask 108 to contact the top surface of the recessed gate electrode 105.

[0080] exist Figure 22A and Figure 22B In this configuration, gate contact 114 and source / drain contact 112 are formed through the second ILD 110 and the first ILD 96. Openings for the source / drain contact 112 are formed through the first ILD 96 and the second ILD 110, and an opening for the gate contact 114 is formed through the second ILD 110 and the gate mask 108. These openings can be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer or adhesion layer, and conductive material are formed within these openings. The liner may include titanium, titanium nitride, tantalum, or tantalum nitride. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, or nickel. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 110. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 114 within the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 92 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 92, and the gate contact 114 is physically and electrically coupled to the gate electrode 105. The source / drain contact 112 and the gate contact 114 can be formed by different processes or by the same process. Although shown as being formed in the same cross-section, it should be understood that each source / drain contact 112 and the gate contact 110 can be formed in different cross-sections, which avoids short circuits of the contacts.

[0081] The embodiments can achieve several advantages. For example, forming the p-type work function structure through an iterative process including a deposition step and a subsequent oxygen exposure step increases the oxygen concentration within the p-type work function structure and at the interface between the p-type work function structure and the underlying gate dielectric layer. This increases the effective work function in the p-type region of the complete device and increases the flat-band voltage (Vp). FB ), and reduced the threshold voltage (V t This increases device speed and improves the overall device performance.

[0082] According to one embodiment, a device includes: a first channel region; a second channel region; and a gate structure surrounding the first channel region and the second channel region. The gate structure includes: a gate dielectric; a first p-type work function metal located on the gate dielectric, the first p-type work function metal comprising oxygen, a first portion of the first p-type work function metal surrounding the first channel region, and a second portion of the first p-type work function metal separated from the first portion and surrounding the second channel region; a second p-type work function metal located on the first p-type work function metal, the second p-type work function metal having a lower oxygen concentration than the first p-type work function metal, a third portion of the second p-type work function metal surrounding the first channel region, and a fourth portion of the second p-type work function metal connected to the third portion and surrounding the second channel region; and a filler layer located on the second p-type work function metal. In one embodiment, the first p-type work function metal further includes titanium nitride. In one embodiment, the oxygen concentration of the first p-type work function metal is 50 at.% to 60 at.%. In one embodiment, the gate dielectric comprises hafnium oxide, the first p-type work function metal further comprises titanium nitride, and the oxygen concentration at the interface between the gate dielectric and the first p-type work function metal is 50 at.% to 60 at.%. In one embodiment, the first p-type work function metal has a gradient oxygen concentration that decreases with increasing distance from the gate dielectric. In one embodiment, the device further comprises a third p-type work function metal located between the first and second p-type work function metals, the third p-type work function metal having a gradient oxygen concentration that decreases with increasing distance from the gate dielectric, and the first, second, and third p-type work function metals all comprising transition metal nitrides.

[0083] According to another embodiment, a device includes: a channel region; an interface layer located on the channel region; a high-k gate dielectric layer located on the interface layer; a first work function structure located on the high-k gate dielectric layer, the first work function structure including a plurality of first work function layers, each of the first work function layers including a first p-type work function material and oxygen, the oxygen concentration in the first work function structure decreasing with increasing distance from the high-k gate dielectric layer; an adhesion layer located on the first work function structure; and a fill layer located on the adhesion layer. In one embodiment, the oxygen concentration at the interface between the high-k gate dielectric layer and the first work function structure is 50 at.% to 60 at.%. In one embodiment, the high-k gate dielectric layer includes hafnium oxide. In one embodiment, both the first p-type work function material and the adhesion layer include titanium nitride. In one embodiment, the adhesion layer is oxygen-free.

[0084] In another embodiment, a method includes: depositing a gate dielectric layer on a channel region above a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and depositing a second p-type work function metal on the first p-type work function metal after performing the oxygen treatment. In one embodiment, performing the oxygen treatment includes exposing the first p-type work function metal to an ambient environment. In one embodiment, the first p-type work function metal is exposed to the ambient environment for a duration of 2 hours to 8 hours. In one embodiment, performing the oxygen treatment includes exposing the first p-type work function metal to an ozone-containing environment. In one embodiment, the first p-type work function metal is exposed to an ozone-containing environment for a duration of 10 seconds to 300 seconds. In one embodiment, performing the oxygen treatment on the first p-type work function metal causes oxygen to diffuse through the first p-type work function metal to the interface between the first p-type work function metal and the gate dielectric layer. In one embodiment, performing the oxygen treatment on the first p-type work function metal includes removing the semiconductor substrate from a deposition chamber used to deposit the first p-type work function metal. In one embodiment, the first p-type work function metal is deposited at a temperature of 200°C to 500°C and a pressure of 0.5 Torr to 40 Torr. In one embodiment, the method further includes: depositing an adhesion layer on a second p-type work function metal, the second p-type work function metal and the adhesion layer being deposited in a deposition chamber, maintaining a vacuum in the deposition chamber between the deposition of the second p-type work function metal and the deposition of the adhesion layer; and depositing a conductive filler material on the adhesion layer.

[0085] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0086] Example 1. A semiconductor device comprising: a first channel region; a second channel region; and a gate structure surrounding the first channel region and the second channel region, the gate structure comprising: a gate dielectric; a first p-type work function metal located on the gate dielectric, the first p-type work function metal comprising oxygen, wherein a first portion of the first p-type work function metal surrounds the first channel region, and wherein a second portion of the first p-type work function metal is separated from the first portion of the first p-type work function metal and surrounds the second channel region; a second p-type work function metal located on the first p-type work function metal, the second p-type work function metal having a lower oxygen concentration than the first p-type work function metal, wherein a third portion of the second p-type work function metal surrounds the first channel region, and wherein a fourth portion of the second p-type work function metal is connected to the third portion and surrounds the second channel region; and a fill layer located on the second p-type work function metal.

[0087] Example 2. The semiconductor device according to Example 1, wherein the first p-type work function metal further comprises titanium nitride.

[0088] Example 3. The semiconductor device according to Example 1, wherein the oxygen concentration of the first p-type work function metal is 50 at.% to 60 at.%.

[0089] Example 4. The semiconductor device according to Example 1, wherein the gate dielectric comprises hafnium oxide, wherein the first p-type work function metal further comprises titanium nitride, and wherein the oxygen concentration at the interface between the gate dielectric and the first p-type work function metal is 50 at.% to 60 at.%.

[0090] Example 5. The semiconductor device according to Example 1, wherein the first p-type work function metal has a gradient oxygen concentration that decreases with increasing distance from the gate dielectric.

[0091] Example 6. The semiconductor device according to Example 5 further includes a third p-type work function metal located between the first p-type work function metal and the second p-type work function metal, the third p-type work function metal having a gradient oxygen concentration that decreases with increasing distance from the gate dielectric, wherein the first p-type work function metal, the second p-type work function metal and the third p-type work function metal all comprise transition metal nitrides.

[0092] Example 7. A semiconductor device, comprising: a channel region; an interface layer located on the channel region; a high-k gate dielectric layer located on the interface layer; a first work function structure located on the high-k gate dielectric layer, the first work function structure comprising a plurality of first work function layers, each of the first work function layers comprising a first p-type work function material and oxygen, wherein the oxygen concentration in the first work function structure decreases with increasing distance from the high-k gate dielectric layer; an adhesion layer located on the first work function structure; and a fill layer located on the adhesion layer.

[0093] Example 8. The semiconductor device according to Example 7, wherein the oxygen concentration at the interface between the high-k gate dielectric layer and the first work function structure is 50 at.% to 60 at.%.

[0094] Example 9. The semiconductor device according to Example 7, wherein the high-k gate dielectric layer comprises hafnium oxide.

[0095] Example 10. The semiconductor device according to Example 7, wherein both the first p-type work function material and the adhesion layer comprise titanium nitride.

[0096] Example 11. The semiconductor device according to Example 10, wherein the adhesion layer is oxygen-free.

[0097] Example 12. A method of manufacturing a semiconductor device, comprising: depositing a gate dielectric layer on a channel region above a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and depositing a second p-type work function metal on the first p-type work function metal after performing the oxygen treatment.

[0098] Example 13. The method according to Example 12, wherein performing the oxygen treatment includes exposing the first p-type work function metal to the surrounding environment.

[0099] Example 14. The method according to Example 13, wherein the first p-type work function metal is exposed to the surrounding environment for a duration of 2 to 8 hours.

[0100] Example 15. The method according to Example 12, wherein performing the oxygen treatment includes exposing the first p-type work function metal to an ozone-containing environment.

[0101] Example 16. The method according to Example 15, wherein the first p-type work function metal is exposed to the ozone-containing environment for a duration of 10 seconds to 300 seconds.

[0102] Example 17. The method according to Example 12, wherein the oxygen treatment is performed on the first p-type work function metal to allow oxygen to diffuse through the first p-type work function metal to the interface between the first p-type work function metal and the gate dielectric layer.

[0103] Example 18. The method according to Example 12, wherein performing the oxygen treatment on the first p-type work function metal comprises: removing the semiconductor substrate from the deposition chamber for depositing the first p-type work function metal.

[0104] Example 19. The method according to Example 12, wherein the first p-type work function metal is deposited at a temperature of 200°C to 500°C and a pressure of 0.5 Torr to 40 Torr.

[0105] Example 20. The method according to Example 12 further includes: depositing an adhesion layer on the second p-type work function metal, wherein the second p-type work function metal and the adhesion layer are deposited in a deposition chamber, wherein a vacuum is maintained in the deposition chamber between the deposition of the second p-type work function metal and the deposition of the adhesion layer; and depositing a conductive filler material on the adhesion layer.

Claims

1. A semiconductor device, comprising: First trench area; Second trench area; as well as A gate structure, the gate structure surrounding the first channel region and the second channel region, the gate structure comprising: Gate dielectric; A first p-type work function metal is located on the gate dielectric and includes oxygen. A first portion of the first p-type work function metal surrounds the first channel region, and a second portion of the first p-type work function metal is separated from the first portion and surrounds the second channel region. A second p-type work function metal is located on top of a first p-type work function metal, the second p-type work function metal having a lower oxygen concentration than the first p-type work function metal, wherein a third portion of the second p-type work function metal surrounds the first channel region, and wherein a fourth portion of the second p-type work function metal is connected to the third portion and surrounds the second channel region; and A filling layer is located on the second p-type work function metal.

2. The semiconductor device according to claim 1, wherein, The first p-type work function metal also includes titanium nitride.

3. The semiconductor device according to claim 1, wherein, The oxygen concentration of the first p-type work function metal is 50 at.% to 60 at.%.

4. The semiconductor device according to claim 1, wherein, The gate dielectric includes hafnium oxide, wherein the first p-type work function metal further includes titanium nitride, and wherein the oxygen concentration at the interface between the gate dielectric and the first p-type work function metal is 50 at.% to 60 at.%.

5. The semiconductor device according to claim 1, wherein, The first p-type work function metal has a gradient oxygen concentration that decreases with increasing distance from the gate dielectric.

6. The semiconductor device of claim 5, further comprising a third p-type work function metal located between the first p-type work function metal and the second p-type work function metal, the third p-type work function metal having a gradient oxygen concentration that decreases with increasing distance from the gate dielectric, wherein, The first p-type work function metal, the second p-type work function metal, and the third p-type work function metal all include transition metal nitrides.

7. A semiconductor device, comprising: Channel area; An interface layer, the interface layer being located on the channel region; A high-k gate dielectric layer is located on the interface layer; A first work function structure is located on the high-k gate dielectric layer. The first work function structure includes a plurality of first work function layers. Each of the first work function layers includes a first p-type work function material and oxygen. The oxygen concentration in the first work function structure decreases as the distance from the high-k gate dielectric layer increases. An adhesion layer, the adhesion layer being located on the first work function structure; and A filler layer, which is located on the adhesive layer.

8. The semiconductor device according to claim 7, wherein, The oxygen concentration at the interface between the high-k gate dielectric layer and the first work function structure is 50 at.% to 60 at.%.

9. The semiconductor device according to claim 7, wherein, The high-k gate dielectric layer includes hafnium oxide.

10. The semiconductor device according to claim 7, wherein, Both the first p-type work function material and the adhesion layer comprise titanium nitride.

11. The semiconductor device according to claim 10, wherein, The adhesion layer is oxygen-free.

12. A method for manufacturing a semiconductor device, comprising: A gate dielectric layer is deposited on the channel region above the semiconductor substrate; A first p-type work function metal is deposited on the gate dielectric layer; Oxygen treatment is performed on the first p-type work function metal; as well as After performing the oxygen treatment, a second p-type work function metal is deposited on the first p-type work function metal.

13. The method according to claim 12, wherein, Performing the oxygen treatment involves exposing the first p-type work function metal to the surrounding environment.

14. The method according to claim 13, wherein, The first p-type work function metal is exposed to the surrounding environment for a duration of 2 to 8 hours.

15. The method according to claim 12, wherein, Performing the oxygen treatment involves exposing the first p-type work function metal to an ozone-containing environment.

16. The method according to claim 15, wherein, The first p-type work function metal was exposed to the ozone-containing environment for a duration of 10 to 300 seconds.

17. The method according to claim 12, wherein, The oxygen treatment is performed on the first p-type work function metal to allow oxygen to diffuse through the first p-type work function metal to the interface between the first p-type work function metal and the gate dielectric layer.

18. The method according to claim 12, wherein, Performing the oxygen treatment on the first p-type work function metal includes removing the semiconductor substrate from the deposition chamber used to deposit the first p-type work function metal.

19. The method according to claim 12, wherein, The first p-type work function metal was deposited at a temperature of 200°C to 500°C and a pressure of 0.5 Torr to 40 Torr.

20. The method of claim 12, further comprising: An adhesion layer is deposited on the second p-type work function metal, wherein the second p-type work function metal and the adhesion layer are deposited in a deposition chamber, wherein a vacuum is maintained in the deposition chamber between the deposition of the second p-type work function metal and the deposition of the adhesion layer; and A conductive filler material is deposited on the adhesion layer.

Images