Semiconductor device

Abstract

The present invention discloses a semiconductor device, which includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked. The memory strings pass through the stack along a first direction, and each memory string includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and a second conductive pillar extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar, and the channel layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a three-dimensional semiconductor device and a method for manufacturing the same. Background Art

[0002] Recently, due to the increasing demand for more excellent memory elements, various three-dimensional (3D) memory elements have been provided. However, in order to enable such three-dimensional memory elements to achieve higher storage capacity and better performance, there is still a need to provide an improved three-dimensional memory device and a method for manufacturing the same. Summary of the Invention

[0003] The present invention relates to a semiconductor device. Compared with a comparative example in which a channel layer is disposed outside a first conductive pillar and a second conductive pillar and surrounds the first conductive pillar and the second conductive pillar, since the channel layer of the semiconductor device of the present invention is disposed between the first conductive pillar and the second conductive pillar, a shorter channel length can be achieved, which can not only improve the performance of the semiconductor device, but also increase the chip density.

[0004] According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The memory strings pass through the stack along a first direction, and each memory string includes a first conductive pillar, a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar, and the channel layer.

[0005] According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The memory strings pass through the stack along a first direction, and each memory string includes a first conductive pillar, a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar, and the channel layer. The conductive layer includes a first bottom conductive layer, and the first bottom conductive layer is disposed under the first conductive pillar and the second conductive pillar.

[0006] According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps. First, a stack is formed on a substrate. The stack includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. Thereafter, a plurality of memory strings are formed. The memory strings penetrate the stack along a first direction, and each memory string includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar, and the channel layer.

[0007] For a better understanding of the above and other aspects of the present invention, the following specific embodiments are given, and are described in detail in conjunction with the accompanying drawings as follows: Description of the Drawings

[0008] Figure 1A A top view of a semiconductor device according to an embodiment of the present invention is shown;

[0009] Figure 1B A sectional view taken along the Figure 1A A-A' line is shown; and

[0010] Figures 2A to 12B A schematic diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention is shown.

[0011]

Symbol Description

[0012] 18a, 18b: Bottom structure

[0013] 100: Semiconductor device

[0014] 101: Substrate

[0015] 103: First bottom insulating layer

[0016] 105: First bottom conductive layer

[0017] 107: Second bottom insulating layer

[0018] 109: Bottom sacrificial layer

[0019] 112: Bottom sacrificial layer

[0020] 110: Third bottom insulating layer

[0021] 111: Upper sacrificial layer

[0022] 116: Upper conductive layer

[0023] 114: Insulating layer

[0024] 116: Upper conductive layer

[0025] 118a: First conductive pillar

[0026] 118b: Second conductive pillar

[0027] 120: Channel layer

[0028] 120n: Annular inner surface

[0029] 120t: Annular outer surface

[0030] 122: Memory structure

[0031] 124: Insulating pillar

[0032] 132: First opening

[0033] 134: Second opening

[0034] 136: Third opening

[0035] 138: Channel

[0036] 140: Fourth opening

[0037] 146: Second oxide layer

[0038] 148: Oxide material

[0039] A, A’, B, B’: Hatching endpoints

[0040] C1: First position

[0041] C2: Second position

[0042] CL: Conductive layer

[0043] IL: Insulating layer

[0044] L1, L2: Lengths

[0045] LS: Stacked structure

[0046] MS: Memory string

[0047] ST: Stack

[0048] W1: First width

[0049] W2: Second width Detailed implementation manners

[0050] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0051] Figure 1AA top view of a semiconductor device 100 according to an embodiment of the present invention, corresponding to Figure 1B the plane of the B-B' connection (i.e., the plane formed by the X-axis and the Y-axis). Figure 1B A cross-sectional view along the Figure 1A A-A' connection (i.e., the plane formed by the X-axis and the Z-axis). In this embodiment, the X-axis, the Y-axis, and the Z-axis are perpendicular to each other, but the present invention is not limited thereto, as long as the X-axis, the Y-axis, and the Z-axis intersect each other.

[0052] Please refer to Figure 1A and Figure 1B simultaneously. The semiconductor device 100 includes a stack ST and a plurality of memory strings MS. The channel 138 can divide the stack ST into a plurality of sub-stacks (not shown). The semiconductor device 100 is formed on a substrate 101. The stack ST includes a plurality of conductive layers CL and a plurality of insulating layers IL stacked alternately. The memory strings MS respectively pass through the stack ST along a first direction. The first direction is, for example, the direction of the Z-axis. Specifically, the conductive layer CL includes a first bottom conductive layer 105, a second bottom conductive layer 112, and a plurality of upper conductive layers 116 stacked in sequence on the substrate 101. The insulating layer IL includes a first bottom insulating layer 103, a second bottom insulating layer 107, a third bottom insulating layer 110, and a plurality of upper insulating layers 114 stacked in sequence on the substrate 101.

[0053] Each memory string MS includes a first conductive pillar 118a and a second conductive pillar 118b, a channel layer 120, an insulating pillar 124, and a memory structure 122. The first conductive pillar 118a and the second conductive pillar 118b extend along the first direction and are electrically isolated from each other. The insulating pillar 124 may include a second oxide layer 146 and an oxide material 148. The channel layer 120 and the insulating pillar 124 extend along the first direction and pass through the first bottom conductive layer 105, the second bottom insulating layer 107, the second bottom conductive layer 112, the third bottom insulating layer 110, and other layers of the stack ST. The channel layer 120 is disposed between the first conductive pillar 118a and the second conductive pillar 118b, as Figure 1A shown. In Figure 1B , the channel layer 120 extends between the insulating pillar 124 and the first conductive pillar 118a and between the insulating pillar 124 and the second conductive pillar 118b. The channel layer 120 is coupled to the first conductive pillar 118a and the second conductive pillar 118b. In addition, the channel layer 120 has an annular cross-section formed along a second direction (e.g., the X-axis direction) and a third direction (e.g., the Y-axis direction), as Figure 1AAs shown. The second direction and the third direction are, for example, perpendicular to the first direction (however, the present invention is not limited thereto). Specifically, the channel layer 120 has an annular inner surface 120n and an annular outer surface 120t, and the first conductive pillar 118a and the second conductive pillar 118b are coupled to the annular outer surface 120t. The insulating pillar 124 is connected to the annular inner surface 120n of the channel layer 120. In other words, the first conductive pillar 118a and the second conductive pillar 118b are disposed outside the channel layer 120 and not inside the channel layer 120. In this embodiment, the cross-section of the channel layer 120 is circular, however, the present invention is not limited thereto, and the cross-section of the channel layer 120 can be oval or other suitable shapes.

[0054] In Figure 1A it, the first conductive pillar 118a is coupled to the first position C1 of the channel layer 120, and the second conductive pillar 118b is coupled to the second position C2 of the channel layer 120. The first position C1 and the second position C2 are, for example, opposite to each other along the second direction. On the extension line between the first position C1 and the second position C2 (for example, passing through the center point of the insulating pillar 124), the channel layer 120 forms a first width W1 (for example, the maximum width), and the width formed by the first conductive pillar 118a to the second conductive pillar 118b is a second width W2 (for example, the maximum width), and the second width W2 is greater than the first width W1. In some embodiments, the first width W1 formed by the channel layer 120 can be referred to as the channel length. Compared with the comparative example in which the channel layer surrounds the first conductive pillar and the second conductive pillar, since the channel layer 120 in the embodiment of the present invention is disposed between the first conductive pillar 118a and the second conductive pillar 118b, the volume occupied by the channel layer 120 is smaller, and the formed channel length can be shorter, so that the density of the chip can be increased, and the semiconductor device can achieve better performance. The first conductive pillar 118a and the second conductive pillar 118a respectively contact the channel layer 120 to form two contact areas, and the size of the contact area can be adjusted according to requirements. In some embodiments, the first conductive pillar 118a and the second conductive pillar 118b contact the opposite sides of the channel layer 120 along the second direction.

[0055] In Figure 1BIn the figure, a first bottom conductive layer 105 is disposed under a first conductive pillar 118a and a second conductive pillar 118b, and the first bottom conductive layer 105 surrounds a bottom portion of the channel layer 120. A conductive layer CL (i.e., a second bottom conductive layer 112 and an upper conductive layer 116) located above the first bottom conductive layer 105 surrounds the first conductive pillar 118a and the second conductive pillar 118b. In a first direction, the first bottom conductive layer 105 overlaps the first conductive pillar 118a and the second conductive pillar 118b. The first bottom conductive layer 105 surrounds the bottom of the channel layer 120. In a second direction, a length L1 of the first bottom conductive layer 105 is greater than a length L2 of the second bottom conductive layer 112 disposed above the first bottom conductive layer 105. In the second direction, the length L1 of the first bottom conductive layer 105 is greater than a length L3 of the upper conductive layer 116. A first bottom insulating layer 103 is disposed between the substrate 101 and the first bottom conductive layer 105, and a second bottom insulating layer 107 is disposed between the first bottom conductive layer 105 and the first conductive pillar 118a and between the first bottom conductive layer 105 and the second conductive pillar 118b. In Figure 1B In the figure, a bottom surface of a bottom structure 18a of the first conductive pillar 118a is substantially coplanar with a bottom surface of the second bottom conductive layer 112.

[0056] In Figure 1A In the figure, a memory structure 122 surrounds a part of the first conductive pillar 118a, a part of the second conductive pillar 118b, and a part of the channel layer 120. In a cross-section in a second direction and a third direction, the memory structure 122 is conformal to the first conductive pillar 118a, the second conductive pillar 118b, and the channel layer 120, as Figure 1A shown. In Figure 1B In the figure, a part of the memory structure 122 extends along a first direction (e.g., the Z direction), and a part of the memory structure 122 extends along a second direction (e.g., the X direction), such that the memory structure 122 surrounds the second bottom conductive layer 112 and the upper conductive layer 116. An insulating pillar 124 is located in a central region of the memory string MS. The channel layer 120 surrounds the insulating pillar 124, that is, the channel layer 120 extends in the first direction between the insulating pillar 124 and the first conductive pillar 118a and between the insulating pillar 124 and the second conductive pillar 118b.

[0057] In some embodiments, the substrate 101 is, for example, a dielectric layer (e.g., a silicon oxide layer). The insulating layer IL may be, for example, a silicon oxide layer, and the silicon oxide layer may include, for example, silicon dioxide. The material of the insulating column 124 is, for example, oxide, and the insulating column 124 may include a second oxide layer 146 and an oxide material 148, wherein the materials of the second oxide layer 146 and the oxide material 148 may be the same, for example, both are silicon dioxide. The conductive layer CL may be formed of a conductive material, and the conductive material may be, for example, polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi X ), cobalt silicide (CoSi X ) or other suitable materials. In the present embodiment, the material of the first bottom conductive layer 105 is different from the material of the conductive layer CL above the first bottom conductive layer 105 (that is, the second bottom conductive layer 112 and the upper conductive layer 116). For example, the material of the first bottom conductive layer 105 is P-type doped polysilicon, and the material of the second bottom conductive layer 112 and the upper conductive layer 116 is tungsten, but the present invention is not limited thereto. In some embodiments, the material of the first bottom conductive layer 105 may be the same as the material of the second bottom conductive layer 112 and the upper conductive layer 116.

[0058] In the present embodiment, the memory structure 122 includes a charge storage material, such as a charge storage material formed by an oxide layer, a nitride layer and an oxide layer, but the present invention is not limited thereto. The material of the channel layer 120 is, for example, undoped polysilicon, but the present invention is not limited thereto. The material of the first conductive pillar 118a and the second conductive pillar 118b is, for example, N-type doped polysilicon, but the present invention is not limited thereto.

[0059] In this embodiment, only 7 insulating layers IL and 6 conductive layers CL are illustrated as examples, but the present invention is not limited thereto. The number of insulating layers IL may be greater than 7, and the number of conductive layers CL may be greater than 6. The number and configuration of insulating layers IL and conductive layers CL may be adjusted as required.

[0060] like Figure 1B As shown, in some embodiments, the intersection of the first conductive pillar 118a, the second conductive pillar 118b, the conductive layer 120, each memory structure 122 and the upper conductive layer 116 can form a memory cell, and a plurality of memory cells arranged along the first direction form a memory string MS. The upper conductive layer 116 can be used as a gate, and the first conductive pillar 118a and the second conductive pillar 118b can be a source or a drain.

[0061] In the present embodiment, there may be residual oxide between the bottom structure 18a of the first conductive pillar 118a and the channel layer 120 and between the bottom structure 18b of the second conductive pillar 118b and the channel layer 120. The second bottom conductive layer 112 may serve as a dummy gate. In addition, a voltage of 0V or less than 0V (e.g., a negative voltage) may be applied to the second bottom conductive layer 112 to prevent leakage current from occurring. However, the present invention is not limited thereto, and in some embodiments, there may be no oxide between the first conductive pillar 118a and the channel layer 120 and between the second conductive pillar 118b and the channel layer 120.

[0062] In some embodiments, the first bottom conductive layer 105 may be used as a dummy gate, and a voltage of 0V or less than 0V (eg, a negative voltage) may be applied to the first bottom conductive layer 105 to prevent leakage current from occurring in the channel layer 120 .

[0063] In some embodiments, the semiconductor device 100 of the present invention may be applied to 3D AND flash memory, 3D NOR memory, or other suitable memories.

[0064] Figures 2A to 12B FIG. 1 is a schematic diagram illustrating a manufacturing process of a semiconductor device 100 according to an embodiment of the present invention. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A Draw the plane formed by the X-axis and the Y-axis, Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B The plane formed by the X-axis and the Z-axis is shown. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A Corresponding to Figure 2B , Figure 3B ,Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B the plane along the B-B' connection line in Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B respectively show Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A the sectional view along the A-A' connection line in

[0065] Figure 2A shows the top view after forming the initial structure P, corresponding to the plane of the B-B' connection line in Figure 2B

[0066] Please also refer to Figure 2A and Figure 2B , provide a substrate 101, and sequentially form a first bottom insulating layer 103, a first bottom conductive layer 105, a second bottom insulating layer 107, a bottom sacrificial layer 109, and a third bottom insulating layer 110 on the substrate 101 through a deposition process to form an initial structure P. The deposition process is, for example, a chemical vapor deposition process.

[0067] Please refer to Figure 3A and Figure 3B , form a plurality of first openings 132 passing through the third bottom insulating layer 110 and the bottom sacrificial layer 109 along a first direction (for example, the Z direction) through an etching process. The bottom of each first opening 132 exposes a part of the upper surface of the second bottom insulating layer 107. Thereafter, fill the first openings 132 with a conductive material through a deposition process to form a first conductive pillar 118a and a second conductive pillar 118b (shown in Figure 1A and Figure 1B ​) multiple bottom structures 18a and 18b. In some embodiments, the bottom structures 18a and 18b and the bottom sacrificial layer 109 have the same thickness. The materials of the bottom structures 18a and 18b are, for example, N-type doped polysilicon, but the present invention is not limited thereto. In some embodiments, after filling the conductive material into the first opening 132, a part of the conductive material can be removed by a re-etching process to form the bottom structures 18a and 18b, and there may be some depressions between the bottom structures 18a and 18b and the third bottom insulating layer 110.

[0068] In some embodiments, after removing the original third bottom insulating layer 110 with depressions, a new third bottom insulating layer 110 can be redeposited on the bottom sacrificial layer 109 and the bottom structures 18a and 18b. In some embodiments, an insulating material can be filled into the depressions of the third bottom insulating layer 110. In some embodiments, through a chemical mechanical polishing (CMP) process, the third bottom insulating layer 110 can have a flat upper surface. However, the present invention is not limited thereto.

[0069] Please refer to Figure 4A and Figure 4B , a stacked structure LS is formed on the third bottom insulating layer 110, where the stacked structure LS includes a plurality of upper sacrificial layers 111 and a plurality of upper insulating layers 114 stacked alternately. The upper sacrificial layer 111 and the upper insulating layer 114 can be formed by deposition processes respectively. In some embodiments, the material of the upper sacrificial layer 111 is a nitride, such as silicon nitride; the material of the upper insulating layer 114 is an oxide, such as silicon dioxide, but the present invention is not limited thereto.

[0070] Please refer to Figure 5A and Figure 5B , after the step of forming the stacked structure LS, a plurality of second openings 134 are formed by an etching process (such as dry etching), where the second openings 134 pass through the stacked structure LS, the third bottom insulating layer 110, the bottom sacrificial layer 109, the second bottom insulating layer 107, and the first bottom conductive layer 105. The second openings 134 are located between the bottom structure 18a of the first conductive pillar 118a and the bottom structure 18b of the second conductive pillar 118b. The first bottom conductive layer 105 can be used as an etching stop layer. In some embodiments, after first exposing the first bottom conductive layer 105 by a deep etching process, a breakthrough etching step is then performed to pass through the first bottom conductive layer 105 and remove a part of the first bottom insulating layer 103, so that the bottom of the second opening 134 is in the first bottom insulating layer 103. The second openings 134 can be used to define the positions where the channel layer 120 (shown in Figure 6A and Figure 6B ) is formed.

[0071] Thereafter, please refer to Figure 6A and Figure 6B to sequentially form a first oxide layer 142, a channel layer 120, and a second oxide layer 146 on the sidewalls of the second opening 134. A portion of the first bottom insulating layer 103 is exposed. In this embodiment, the materials of the first oxide layer 142 and the second oxide layer 146 are, for example, silicon dioxide, and the material of the channel layer 120 is, for example, undoped polysilicon, but the present invention is not limited thereto.

[0072] Please refer to Figure 7A and Figure 7B to fill the oxide material 148 in the second opening 134 and on the stacked structure LS. For example, the oxide material 148 can be the same as the material of the second oxide layer 146 (such as silicon dioxide). The oxide material 148 in the second opening 134 and the second oxide layer 146 can jointly form an insulating column 124, as Figure 1A shown.

[0073] Please refer to Figure 8A and Figure 8B to form a plurality of third openings 136 through the stacked structure LS and the third bottom insulating layer 110. The bottom structures 18a and 18b are exposed through the third openings 136. The bottom structures 18a and 18b can serve as etch stop layers.

[0074] Please refer to Figure 9A and Figure 9B to remove a portion of the stacked structure LS and the third bottom insulating layer 110 through the third openings 136. The first oxide layer 142 is also removed to expose the channel layer 120 above the bottom structures 18a and 18b.

[0075] Please refer to Figure 10A and Figure 10B to fill the conductive material in the third openings 136 to form a first conductive column 118a and a second conductive column 118b. The first conductive column 118a and the second conductive column 118b are respectively in contact with the bottom structures 18a and 18b. In this embodiment, the materials of the first conductive column 118a and the second conductive column 118b are, for example, N-type doped polysilicon, but the present invention is not limited thereto.

[0076] Please refer to Figure 11A and Figure 11B, after forming an insulating material on the first conductive pillar 118a and the second conductive pillar 118b, a plurality of channels 138 are formed. The channels 138 pass through the stacked structure LS, the third bottom insulating layer 110, the bottom sacrificial layer 112, the second bottom insulating layer 107, the first bottom conductive layer 105, and the first bottom insulating layer 103 along a first direction, and the channels 138 extend along a second direction (e.g., the X direction), and the second direction intersects the first direction (e.g., perpendicular to each other). As described in the above part regarding Figure 1A and Figure 1B , the channels 138 can divide the later-formed stack ST into a plurality of sub-stacks (not shown). The later-formed stack ST includes a plurality of conductive layers CL and a plurality of insulating layers IL that are alternately stacked. The memory strings MS respectively pass through the later-formed stack ST along the first direction. Figure 1A and Figure 1B The memory strings MS in

[0077] are within a block of the memory array or within a sub-block distinguished by the channels 138. Figure 12A and Figure 12B , refer to

[0078] , the upper sacrificial layer 111 and the bottom sacrificial layer 109 are removed through the channels 138 by an etching process to form a plurality of fourth openings 140 located between the insulating layers IL. Figure 1A and Figure 1B Thereafter, a memory material and a conductive material are filled in the positions where the upper sacrificial layer 111 and the bottom sacrificial layer 109 are removed (i.e., in the fourth openings 140) to respectively form a plurality of memory structures 122, a plurality of upper conductive layers 116, and a second bottom conductive layer 112, where the upper conductive layers 116 and the second bottom conductive layer 112 respectively correspond to the positions where the upper sacrificial layer 111 and the bottom sacrificial layer 109 are removed. The memory structures 122 are formed on the sidewalls of the fourth openings 140. The memory structures 122 extend along the first direction and the second direction, such that the memory structures 122 respectively surround each upper conductive layer 116 and the second bottom conductive layer 112, and form a semiconductor device 100 as shown in Figure 1A . The memory structures 122 also surround a part of the channel layer 120, as shown in

[0079] In subsequent processes, a plurality of input lines and a plurality of output lines (not shown) can be formed on the semiconductor device 100, and the input lines and the output lines can be electrically connected to the first conductive pillar 118a and the second conductive pillar 118b respectively.

[0080] According to an embodiment of the present invention, a semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The memory strings pass through the stack along a first direction, and each memory string includes a first conductive pillar, a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, and the channel layer is disposed between the first conductive pillar and the second conductive pillar and is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar, and the channel layer.

[0081] Compared with a comparative example in which the channel layer is disposed outside the first conductive pillar and the second conductive pillar and surrounds the first conductive pillar and the second conductive pillar, since the channel layer of the semiconductor device of the present invention is disposed between the first conductive pillar and the second conductive pillar, the channel length can be greatly shortened, so that the size of the memory cell can be reduced, and the stack of the memory cells can be made closer. Therefore, on the one hand, the semiconductor device of the present invention can improve the performance of the semiconductor device, and on the other hand, it can increase the density of the chip.

[0082] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0083] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, wherein, Comprising: A stack formed on a substrate, the stack including a plurality of alternating conductive layers and a plurality of insulating layers; And A plurality of memory strings passing through the stack along a first direction, each memory string including: A first conductive pillar and a second conductive pillar extending along the first direction and electrically isolated from each other; A channel layer extending along the first direction, wherein the channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar; and A memory structure surrounding the first conductive pillar, the second conductive pillar, and the channel layer, wherein, in a cross-section perpendicular to the first direction, the memory structure is conformal to the first conductive pillar, the second conductive pillar, and the channel layer.

2. The semiconductor device according to claim 1, wherein: The channel layer has an annular cross-section formed along a second direction and a third direction, the second direction and the third direction being perpendicular to the first direction, the channel layer having an annular inner surface and an annular outer surface, and the first conductive pillar and the second conductive pillar being coupled to the annular outer surface.

3. The semiconductor device according to claim 2, wherein, Each memory string includes an insulating pillar located in a central region, and the insulating pillar is connected to the annular inner surface of the channel layer.

4. The semiconductor device according to claim 1, wherein, Each memory string includes an insulating pillar located in a central region, and the channel layer extends along the first direction between the insulating pillar and the first conductive pillar and between the insulating pillar and the second conductive pillar.

5. The semiconductor device according to claim 1, wherein, The first conductive pillar is coupled to a first position of the channel layer, the second conductive pillar is coupled to a second position of the channel layer, the first position and the second position being opposite to each other along a second direction, the second direction being staggered with respect to the first direction, On an extension connection line between the first position and the second position, the channel layer forms a first width, and a width formed from the first conductive pillar to the second conductive pillar is a second width, and the second width is greater than the first width.

6. A semiconductor device, wherein, Comprising: A stack formed on a substrate, the stack including a plurality of alternating conductive layers and a plurality of insulating layers; And A plurality of memory strings passing through the stack along a first direction, each memory string including: A first conductive pillar and a second conductive pillar extending along the first direction and electrically isolated from each other; A channel layer extending along the first direction, wherein the channel layer is coupled to the first conductive pillar and the second conductive pillar; and A memory structure surrounding the first conductive pillar, the second conductive pillar, and the channel layer, wherein, in a cross-section perpendicular to the first direction, the memory structure is conformal to the first conductive pillar, the second conductive pillar, and the channel layer; Wherein, these conductive layers include a first bottom conductive layer disposed under the first conductive pillar and the second conductive pillar.

7. The semiconductor device according to claim 6, wherein, In the first direction, the first bottom conductive layer overlaps the first conductive pillar and the second conductive pillar.

8. The semiconductor device according to claim 6, wherein, The channel layer passes through the first bottom conductive layer.

9. The semiconductor device according to claim 6, wherein, The material of the first bottom conductive layer is different from the material of these conductive layers disposed above the first bottom conductive layer.

10. The semiconductor device according to claim 6, wherein, The first conductive pillar, the channel layer, and the second conductive pillar are arranged along a second direction different from the first direction, and the first conductive pillar and the second conductive pillar contact opposite sides of the channel layer along the second direction.

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