semiconductor memory, non-volatile memory

Abstract

An embodiment of the present application can provide a semiconductor memory, a nonvolatile memory capable of suppressing an increase in chip area. According to an embodiment, a semiconductor memory (100) includes a memory group (MG) including a plurality of memory elements (MC) capable of holding data of a plurality of bits in a plurality of states of three or more, a word line (WL) connected to the plurality of memory elements, and a first circuit (121) that converts one external address received from an external controller (200) into a plurality of internal addresses. A first page size of page data that the memory group is capable of holding is smaller than a second page size of input data corresponding to the external address.

Description

[0001] Related applications

[0002] This application enjoys priority to Japanese Patent Application No. 2020-192523 (filed November 19, 2020), Japanese Patent Application No. 2020-214800 (filed December 24, 2020), and Japanese Patent Application No. 2021-138120 (filed August 26, 2021). This application incorporates the entire contents of the basic applications. Technical Field

[0003] The embodiments of the present invention relate to semiconductor memories and non-volatile memories. Background Technology

[0004] As memory chips used in memory systems, known types include semiconductor memory and non-volatile memory that use NAND flash memory. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor memory, a non-volatile memory, capable of suppressing the increase in chip area.

[0006] One embodiment of the semiconductor memory includes: a memory bank including multiple memory elements capable of holding multiple bits of data in three or more states; word lines connected to the multiple memory elements; and a first circuitry for translating a single external address received from an external controller into multiple internal addresses. The size of a first page of page data that the memory bank can hold is smaller than the size of a second page of input data corresponding to the external address. Attached Figure Description

[0007] Figure 1 This is a block diagram of a memory system including the semiconductor memory of the first embodiment.

[0008] Figure 2 This is a block diagram of the semiconductor memory according to the first embodiment.

[0009] Figure 3 This is a circuit diagram of the memory element array included in the semiconductor memory of the first embodiment.

[0010] Figure 4 This is a cross-sectional view of the memory element array included in the semiconductor memory of the first embodiment.

[0011] Figure 5 This is a block diagram of the sense amplifier and page buffer included in the semiconductor memory of the first embodiment.

[0012] Figure 6This is a perspective view of the semiconductor memory according to the first embodiment.

[0013] Figure 7 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistors in the semiconductor memory of the first embodiment and the data allocation.

[0014] Figure 8 This is a flowchart illustrating the process of changing the logical page address and the physical page address in the semiconductor memory of the first embodiment.

[0015] Figure 9 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the first embodiment.

[0016] Figure 10 This is a flowchart of the read operation in the semiconductor memory of the first embodiment.

[0017] Figure 11 This is a flowchart of the read operation in the semiconductor memory of the first embodiment.

[0018] Figure 12 This is a timing diagram showing the voltage of the select word line during the read operation of the first logical page in the semiconductor memory of the first embodiment.

[0019] Figure 13 This is a timing diagram showing the voltage of the select word line during the read operation of the second logical page in the semiconductor memory of the first embodiment.

[0020] Figure 14 It is the instruction sequence for reading the logical first page of the semiconductor memory in the first embodiment.

[0021] Figure 15 It is the instruction sequence for reading the logical second page of the semiconductor memory in the first embodiment.

[0022] Figure 16 This is a flowchart of the write operation in the semiconductor memory of the first embodiment.

[0023] Figure 17 This is a flowchart of the write operation in the semiconductor memory of the first embodiment.

[0024] Figure 18 It is the instruction sequence for the full-sequence write operation in the semiconductor memory of the first embodiment.

[0025] Figure 19 This is a table showing the allocation of data to each state in the semiconductor memory of the first example of the second embodiment.

[0026] Figure 20 This is a table showing the allocation of data to each state in the semiconductor memory of the second example of the second embodiment.

[0027] Figure 21 This is a table showing the allocation of data to each state in the semiconductor memory of the third example of the second embodiment.

[0028] Figure 22 This is a table showing the allocation of data to each state in the semiconductor memory of the fourth example of the second embodiment.

[0029] Figure 23 This is a table showing the allocation of data to each state in the semiconductor memory of the fifth example of the second embodiment.

[0030] Figure 24 This is a table showing the allocation of data to each state in the semiconductor memory of the sixth example of the second embodiment.

[0031] Figure 25 This is a table showing the allocation of data to each state in the semiconductor memory of the seventh example of the second embodiment.

[0032] Figure 26 It is the instruction sequence for reading the logical first page of the semiconductor memory in the first example of the third embodiment.

[0033] Figure 27 It is the instruction sequence for reading the logical second page of the semiconductor memory in the first example of the third embodiment.

[0034] Figure 28 It is the instruction sequence for sequential readout operations in the semiconductor memory of the second example of the third embodiment.

[0035] Figure 29 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistors in the semiconductor memory of the fourth embodiment and the data allocation.

[0036] Figure 30 This is a flowchart illustrating the process of changing the logical page address and the physical page address in the semiconductor memory of the fourth embodiment.

[0037] Figure 31 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the fourth embodiment.

[0038] Figure 32 This is a flowchart of the read operation in the semiconductor memory of the fourth embodiment.

[0039] Figure 33It is the instruction sequence for reading the logical first page of the semiconductor memory in the fourth embodiment.

[0040] Figure 34 This is a flowchart of the write operation in the semiconductor memory of the fourth embodiment.

[0041] Figure 35 This is a flowchart of the write operation in the semiconductor memory of the fourth embodiment.

[0042] Figure 36 It is the instruction sequence for the full-sequence write operation in the semiconductor memory of the fourth embodiment.

[0043] Figure 37 This is a block diagram of the sense amplifier and page buffer included in the semiconductor memory of the fifth embodiment.

[0044] Figure 38 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistors in the semiconductor memory of the fifth embodiment and the data allocation.

[0045] Figure 39 This is a diagram illustrating the flow of the transformation between logical page addresses and physical page addresses in the semiconductor memory of the fifth embodiment.

[0046] Figure 40 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the fifth embodiment.

[0047] Figure 41 This is a flowchart of the read operation in the semiconductor memory of the fifth embodiment.

[0048] Figure 42 This is a flowchart of the read operation in the semiconductor memory of the fifth embodiment.

[0049] Figure 43 This is a flowchart of the read operation in the semiconductor memory of the fifth embodiment.

[0050] Figure 44 It is the instruction sequence for reading the logical first page of the semiconductor memory in the fifth embodiment.

[0051] Figure 45 It is the instruction sequence for reading the logical second page in the semiconductor memory of the fifth embodiment.

[0052] Figure 46 It is the instruction sequence for reading the logical third page in the semiconductor memory of the fifth embodiment.

[0053] Figure 47This is a flowchart of the write operation in the semiconductor memory of the fifth embodiment.

[0054] Figure 48 This is a flowchart of the write operation in the semiconductor memory of the fifth embodiment.

[0055] Figure 49 This is a flowchart of the write operation in the semiconductor memory of the fifth embodiment.

[0056] Figure 50 It is the instruction sequence for the full-sequence write operation in the semiconductor memory of the fifth embodiment.

[0057] Figure 51 This is a table showing the allocation of data to each state in the semiconductor memory of the first example of the sixth embodiment.

[0058] Figure 52 This is a table showing the allocation of data to each state in the semiconductor memory of the second example of the sixth embodiment.

[0059] Figure 53 This is a table showing the allocation of data to each state in the semiconductor memory of the third example of the sixth embodiment.

[0060] Figure 54 This is a table showing the allocation of data to each state in the semiconductor memory of the fourth example of the sixth embodiment.

[0061] Figure 55 This is a table showing the allocation of data to each state in the semiconductor memory of the fifth example of the sixth embodiment.

[0062] Figure 56 This is a table showing the allocation of data to each state in the semiconductor memory of the sixth example of the sixth embodiment.

[0063] Figure 57 This is a table showing the allocation of data to each state in the semiconductor memory of the seventh example of the sixth embodiment.

[0064] Figure 58 This is a table showing the allocation of data to each state in the semiconductor memory of the eighth example of the sixth embodiment.

[0065] Figure 59 This is a table showing the allocation of data to each state in the semiconductor memory of the 9th example of the 6th embodiment.

[0066] Figure 60 This is a table showing the allocation of data to each state in the semiconductor memory of the 10th example of the 6th embodiment.

[0067] Figure 61This is a table showing the allocation of data to each state in the semiconductor memory of the 11th example of the 6th embodiment.

[0068] Figure 62 This is a table showing the allocation of data to each state in the semiconductor memory of the 12th example of the 6th embodiment.

[0069] Figure 63 It is the instruction sequence for reading the logical first page of the semiconductor memory in the first example of the seventh embodiment.

[0070] Figure 64 It is the instruction sequence for reading the logical second page of the semiconductor memory in the first example of the seventh embodiment.

[0071] Figure 65 It is the instruction sequence for reading the logical third page of the semiconductor memory in the first example of the seventh embodiment.

[0072] Figure 66 It is the instruction sequence for sequential readout operations in the semiconductor memory of the second example of the seventh embodiment.

[0073] Figure 67 This is a flowchart illustrating the process of changing the logical page address and the physical page address in the semiconductor memory of the eighth embodiment.

[0074] Figure 68 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the eighth embodiment.

[0075] Figure 69 This is a block diagram of the sense amplifier and page buffer included in the semiconductor memory of the first example of the 9th embodiment.

[0076] Figure 70 This is a block diagram of the sense amplifier and page buffer included in the semiconductor memory of the second example of the 9th embodiment.

[0077] Figure 71 This is a block diagram of the sense amplifier and page buffer included in the semiconductor memory of the third example of the ninth embodiment.

[0078] Figure 72 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the tenth embodiment.

[0079] Figure 73 This is a table showing the allocation of data to each state in the semiconductor memory of the tenth embodiment.

[0080] Figure 74This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the first example of the 11th embodiment.

[0081] Figure 75 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistors in the semiconductor memory of the second example of the 11th embodiment and the data allocation.

[0082] Figure 76 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the second example of the 11th embodiment.

[0083] Figure 77 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistors and the data allocation in the semiconductor memory of the third example of the 11th embodiment.

[0084] Figure 78 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the third example of the 11th embodiment.

[0085] Figure 79 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the 12th embodiment.

[0086] Figure 80 This is a table showing the allocation of data to each state in the semiconductor memory of the 12th embodiment.

[0087] Figure 81 This is a threshold voltage distribution diagram of the memory element transistor in the semiconductor memory of the 13th embodiment.

[0088] Figure 82 This is a table showing the allocation of data based on two memory element transistors in the semiconductor memory of the 13th embodiment.

[0089] Figure 83 This is a diagram showing the relationship between the allocation of data to elements A and B in the semiconductor memory of the 13th embodiment and the bit value of a section.

[0090] Figure 84 This is a flowchart illustrating the process of changing logical page addresses and physical page addresses in the semiconductor memory of the 13th embodiment.

[0091] Figure 85 This is a diagram illustrating the allocation of logical page data relative to physical pages in the semiconductor memory of the 13th embodiment.

[0092] Figure 86This is a flowchart of the read operation in the semiconductor memory of the 13th embodiment.

[0093] Figure 87 This is a flowchart of the read operation in the semiconductor memory of the 13th embodiment.

[0094] Figure 88 It is the instruction sequence for reading the logical first page of the semiconductor memory in the 13th embodiment.

[0095] Figure 89 This is a flowchart of the write operation in the semiconductor memory of the 13th embodiment.

[0096] Figure 90 This is a flowchart of the write operation in the semiconductor memory of the 13th embodiment.

[0097] Figure 91 It is the instruction sequence for the full-sequence write operation in the semiconductor memory of the 13th embodiment.

[0098] Figure 92 This is a graph showing the relationship between the write operation and the threshold voltage distribution of the memory element transistor in a modified semiconductor memory. Detailed Implementation

[0099] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this description, constituent elements having substantially the same function and structure will be labeled with the same reference numerals. Furthermore, the embodiments shown below exemplify apparatus and methods for embodying the technical concept of these embodiments; the technical concept of the embodiments does not specify the material, shape, structure, arrangement, etc., of the constituent components as described below. The technical concept of the embodiments can be modified in various ways as stated in the claims.

[0100] 1. First Implementation Method

[0101] The memory system of the first embodiment will be described. Hereinafter, NAND flash memory will be used as an example of the semiconductor memory included in the memory system.

[0102] 1.1 Composition

[0103] 1.1.1 Overall Structure of the Memory System

[0104] First, use Figure 1 The overall configuration of a memory system equipped with the semiconductor memory of this embodiment will be described. Figure 1 This is a block diagram illustrating an example of the overall structure of a memory system. Furthermore, Figure 1The illustrated memory controller configuration is one example. The internal bus can be configured in a segmented, hierarchical, or interconnected manner, and various other derived configurations are also possible. The memory system 1 communicates with the host device 2, retaining data from the host device 2 based on instructions (commands) received from it, and also outputting data to the host device 2. The host device 2, such as a server computer or personal computer, performs information processing and uses the memory system 1 to store data. The memory system 1 can function as a storage device for the host device 2, which functions as an information processing device. The memory system 1 can be built into the host device 2 or connected to it via cable or network. Furthermore, an information processing system incorporating both the memory system 1 and the host device 2 can be constructed.

[0105] like Figure 1 As shown, the memory system 1 includes a NAND flash memory 100 (hereinafter also referred to as "memory 100") used as a semiconductor memory and a memory controller (also referred to as "external controller") 200. The memory controller 200 and the memory 100 can, for example, be combined to form a semiconductor memory device; an example of this is an SD card. TM Memory cards such as memory cards, SSDs (solid state drives), etc.

[0106] The memory 100 is a non-volatile memory that includes multiple memory element transistors (hereinafter also referred to as "memory elements" or simply "elements") and is configured to store data non-volatilely. Alternatively, the memory 100 may be composed of multiple NAND flash memories. In this case, the multiple NAND flash memories within the memory 100 and the memory controller 200 may be connected via through-silicon vias (TSVs). Furthermore, the NAND flash memory may be a three-dimensional stacked NAND flash memory where memory element transistors are three-dimensionally stacked on a semiconductor substrate, or a planar NAND flash memory where memory element transistors are two-dimensionally arranged on a semiconductor substrate.

[0107] The memory 100 is connected to the memory controller 200 via a memory bus and operates based on commands from the memory controller 200. More specifically, the memory 100 and the memory controller 200 exchange, for example, 8-bit signals DQ[7:0] and clock signals DQS and DQSn. Signals DQ[7:0] can be, for example, data, address, and instructions. Clock signals DQS and DQSn are clock signals used when inputting and outputting signals DQ, and clock signal DQSn is the inverted version of clock signal DQS.

[0108] Additionally, the memory 100 receives, for example, a chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the memory controller 200. Furthermore, the memory 100 sends a ready / busy signal RBn to the memory controller 200.

[0109] The chip enable signal CEn is used to enable memory 100, for example, it is activated at a Low ("L") level. The instruction latch enable signal CLE is used to indicate that signal DQ is an instruction, for example, it is activated at a High ("H") level.

[0110] The address latch enable signal ALE indicates that the signal DQ is an address, for example, it is activated at the "H" level.

[0111] The write enable signal WEn is used to fetch received signals into memory 100. It is activated, for example, at an "L" level, whenever the memory controller 200 receives instructions, addresses, or data. Thus, whenever WEn is switched, the signal DQ is fetched into memory 100.

[0112] The read enable signal REn is used by the memory controller 200 to read data from the memory 100. The read enable signal REn is activated, for example, at an "L" level.

[0113] The ready / busy signal RBn is a signal that indicates whether the memory 100 is unable to receive the signal DQ from the memory controller 200 or is able to receive the signal DQ from the memory controller 200. For example, it is set to the "L" level when the memory 100 is in a busy state.

[0114] The memory controller 200 responds to requests (commands) from the host device 2, performing read, write, and erase operations on the memory 100. Additionally, the memory controller 200 manages the memory space (memory regions) of the memory 100.

[0115] The memory controller 200 includes a host interface circuit 210, built-in memory (RAM; Random Access Memory) 220, a processor 230, a buffer memory 240, a memory interface circuit 250, and an ECC circuit 260. Furthermore, the functions of the memory controller 200 can be implemented either by dedicated circuitry or by firmware executed by the processor.

[0116] The host interface circuit 210 is connected to the host device 2 via the host bus and manages communication with the host device 2. The host interface circuit 210 transmits requests and data received from the host device 2 to the processor 230 and the buffer memory 240. Hereinafter, the data received from the host device 2 will be referred to as "user data". The host interface circuit 210 responds to commands from the processor 230 and transmits the user data in the buffer memory 240 to the host device 2.

[0117] RAM 220 is, for example, volatile memory such as DRAM, and is used as the working area of ​​processor 230. RAM 220 holds firmware, various management tables, etc., used to manage memory 100. In addition, RAM 220 temporarily stores lookup tables, which will be described later.

[0118] Processor 230 controls the overall operation of memory controller 200. For example, the processor is a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Upon receiving a request from host device 2, processor 230 performs control according to that request. For example, when processor 230 receives a write request (including instructions, logical addresses, and user data) from host device 2, it causes memory 100 to perform a write operation via memory interface circuit 250. Similarly, when processor 230 receives a read request (including instructions and logical addresses) from host device 2, it causes memory 100 to perform a read operation via memory interface circuit 250.

[0119] Processor 230 performs various processes for managing memory 100, such as wear leveling. Furthermore, processor 230 performs various operations. For example, processor 230 performs data encryption and randomization.

[0120] In addition, the processor 230 determines the storage area (memory region) in the memory 100 based on the logical address and user data received from the host device 2.

[0121] More specifically, for example, when the processor 230 receives a write request from the host device 2, it reads from the memory 100 data (hereinafter referred to as a "lookup table") that associates logical addresses and logical page addresses (also denoted as external addresses). The logical address is attached to the access request from the host device 2. A logical page is a unit of data (input data to the memory 100) attached to one address, sent to the memory 100 by the processor 230 when controlling write and read operations in the memory 100. The page size of a logical page (also denoted as "data length" or "data size") corresponds to the size of the user data attached to one logical address. Hereinafter, the address with the attached logical page will be referred to as the "logical page address" (or, since it is an address input from outside the memory 100, it will also be referred to as the "external address"). In this embodiment, the unit of a logical page is different from that of a page written to the memory 100 (hereinafter referred to as a "physical page"). The relationship between logical pages and physical pages will be described later. A logical page address corresponds to one logical page and specifies a portion of the memory region of memory 100. Therefore, the size of the logical memory region composed of multiple logical pages is the same as the size of the memory region of memory 100 composed of physical pages.

[0122] If the processor 230 receives a write request from the host device 2, it updates the lookup table in the memory controller 200, allocating one logical page address for each logical address. After allocating the new logical page address, the processor 230 causes the memory 100 to perform a write operation. Additionally, the processor 230 updates the lookup table in the memory 100 at arbitrary time intervals.

[0123] In addition, if the processor 230 receives a read request, for example, from the host device 2, it uses a lookup table to transform the logical address into a logical page address and then causes the memory 100 to perform a read operation.

[0124] The buffer memory 240 temporarily stores user data received from the host device 2 and read data received by the memory controller 200 from the memory 100.

[0125] The memory interface circuit 250 is connected to the memory 100 via the memory bus and manages communication with the memory 100. The memory interface circuit 250 controls write operations, read operations, and erase operations in the memory 100 based on the control of the processor 230.

[0126] ECC circuit 260 encodes user data to generate codewords. The user data is then stored in memory 100 as encoded codewords. Additionally, ECC circuit 260 decodes codewords read from memory 100.

[0127] Furthermore, the memory controller 200 may choose not to encode the user data. When the memory controller 200 does not encode the data, the data written to the memory 100 is identical to the user data. Additionally, the ECC circuit 260 can generate a codeword based on user data corresponding to one logical page, or it can generate a codeword based on segmented data resulting from the segmentation of user data. Moreover, the ECC circuit 260 can also use user data corresponding to multiple logical pages to generate a codeword.

[0128] Furthermore, the ECC circuit 260 can be integrated into either the memory interface circuit 250 or the memory 100.

[0129] 1.1.2 Structure of NAND Flash Memory

[0130] Next, use Figure 2 The configuration of memory 100 will be described. Figure 2 This is a block diagram illustrating an example of the internal structure of the memory 100 in this embodiment. Furthermore, in Figure 2 In the diagram, a portion of the connections between the boxes is shown using arrow lines, but the connections between the boxes are not limited to this.

[0131] like Figure 2 As shown, the memory 100 includes an input / output circuit 110, a control unit 120, a memory element array 130, a line decoder 131, a sense amplifier 132, and a page buffer 133. The memory 100 is formed on a semiconductor substrate (silicon substrate) and thus chip-based.

[0132] Input / output circuit 110 controls the input and output of signals to memory controller 200. More specifically, input / output circuit 110 sends, for example, signals DQ (data DAT, logical page address, instruction CMD) received from memory controller 200 and various control signals (signals CEn, CLE, ALE, WEn, and REn) to control unit 120. Additionally, input / output circuit 110 sends data DAT received from control unit 120 to memory controller 200.

[0133] The control unit 120 controls the operation of the memory 100 based on instructions such as CMD received from the memory controller 200 via the input / output circuit 110. Specifically, upon receiving a write command, the control unit 120 controls the writing of the received write data DAT to the physical pages of the memory element array 130. Furthermore, upon receiving a read command, the control unit 120 controls the reading of data DAT from the memory element array 130 and outputs it to the memory controller 200 via the input / output circuit 110.

[0134] The control unit 120 includes an instruction user interface circuit 121, an oscillator 122, a sequencer 123, a voltage generation circuit 124, a column counter 125, and a serial access controller 126.

[0135] The instruction user interface circuit 121 receives the instruction CMD and the logical page address from the input / output circuit 110. The instruction user interface circuit 121 sends the received instruction CMD to the sequencer 123. Additionally, the instruction user interface circuit 121 transforms the received logical page address into an address ADD corresponding to a physical page (hereinafter also referred to as "physical page address" or "internal address") and sends it to the sequencer 123. In this embodiment, since the page size of a logical page is larger than the page size of a physical page, multiple physical pages are allocated to the data of one logical page. Therefore, the instruction user interface circuit 121 transforms one logical page address into multiple corresponding physical page addresses ADD and sends them to the sequencer 123. Alternatively, the sequencer 123 may transform the logical page address into a physical page address ADD.

[0136] Oscillator 122 is a circuit that generates a clock signal. The clock signal generated by oscillator 122 is supplied to the components including sequencer 123. Sequencer 123 is a state machine driven by the clock signal supplied from oscillator 122.

[0137] The sequencer 123 controls the overall operation of the memory 100. For example, the sequencer 123 controls the instruction user interface circuit 121, oscillator 122, voltage generation circuit 124, column counter 125, serial access controller 126, row decoder 131, sense amplifier 132, and page buffer 133. The sequencer 123 controls access to the memory element array 130 (write operations, read operations, and erase operations, etc.). For example, the sequencer 123 sends control signals to the voltage generation circuit 124 and column counter 125 to control operation timing, etc., based on the instruction CMD received from the instruction user interface circuit 121. Additionally, the sequencer 123 supplies the row address RA contained in the physical page address ADD received from the instruction user interface circuit 121 to the row decoder 131. The row address RA is used to select the address of the wiring (word line, etc.) arranged in the row direction in the memory element array 130. Furthermore, the sequencer 123 supplies the column address CA contained in the physical page address ADD received from the instruction user interface circuit 121 to the column counter 125. The column address CA is used to select the address of the wiring (bit line, etc.) arranged in the column direction in the memory element array 130.

[0138] The voltage generation circuit 124 generates voltage based on the control of the sequencer 123 and supplies it to the line decoder 131 and the sensing amplifier 132, etc.

[0139] During a write or read operation, column counter 125 sends column address CA to page buffer 133. Starting with the column address CA supplied from sequencer 123, column counter 125 advances (counts) column address CA sequentially according to control signals supplied from serial access controller 126.

[0140] The serial access controller 126 controls the transmission and reception of data DAT with the page buffer 133. More specifically, the serial access controller 126 is connected to the page buffer 133 via a data bus. During a write operation, the serial access controller 126 sends the data DAT (e.g., 8 bits of serial data corresponding to the 8-bit signal DQ) received from the input / output circuit 110 to the page buffer 133. Conversely, during a read operation, the serial access controller 126 sends the data DAT (serial data) received from the page buffer 133 to the input / output circuit 110.

[0141] The memory element array 130 includes multiple blocks BLK (BLK0, BLK1, ...) comprising non-volatile memory element transistors (hereinafter also referred to as "memory elements") corresponding to rows and columns. Each BLK block includes multiple string cells SU. Figure 2 In the example, a block BLK includes four string units SU0, SU1, SU2, and SU3. Furthermore, each string unit SU includes multiple NAND strings NS. Additionally, the number of blocks BLK within the memory element array 130 and the number of string units SU within a block BLK can be arbitrarily designed. Details regarding the memory element array 130 will be described later.

[0142] The row decoder 131 is connected in each BLK to wiring arranged along the row direction (e.g., word lines and select gate lines). During write, read, and erase operations, the row decoder 131 decodes the row address RA and applies voltage to the wiring of the selected BLK.

[0143] During a write operation, the sense amplifier 132 transmits the data stored in the page buffer 133 to the memory element transistors. Conversely, during a read operation, the sense amplifier 132 determines whether the data read from the memory element array 130 is "0" or "1". The sense amplifier 132 then transmits the obtained data to the page buffer 133. The data stored in the page buffer 133 is output to the memory controller 200 via the serial access controller 126 and the input / output circuit 110.

[0144] Page buffer 133 is a buffer that temporarily stores data DAT received from memory controller 200 and data read from memory element array 130. Page buffer 133 includes multiple latch circuits. During a write operation, page buffer 133 sequentially saves the data DAT received from serial access controller 126 to the latch circuit corresponding to the column address CA received from column counter 125. Conversely, during a read operation, page buffer 133 sequentially sends the data stored in the latch circuit corresponding to the column address CA received from column counter 125 back to serial access controller 126.

[0145] Hereinafter, the circuits other than the memory element array 130 (control unit 120, line decoder 131, sense amplifier 132, and page buffer 133, etc.) will be summarized and referred to as "peripheral circuits".

[0146] 1.1.3 Circuit configuration of memory element array

[0147] Next, use Figure 3 An example of the circuit configuration of the memory element array 130 will be described. Figure 3 The example is shown by extracting one of the multiple block BLKs contained in the memory element array 130.

[0148] like Figure 3 As shown, block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes multiple NAND strings NS.

[0149] Multiple NAND strings NS are associated with bit lines BL0 to BL(k-1) (where k is an integer greater than or equal to 2). Each NAND string NS includes, for example, memory element transistors MC0 to MC7 and select transistors ST1 and ST2. Hereinafter, without specifying any one of the bit lines BL0 to BL(k-1), it will be abbreviated as bit line BL. Without specifying any one of the memory element transistors MC0 to MC7, it will be abbreviated as memory element transistor MC.

[0150] The memory element transistor MC includes a control gate and a charge storage layer, which non-volatilely stores data. Selection transistors ST1 and ST2 are each used to select the serial cell SU during various operations.

[0151] Furthermore, the memory element transistor MC can be either a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type, which uses an insulating layer for the charge storage layer, or an FG (Floating Gate) type, which uses a conductive layer for the charge storage layer. In this embodiment, the MONOS type will be used as an example for explanation.

[0152] In each NAND string NS, the drain of the select transistor ST1 is connected to the associated bit line BL, and the source of the select transistor ST1 is connected to one end of the memory element transistors MC0 to MC7 connected in series. In the same BLK, the gates of the select transistors ST1 in the string cells SU0 to SU3 are respectively connected to the select gate lines SGD0 to SGD3. The select gate lines SGD0 to SGD3 are connected to the line decoder 131.

[0153] In each NAND string NS, the drain of select transistor ST2 is connected to the other end of the memory element transistors MC0 to MC7 connected in series. In the same BLK, the sources of select transistor ST2 are connected to the source line SL, and the gates of select transistor ST2 are connected to the select gate line SGS. The select gate line SGS is connected to the line decoder 131.

[0154] The bit line BL connects one NAND string NS contained in each of the string units SU0 to SU3 of each BLK block. The source line SL is connected between multiple BLK blocks, for example.

[0155] Hereinafter, a collection of multiple memory element transistors MC connected to a common word line WL within a single string cell SU will be referred to as a "memory group MG". Each memory element transistor MC in a memory group MG is associated with a bit line BL0 to BL(k-1). Therefore, the number of memory element transistors MC in a memory group MG is k. For example, the storage capacity of a memory group MG including k memory element transistors MC that each store 1 bit of data is defined as 1 page of data (page size) in physical pages. A memory group MG can have a storage capacity of 2 or more pages of data in physical pages, depending on the number of bits of data stored by the memory element transistors MC. In this embodiment, the case where the memory element transistors MC can store 3 bits of data, i.e., the memory group MG has a storage capacity of 3 pages of data in physical pages, will be described.

[0156] Furthermore, the circuit configuration of the memory element array 130 is not limited to the configuration described above. For example, the number of memory element transistors MC and selection transistors ST1 and ST2 contained in each NAND string NS can be designed to be arbitrary. The number of string cells SU contained in each BLK can be designed to be arbitrary.

[0157] 1.1.4 Cross-sectional structure of memory element array

[0158] Next, use Figure 4 The cross-sectional configuration of the memory element array 130 will be described. Figure 4 The example shows a cross-section of a NAND string NS. Furthermore, in Figure 4 In the example, for simplicity, one transistor used in the sense amplifier 132 is shown on the semiconductor substrate 30. Additionally, in Figure 4 In the example, part of the interlayer insulation film is omitted.

[0159] like Figure 4 As shown, a transistor used in the sense amplifier 132 is disposed on the semiconductor substrate 30. That is, the sense amplifier 132 is disposed between the semiconductor substrate 30 and the memory element array 130. In addition, other peripheral circuits such as a line decoder 131 or a page buffer 133 may also be disposed between the semiconductor substrate 30 and the memory element array 130. The configuration in which peripheral circuits are disposed below the memory element array 130 is also referred to as a CUA (CMOS Under Allay) configuration. In this embodiment, the case in which the sense amplifier 132 and the page buffer 133 are disposed between the semiconductor substrate 30 and the memory element array 130 in the CUA configuration will be described. In addition, the memory 100 may also be a configuration in which the array chip on which the memory element array 130 is disposed and the circuit chip on which the peripheral circuits are disposed are bonded together.

[0160] First, the configuration of the memory element array 130 will be described. A wiring layer 32 is formed that extends in the X direction, which is substantially parallel to the semiconductor substrate 30, and in the Y direction, which intersects the X direction, and functions as source lines SL. The wiring layer 32 is made of a conductive material, such as a semiconductor material or a metal material with added impurities.

[0161] Above the wiring layer 32, wiring layers 33, which function as select gate line SGS, word lines WL0 to WL7 and select gate line SGD and extend in the X direction, for example 10 layers, are arranged sequentially separated in the Z direction, which is approximately perpendicular to the semiconductor substrate 30, with each layer separated by an interlayer insulating film (not shown).

[0162] The wiring layer 33 is made of a conductive material, such as a semiconductor material or a metal material with added impurities. For example, a titanium nitride (TiN) / tungsten (W) stacked structure is used as the wiring layer 33. TiN, for example, functions as a barrier layer to prevent the reaction of W with SiO2 during the formation of W films by CVD (chemical vapor deposition) or as a bonding layer to improve the adhesion of W.

[0163] Furthermore, a memory pillar MP is formed with a wiring layer 33 that extends through 10 layers and reaches the wiring layer 32 at its bottom. One memory pillar MP corresponds to one NAND string NS. The memory pillar MP includes a block insulating film 34, a charge storage layer 35, a tunnel insulating film 36, a semiconductor layer 37, a core layer 38, and a capping layer 39.

[0164] More specifically, a hole corresponding to the memory pillar MP is formed, penetrating through the wiring layer 33 and reaching the wiring layer 32 from the bottom. An insulating film 34, a charge storage layer 35, and a tunnel insulating film 36 are sequentially stacked on the sides of the hole. Furthermore, a semiconductor layer 37 is formed with its sides in contact with the tunnel insulating film 36 and its bottom surface in contact with the wiring layer 32. The semiconductor layer 37 is the region where the channels for the memory element transistor MC and the select transistors ST1 and ST2 are formed. Thus, the semiconductor layer 37 functions as a signal line connecting the current path of the select transistor ST2, the memory element transistors MC0 to MC7, and the select transistor ST1. A core layer 38 is disposed within the semiconductor layer 37. Furthermore, a capping layer 39 with its sides in contact with the tunnel insulating film 36 is formed on the semiconductor layer 37 and the core layer 38.

[0165] For example, SiO2 is used for the bulk insulating film 34, the tunnel insulating film 36, and the core layer 38. For example, silicon nitride (SiN) is used for the charge storage layer 35. For example, polysilicon is used for the semiconductor layer 37 and the capping layer 39.

[0166] A contact plug 40 is formed on the capping layer 39. A wiring layer 41, which functions as a bit line BL and extends in the Y direction, is formed on the contact plug 40. The contact plug 40 and the wiring layer 41 are made of conductive materials, such as a titanium (Ti) / TiN / W laminate or copper (Cu).

[0167] In addition, Figure 4 In the example, the wiring layer 33, which is used to select the gate line SGD and SGS to perform their functions, is provided with one layer, but multiple layers can also be provided.

[0168] The memory element transistors MC0 to MC7 are formed by the memory pillar MP and the 8-layer wiring layer 33, which functions as word lines WL0 to WL7 respectively. Similarly, the memory pillar MP and the 2-layer wiring layer 33, which functions as select gate lines SGD and SGS respectively, are formed as select transistors ST1 and ST2 respectively.

[0169] Next, the transistors included in the sense amplifier 132 will be briefly described.

[0170] Transistors included in the sense amplifier 132 are disposed on the semiconductor substrate 30, for example. For example, two wiring layers 53 and 55 are connected to the source and drain of the transistor via contact plugs 51 and 54. A wiring layer 53 is connected to the gate electrode 52 of the transistor via contact plug 51.

[0171] A contact plug 56 is formed on wiring layer 55 corresponding to one of the source and drain electrodes of the transistor, with its upper surface positioned above the uppermost wiring layer 33. Contact plug 56 is not electrically connected to wiring layers 32 and 33. A contact plug 57 is formed above contact plug 56. Contact plug 56 is connected to wiring layer 41 via contact plug 57. Contact plugs 51, 54, 56, and 57, the gate electrode 52, and wiring layers 53 and 55 are made of conductive material.

[0172] 1.1.5 Composition of Sensing Amplifier and Page Buffer

[0173] Next, use Figure 5 and Figure 6 An example of the configuration of the sense amplifier 132 and the page buffer 133 will be described. Figure 5 This is a block diagram of the sense amplifier 132 and the page buffer 133. Figure 6 This is a three-dimensional diagram showing the structure of the CUA.

[0174] like Figure 5 As shown, in this embodiment, the sequencer 123 controls the multiple memory element transistors MC within a memory bank MG by dividing them into two regions: a first element region and a second element region. Similarly, the sequencer 123 controls the sense amplifier 132 and the page buffer 133 by dividing them into two regions corresponding to the first and second element regions. For example, the memory element transistors MC in the first element region are associated with bit lines BL0 to BL(i-1) (where i is an integer greater than or equal to 1 and less than k). The memory element transistors MC in the second element region are associated with bit lines BL(i) to BL(k-1). Furthermore, the number of memory element transistors MC in the first and second element regions is preferably the same. For example, when the number of memory element transistors MC in the first and second element regions is the same, i and k are in a relationship of i = k / 2.

[0175] The sensing amplifier 132 includes multiple sensing circuits SA for each bit line BL. During a read operation, the sensing circuit SA reads data from the memory element transistor MC connected to the corresponding bit line BL and determines whether the data is "0" or "1". During a write operation, the sensing circuit SA applies a voltage to the bit line BL based on the data to be written. The sensing circuit SA may also include a latch circuit for temporarily storing the read or written data. Hereinafter, the sensing circuit connected to the bit line BL corresponding to the memory element transistor MC included in the first element region will be referred to as "sensing circuit SA1". The sensing circuit connected to the bit line BL corresponding to the memory element transistor MC included in the second element region will be referred to as "sensing circuit SA2".

[0176] Page buffer 133 includes latch circuits ADL, BDL, and XDL corresponding to a sensing circuit SA. The sensing circuit SA and the latch circuits ADL, BDL, and XDL are interconnected. In other words, the sensing circuit SA and the latch circuits ADL, BDL, and XDL are connected in a manner capable of sending and receiving data. The latch circuits ADL, BDL, and XDL temporarily store data DAT. For example, during a read operation, the read data determined by the sensing circuit SA is transmitted from the sensing circuit SA to one of the latch circuits ADL, BDL, and XDL.

[0177] The latch circuit XDL is connected to the serial access controller 126 via the data bus and is used for data transmission and reception between the serial access controller 126 and the sense amplifier 132.

[0178] Furthermore, the configuration of page buffer 133 is not limited to this and can be modified in various ways. For example, the number of latching circuits provided in page buffer 133 can be designed based on the number of bits of data held by one memory element transistor MC.

[0179] Hereinafter, the latch circuits ADL, BDL, and XDL corresponding to the sensing circuit SA1 will be referred to as "Latch Circuit ADL1", "Latch Circuit BDL1", and "Latch Circuit XDL1". Similarly, the latch circuits ADL, BDL, and XDL corresponding to the sensing circuit SA2 will be referred to as "Latch Circuit ADL2", "Latch Circuit BDL2", and "Latch Circuit XDL2". Furthermore, the group of sensing circuit SA, latch circuits ADL, BDL, and XDL corresponding to one bit line BL will be referred to as "Sensing Amplifier Unit SAU". Moreover, the group of sensing circuit SA1, latch circuits ADL1, BDL1, and XDL1 will be referred to as "Sensing Amplifier Unit SAU1", and the group of sensing circuit SA2, latch circuits ADL2, BDL2, and XDL2 will be referred to as "Sensing Amplifier Unit SAU2".

[0180] In this embodiment, the plurality of sensing amplifier units SAU1 corresponding to the first element region are centrally arranged in one region, and the plurality of sensing amplifier units SAU2 corresponding to the second element region are centrally arranged in other regions.

[0181] Next, the relationship between the configuration of the memory group MG and the configuration of the sensing amplifier unit SAU will be explained.

[0182] like Figure 6 As shown, in the case of the CUA configuration, a memory element array 130 is arranged above the sense amplifier 132 and the page buffer 133 in the Z direction. For example, in the memory element array 130, multiple memory element transistors MC included in the memory group MG are arranged in the X direction. In addition, multiple blocks BLK are arranged in the Y direction. In the sense amplifier 132 and the page buffer 133, within the sense amplifier unit SAU corresponding to one memory element transistor MC, the sense circuit SA and the latch circuits ADL, BDL and XDL are arranged in the Y direction. Furthermore, if it is difficult to arrange the sense circuit SA and the latch circuits ADL, BDL and XDL in one layer, they can be arranged in multiple layers.

[0183] 1.2 Threshold voltage distribution of memory element transistors

[0184] Next, use Figure 7 The threshold voltage distribution that can be taken for the transistor MC of the memory element is explained. Figure 7 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistor MC and the data allocation. Hereinafter, in this embodiment, the case where the memory element transistor MC is a TLC (Triple Level Cell) capable of holding 8 values ​​(3 bits) of data (or also referred to as "3bit / Cell") will be described. However, the data that the memory element transistor MC can hold is not limited to 8 values.

[0185] like Figure 7 As shown, the threshold voltage of each memory element transistor MC takes a value from one of eight discrete distributions, for example. Hereinafter, the eight distributions are referred to as “S0” state (or threshold region), “S1” state, “S2” state, “S3” state, “S4” state, “S5” state, “S6” state and “S7” state, in order of increasing threshold voltage.

[0186] The "S0" state is equivalent to, for example, the erased state of data. Also, the "S1" to "S7" states are equivalent to the states where data has been written by injecting charge into the charge storage layer. In the write operation, the verification voltages corresponding to the respective threshold voltage distributions are set as V1 to V7. Then, these voltage values are in the relationship of V1 < V2 < V3 < V4 < V5 < V6 < V7 < Vread. The voltages V1 to V7 are the voltages applied to the word line WL (hereinafter also referred to as "selected word line WL") connected to the memory element transistor MC to be read out during the read operation. The voltage Vread is the voltage applied to the word line WL (hereinafter also referred to as "non-selected word line WL") connected to the memory element transistor MC that is not the readout object during the read operation. When the voltage Vread is applied to the gate, the memory element transistor MC is set to the on state regardless of the data held.

[0187] More specifically, the threshold voltage included in the "S0" state is lower than the voltage V1. The threshold voltage included in the "S1" state is not less than the voltage V1 and lower than the voltage V2. The threshold voltage included in the "S2" state is not less than the voltage V2 and lower than the voltage V3. The threshold voltage included in the "S3" state is not less than the voltage V3 and lower than the voltage V4. The threshold voltage included in the "S4" state is not less than the voltage V4 and lower than the voltage V5. The threshold voltage included in the "S5" state is not less than the voltage V5 and lower than the voltage V6. The threshold voltage included in the "S6" state is not less than the voltage V6 and lower than the voltage V7. And, the threshold voltage included in the "S7" state is not less than the voltage V7 and lower than the voltage Vread.

[0188] In addition, the set values of the verification voltage and the read voltage corresponding to each state may be the same or different. Hereinafter, for the sake of simplicity of explanation, the case where the verification voltage and the read voltage have the same set value will be described.

[0189] Hereinafter, the read operations corresponding to the read operations of the "S1" to "S7" states will be respectively denoted as read operations R1, R2, R3, R4, R5, R6, and R7. The read operation R1 determines whether the threshold voltage of the memory element transistor MC is lower than the voltage V1. The read operation R2 determines whether the threshold voltage of the memory element transistor MC is lower than the voltage V2. Hereinafter, it is the same. The read operations R3 to R7 respectively determine whether the threshold voltage of the memory element transistor MC is lower than the voltages V3 to V7.

[0190] Each memory element transistor MC can take on eight states by having one of eight threshold voltage distributions. By assigning these states to "000" to "111" in binary notation, each memory element transistor MC can hold 3 bits of data. Hereinafter, the 3 bits of data will be denoted as Lower bits, Middle bits, and Upper bits. In addition, the set of Lower bits written (or read) to the memory bank MG is denoted as Lower page, the set of Middle bits as Middle page, and the set of Upper bits as Upper page.

[0191] exist Figure 7 In the example, for the memory element transistors MC included in each threshold voltage distribution, data is allocated to the "Upper bit / Middle bit / Lower bit" as shown below. For each state, data is allocated in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0192] "S0" status: "111" data

[0193] "S1" status: "101" data

[0194] "S2" status: "001" data

[0195] "S3" status: "011" data

[0196] "S4" status: "010" data

[0197] "S5" status: "110" data

[0198] "S6" status: "100" data

[0199] "S7" status: "000" data

[0200] When reading data in this manner, the Lower page is determined by read action R4. The Middle page is determined by read actions R1, R3, and R6. The Upper page is determined by read actions R2, R5, and R7. In other words, the values ​​of the Lower, Middle, and Upper bits are determined by 1, 3, and 3 read actions, respectively. In other words, the number of voltages used to determine the bit values ​​(hereinafter referred to as the "boundary number") is 1, 3, and 3 for the Lower, Middle, and Upper bits, respectively. Hereinafter, this data allocation will be referred to as "1-3-3 encoding" using the boundary number.

[0201] In this implementation, the allocation of data for the Upper, Middle, and Lower bits includes one bit with a boundary count of 1. Furthermore, the boundary count of bits with a boundary count other than 1 is encoded so that the maximum boundary count is minimized. For example, in the case of TLC (3 bits / cell), the total boundary count is 7. Therefore, when the remaining 6 boundaries are distributed among the remaining 2 bits, the maximum boundary count is minimized when the boundary count for each bit is set to 3.

[0202] Furthermore, the allocation of data to states “S0” to “S7” is not limited to 1-3-3 encoding.

[0203] 1.3 Transformation between logical page address and physical page address

[0204] Next, use Figure 8 and Figure 9 An example illustrating the transformation between logical page addresses and physical page addresses is provided. Figure 8 It is a diagram illustrating the process of changing logical page addresses and physical page addresses. Figure 9 This is a diagram showing the allocation of logical page data relative to physical pages.

[0205] In this embodiment, the case where input data from 2 logical pages is allocated to 3 physical pages (i.e., a memory group MG capable of storing 3 pages of data) will be described.

[0206] like Figure 8 As shown, for example, if the memory controller 200 receives a write request from the host device 2, it allocates two logical page addresses "90001" and "90002" corresponding to the received two logical addresses "00001" and "00002". Hereinafter, the two allocated logical pages will be referred to as "Logical Page 1" and "Logical Page 2". Figure 8 In the example, logical page 1 corresponds to logical page address "90001", and logical page 2 corresponds to logical page address "90002".

[0207] If the instruction user interface circuit 121 receives a logical page address including two pages and a write command for the logical pages from the memory controller 200, it transforms the two logical page addresses into three physical page addresses according to a pre-set mapping. In this embodiment, the instruction user interface circuit 121 transforms the logical page address of the first logical page into the physical page address of the first element region of the Lower page and the Middle page. Furthermore, the instruction user interface circuit 121 transforms the logical page address of the second logical page into the physical page address of the second element region of the Lower page and the Upper page.

[0208] The page size of a logical page is larger than the page size of a physical page. However, the data volume (data length) of a logical page is the same as the data volume (data length) of a physical page.

[0209] In this embodiment, the page size of one logical page is set to m (m is a number greater than or equal to 1), and the number of logical pages written (i.e., the number of logical page addresses contained in the command) is set to a (a is an integer greater than or equal to 1). Furthermore, the page size of one physical page is set to n (n is a number less than m), and the number of physical pages written (i.e., the number of bits of data that the memory element transistor MC can store) is set to b (b is an integer greater than a). Therefore, the page size n of one physical page, i.e., one memory group MG, can be represented by n = m × a / b. Additionally, the page sizes of the first element region and the second element region can each be represented by n / 2. In this embodiment, since a = 2 and b = 3, the page size of the physical page is n = m × 2 / 3. For example, when the page size of the logical page is 16 [kB], the page size of the physical page is n = 16 × 2 / 3 = 10.67 [kB]. In this case, the number of memory element transistors MC capable of achieving a page size n = 10.67 [kB] for one physical page becomes an integer value that is the same as or larger than the integer value obtained by rounding down 10.67 × 1024. That is, the number of memory element transistors MC becomes an integer value that is the same as or larger than the integer value obtained by rounding down the page size for one physical page.

[0210] In this embodiment, the page size of the physical page is smaller than the page size of the logical page. In this case, if the number of string units SU within the logical block BLK composed of logical pages is the same as the number of string units SU within the physical block BLK composed of physical pages (i.e., the block BLK of the memory element array 130), then the block size (memory capacity) of the physical block BLK is smaller than the block size (memory capacity) of the logical block BLK. Therefore, the number of string units SU within the physical block BLK can be increased, for example, from 4 to 6, so that the memory capacity of the logical block BLK is the same as the memory capacity of the physical block BLK. Alternatively, the number of physical blocks BLK can be greater than the number of logical blocks BLK.

[0211] For example, the sequencer 123 writes data of the first logical page to the first element region of the Lower page and the first and second element regions of the Middle page of a memory bank MG based on the physical page address transformed in the instruction user interface circuit 121, and writes data of the second logical page to the second element region of the Lower page and the first and second element regions of the Upper page.

[0212] Next, the configuration of logical page data in a memory group MG is described in detail.

[0213] like Figure 9 As shown, the data on logical page 1 and logical page 2 are divided into three groups, starting from the first data and designated as clusters 1 through 3. For example, sequencer 123 writes logical page 1 cluster 1 to the first element area of ​​the Lower page, logical page 2 cluster 2 to the second element area of ​​the Middle page, and logical page 3 cluster 3 to the first element area of ​​the Middle page. Additionally, sequencer 123 writes logical page 1 cluster 2 to the second element area of ​​the Lower page, logical page 2 cluster 2 to the first element area of ​​the Upper page, and logical page 3 cluster 3 to the second element area of ​​the Upper page.

[0214] 1.4 Reading Action

[0215] Next, the read operation will be explained. In the read operation of this embodiment, if the memory 100 receives a read command based on a logical page from the memory controller 200, it reads data from the corresponding multiple physical pages, combines the read data, and outputs it as the data of the logical page.

[0216] In this embodiment, the read operation differs depending on whether the logical page to be read is logical page 1 or logical page 2. When the logical page is logical page 1, the physical pages to be read are the Lower page (first element region) and the Middle page (first element region and second element region). In this case, the memory 100 sends (outputs) the data from the first element region of the Lower page and the data from the first and second element regions of the Middle page to the memory controller 200. Conversely, when the logical page is logical page 2, the physical pages to be read are the Lower page (second element region) and the Upper page (first element region and second element region). In this case, the memory 100 sends (outputs) the data from the second element region of the Lower page and the data from the first and second element regions of the Upper page to the memory controller 200.

[0217] 1.4.1 Reading Action Flow

[0218] First, use Figure 10 and Figure 11 The process of reading from memory 100 is explained. Figure 10 and Figure 11 This is a flowchart of the reading action.

[0219] like Figure 10 and Figure 11 As shown, the memory 100 receives a read command for logical page 1 or logical page 2 from the memory controller 200 (step S1). After the instruction user interface circuit 121 converts the logical page address into a physical page address, it sends the received instruction and the converted physical page address to the sequencer 123.

[0220] If the logical page address is the logical page address of logical page 1 (step S2_yes), sequencer 123 first executes the Lower page read operation (step S3). More specifically, sequencer 123 executes the read operation R4 corresponding to the read voltage V4.

[0221] The sequencer 123 determines the data of the Lower page based on the result of the read action R4 (step S4).

[0222] The sequencer 123 transmits the data of the Lower page read by the sensing circuits SA1 and SA2 to the latching circuits ADL1 and ADL2 respectively (step S5).

[0223] Sequencer 123 transmits the data of latch circuit ADL1 (data of the first cluster of the first logical page) to latch circuit XDL1 (step S6).

[0224] Sequencer 123 sets the starting address of latch circuit XDL1 as column address CA in column counter 125 (step S7). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL1 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data to latch circuit XDL1 of memory controller 200.

[0225] The sequencer 123 executes the Middle page read operation in parallel with the data output of the latch circuit XDL1 (step S8). More specifically, the sequencer 123 executes read operation R1 corresponding to read voltage V1, read operation R3 corresponding to read voltage V3, and read operation R6 corresponding to read voltage V6. Furthermore, the order of read operations R1, R3, and R6 can be arbitrarily set.

[0226] The sequencer 123 determines the data of the Middle page based on the results of the read actions R1, R3 and R6 (step S9).

[0227] Sequencer 123 transmits the data of the Middle page read by sensing circuits SA1 and SA2 to latching circuits ADL1 and ADL2 respectively (step S10).

[0228] Sequencer 123 transmits the data of latch circuit ADL2 (data of the second cluster of the first logical page) to latch circuit XDL2 (step S11).

[0229] If the output of the data in the latch circuit XDL1 (the data of the first cluster of the first page of logic) has not ended (step S12_No), the sequencer 123 repeatedly performs the data output confirmation action until the output ends.

[0230] If the output of data from latch circuit XDL1 ends (step S12_Yes), then sequencer 123 transmits the data from latch circuit ADL1 (data from the third cluster of the first logical page) to latch circuit XDL1 (step S13). If the output of data from latch circuit XDL2 (data from the second cluster of the first logical page) and latch circuit XDL1 (data from the third cluster of the first logical page) ends, then sequencer 123 ends the read operation of the first logical page.

[0231] If the logical page address is not the logical page address of the logical first page (step S2_No), that is, if the logical page address is the logical page address of the logical second page, the sequencer 123 first performs the Lower page reading operation in the same way as in step S3 (step S14).

[0232] Sequencer 123 determines the data for the Lower page based on the result of read action R4 (step S15).

[0233] The sequencer 123 transmits the data of the Lower page read by the sensing circuits SA1 and SA2 to the latching circuits ADL1 and ADL2 respectively (step S16).

[0234] Sequencer 123 transmits the data of latch circuit ADL2 (data of the first cluster of the second logical page) to latch circuit XDL2 (step S17).

[0235] Sequencer 123 sets the starting address of latch circuit XDL2 as column address CA in column counter 125 (step S18). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL2 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data to latch circuit XDL2 of memory controller 200.

[0236] The sequencer 123 executes the upper page read operation in parallel with the data output of the latch circuit XDL2 (step S19). More specifically, the sequencer 123 executes the read operation R2 corresponding to the read voltage V2, the read operation R5 corresponding to the read voltage V5, and the read operation R7 corresponding to the read voltage V7. Furthermore, the order of the read operations R2, R5, and R7 can be arbitrarily set.

[0237] Sequencer 123 determines the data of the Upper page based on the results of read actions R2, R5 and R7 (step S20).

[0238] Sequencer 123 transmits the data of the Upper page read by sensing circuits SA1 and SA2 to latching circuits ADL1 and ADL2 respectively (step S21).

[0239] Sequencer 123 transmits the data of latch circuit ADL1 (data of the second cluster of the second logical page) to latch circuit XDL1 (step S22).

[0240] If the output of the data in the latch circuit XDL2 (the data of the first cluster of the second page of logic) has not ended (step S23_No), the sequencer 123 repeatedly performs the data output confirmation action until the output ends.

[0241] If the output of data from latch circuit XDL2 ends (step S23_Yes), then sequencer 123 transmits the data from latch circuit XDL2 (data from the third cluster of the second logical page) to latch circuit XDL2 (step S24). Additionally, sequencer 123 sets the starting address of latch circuit XDL1 in column counter 125 as column address CA. Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL1 based on the column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data to latch circuit XDL1 of memory controller 200. If the output of data from latch circuit XDL1 (data from the second cluster of the second logical page) and latch circuit XDL2 (data from the third cluster of the second logical page) ends, then sequencer 123 terminates the read operation of the second logical page.

[0242] 1.4.2 Voltage of the selected word line during readout operation

[0243] Next, use Figure 12 and Figure 13 The voltage of the selected word line during the readout operation is explained. Figure 12 This is a timing diagram showing the voltage of the select word line WL during the read operation of the first page of logic. Figure 13This is a timing diagram showing the voltage of the select word line WL during the read operation of the logic page 2.

[0244] like Figure 12 As shown, in order to read the data of the first logical page, the sequencer 123 reads the data of the Lower page and the Middle page. That is, the sequencer 123 executes the read action R4 corresponding to the Lower page and the read actions R1, R3 and R6 corresponding to the Middle page in sequence.

[0245] More specifically, at time t0, the line decoder 131 applies a read voltage V4 to the select word line WL, corresponding to the read action R4.

[0246] At time t1, the line decoder 131 applies a read voltage V1 to the select word line WL, which corresponds to the read action R1.

[0247] At time t2, the line decoder 131 applies the read voltage V3 corresponding to the read action R3 to the select word line WL.

[0248] At time t3, the line decoder 131 applies the read voltage V6 corresponding to the read action R6 to the select word line WL.

[0249] At time t4, the line decoder 131 applies a ground voltage VSS to the select word line WL, ending the application of the read voltage.

[0250] Furthermore, the order in which the line decoder 131 applies voltages V1, V3, V4, and V6 to the select word line WL is interchangeable. For example, the line decoder 131 may also apply voltages V4, V6, V3, and V1 to the select word line WL in sequence, or it may apply voltages V1, V3, V4, and V6 in sequence. Alternatively, the line decoder 131 may apply voltages V6, V4, V3, and V1 in sequence.

[0251] like Figure 13 As shown, in order to read the data of the second logical page, the sequencer 123 reads the data of the Lower page and the Upper page. That is, the sequencer 123 executes the read action R4 corresponding to the Lower page and the read actions R2, R5 and R7 corresponding to the Upper page in sequence.

[0252] More specifically, at time t0, the line decoder 131 applies a read voltage V4 to the select word line WL, corresponding to the read action R4.

[0253] At time t1, the line decoder 131 applies a read voltage V2 to the select word line WL, which corresponds to the read action R2.

[0254] At time t2, the line decoder 131 applies a read voltage V5 to the select word line WL, which corresponds to the read action R5.

[0255] At time t3, the line decoder 131 applies the read voltage V7 corresponding to the read action R7 to the select word line WL.

[0256] At time t4, the line decoder 131 applies a ground voltage VSS to the select word line WL, ending the application of the read voltage.

[0257] Furthermore, the order in which the line decoder 131 applies voltages V2, V4, V5, and V7 to the select word line WL is interchangeable. For example, the line decoder 131 may also apply voltages V4, V7, V5, and V2 to the select word line WL in sequence, or it may apply voltages V2, V4, V5, and V7 in sequence. Alternatively, the line decoder 131 may apply voltages V7, V5, V4, and V2 in sequence.

[0258] 1.4.3 Reading the instruction sequence of the action

[0259] Next, use Figure 14 and Figure 15 An example of a sequence of instructions for reading out actions is illustrated. Figure 14 This shows the instruction sequence for reading the first logical page. Figure 15 This shows the instruction sequence for the logical second page read operation. Figure 14 and Figure 15 In the example, for simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. In the following description, the ready / busy signal RBn sent from memory 100 to memory controller 200 is referred to as the "external RBn signal." Additionally, the internal signal within memory 100 indicating whether memory 100 is busy is referred to as the "internal RBn signal." In signal DQ, instructions are recorded within a circle, addresses within a four-sided border, and data within a six-sided border. Furthermore, when valid data is stored in any latch circuit of page buffer 133, the latch circuit is represented by a rounded four-sided border. Moreover, in... Figure 14 and Figure 15 In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[0260] First, let's explain the instruction sequence in the read operation of the first page of logic.

[0261] like Figure 14As shown, for example, when the object to be read is the logical first page, the memory controller 200 sends an instruction "00h" to the memory 100 to notify it to perform a read operation. Next, the memory controller 200 sends the logical page address "AD-P1" of the logical first page. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address. Then, the memory controller 200 sends an instruction "30h" to the memory 100 to command the execution of the read operation. The instruction user interface circuit 121 sequentially sends the received instruction and the converted physical page address to the sequencer 123.

[0262] The sequencer 123 responds to the instruction "30h" and begins the read operation. First, the sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, the sequencer 123 executes the lower page read operation (read operation R4). That is, a read voltage V4 is applied to the select word line WL. The lower page read result is stored in latch circuits ADL1 and ADL2. Furthermore, the data in latch circuit ADL1 is transmitted to latch circuit XDL1. If the lower page read operation ends, the sequencer 123 sets the external RBn signal to the "H" level, indicating a ready state. Alternatively, if the lower page read operation ends, the sequencer 123 then begins the middle page read operation (read operations R1, R3, and R6). That is, read voltages V1, V3, and V6 are applied sequentially to the select word line WL.

[0263] If the memory controller 200 receives an external RBn signal at a level of "H", it sends a signal REn (not shown) to the memory 100. The input / output circuit 110 starts outputting data based on the signal REn. First, the input / output circuit 110 outputs the data of the latch circuit XDL1. If the reading operation of the Middle page ends while the data of the latch circuit XDL1 is being output, the sequencer 123 sets the internal RBn signal to a level of "H". The reading result of the Middle page is stored in the latch circuits ADL1 and ADL2. Furthermore, if the output of the data of the latch circuit XDL1 ends before the reading operation of the Middle page ends, the sequencer 123 can also temporarily set the external RBn signal to a level of "L" (busy state) to interrupt the output of data to the memory controller 200. Thus, it is possible to continuously output the data of the Second Element Area of ​​the Middle Page after outputting the data of the First Element Area of ​​the Lower Page.

[0264] Next, data from latch circuit ADL2 is transferred to latch circuit XDL2. If the output of data from latch circuit XDL1 ends, input / output circuit 110 then begins outputting data from latch circuit XDL2. During the output of data from latch circuit XDL2, data from latch circuit ADL1 is transferred to latch circuit XDL1. If the output of data from latch circuit XDL2 ends, input / output circuit 110 then begins outputting data from latch circuit XDL1. If the output of data from latch circuit XDL1 ends, the read operation of the first logical page ends. Alternatively, memory 100 can set the external RBn signal to be the same as the internal RBn signal, and after reading all the data from the first logical page, set the external RBn signal (internal RBn signal) to "H" level and output the data.

[0265] Next, the instruction sequence in the read operation of the second page of logic will be explained.

[0266] like Figure 15 As shown, for example, when the object to be read is logical page 2, the memory controller 200 sends an instruction "00h" to the memory 100 to notify it to perform a read operation. Next, the memory controller 200 sends the logical page address "AD-P2" of logical page 2. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P2" into a physical page address. Then, the memory controller 200 sends an instruction "30h" to the memory 100 to command the read operation to be performed. The instruction user interface circuit 121 sequentially sends the received instruction and the converted physical page address to the sequencer 123.

[0267] The sequencer 123 responds to the instruction "30h" and begins the read operation. First, the sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, the sequencer 123 executes the lower page read operation (read operation R4). That is, a read voltage V4 is applied to the select word line WL. The lower page read result is stored in latch circuits ADL1 and ADL2. Furthermore, the data in latch circuit ADL2 is transmitted to latch circuit XDL2. If the lower page read operation ends, the sequencer 123 sets the external RBn signal to the "H" level, indicating a ready state. Alternatively, if the lower page read operation ends, the sequencer 123 then begins the upper page read operation (read operations R2, R5, and R7). That is, read voltages V2, V5, and V7 are applied sequentially to the select word line WL.

[0268] If the memory controller 200 receives an external RBn signal at level "H", it sends a signal REn (not shown) to the memory 100. The input / output circuit 110 starts outputting data based on the signal REn. First, the input / output circuit 110 outputs the data of the latch circuit XDL2. If the read operation of the Upper page ends while the data of the latch circuit XDL2 is being output, the sequencer 123 sets the internal RBn signal to level "H". The read result of the Upper page is stored in the latch circuits ADL1 and ADL2. Furthermore, if the output of the data of the latch circuit XDL2 ends before the read operation of the Upper page ends, the sequencer 123 can also temporarily set the external RBn signal to level "L" (busy state) to interrupt the output of data to the memory controller 200. Thus, the data of the first element area of ​​the Upper page can be continuously output after the data of the second element area of ​​the Lower page is output.

[0269] Next, data from latch circuit ADL1 is transmitted to latch circuit XDL1. If the output of data from latch circuit XDL2 ends, input / output circuit 110 then begins outputting data from latch circuit XDL1. During the output of data from latch circuit XDL1, data from latch circuit ADL2 is transmitted to latch circuit XDL2. If the output of data from latch circuit XDL1 ends, input / output circuit 110 then executes the output of data from latch circuit XDL2. If the output of data from latch circuit XDL2 ends, the read operation of the second logical page ends. Alternatively, memory 100 can set the external RBn signal to be the same as the internal RBn signal, read all data from the second logical page, set the external RBn signal (internal RBn signal) to "H" level, and output the data.

[0270] 1.5 Write Action

[0271] Next, the write operation will be explained. The write operation broadly includes a program operation and a program verification operation. The program operation is the action of increasing the threshold voltage by injecting electrons into the charge accumulation layer (or maintaining the threshold voltage by injecting almost no electrons into the charge accumulation layer). The program verification operation is the action of reading data after the program operation and determining whether the threshold voltage of the memory element transistor MC has reached the target level. Hereinafter, the case where the threshold voltage of the memory element transistor MC reaches the target level will be denoted as "verification passed," and the case where the target level is not reached will be denoted as "verification failed." More specifically, for example, in the program verification operation, if the number of failed read data bits exceeds a preset reference value, it will be determined as "verification failed." Furthermore, by repeatedly performing the combination of program operations and program verification operations (hereinafter referred to as "program loop"), the threshold voltage of the memory element transistor MC rises to the target level.

[0272] In this embodiment, data from the first and second logical pages are written together to the memory group MG, which has a Lower page, a Middle page, and an Upper page. That is, 3 bits of data are written together to a single memory element transistor MC. Hereinafter, the operation of writing data to multiple physical pages simultaneously is referred to as a "full-sequence write operation." In the full-sequence write operation of this embodiment, writing is performed in states "S1" to "S7". For example, in the full-sequence write operation, writing occurs sequentially starting from the state with the lowest threshold voltage. For example, if the page size of the logical page and the page size of the physical page are the same, and states "S1" to "S3" are written to the memory element array 130, then the latch circuit XDL is not needed in the write operations of states "S1" to "S3". Therefore, the latch circuit XDL is used as flash memory for the next data write. However, in this embodiment, since the number of physical latch circuits XDL is 2 / 3 of the page size of the logic page (e.g., 16kB) (e.g., 10.67kB), it is impossible to save all the data of one page of the logic page to the latch circuit XDL. Therefore, after inputting 2 / 3 of the page data of the logic page to the idle latch circuit XDL, the signal RBn is temporarily set to the busy state. Furthermore, the memory element array 130 can be written to states "S1" to "S5". When the latch circuit ADL or latch circuit BDL is not needed during the write operation, the signal RBn is set to the ready state, and the remaining page data of the logic page is input to the latch circuit XDL. Alternatively, one latch circuit can be added to each sense amplifier unit SAU.

[0273] In this embodiment, the memory 100 is controlled by alternately transmitting input data to latch circuits XDL1 and XDL2 so that data input to the logic page can be performed continuously.

[0274] 1.5.1 Write operation process

[0275] Next, use Figure 16 and Figure 17 The process of writing operations in memory 100 is described. Figure 16 and Figure 17 This is a flowchart of the write operation.

[0276] like Figure 16 and Figure 17 As shown, during the receipt of a write command, memory 100 receives the logical page address of the logical first page from memory controller 200 (step S201). Instruction user interface circuit 121 converts the logical page address of the logical first page into a physical page address.

[0277] The sequencer 123 sets the starting address of the latch circuit XDL1 as the column address CA in the column counter 125 (step S202).

[0278] In page buffer 133, data input to the first cluster of the first logical page of latch circuit XDL1 begins based on the column address CA received from column counter 125 (step S203).

[0279] If the data input to the first cluster of the first logical page of the latch circuit XDL1 has not ended (step S204_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0280] If the data input to latch circuit XDL1 ends (step S204_Yes), then sequencer 123 transmits the data from latch circuit XDL1 to latch circuit ADL1 (step S205). Alternatively, if the data input to latch circuit XDL1 ends, then the data input to the second cluster of the first logical page of latch circuit XDL2 begins. Furthermore, step S205 can also be executed during the data input to the second cluster of the first logical page of latch circuit XDL2.

[0281] If the data input to the second cluster of the first logical page of the latch circuit XDL2 has not ended (step S206_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0282] If the data input to the latch circuit XDL2 ends (step S206_Yes), then the sequencer 123 sets the starting address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S207).

[0283] In page buffer 133, data input to the third cluster of the first logical page of latch circuit XDL1 begins based on the column address CA received from column counter 125.

[0284] If the data input to the third cluster of the first logical page of the latch circuit XDL1 has not ended (step S208_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0285] If the data input to latch circuit XDL1 is completed (step S208_Yes), then the data input to the first logical page of latch circuits XDL1 and XDL2 is completed.

[0286] Sequencer 123 transmits the data from latch circuits XDL1 and XDL2 to latch circuits BDL1 and BDL2 respectively (step S209).

[0287] Next, memory 100 receives the logical page address of logical page 2 from memory controller 200 (step S210). Instruction user interface circuit 121 translates the logical page address of logical page 2 into a physical page address. Furthermore, in the data input to the third cluster of logical page 1 of latch circuit XDL1, sequencer 123 can also transmit data from latch circuit XDL2 to latch circuit BDL2.

[0288] The sequencer 123 sets the starting address of the latch circuit XDL2 as the column address CA in the column counter 125 (step S211).

[0289] In page buffer 133, data input to the first cluster of the logical second page of latch circuit XDL2 begins based on the column address CA received from column counter 125 (step S212). Furthermore, during data input to the first cluster of the logical second page of latch circuit XDL2, sequencer 123 can also transfer data from latch circuit XDL1 to latch circuit BDL1.

[0290] If the data input to the first cluster of the second logical page of the latch circuit XDL2 has not ended (step S213_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0291] If the data input to latch circuit XDL2 ends (step S213_Yes), then sequencer 123 transmits the data from latch circuit XDL2 to latch circuit ADL2 (step S214). Additionally, sequencer 123 sets the starting address of latch circuit XDL1 in column counter 125 as column address CA (step S215). In page buffer 133, based on the column address CA received from column counter 125, data input to the second cluster of the logical second page of latch circuit XDL1 and data input to the third cluster of the logical second page of latch circuit XDL2 are executed sequentially. Furthermore, if step S213_Yes, then data input to the second cluster of the logical second page of latch circuit XDL1 begins, and during this period, sequencer 123 may also execute step S214.

[0292] If the data input to the third cluster of the second logical page of the latch circuit XDL2 has not ended (step S216_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[0293] If the data input to latch circuit XDL2 is complete (step S216_Yes), then the data input to the second logic page of latch circuits XDL1 and XDL2 is complete. Sequencer 123 sets the external RBn signal and the internal RBn signal to "L" level. Furthermore, sequencer 123 determines the state of each memory element transistor MC based on the combination of the input data from the first logic page and the data from the second logic page, i.e., the data from the Lower page, Middle page, and Upper page.

[0294] The sequencer 123 executes program actions based on the determined state (step S217).

[0295] After the program action is completed, the sequencer 123 performs the program verification action (step S218).

[0296] If the verification fails (step S219_No), the sequencer 123 checks whether the number of program loops has reached the preset upper limit (step S220).

[0297] If the program loop count has not reached the upper limit (step S220_No), the sequencer 123 executes the program action (step S217). That is, the sequencer 123 repeatedly performs the program loop.

[0298] If the program loop count reaches the upper limit (step S220_Yes), the sequencer 123 ends the write operation and reports to the memory controller 200 that the write operation has not ended normally.

[0299] If the verification is successful (step S219_ is), that is, if the writing of states “S1” to “S7” is completed, the sequencer 123 sets the external RBn signal to the “H” level and ends the full sequence writing operation.

[0300] 1.5.2 Command sequence for writing actions

[0301] Next, use Figure 18 An example of a sequence of instructions for a write operation is illustrated. Figure 18 This shows the instruction sequence for a full-sequence write operation. Figure 18 In the example, for the sake of simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted.

[0302] like Figure 18 As shown, firstly, the memory controller 200 sends a write operation notification instruction "80h" to the memory 100. Next, the memory controller 200 sends the logical page address "AD-P1" of the first logical page. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address. Then, the memory controller 200 sends the data of the first logical page to the memory 100. The first cluster of the first logical page is saved to latch circuit XDL1 and then transmitted to latch circuit ADL1. The second cluster of the first logical page is saved to latch circuit XDL2 and then transmitted to latch circuit BDL2. The third cluster of the first logical page is saved to latch circuit XDL1 and then transmitted to latch circuit BDL1.

[0303] Next, the memory controller 200 sends an instruction "1Ah" to the memory 100 notifying the input of data for the next logical page. Then, the memory controller 200 sends the instruction "80h" and the logical page address "AD-P2" for the second logical page to the memory 100. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P2" into a physical page address. Next, the memory controller 200 sends the data for the second logical page to the memory 100. After the first cluster of the second logical page is saved to the latch circuit XDL2, it is transferred to the latch circuit ADL2. The second cluster of the second logical page is saved to the latch circuit XDL1. The third cluster of the second logical page is saved to the latch circuit XDL2. Next, the memory controller 200 sends an instruction "10h" to the memory 100 instructing the execution of the write operation.

[0304] If sequencer 123 receives the instruction "10h", it sets both the internal and external RBn signals to "L" level. Furthermore, sequencer 123 determines the state of the transistor MC of each memory element and performs the write operation based on the data stored in latch circuits ADL1, ADL2, BDL1, BDL2, XDL1, and XDL2. After the write operation is completed, sequencer 123 sets both the internal and external RBn signals to "H" level. Additionally, after the first cluster of the first logical page is saved to latch circuit XDL1, the data of the second cluster of the first logical page is transmitted to latch circuit ADL1 while the data of the third cluster of the first logical page is stored in latch circuit XDL2. After the second cluster of the first logical page is saved to latch circuit XDL2, the data of the third cluster of the first logical page is transmitted to latch circuit BDL2 while the data of the third cluster of the first logical page is stored in latch circuit XDL1. After the third cluster of logical page 1 is saved to latch circuit XDL1, the data of the first cluster of logical page 2 is transferred to latch circuit BDL1 while the data of the second cluster of logical page 2 is saved to latch circuit XDL2. After the first cluster of logical page 2 is saved to latch circuit XDL2, the data of the second cluster of logical page 2 is transferred to latch circuit ADL2 while the data of the second cluster of logical page 2 is saved to latch circuit XDL1. The second cluster of logical page 2 is saved to latch circuit XDL1. The third cluster of logical page 2 is saved to latch circuit XDL2. By doing so as described above, the time of data transfer from latch circuit XDL1 or latch circuit XDL2 to latch circuit ADL1 or latch circuit ADL2 or latch circuit BDL1 or latch circuit BDL2 is not visible externally (to memory controller 200). Additionally, when data input occurs from the address of the second or third cluster within the first logical page, data is input to latch circuits XDL2 and XDL1 or latch circuit XDL1, and then transferred to latch circuits BDL2 and BDL1 or latch circuit BDL1. Similarly, when data input occurs from the address of the second or third logical page within the second logical page, data is input to latch circuits XDL1 and XDL2 or latch circuit XDL2, and then the write operation begins. In this case, latch circuit XDL with no data input is set to "1" (no data being written).

[0305] 1.6 Effects of this implementation method

[0306] If this embodiment is configured, the increase in the chip area of ​​the semiconductor memory can be suppressed. This effect will be described in detail.

[0307] To increase the storage capacity of flash memory, miniaturization of memory element transistors is underway. If peripheral circuitry such as sense amplifiers and page buffers are also miniaturized along with the memory element transistors, the chip area can be reduced, increasing the capacity density per chip area. However, the miniaturization rate of peripheral circuitry is slower than that of memory element transistors. This is because reducing the size of transistors in peripheral circuitry without decreasing the operating voltage will lead to increased leakage current and reduced memory lifetime.

[0308] To improve capacity density per chip area, configurations have been proposed such as placing peripheral circuitry below the memory element array (between the memory element array and the semiconductor substrate) or forming the peripheral circuitry on a separate semiconductor substrate and bonding it to the memory element array. However, with such configurations, if the miniaturization and high integration (high-layer stacking) of the memory element array progresses, the following situation arises: although the area of ​​the memory element array decreases, the area of ​​the peripheral circuitry does not decrease significantly, and the area of ​​the peripheral circuitry tends to be larger than that of the memory element array. As a result, the chip size becomes determined by the size of the peripheral circuitry, and the miniaturization and high-layer stacking of the memory element array are not easily reflected in the reduction of the chip area.

[0309] In contrast, with the configuration of this embodiment, the page size of the physical page can be smaller than that of the logical page. More specifically, write data consisting of the page size of the logical page can be divided and written to multiple physical pages. Furthermore, data read from multiple physical pages can be combined and output as data for the logical page. Because the page size of the physical page can be reduced, the number of sense amplifier units (SAUs) corresponding to the physical page can be reduced. That is, the number of sensing circuits in the sense amplifier 132 and the number of latching circuits in the page buffer 133 can be reduced. Therefore, the increase in the chip area of ​​the semiconductor memory can be suppressed.

[0310] Furthermore, with this embodiment, by making the physical page size smaller than the logical page, the area (number of sensing circuits and latching circuits) of the sense amplifier 132 and page buffer 133 can be reduced. Therefore, when the area of ​​the memory element array 130 is reduced due to miniaturization and layer stacking, the area of ​​the peripheral circuits can also be reduced. That is, the mismatch between the area of ​​the memory element array 130 and the area of ​​the peripheral circuits disposed below the memory element array 130 can be reduced. Thus, the miniaturization and layer stacking of the memory element array 130 are easily reflected in the reduction of the chip area.

[0311] Furthermore, with this embodiment, data read from multiple physical pages can be combined and output as data for a logical page. Therefore, the semiconductor memory of this embodiment can be used without changing the specifications of the memory controller 200. That is, the data management method in a memory system equipped with the semiconductor memory of this embodiment can be directly reused, thus facilitating system design.

[0312] Furthermore, with this embodiment, the physical page size can be reduced. That is, the number of memory element transistors MC in a memory group MG shared by the word line WL can be reduced. This shortens the wiring length of the word line WL. Consequently, the wiring resistance and wiring capacitance of the word line WL can be reduced. Therefore, the charging and discharging time of the voltage applied to the word line WL can be shortened during read and write operations. Thus, the increase in processing time during read and write operations can be suppressed.

[0313] Furthermore, in this embodiment, the data encoding applied to the physical page includes a bit with a boundary count of 1. Moreover, the boundary count of bits with a non-zero boundary count is encoded so that the maximum boundary count is minimized. Therefore, when reading multiple physical pages corresponding to one logical page, the increase in read time caused by the increase in the boundary count (the number of read operations) can be suppressed.

[0314] 2. Second Implementation Method

[0315] Next, the second embodiment will be described. In the second embodiment, seven examples are shown regarding the TLC encoding that differs from the first embodiment. Hereinafter, the description will focus on the points that differ from the first embodiment.

[0316] 2.1 Case 1

[0317] First, use Figure 19 The encoding of the first example will be explained. Figure 19 It is a table that shows the allocation of data to each state.

[0318] like Figure 19 As shown, in this example, similar to the first embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0319] "S0" status: "111" data

[0320] "S1" status: "011" data

[0321] "S2" status: "001" data

[0322] "S3" status: "101" data

[0323] "S4" status: "100" data

[0324] "S5" status: "110" data

[0325] "S6" status: "010" data

[0326] "S7" status: "000" data

[0327] When the data is read in this manner, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R2, R5, and R7. The Upper page is determined by reading actions R1, R3, and R6. Therefore, the data allocation in this example is the same as in the first embodiment, and is 1-3-3 encoded.

[0328] In this example, similar to the first embodiment, the allocation of data relative to the Upper, Middle, and Lower bits includes one bit with a boundary number of 1. Furthermore, the boundary number of bits with a boundary number other than 1 is encoded so that the maximum boundary number becomes the minimum.

[0329] 2.2 Case 2

[0330] Next, use Figure 20 The encoding of example 2 will be explained. Figure 20 It is a table that shows the allocation of data to each state.

[0331] like Figure 20 As shown, in this example, similar to the first embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0332] "S0" status: "110" data

[0333] "S1" status: "100" data

[0334] "S2" status: "000" data

[0335] "S3" status: "010" data

[0336] "S4" status: "011" data

[0337] "S5" status: "111" data

[0338] "S6" status: "101" data

[0339] "S7" status: "001" data

[0340] When the data is read in this manner, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R1, R3, and R6. The Upper page is determined by reading actions R2, R5, and R7. Therefore, the data allocation in this example is the same as in the first embodiment, and is 1-3-3 encoded.

[0341] In this example, similar to the first embodiment, the allocation of data relative to the Upper, Middle, and Lower bits includes one bit with a boundary number of 1. Furthermore, the boundary number of bits with a boundary number other than 1 is encoded so that the maximum boundary number becomes the minimum.

[0342] 2.3 Example 3

[0343] Next, use Figure 11 The encoding of example 3 will be explained. Figure 21 It is a table that shows the allocation of data to each state.

[0344] like Figure 21 As shown, in this example, similar to the first embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0345] "S0" status: "110" data

[0346] "S1" status: "010" data

[0347] "S2" status: "000" data

[0348] "S3" status: "100" data

[0349] "S4" status: "101" data

[0350] "S5" status: "111" data

[0351] "S6" status: "011" data

[0352] "S7" status: "001" data

[0353] When the data is read in this manner, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R2, R5, and R7. The Upper page is determined by reading actions R1, R3, and R6. Therefore, the data allocation in this example is the same as in the first embodiment, and is 1-3-3 encoded.

[0354] In this example, similar to the first embodiment, the allocation of data relative to the Upper, Middle, and Lower bits includes one bit with a boundary number of 1. Furthermore, the boundary number of bits with a boundary number other than 1 is encoded so that the maximum boundary number becomes the minimum.

[0355] 2.4 Case 4

[0356] Next, use Figure 22 The encoding of example 4 will be explained. Figure 22 It is a table that shows the allocation of data to each state.

[0357] like Figure 22 As shown, in this example, similar to the first embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0358] "S0" status: "111" data

[0359] "S1" status: "101" data

[0360] "S2" status: "001" data

[0361] "S3" status: "011" data

[0362] "S4" status: "010" data

[0363] "S5" status: "000" data

[0364] "S6" status: "100" data

[0365] "S7" status: "110" data

[0366] Given this data allocation, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R1, R3, R5, and R7. The Upper page is determined by reading actions R2 and R6. Therefore, the data allocation in this example is 1-4-2 encoded.

[0367] In this example, similar to the first embodiment, the allocation of data relative to the Upper, Middle, and Lower bits includes one bit with a boundary count of 1. However, in this example, the boundary count of bits with a boundary count other than 1 is not encoded so that the maximum boundary count becomes the minimum.

[0368] 2.5 Example 5

[0369] Next, use Figure 23 The encoding of example 5 will be explained. Figure 23It is a table that shows the allocation of data to each state.

[0370] like Figure 23 As shown, in this example, similar to the first embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0371] "S0" status: "111" data

[0372] "S1" status: "011" data

[0373] "S2" status: "001" data

[0374] "S3" status: "101" data

[0375] "S4" status: "100" data

[0376] "S5" status: "000" data

[0377] "S6" status: "010" data

[0378] "S7" status: "110" data

[0379] Given this data allocation, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R2 and R6. The Upper page is determined by reading actions R1, R3, R5, and R7. Therefore, the data allocation in this example is 1-2-4 encoded.

[0380] In this example, similar to the first embodiment, the allocation of data relative to the Upper, Middle, and Lower bits includes one bit with a boundary count of 1. However, in this example, the boundary count of bits with a boundary count other than 1 is not encoded so that the maximum boundary count becomes the minimum.

[0381] 2.6 Case 6

[0382] Next, use Figure 24 The encoding of example 6 will be explained. Figure 24 It is a table that shows the allocation of data to each state.

[0383] like Figure 24 As shown, in this example, similar to the first embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0384] "S0" status: "110" data

[0385] "S1" status: "100" data

[0386] "S2" status: "000" data

[0387] "S3" status: "010" data

[0388] "S4" status: "011" data

[0389] "S5" status: "001" data

[0390] "S6" status: "101" data

[0391] "S7" status: "111" data

[0392] Given this data allocation, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R1, R3, R5, and R7. The Upper page is determined by reading actions R2 and R6. Therefore, the data allocation in this example is 1-4-2 encoded.

[0393] In this example, similar to the first embodiment, the allocation of data relative to the Upper, Middle, and Lower bits includes one bit with a boundary count of 1. However, in this example, the boundary count of bits with a boundary count other than 1 is not encoded so that the maximum boundary count becomes the minimum.

[0394] 2.7 Case 7

[0395] Next, use Figure 25 The encoding of example 7 is explained. Figure 25 It is a table that shows the allocation of data to each state.

[0396] like Figure 25 As shown, in this example, similar to the first embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0397] "S0" status: "110" data

[0398] "S1" status: "010" data

[0399] "S2" status: "000" data

[0400] "S3" status: "100" data

[0401] "S4" status: "101" data

[0402] "S5" status: "001" data

[0403] "S6" status: "011" data

[0404] "S7" status: "111" data

[0405] Given this data allocation, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R2 and R6. The Upper page is determined by reading actions R1, R3, R5, and R7. Therefore, the data allocation in this example is 1-2-4 encoded.

[0406] In this example, similar to the first embodiment, the allocation of data relative to the Upper, Middle, and Lower bits includes one bit with a boundary count of 1. However, in this example, the boundary count of bits with a boundary count other than 1 is not encoded so that the maximum boundary count becomes the minimum.

[0407] 2.8 Effects of this implementation method

[0408] The coding of this embodiment can be applied to the first embodiment.

[0409] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0410] 3. Third Implementation Method

[0411] Next, the third embodiment will be described. In the third embodiment, two examples will be given regarding the readout operation that differs from the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0412] 3.1 Example 1

[0413] First, let's explain the reading action in the first example. In the first example, the reading action is used... Figure 26 and Figure 27 The order of the read voltage applied to the select word line WL during the read operation of the first and second logic pages will be explained as different from that in the first embodiment. Figure 26 This shows the instruction sequence for reading the first logical page. Figure 27 This shows the instruction sequence for the logical second page read operation. Figure 26 and Figure 27 In the example, for simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. Additionally, in... Figure 26 and Figure 27 In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[0414] First, let's explain the instruction sequence in the read operation of the first page of logic.

[0415] like Figure 26As shown, in the read operation (read operation R4) of the Lower page corresponding to the first logical page and the read operation (read operations R1, R3, and R6) of the Middle page, the sequencer 123 executes the read operation in the order of R6, R4, R3, and R1. That is, read voltages V6, V4, V3, and V1 are applied sequentially to the select word line WL. In this case, similar to the first embodiment, after the read operation R4 corresponding to the Lower page is completed, the external RBn signal is set to the "H" level. Furthermore, the read result of the Lower page is stored in the latch circuits ADL1 and ADL2. Alternatively, the memory 100 may set the external RBn signal to be the same as the internal RBn signal, and after reading all the data of the first logical page, set the external RBn signal (internal RBn signal) to the "H" level and output the data.

[0416] Furthermore, the sequencer 123 can also perform the read operation in the order of R1, R3, R4, and R6. That is, the read voltages V1, V3, V4, and V6 can be applied sequentially to the select word line WL.

[0417] Next, the instruction sequence in the read operation of the second page of logic will be explained.

[0418] like Figure 27 As shown, in the read operation (read operation R4) of the Lower page corresponding to the second logical page and the read operation (read operations R2, R5, and R7) of the Upper page, the sequencer 123 executes the read operation in the order of R7, R5, R4, and R2. That is, read voltages V7, V5, V4, and V2 are applied to the select word line WL in sequence. In this case, similar to the first embodiment, after the read operation R4 corresponding to the Lower page is completed, the external RBn signal is set to the "H" level. Furthermore, the read result of the Lower page is stored in the latch circuits ADL1 and ADL2. Alternatively, the memory 100 may set the external RBn signal to be the same as the internal RBn signal, and after reading all the data of the second logical page, set the external RBn signal (internal RBn signal) to the "H" level and output the data.

[0419] Furthermore, the sequencer 123 can also perform the read operation in the order of R2, R4, R5, and R7. That is, the read voltages V2, V4, V5, and V7 can be applied to the select word line WL in sequence.

[0420] 3.2 Case 2

[0421] Next, the reading action in the second example will be explained. In this example, the reading action is used. Figure 28This section explains the scenario where data from the Lower, Middle, and Upper pages are read together. This type of read operation will be referred to as a "sequential read operation." In this example, states "S0" through "S7" are read together. Figure 28 This shows the instruction sequence for the sequential readout action. Figure 28 In the example, for simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. Additionally, in... Figure 28 In the example, part of the instruction and the address were also omitted. Furthermore, in Figure 28 In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[0422] like Figure 28 As shown, if sequencer 123 receives the instruction "30h", it responds by initiating a read operation. First, sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, sequencer 123 performs a sequential read operation. More specifically, sequencer 123 executes read operations R1 to R7 sequentially. During this time, read voltages V1 to V7 are applied sequentially to the select word line WL. If read operation R4 ends, sequencer 123 determines the data for the Lower page and sets the external RBn signal to the "H" level. The data for the Lower page is stored in latch circuits ADL1 and ADL2. Furthermore, the data in latch circuit ADL1 (the data of the first cluster of the first logical page) is transferred to latch circuit XDL1. If memory controller 200 receives the "H" level external RBn signal, it sends a signal REn (not shown) to memory 100. Input / output circuit 110 begins outputting data based on signal REn. First, the input / output circuit 110 outputs the data of the latch circuit XDL1 (the data of the first cluster of the first page of logic).

[0423] If the read operation R6 ends, sequencer 123 then determines the data for the Middle page. The data for the Middle page is stored in latch circuits BDL1 and BDL2. The data in latch circuit BDL2 (data for the second cluster of logical page 1) is transmitted to latch circuit XDL2. The data in latch circuit BDL1 (data for the third cluster of logical page 1) is transmitted to latch circuit XDL1 after the data for the Lower page (data for the first cluster of logical page 1) stored in latch circuit XDL1 is output.

[0424] If the sequential reading operation ends during the period when the data of latch circuit XDL1 or XDL2 is output, the sequencer 123 sets the internal RBn signal to the "H" level.

[0425] If the data stored in the Middle page of latch circuit XDL2 (data of the second cluster of the first logical page) is output, then the data of latch circuit ADL2 (data of the first cluster of the second logical page) is transmitted to latch circuit XDL2.

[0426] If the output of data stored in the Middle page of latch circuit XDL1 (data of the third cluster of logic page 1) ends, the data output of logic page 1 ends, and then the data output of logic page 2 begins. First, the data stored in the Lower page of latch circuit XDL2 (data of the first cluster of logic page 2) is output. Additionally, if the output of data stored in the Middle page of latch circuit XDL1 (data of the third cluster of logic page 1) ends, then the data of the Upper page (data of the second cluster of logic page 2) is transmitted from sensing circuit SA1 to latch circuit XDL1.

[0427] If the data stored in the Upper page of latch circuit XDL2 (data of the first cluster of the second logical page) is output, then the data of sensing circuit SA2 (data of the third cluster of the second logical page) is transmitted to latch circuit XDL2. If the data output of latch circuit XDL2 (data of the third cluster of the second logical page) is output, then the sequential readout operation ends.

[0428] Furthermore, the sequencer 123 can also perform the read operation in the order of R7 to R1. That is, the read voltage can also be applied to the select word line WL in the order of voltage V7 to V1. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and after reading all the data, set the external RBn signal (internal RBn signal) to the "H" level and output the data.

[0429] 3.3 Effects of this implementation method

[0430] The coding of this embodiment can be applied to the first embodiment.

[0431] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0432] Furthermore, with this embodiment, the read voltage can be applied in ascending or descending order during the read operation. This suppresses the increase in the amplitude of voltage variation applied to the select word line WL. Consequently, the time spent on voltage transition applied to the select word line WL can be shortened, reducing the processing time of the read operation.

[0433] 4. Fourth Implementation Method

[0434] Next, the fourth embodiment will be described. In the fourth embodiment, a case where data of one logical page is allocated to two physical pages (i.e., one memory group MG capable of storing two-page data) will be described. Hereinafter, the description will focus on the points different from the first to the third embodiments.

[0435] 4.1 Threshold Voltage Distribution of Memory Element Transistors

[0436] First, use Figure 29 to describe the threshold voltage distribution that the memory element transistor MC can take. Figure 29 is a diagram showing the relationship between the threshold voltage distribution of the memory element transistor MC and the allocation of data. Hereinafter, in the present embodiment, a case where the memory element transistor MC is an MLC (Multi Level Cell: multi-level element) (or also denoted as "2bit / Cell") capable of holding 4-value (2-bit) data will be described.

[0437] As Figure 29 shown, the threshold voltage of each memory element transistor MC takes a value included in one of, for example, four discrete distributions. Hereinafter, the four distributions will be denoted as the "S0" state, the "S1" state, the "S2" state, and the "S3" state in ascending order of threshold voltage.

[0438] The "S0" state, for example, corresponds to the erased state of data. And the "S1" to "S3" states correspond to the states where data is written by injecting charge into the charge storage layer. In the write operation, the verification voltages corresponding to the respective threshold voltage distributions are set as V1 to V3. Then, these voltage values are in the relationship of V1 < V2 < V3 < Vread.

[0439] In addition, the set values of the verification voltage and the read voltage corresponding to each state may be the same or different. Hereinafter, for simplicity of description, a case where the verification voltage and the read voltage have the same set value will be described.

[0440] Hereinafter, the read operations corresponding to the read operations of the "S1" to "S3" states will be denoted as read operations R1, R2, and R3, respectively. The read operation R1 determines whether the threshold voltage of the memory element transistor MC is lower than the voltage V1. The read operation R2 determines whether the threshold voltage of the memory element transistor MC is lower than the voltage V2. The read operation R3 determines whether the threshold voltage of the memory element transistor MC is lower than the voltage V3.

[0441] As described above, each memory element transistor MC can take on four states by having one of four threshold voltage distributions. By assigning these states to "00" through "11" in binary notation, each memory element transistor MC can hold 2 bits of data. Hereinafter, the 2 bits of data will be referred to as Lower bits and Upper bits, respectively. In addition, the set of Lower bits written (or read) to the memory bank MG is referred to as Lower page, and the set of Upper bits is referred to as Upper page.

[0442] exist Figure 29 In the example, for the memory element transistor MC included in each threshold voltage distribution, data is allocated to the "Upper bit / Lower bit" as shown below. For each state, data is allocated in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0443] "S0" status: "11" data

[0444] "S1" status: "01" data

[0445] "S2" status: "00" data

[0446] "S3" status: "10" data

[0447] When reading data with this allocation, the Lower page is determined by read action R2. The Upper page is determined by read actions R1 and R3. That is, the values ​​of the Lower and Upper bits are determined by one and two read actions, respectively. Therefore, the data allocation in this example is 1-2 encoding.

[0448] Furthermore, the allocation of data to states “S0” to “S3” is not limited to 1-2 encoding.

[0449] 4.2 Transformation between logical page address and physical page address

[0450] Next, use Figure 30 and Figure 31 An example illustrating the transformation between logical page addresses and physical page addresses is provided. Figure 30 It is a diagram illustrating the process of changing logical page addresses and physical page addresses. Figure 31 This is a diagram showing the allocation of logical page data relative to physical pages.

[0451] like Figure 30As shown, for example, if the memory controller 200 receives a write request from the host device 2, it allocates a logical page address "90001" corresponding to the received logical address "00001". Hereinafter, the allocated logical page will be referred to as "Logical Page 1". Figure 30 In the example, logical page 1 corresponds to logical page address "90001".

[0452] If the instruction user interface circuit 121 receives a logical page address and a write command for a logical page from the memory controller 200, it transforms the logical page address of the logical page into the physical page address of two pages. In this embodiment, the instruction user interface circuit 121 transforms the logical page address of the first logical page into the physical page addresses of the Lower and Upper pages.

[0453] At this point, the data length of one logical page is the same as the data length of two physical pages. In this embodiment, the number of logical pages written is a = "1", and the number of physical pages written is b = "2". Therefore, the page size n of one physical page, i.e., one memory group MG, can be represented by n = m / 2. For example, when the page size of the logical page is 16 [kB], the page size of the physical page is n = 16 / 2 = 8 [kB].

[0454] For example, sequencer 123 writes data of logical first page to the Lower and Upper pages of a memory bank MG based on the physical page address transformed in instruction user interface circuit 121.

[0455] Next, the configuration of logical page data in a memory group MG is described in detail.

[0456] like Figure 31 As shown, in this embodiment, the data of the logical first page is divided into two groups, designated as the first cluster and the second cluster starting from the beginning of the data. For example, the memory 100 writes the first half of the data of the first cluster of the logical first page to the first element area of ​​the Lower page, and writes the second half of the data of the first cluster of the logical first page to the second element area. Similarly, the memory 100 writes the first half of the data of the second cluster of the logical first page to the first element area of ​​the Upper page, and writes the second half of the data of the second cluster of the logical first page to the second element area.

[0457] 4.3 Reading Action

[0458] Next, the read operation will be explained. In this embodiment, the physical pages that are read from relative to the logical first page are the Lower page (first element area and second element area) and the Upper page (first element area and second element area). In this case, the memory 100 sends (outputs) the data from the Lower page (first element area and second element area) and the data from the Upper page (first element area and second element area) to the memory controller 200.

[0459] 4.3.1 Reading out the action flow

[0460] First, use Figure 32 The process of reading from memory 100 is explained. Figure 32 This is a flowchart of the reading action.

[0461] like Figure 32 As shown, memory 100 receives a read command from memory controller 200 (step S1). After the instruction user interface circuit 121 converts the logical page address into a physical page address, it sends the received instruction and the converted physical page address to sequencer 123.

[0462] The sequencer 123 first executes the read operation of the Lower page (step S30). More specifically, the sequencer 123 executes the read operation R2 corresponding to the read voltage V2.

[0463] Sequencer 123 determines the data of the Lower page (the data of the first cluster of the logical first page) based on the result of the read action R2 (step S31).

[0464] Sequencer 123 transmits the data of the Lower page read by sensing circuits SA1 and SA2 to latching circuits ADL1 and ADL2 respectively (step S32).

[0465] Sequencer 123 transmits the data (data of the first cluster of the first logical page) of latch circuits ADL1 and ADL2 to latch circuits XDL1 and XDL2 respectively (step S33). In addition, sequencer 123 can also directly transmit the data of the Lower page read by sensing circuits SA1 and SA2 to latch circuits XDL1 and XDL2 respectively.

[0466] Sequencer 123 sets the starting address of latch circuit XDL1 as column address CA in column counter 125 (step S34). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL1 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data to latch circuits XDL1 and XDL2 of memory controller 200.

[0467] The sequencer 123 performs the Upper page read operation in parallel with the data outputs of the latch circuits XDL1 and XDL2 (step S35). More specifically, the sequencer 123 performs read operation R1 corresponding to the read voltage V1 and read operation R3 corresponding to the read voltage V3. Furthermore, the order of read operations R1 and R3 can be arbitrarily set.

[0468] Sequencer 123 determines the data of the Upper page (the data of the second cluster of the logical first page) based on the results of read actions R1 and R3 (step S36).

[0469] Sequencer 123 transmits the data of the Upper page read by sensing circuits SA1 and SA2 to latching circuits ADL1 and ADL2 respectively (step S37).

[0470] If the output of data from the latch circuit XDL1 has not ended (step S38_No), the sequencer 123 will repeatedly perform the data output confirmation action until the output ends.

[0471] If the data output of latch circuit XDL1 ends (step S38_Yes), then sequencer 123 transmits the data of latch circuit ADL1 to latch circuit XDL1 (step S39). Furthermore, if step S38_Yes, then the data output of latch circuit XDL2 begins, and during the data output of latch circuit XDL2, sequencer 123 may also execute step S39.

[0472] If the output of data from the latch circuit XDL2 has not ended (step S40_No), the sequencer 123 will repeatedly perform the data output confirmation action until the output ends.

[0473] If the data output of latch circuit XDL2 ends (step S40_Yes), then sequencer 123 transmits the data of latch circuit ADL2 to latch circuit XDL2 (step S41). If the data output of latch circuits XDL1 and XDL2 (data of the second cluster of the first logical page) ends, then sequencer 123 ends the read operation of the first logical page. Furthermore, if step S40_Yes, then the data output of latch circuit XDL1 begins, and during the data output of latch circuit XDL1, sequencer 123 may also execute step S41.

[0474] 4.3.2 Reading the instruction sequence of the action

[0475] Next, use Figure 33 An example of a sequence of instructions for reading out actions is illustrated. Figure 33 This is the instruction sequence for reading the logical first page. Figure 33 In the example, for the sake of simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. Furthermore, in Figure 33 In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[0476] like Figure 33 As shown, the memory controller 200 first sends the instruction "00h". Next, the memory controller 200 sends the logical page address "AD-P1" for the first logical page. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address. Then, the memory controller 200 sends the instruction "30h" to the memory 100. The instruction user interface circuit 121 sequentially sends the received instruction and the converted physical page address to the sequencer 123.

[0477] The sequencer 123 responds to the instruction "30h" and begins the read operation. First, the sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, the sequencer 123 executes the lower page read operation (read operation R2). That is, a read voltage V2 is applied to the select word line WL. The lower page read result is stored in latch circuits ADL1 and ADL2. Data from latch circuit ADL1 is transferred to latch circuit XDL1. Data from latch circuit ADL2 is transferred to latch circuit XDL2. If the lower page read operation ends, the sequencer 123 sets the external RBn signal to the "H" level. Furthermore, if the lower page read operation ends, the sequencer 123 then begins the upper page read operation (read operations R1 and R3). That is, read voltages V1 and V3 are applied sequentially to the select word line WL.

[0478] If the memory controller 200 receives an external RBn signal at level "H", it sends a signal REn (not shown) to the memory 100. The input / output circuit 110 starts outputting data based on the signal REn. First, the input / output circuit 110 outputs the data from the latch circuit XDL1. If the read operation of the Upper page ends while the data from the latch circuit XDL1 is being output, the sequencer 123 sets the internal RBn signal to level "H". The read result of the Upper page is stored in the latch circuits ADL1 and ADL2. Furthermore, if the data output from the latch circuits XDL1 and XDL2 ends before the read operation of the Upper page ends, the sequencer 123 can also temporarily set the external RBn signal to level "L" (busy state) to interrupt the data output to the memory controller 200. Thus, it is possible to continuously output the data of the Upper page after outputting the data of the Lower page.

[0479] If the data output of latch circuit XDL1 ends, input / output circuit 110 then begins the data output of latch circuit XDL2. During the output of data from latch circuit XDL2, data from latch circuit ADL1 is transferred to latch circuit XDL1. If the data output of latch circuit XDL2 ends, input / output circuit 110 then executes the output of data from latch circuit XDL1. During the output of data from latch circuit XDL1, data from latch circuit ADL2 is transferred to latch circuit XDL2. If the output of data from latch circuit XDL2 ends, the read operation of the first logical page ends. Alternatively, memory 100 can set the external RBn signal to be the same as the internal RBn signal, and after reading all data, set the external RBn signal (internal RBn signal) to "H" level and output the data.

[0480] 4.4 Write Action

[0481] Next, the write operation will be explained. In this embodiment, a full-sequence write operation is performed, where data from the first page of the execution logic is written to the memory group MG, which has both Lower and Upper pages. That is, two bits of data are written to one memory element transistor MC. In the full-sequence write operation of this embodiment, the write operation is performed in states "S1" to "S3".

[0482] 4.4.1 Write operation process

[0483] Next, use Figure 34 and Figure 35 The process of writing operations in memory 100 is described. Figure 34 and Figure 35 This is a flowchart of the write operation.

[0484] like Figure 34 and Figure 35 As shown, during the write command reception, memory 100 receives a write command for logical page 1 from memory controller 200 (step S230). At this time, instruction user interface circuit 121 converts the logical page address of logical page 1 into a physical page address.

[0485] The sequencer 123 sets the starting address of the latch circuit XDL1 as the column address CA in the column counter 125 (step S231).

[0486] In page buffer 133, data input to the first half of the first cluster of the first logical page of latch circuit XDL1 begins based on the column address CA received from column counter 125 (step S232).

[0487] If the data input to the first half of the first cluster of the first page of the logic of the latch circuit XDL1 has not ended (step S233_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[0488] If the data input to the first half of the first cluster of the first logical page of latch circuit XDL1 is completed (step S233_Yes), then sequencer 123 transmits the data from latch circuit XDL1 to latch circuit ADL1 (step S234). Alternatively, if the data input to the first half of the first cluster of the first logical page of latch circuit XDL1 is completed, then the data input to the second half of the first cluster of the first logical page of latch circuit XDL2 begins. Furthermore, if step S233_Yes is completed, then the data input to the second half of the first cluster of the first logical page of latch circuit XDL2 begins, and during the data input of latch circuit XDL2, sequencer 123 may also execute step S234.

[0489] If the data input to the second half of the first cluster of the first logical page of the latch circuit XDL2 has not ended (step S235_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[0490] If the data input to the latter half of the first cluster of the logical first page of the latch circuit XDL2 ends (step S235_Yes), then the sequencer 123 sets the starting address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S236). In the page buffer 133, based on the column address CA received from the column counter 125, the data input to the first half of the second cluster of the logical first page of the latch circuit XDL1 begins.

[0491] During the period when the sequencer 123 is inputting data to the first half of the second cluster of the first logical page of the latch circuit XDL1, it transmits the data of the second half of the first cluster of the first logical page of the latch circuit XDL2 to the latch circuit ADL2 (step S237).

[0492] After the data input to the first half of the second cluster of the first logical page of latch circuit XDL1 is completed, the data input to the second half of the second cluster of the first logical page of latch circuit XDL2 begins. Furthermore, if the data input to the second half of the second cluster of the first logical page of latch circuit XDL2 is not completed (step S238_No), the sequencer 123 repeatedly performs a data input confirmation operation until the input is completed.

[0493] If the data input to the second half of the second cluster of the first logical page of latch circuit XDL2 ends (step S238_Yes), then the data input to the first logical page of latch circuits XDL1 and XDL2 ends. Sequencer 123 sets the external RBn signal and the internal RBn signal to the "L" level. Sequencer 123 determines the state of each memory element transistor MC based on the combination of data from the Lower page and the Upper page.

[0494] The sequencer 123 executes program actions based on the determined state (step S239).

[0495] After the program action is completed, the sequencer 123 performs the program verification action (step S240).

[0496] If the verification fails (step S241_No), the sequencer 123 checks whether the number of program loops has reached the preset upper limit (step S242).

[0497] If the program loop count has not reached the upper limit (step S242_No), the sequencer 123 executes the program action (step S239). That is, the sequencer 123 repeatedly performs the program loop.

[0498] If the program loop count reaches the upper limit (step S242_Yes), the sequencer 123 ends the write operation and reports to the memory controller 200 that the write operation has not ended normally.

[0499] If the verification is successful (step S241_Yes), that is, if the writing of states “S1” to “S3” is completed, the sequencer 123 sets the external RBn signal to the “H” level and ends the full sequence writing operation.

[0500] 4.4.2 Command sequence for writing operations

[0501] Next, use Figure 36 An example of a sequence of instructions for a write operation is illustrated. Figure 36 It is a sequence of instructions for a full-sequence write operation. Figure 36 In the example, for the sake of simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted.

[0502] like Figure 36 As shown, firstly, the memory controller 200 sends the instruction "80h" to the memory 100. Next, the memory controller 200 sends the logical page address "AD-P1" of the logical first page. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address. Next, the memory controller 200 sends the data of the logical first page to the memory 100. If the input of data to the first half of the first cluster of the logical first page of latch circuit XDL1 ends, then the input of data to the second half of the first cluster of the logical first page of latch circuit XDL2 begins. During the input of data to the second half of the first cluster of the logical first page of latch circuit XDL2, the data stored in latch circuit XDL1 is transferred to latch circuit ADL1. If the input of data to the second half of the first cluster of the logical first page of latch circuit XDL2 ends, then the input of data to the first half of the second cluster of the logical first page of latch circuit XDL1 begins. During the input of data to the first half of the second cluster of the first logical page of latch circuit XDL1, data stored in latch circuit XDL2 is transferred to latch circuit ADL2. Once the input of data to the first half of the second cluster of the first logical page of latch circuit XDL1 is complete, the input of data to the second half of the second cluster of the first logical page of latch circuit XDL2 begins. The second cluster of the first logical page is stored in both latch circuits XDL1 and XDL2.

[0503] Next, the memory controller 200 sends the instruction "10h" to the memory 100, indicating that the write operation should be performed.

[0504] If the sequencer 123 receives the instruction "10h", it sets both the internal and external RBn signals to the "L" level. Furthermore, the sequencer 123 determines the state of the transistors MC of each memory element and performs the write operation based on the data stored in the latch circuits ADL1, ADL2, XDL1, and XDL2. After the write operation is completed, the sequencer 123 sets both the internal and external RBn signals to the "H" level.

[0505] 4.5 Effects of this implementation method

[0506] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0507] 5. Fifth Implementation Method

[0508] Next, the fifth embodiment will be described. In the fifth embodiment, the case where data from 3 logical pages is allocated to 4 physical pages (i.e., a memory group MG capable of storing 4 pages of data) will be described. Hereinafter, the description will focus on the differences from the first to fourth embodiments.

[0509] 5.1 Composition of the Sensing Amplifier and Page Buffer

[0510] First, use Figure 37 An example of the configuration of the sense amplifier 132 and the page buffer 133 will be described. Figure 37 This is a block diagram of the sense amplifier 132 and the page buffer 133.

[0511] like Figure 37 As shown, in this embodiment, the sequencer 123 divides the multiple memory element transistors MC of a memory bank MG into three regions: a first region, a second region, and a third region, for control. Similarly, the sequencer 123 controls the sense amplifier 132 and the page buffer 133 in three separate regions corresponding to the first to third region. For example, the memory element transistors MC in the first region are associated with bit lines BL0 to BL(i-1). The memory element transistors MC in the second region are associated with bit lines BL(i) to BL(j-1) (where j is an integer greater than i and less than k). The memory element transistors MC in the third region are associated with bit lines BL(j) to BL(k-1). Furthermore, the number of memory element transistors MC in the first region, the second region, and the third region is preferably the same. For example, if the number of memory element transistors MC in the first element region, the number of memory element transistors MC in the second element region, and the number of memory element transistors MC in the third element region are the same, then i, j, and k are in the relationship i = j / 2 = k / 3.

[0512] In this embodiment, the page buffer 133 includes latch circuits ADL, BDL, CDL, and XDL corresponding to one sensing circuit SA. The sensing circuit SA and the latch circuits ADL, BDL, CDL, and XDL are interconnected. In other words, the sensing circuit SA and the latch circuits ADL, BDL, CDL, and XDL are connected in a manner capable of transmitting and receiving data. The latch circuits ADL, BDL, CDL, and XDL temporarily store data DAT. For example, during a read operation, the read data determined by the sensing circuit SA is transmitted from the sensing circuit SA to one of the latch circuits ADL, BDL, CDL, and XDL. Hereinafter, the sensing circuit connected to the bit line BL corresponding to the memory element transistor MC included in the third element region will be referred to as "sensing circuit SA3". The latch circuit CDL corresponding to the sensing circuit SA1 will be referred to as "latch circuit CDL1". The latch circuit CDL corresponding to the sensing circuit SA2 will be referred to as "latch circuit CDL2". The latch circuits ADL, BDL, CDL, and XDL corresponding to the sensing circuit SA3 are designated as "Latch Circuit ADL3", "Latch Circuit BDL3", "Latch Circuit CDL3", and "Latch Circuit XDL3". Furthermore, in this embodiment, the group consisting of sensing circuit SA1, latch circuits ADL1, BDL1, CDL1, and XDL1 is designated as "Sensing Amplifier Unit SAU1". The group consisting of sensing circuit SA2, latch circuits ADL2, BDL2, CDL2, and XDL2 is designated as "Sensing Amplifier Unit SAU2". The group consisting of sensing circuit SA3, latch circuits ADL3, BDL3, CDL3, and XDL3 is designated as "Sensing Amplifier Unit SAU3".

[0513] In this embodiment, similar to the multiple sensing amplifier units SAU1 and multiple sensing amplifier units SAU2, multiple sensing amplifier units SAU3 are centrally configured in one region.

[0514] 5.2 Threshold voltage distribution of memory element transistors

[0515] Next, use Figure 38 The threshold voltage distribution that can be taken for the transistor MC of the memory element is explained. Figure 38 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistor MC and the data allocation. Hereinafter, in this embodiment, the case where the memory element transistor MC is a QLC (Quad Level Cell) (or also referred to as "4bit / Cell") capable of holding 16 values ​​(4 bits) of data will be described.

[0516] like Figure 38As shown, the threshold voltages of the respective memory element transistors MC take values included in one of, for example, 16 discrete distributions. Hereinafter, the 16 distributions are respectively denoted as the "S0" state, the "S1" state, the "S2" state, the "S3" state, the "S4" state, the "S5" state, the "S6" state, the "S7" state, the "S8" state, the "S9" state, the "S10" state, the "S11" state, the "S12" state, the "S13" state, the "S14" state, and the "S15" state in ascending order of the threshold voltage.

[0517] The "S0" state, for example, corresponds to the erased state of data. Also, the "S1" to "S15" states correspond to the states in which data is written by injecting charges into the charge storage layer. In the writing operation, verification voltages corresponding to the respective threshold voltage distributions are set as V1 to V15. Then, these voltage values are in the relationship of V1 < V2 < V3 < V4 < V5 < V6 < V7 < V8 < V9 < V10 < V11 < V12 < V13 < V14 < V15 < Vread. The voltages V1 to V15 are the voltages applied to the select word line WL during the reading operation.

[0518] More specifically, the threshold voltage included in the "S0" state is lower than the voltage V1. The threshold voltage included in the "S1" state is not less than the voltage V1 and lower than the voltage V2. The threshold voltage included in the "S2" state is not less than the voltage V2 and lower than the voltage V3. The threshold voltage included in the "S3" state is not less than the voltage V3 and lower than the voltage V4. The threshold voltage included in the "S4" state is not less than the voltage V4 and lower than the voltage V5. The threshold voltage included in the "S5" state is not less than the voltage V5 and lower than the voltage V6. The threshold voltage included in the "S6" state is not less than the voltage V6 and lower than the voltage V7. The threshold voltage included in the "S7" state is not less than the voltage V7 and lower than the voltage V8. The threshold voltage included in the "S8" state is not less than the voltage V8 and lower than the voltage V9. The threshold voltage included in the "S9" state is not less than the voltage V9 and lower than the voltage V10. The threshold voltage included in the "S10" state is not less than the voltage V10 and lower than the voltage V11. The threshold voltage included in the "S11" state is not less than the voltage V11 and lower than the voltage V12. The threshold voltage included in the "S12" state is not less than the voltage V12 and lower than the voltage V13. The threshold voltage included in the "S13" state is not less than the voltage V13 and lower than V14. The threshold voltage included in the "S14" state is not less than the voltage V14 and lower than V15. The threshold voltage included in the "S15" state is not less than the voltage V15 and lower than the voltage Vread.

[0519] Furthermore, the set values ​​for the verification voltage and the readout voltage corresponding to each state can be the same or different. For simplicity, the following explanation will focus on the case where the verification voltage and readout voltage are the same.

[0520] Hereinafter, the read actions corresponding to states "S1" to "S15" will be denoted as read actions R1 to R15. Read action R1 determines whether the threshold voltage of the memory element transistor MC is lower than voltage V1. Read action R2 determines whether the threshold voltage of the memory element transistor MC is lower than voltage V2. The same applies below. Read actions R3 to R15 respectively determine whether the threshold voltage of the memory element transistor MC is lower than voltage V3 to V15.

[0521] As described above, each memory element transistor MC can take on 16 states through one of 16 threshold voltage distributions. By assigning these states to "0000" to "1111" in binary notation, each memory element transistor MC can hold 4 bits of data. Hereinafter, these 4 bits of data will be denoted as Lower bits, Middle bits, Upper bits, and Top bits. Furthermore, the set of Lower bits written (or read) to the memory bank MG is denoted as the Lower page, the set of Middle bits as the Middle page, the set of Upper bits as the Upper page, and the set of Top bits as the Top page.

[0522] exist Figure 38 In the example, for the memory element transistors MC included in each threshold voltage distribution, data is allocated to the "Top bit / Upper bit / Middle bit / Lower bit" as shown below. For each state, data is allocated in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0523] "S0" status: "1111" data

[0524] "S1" status: "0111" data

[0525] "S2" status: "0011" data

[0526] "S3" status: "0001" data

[0527] "S4" status: "0101" data

[0528] "S5" status: "1101" data

[0529] "S6" status: "1001" data

[0530] "S7" status: "1011" data

[0531] "S8" status: "1010" data

[0532] "S9" status: "1110" data

[0533] "S10" status: "0110" data

[0534] "S11" status: "0100" data

[0535] "S12" status: "1100" data

[0536] "S13" status: "1000" data

[0537] "S14" status: "0000" data

[0538] "S15" Status: "0010" Data

[0539] When reading data with this allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R3, R7, R11, and R15. The Upper page is determined by reading actions R2, R4, R6, R9, and R13. The Top page is determined by reading actions R1, R5, R10, R12, and R14. In other words, the values ​​of the Lower, Middle, Upper, and Top bits are determined by 1, 4, 5, and 5 reading actions, respectively. That is, the number of boundaries relative to the Lower, Middle, Upper, and Top bits is 1, 4, 5, and 5, respectively. Therefore, the data allocation in this embodiment is 1-4-5-5 encoded.

[0540] In this implementation, the allocation of data relative to the Top, Upper, Middle, and Lower bits includes one bit with a boundary count of 1. Furthermore, the boundary count of bits with a boundary count other than 1 is encoded so that the maximum boundary count is minimized. For example, in QLC (4 bits / cell), the total boundary count is 15. Therefore, when distributing the remaining 14 boundary bits across the remaining 3 bits, the maximum boundary count is minimized when the boundary count is set to 4, 5, or 5 bits.

[0541] Furthermore, the allocation of data to states “S0” to “S15” is not limited to 1-4-5-5 encoding.

[0542] 5.3 Transformation between logical page address and physical page address

[0543] Next, use Figure 39 and Figure 40An example illustrating the transformation between logical page addresses and physical page addresses is provided. Figure 39 It is a diagram illustrating the process of changing logical page addresses and physical page addresses. Figure 40 This is a diagram showing the allocation of logical page data relative to physical pages.

[0544] like Figure 39 As shown, for example, if the memory controller 200 receives a write request from the host device 2, it allocates three logical page addresses "90001", "90002", and "90003" corresponding to the received three logical addresses "00001", "00002", and "00003". Hereinafter, the three allocated logical pages will be referred to as "Logical Page 1", "Logical Page 2", and "Logical Page 3". Figure 39 In the example, logical page 1 corresponds to logical page address "90001", logical page 2 corresponds to logical page address "90002", and logical page 3 corresponds to logical page address "90003".

[0545] If the instruction user interface circuit 121 receives a logical page address of 3 pages and a write command for the logical pages from the memory controller 200, it transforms the logical page address of 3 pages into a physical page address of 4 pages. In this embodiment, the instruction user interface circuit 121 transforms the logical page address of the first logical page into the physical page address of the first element region of the Lower page and the Middle page. The instruction user interface circuit 121 transforms the logical page address of the second logical page into the physical page address of the second element region of the Lower page and the Upper page. Furthermore, the instruction user interface circuit 121 transforms the logical page address of the third logical page into the physical page address of the third element region of the Lower page and the Top page.

[0546] At this point, the data length of 3 logical pages is the same as the data length of 4 physical pages. In this embodiment, the number of logical pages written is a = "3", and the number of physical pages written is b = "4". Therefore, the page size n of 1 physical page, i.e., 1 memory group MG, can be represented by n = m × 3 / 4. In addition, the page sizes of the 1st to 3rd element regions can each be represented by n / 3. For example, when the page size of the logical page is 16 [kB], the page size of the physical page is n = 16 × 3 / 4 = 12 [kB].

[0547] For example, sequencer 123 writes logical first page data to the first element region of the Lower page and the first to third element regions of the Middle page of a memory bank MG, based on the physical page address transformed in the instruction user interface circuit 121. Sequencer 123 writes logical second page data to the second element region of the Lower page and the first to third element regions of the Upper page. Sequencer 123 writes logical third page data to the third element region of the Lower page and the first to third element regions of the Top page.

[0548] Next, the configuration of logical page data in a memory group MG is described in detail.

[0549] like Figure 40 As shown, in this embodiment, the data of the logical first page, logical second page, and logical third page are each divided into four groups, designated as clusters 1 through 4 starting from the beginning of the data. For example, memory 100 writes the first cluster of logical first page to the first element area of ​​the Lower page, the second cluster of logical first page to the second element area of ​​the Middle page, the third cluster of logical first page to the third element area of ​​the Middle page, and the fourth cluster of logical first page to the first element area of ​​the Middle page. Similarly, memory 100 writes the first cluster of logical second page to the second element area of ​​the Lower page, the second cluster of logical second page to the third element area of ​​the Upper page, the third cluster of logical second page to the first element area of ​​the Upper page, and the fourth cluster of logical second page to the second element area of ​​the Upper page. The memory 100 writes the first cluster of the logical third page to the third element area of ​​the Lower page, writes the second cluster of the logical third page to the first element area of ​​the Top page, writes the third cluster of the logical third page to the second element area of ​​the Top page, and writes the fourth cluster of the logical third page to the third element area of ​​the Top page.

[0550] 5.4 Reading Action

[0551] Next, the read operation will be explained. In this embodiment, the read operation differs depending on whether the logical page to be read is the first logical page, the second logical page, or the third logical page. When the logical page is the first logical page, the physical pages to be read are the Lower page (first element area) and the Middle page (first to third element areas). In this case, the memory 100 sends (outputs) the data from the first element area of ​​the Lower page and the data from the first to third element areas of the Middle page to the memory controller 200. When the logical page is the second logical page, the physical pages to be read are the Lower page (second element area) and the Upper page (first to third element areas). In this case, the memory 100 sends (outputs) the data from the second element area of ​​the Lower page and the data from the first to third element areas of the Upper page to the memory controller 200. Furthermore, when the logical page is logical page 3, the physical pages that are read are the Lower page (third element area) and the Top page (first to third element areas). In this case, the memory 100 sends (outputs) the data of the third element area of ​​the Lower page and the data of the first to third element areas of the Top page to the memory controller 200.

[0552] 5.4.1 Reading out the action flow

[0553] First, use Figures 41-43 The process of reading from memory 100 is explained. Figures 41-43 This is a flowchart of the reading action.

[0554] like Figures 41-43 As shown, the memory 100 receives a read command for logical page 1, logical page 2, or logical page 3 from the memory controller 200 (step S1). After the instruction user interface circuit 121 converts the logical page address into a physical page address, it sends the received instruction and the converted physical page address to the sequencer 123.

[0555] If the logical page address is the logical page address of logical page 1 (step S50_Yes), sequencer 123 first executes the Lower page read operation (step S51). More specifically, sequencer 123 executes the read operation R8 corresponding to the read voltage V8.

[0556] The sequencer 123 determines the data of the Lower page based on the result of the read action R8 (step S52).

[0557] The sequencer 123 transmits the data of the Lower page read by the sensing circuits SA1 to SA3 to the latching circuits ADL1 to ADL3 respectively (step S53).

[0558] Sequencer 123 transmits the data of latch circuit ADL1 (data of the first cluster of the first page of logic) to latch circuit XDL1 (step S54).

[0559] Sequencer 123 sets the starting address of latch circuit XDL1 as column address CA in column counter 125 (step S55). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL1 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data to latch circuit XDL1 of memory controller 200. Furthermore, after sequencer 123 transmits the data of the Lower page read by sensing circuits SA1 to SA3 to latch circuits ADL1 to ADL3, it causes data in latch circuit ADL1 to be transmitted to latch circuit XDL1. However, it is also possible to directly transmit data from sensing circuit SA1 to latch circuit XDL1.

[0560] The sequencer 123 executes the Middle page read operation in parallel with the data output of the latch circuit XDL1 (step S56). More specifically, the sequencer 123 executes read operation R3 corresponding to read voltage V3, read operation R7 corresponding to read voltage V7, read operation R11 corresponding to read voltage V11, and read operation R15 corresponding to read voltage V15. Furthermore, the order of read operations R3, R7, R11, and R15 can be arbitrarily set.

[0561] The sequencer 123 determines the data of the Middle page based on the results of the read actions R3, R7, R11 and R15 (step S57).

[0562] The sequencer 123 transmits the data of the Middle page read by the sensing circuits SA1 to SA3 to the latching circuits ADL1 to ADL3 respectively (step S58).

[0563] Sequencer 123 transmits the data of latch circuits ADL2 and ADL3 (data of the second and third clusters of the first logical page) to latch circuits XDL2 and XDL3 respectively (step S59).

[0564] If the output of the data in the latch circuit XDL1 (the data of the first cluster of the first page of logic) has not ended (step S60_No), the sequencer 123 repeatedly performs the data output confirmation action until the output ends.

[0565] If the data output of latch circuit XDL1 ends (step S60_Yes), then sequencer 123 transmits the data of latch circuit ADL1 (data of the 4th cluster of the first logical page) to latch circuit XDL1 (step S61). If the data output of latch circuits XDL2 and XDL3 ends, then sequencer 123 sets the starting address of latch circuit XDL1 in column counter 125 as column address CA. Furthermore, if the data output of latch circuit XDL1 ends, then sequencer 123 terminates the read operation of the first logical page.

[0566] If the logical page address is the logical page address of the logical second page (step S50_No and step S62_Yes), the sequencer 123 performs the Lower page reading operation in the same way as in step S51 (step S63).

[0567] Sequencer 123 determines the data for the Lower page based on the result of the read action R8 (step S64).

[0568] The sequencer 123 transmits the data of the Lower page read by the sensing circuits SA1 to SA3 to the latching circuits ADL1 to ADL3 respectively (step S65).

[0569] Sequencer 123 transmits the data from latch circuit ADL2 (data from the first cluster of the second logical page) to latch circuit XDL2 (step S66). Furthermore, after sequencer 123 transmits the data from the Lower page read by sensing circuits SA1 to SA3 to latch circuits ADL1 to ADL3, it also transmits the data from latch circuit ADL2 to latch circuit XDL2. However, it can also directly transmit the data from sensing circuit SA2 to latch circuit XDL2.

[0570] Sequencer 123 sets the starting address of latch circuit XDL2 as column address CA in column counter 125 (step S67). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL2 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data to latch circuit XDL2 of memory controller 200.

[0571] The sequencer 123 executes the upper page read operation in parallel with the data output of the latch circuit XDL2 (step S68). More specifically, the sequencer 123 executes the read operation R2 corresponding to the read voltage V2, the read operation R4 corresponding to the read voltage V4, the read operation R6 corresponding to the read voltage V6, the read operation R9 corresponding to the read voltage V9, and the read operation R13 corresponding to the read voltage V13. Furthermore, the order of the read operations R2, R4, R6, R9, and R13 can be arbitrarily set.

[0572] Sequencer 123 determines the data of the Upper page based on the results of read actions R2, R4, R6, R9 and R13 (step S69).

[0573] The sequencer 123 transmits the data of the Upper page read by the sensing circuits SA1 to SA3 to the latching circuits ADL1 to ADL3 respectively (step S70).

[0574] Sequencer 123 transmits the data of latch circuits ADL1 and ADL3 (data of the second and third clusters of the second logical page) to latch circuits XDL1 and XDL3 respectively (step S71).

[0575] If the output of the data in the latch circuit XDL2 (the data of the first cluster of the second page of logic) has not ended (step S72_No), the sequencer 123 repeatedly performs the data output confirmation action until the output ends.

[0576] If the output of data from latch circuit XDL2 ends (step S72_Yes), then sequencer 123 transmits the data from latch circuit ADL2 (data from the fourth cluster of the second logical page) to latch circuit XDL2 (step S73). If the output of data from latch circuit XDL3 (data from the second cluster of the second logical page) ends, then sequencer 123 sets the starting address of latch circuit XDL1 in column counter 125 as column address CA. Furthermore, if the output of data from latch circuit XDL1 (data from the third cluster of the second logical page) and latch circuit XDL2 (data from the fourth cluster of the second logical page) ends, then sequencer 123 ends the read operation of the second logical page.

[0577] If the logical page address is the logical page address of the logical third page (step S50_No and step S62_No), the sequencer 123 performs the Lower page reading operation in the same way as in step S51 (step S74).

[0578] Sequencer 123 determines the data for the Lower page based on the result of read action R8 (step S74).

[0579] The sequencer 123 transmits the data of the Lower page read by the sensing circuits SA1 to SA3 to the latching circuits ADL1 to ADL3 respectively (step S76).

[0580] Sequencer 123 transmits the data from latch circuit ADL3 (data from the first cluster of the third logical page) to latch circuit XDL3 (step S77). Furthermore, after sequencer 123 transmits the data from the Lower page read by sensing circuits SA1 to SA3 to latch circuits ADL1 to ADL3, it transmits the data from latch circuit ADL3 to latch circuit XDL3. However, it is also possible to directly transmit the data from sensing circuit SA3 to latch circuit XDL3.

[0581] Sequencer 123 sets the starting address of latch circuit XDL3 as column address CA in column counter 125 (step S78). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL3 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data to latch circuit XDL3 of memory controller 200.

[0582] The sequencer 123 executes the Top page readout operation in parallel with the data output of the latch circuit XDL3 (step S79). More specifically, the sequencer 123 executes the readout operation R1 corresponding to the readout voltage V1, the readout operation R5 corresponding to the readout voltage V5, the readout operation R10 corresponding to the readout voltage V10, the readout operation R12 corresponding to the readout voltage V12, and the readout operation R14 corresponding to the readout voltage V14. Furthermore, the order of the readout operations R1, R5, R10, R12, and R14 can be arbitrarily set.

[0583] The sequencer 123 determines the data of the Top page based on the results of the read actions R1, R5, R10, R12 and R14 (step S80).

[0584] The sequencer 123 transmits the data of the Top page read by the sensing circuits SA1 to SA3 to the latching circuits ADL1 to ADL3 respectively (step S81).

[0585] Sequencer 123 transmits the data of latch circuits ADL1 and ADL2 (data of the second and third clusters of the third logical page) to latch circuits XDL1 and XDL2 respectively (step S82).

[0586] If the output of the data in the latch circuit XDL3 (the data of the first cluster of the third page of logic) has not ended (step S83_No), the sequencer 123 repeatedly performs the data output confirmation action until the output ends.

[0587] If the output of data from latch circuit XDL3 ends (step S83_Yes), then sequencer 123 transmits the data from latch circuit ADL3 (data from the 4th cluster of the second logical page) to latch circuit XDL3 (step S84). Additionally, if the output of data from latch circuit XDL3 (data from the 1st cluster of the third logical page) ends, then sequencer 123 sets the starting address of latch circuit XDL1 in column counter 125 as column address CA. Furthermore, if the output of data from latch circuit XDL1 (data from the 2nd cluster of the third logical page), latch circuit XDL2 (data from the 3rd cluster of the third logical page), and latch circuit XDL3 (data from the 4th cluster of the third logical page) ends, then sequencer 123 terminates the read operation of the third logical page.

[0588] 5.4.2 Reading the instruction sequence of the action

[0589] Next, use Figures 44-46 An example of a sequence of instructions for reading out actions is illustrated. Figure 44 It is the instruction sequence for reading the first page of the logic. Figure 45 It is the instruction sequence for reading the second page of the logic. Figure 46 This is the instruction sequence for reading from page 3 of the logic. Figures 44-46 In the example, for simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. Additionally, in... Figures 44-46 In the example, part of the instruction and the address were also omitted. Furthermore, in Figures 44-46 In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[0590] First, let's explain the instruction sequence in the read operation of the first page of logic.

[0591] like Figure 44As shown, sequencer 123 responds to the instruction "30h" and begins the read operation. First, sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, sequencer 123 executes the lower page read operation (read operation R8). That is, a read voltage V8 is applied to the select word line WL. The lower page read result is stored in latch circuits ADL1 to ADL3. Furthermore, the data in latch circuit ADL1 is transmitted to latch circuit XDL1. If the lower page read operation ends, sequencer 123 sets the external RBn signal to the "H" level, indicating a ready state. Additionally, if the lower page read operation ends, sequencer 123 then begins the middle page read operation (read operations R3, R7, R11, and R15). That is, read voltages V3, V7, V11, and V15 are applied sequentially to the select word line WL.

[0592] If the memory controller 200 receives an external RBn signal at a level of "H", it sends a signal REn (not shown) to the memory 100. The input / output circuit 110 begins outputting data based on the signal REn. First, the input / output circuit 110 outputs the data from the latch circuit XDL1. If the sequencer 123 stops outputting data from the latch circuit XDL1 during the middle page read operation, it temporarily sets the external RBn signal to a level of "L" until the middle page read operation is completed.

[0593] The read result of the Middle page is stored in latch circuits ADL1 to ADL3. Furthermore, the data from latch circuits ADL1 to ADL3 is transmitted to latch circuits XDL1 to XDL3. If the Middle page read operation is completed, the sequencer 123 sets both the external RBn signal and the internal RBn signal to the "H" level.

[0594] If the memory controller 200 receives an external RBn signal at a "H" level, it restarts the transmission of signal REn (not shown). The input / output circuit 110 outputs data according to the signal REn, following the sequence of latch circuits XDL2, XDL3, and XDL1. When the output of data from latch circuit XDL1 ends, the read operation of the first logical page ends. Alternatively, the memory 100 can set the external RBn signal to be the same as the internal RBn signal, read all data, and then set the external RBn signal (internal RBn signal) to a "H" level before outputting the data.

[0595] Next, the instruction sequence in the read operation of the second page of logic will be explained.

[0596] like Figure 45As shown, sequencer 123 responds to the instruction "30h" and begins the read operation. First, sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, sequencer 123 executes the lower page read operation (read operation R8). That is, a read voltage V8 is applied to the select word line WL. The lower page read result is stored in latch circuits ADL1 to ADL3. Furthermore, data from latch circuit ADL2 is transmitted to latch circuit XDL2. If the lower page read operation ends, sequencer 123 sets the external RBn signal to the "H" level, indicating a ready state. Additionally, if the lower page read operation ends, sequencer 123 then begins the upper page read operation (read operations R2, R4, R6, R9, and R13). That is, read voltages V2, V4, V6, V9, and V13 are applied sequentially to the select word line WL.

[0597] If the memory controller 200 receives an external RBn signal at a level of "H", it sends a signal REn (not shown) to the memory 100. The input / output circuit 110 begins outputting data based on the signal REn. First, the input / output circuit 110 outputs the data from the latch circuit XDL2. If the sequencer 123 stops outputting the data from the latch circuit XDL2 during the read operation of the Upper page, it temporarily sets the external RBn to a level of "L" until the read operation of the Upper page is completed.

[0598] The read result of the Upper page is stored in latch circuits ADL1 to ADL3. Furthermore, the data from latch circuits ADL1 to ADL3 is transmitted to latch circuits XDL1 to XDL3. If the read operation of the Upper page is completed, the sequencer 123 sets both the external RBn and internal RBn to the "H" level.

[0599] If the memory controller 200 receives an external RBn signal at a "H" level, it restarts the transmission of signal REn (not shown). The input / output circuit 110 outputs data according to the signal REn, following the sequence of latch circuits XDL3, XDL1, and XDL2. When the data output from latch circuit XDL2 ends, the read operation of the second logical page ends. Alternatively, the memory 100 can set the external RBn signal to be the same as the internal RBn signal, read all data, and then set the external RBn signal (internal RBn signal) to a "H" level before outputting the data.

[0600] Next, the instruction sequence in the read operation of the logic page 3 will be explained.

[0601] like Figure 46As shown, sequencer 123 responds to the instruction "30h" and begins the read operation. First, sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, sequencer 123 executes the Lower page read operation (read operation R8). That is, a read voltage V8 is applied to the select word line WL. The read result of the Lower page is stored in latch circuits ADL1 to ADL3. Furthermore, the data in latch circuit ADL3 is transmitted to latch circuit XDL3. If the Lower page read operation ends, sequencer 123 sets the external RBn signal to the "H" level, indicating a ready state. Additionally, if the Lower page read operation ends, sequencer 123 then begins the Top page read operation (read operations R1, R5, R10, R12, and R14). That is, read voltages V1, V5, V10, V12, and V14 are applied sequentially to the select word line WL.

[0602] If the memory controller 200 receives an external RBn signal at a level of "H", it sends a signal REn (not shown) to the memory 100. The input / output circuit 110 begins outputting data based on the signal REn. First, the input / output circuit 110 outputs the data from the latch circuit XDL3. If the sequencer 123 finishes outputting the data from the latch circuit XDL3 during the read operation of the Top page, it temporarily sets the external RBn to a level of "L" until the read operation of the Top page is completed.

[0603] The read result of the Top page is stored in latch circuits ADL1 to ADL3. Furthermore, the data from latch circuits ADL1 to ADL3 is transmitted to latch circuits XDL1 to XDL3. If the read operation of the Top page is completed, the sequencer 123 sets both the external RBn and internal RBn to the "H" level.

[0604] If the memory controller 200 receives an external RBn signal at a "H" level, it restarts the transmission of signal REn (not shown). The input / output circuit 110 outputs data according to the signal REn, following the sequence of latch circuits XDL1, XDL2, and XDL3. When the output of data from latch circuit XDL3 ends, the read operation of the third logical page ends. Alternatively, the memory 100 can set the external RBn signal to be the same as the internal RBn signal, read all data, and then set the external RBn signal (internal RBn signal) to a "H" level before outputting the data.

[0605] 5.5 Write Action

[0606] Next, the write operation will be explained. In this embodiment, a full-sequence write operation is performed, writing data from pages 1 to 3 of the execution logic to the memory group MG, which has Lower, Middle, Upper, and Top pages. That is, 4 bits of data are written to one memory element transistor MC. In the full-sequence write operation of this embodiment, the write is performed in states "S1" to "S15".

[0607] 5.5.1 Write operation process

[0608] Next, use Figures 47-49 The process of writing operations in memory 100 is described. Figures 47-49 This is a flowchart of the write operation.

[0609] like Figures 47-49 As shown, during the receipt of a write command, memory 100 receives the logical page address of the logical first page from memory controller 200 (step S251). Instruction user interface circuit 121 converts the logical page address of the logical first page into a physical page address.

[0610] The sequencer 123 sets the starting address of the latch circuit XDL1 as the column address CA in the column counter 125 (step S252).

[0611] In page buffer 133, data input to the first cluster of the first logical page of latch circuit XDL1 begins based on the column address CA received from column counter 125 (step S253).

[0612] If the data input to the first cluster of the first logical page of the latch circuit XDL1 has not ended (step S254_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[0613] If the data input to latch circuit XDL1 is completed (step S254_Yes), then sequencer 123 transmits the data from latch circuit XDL1 to latch circuit ADL1 (step S255). Alternatively, if the data input to latch circuit XDL1 is completed, then the data input to the second cluster of the first logical page of latch circuit XDL2 and the data input to the third cluster of the first logical page of latch circuit XDL3 are executed sequentially.

[0614] If the data input to the third cluster of the first logical page of the latch circuit XDL3 has not ended (step S256_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0615] If the data input to the latch circuit XDL3 ends (step S256_Yes), then the sequencer 123 sets the starting address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S257).

[0616] In page buffer 133, data input to the fourth cluster of the first logical page of latch circuit XDL1 begins based on the column address CA received from column counter 125.

[0617] If the data input to the fourth cluster of the first logical page of the latch circuit XDL1 has not ended (step S258_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0618] If the data input to latch circuit XDL1 ends (step S258_Yes), then the data input to the first logic page of latch circuits XDL1 to XDL3 ends.

[0619] Sequencer 123 transmits data from latch circuits XDL1 to XDL3 to latch circuits BDL1 to BDL3 respectively (step S259). This completes the data input for the first logic page. Furthermore, sequencer 123 can also transmit data from latch circuit XDL1 to latch circuit ADL1 during the data input period to latch circuit XDL2, from latch circuit XDL2 to latch circuit BDL2 during the data input period to latch circuit XDL3, from latch circuit XDL3 to latch circuit BDL3 during the data input period to latch circuit XDL1, and from latch circuit XDL1 to latch circuit BDL1 during the data input period to latch circuit XDL2.

[0620] Next, memory 100 receives the logical page address of logical second page from memory controller 200 (step S260). At this time, instruction user interface circuit 121 converts the logical page address of logical second page into a physical page address.

[0621] The sequencer 123 sets the starting address of the latch circuit XDL2 as the column address CA in the column counter 125 (step S261).

[0622] In page buffer 133, data input to the first cluster of the second logical page of latch circuit XDL2 begins based on the column address CA received from column counter 125 (step S262).

[0623] If the data input to the first cluster of the second logical page of the latch circuit XDL2 has not ended (step S263_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0624] If the data input to the first cluster of the second logical page of latch circuit XDL2 is completed (step S263_Yes), then sequencer 123 transmits the data from latch circuit XDL2 to latch circuit ADL2 (step S264). Alternatively, if the data input to latch circuit XDL2 is completed, then the data input to the second cluster of the second logical page of latch circuit XDL3 is then executed.

[0625] If the data input to the second cluster of the second logical page of the latch circuit XDL3 has not ended (step S265_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[0626] If the data input to the second cluster of the second logical page of latch circuit XDL3 is completed (step S265_Yes), then sequencer 123 sets the starting address of latch circuit XDL1 in column counter 125 as column address CA (step S266). In page buffer 133, based on the column address CA received from column counter 125, data input to the third cluster of the second logical page of latch circuit XDL1 and data input to the fourth cluster of the second logical page of latch circuit XDL2 are executed sequentially.

[0627] If the data input to the fourth cluster of the second logical page of the latch circuit XDL2 has not ended (step S267_No), the sequencer 123 repeatedly performs the data input confirmation action until the input ends.

[0628] If the data input to the fourth cluster of the second logical page of latch circuit XDL2 is completed (step S267_Yes), then the data input to the second logical page of latch circuits XDL1 to XDL3 is completed.

[0629] Sequencer 123 transmits data from latch circuits XDL1 to XDL3 to latch circuits CDL1 to CDL3 respectively (step S268). Furthermore, sequencer 123 may also transmit data from latch circuit XDL2 to latch circuit ADL2 during the data input period to latch circuit XDL3, transmit data from latch circuit XDL3 to latch circuit BDL3 during the data input period to latch circuit XDL1, transmit data from latch circuit XDL1 to latch circuit BDL1 during the data input period to latch circuit XDL2, and transmit data from latch circuit XDL2 to latch circuit BDL2 during the data input period to latch circuit XDL3.

[0630] Next, the memory 100 receives the logical page address of the logical third page from the memory controller 200 (step S269). At this time, the instruction user interface circuit 121 converts the logical page address of the logical third page into a physical page address.

[0631] The sequencer 123 sets the starting address of the latch circuit XDL3 as the column address CA in the column counter 125 (step S270).

[0632] In page buffer 133, data input to the first cluster of the logical third page of latch circuit XDL3 begins based on the column address CA received from column counter 125 (step S271).

[0633] If the data input to the first cluster of the third logical page of the latch circuit XDL3 has not ended (step S272_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[0634] If the data input to the first cluster of the third logical page of the latch circuit XDL3 is completed (step S272_Yes), then the sequencer 123 will transfer the data of the latch circuit XDL3 to the latch circuit ADL3 (step S273).

[0635] Sequencer 123 sets the starting address of latch circuit XDL1 as column address CA in column counter 125 (step S274). In page buffer 133, based on the column address CA received from column counter 125, data input to the second cluster of the logical third page of latch circuit XDL1, data input to the third cluster of the logical third page of latch circuit XDL2, and data input to the fourth cluster of the logical third page of latch circuit XDL3 are executed sequentially.

[0636] If the data input to the fourth cluster of the third logical page of the latch circuit XDL3 has not ended (step S275_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[0637] If the data input to the fourth cluster of the third logical page of latch circuit XDL3 is completed (step S275_Yes), then the data input to the third logical page of latch circuits XDL1 to XDL3 is completed. Sequencer 123 sets the external RBn signal to the "L" level. Furthermore, sequencer 123 determines the state of each memory element transistor MC based on the combination of the input data from the first to third logical pages, i.e., the data from the Lower page, Middle page, Upper page, and Top page. In addition, sequencer 123 can also transfer data from latch circuit XDL3 to latch circuit ADL3 during the data input to latch circuit XDL1.

[0638] The sequencer 123 executes program actions based on the determined state (step S276).

[0639] After the program action is completed, the sequencer 123 performs the program verification action (step S277).

[0640] If the verification fails (step S278_No), the sequencer 123 checks whether the number of program loops has reached the preset upper limit (step S279).

[0641] If the program loop count has not reached the upper limit (step S279_No), the sequencer 123 executes the program action (step S276). That is, the sequencer 123 repeatedly performs the program loop.

[0642] If the program loop count reaches the upper limit (step S279_Yes), the sequencer 123 ends the write operation and reports to the memory controller 200 that the write operation has not ended normally.

[0643] If the verification is successful (step S278_yes), that is, if the writing of states “S1” to “S15” is completed, the sequencer 123 sets the external RBn signal to the “H” level and ends the full sequence writing operation.

[0644] 5.5.2 Command sequence for writing operations

[0645] Next, use Figure 50 An example of a sequence of instructions for a write operation is illustrated. Figure 50 It is a sequence of instructions for a full-sequence write operation. Figure 50 In the example, for the sake of simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted.

[0646] like Figure 50As shown, firstly, the memory controller 200 sends the instruction "80h" to the memory 100. Next, the memory controller 200 sends the logical page address "AD-P1" of the logical first page. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address.

[0647] Next, the memory controller 200 sends the data of the first logical page to the memory 100. The first cluster of the first logical page is saved to latch circuit XDL1 and then transmitted to latch circuit ADL1. The second and third clusters of the first logical page are saved to latch circuits XDL2 and XDL3 and then transmitted to latch circuits BDL2 and BDL3. The fourth cluster of the first logical page is saved to latch circuit XDL1 and then transmitted to latch circuit BDL1.

[0648] Next, the memory controller 200 sends an instruction "1Ah" to the memory 100 to notify the data input of the next logical page. Then, the memory controller 200 sends the instruction "80h" and the logical page address "AD-P2" of the second logical page to the memory 100. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P2" into a physical page address.

[0649] Next, the memory controller 200 sends the data of the second logical page to the memory 100. The first cluster of the second logical page is saved to latch circuit XDL2 and then transmitted to latch circuit ADL2. The second cluster of the second logical page is saved to latch circuit XDL3 and then transmitted to latch circuit CDL3. The third cluster of the second logical page is saved to latch circuit XDL1 and then transmitted to latch circuit CDL1. The fourth cluster of the second logical page is saved to latch circuit XDL2 and then transmitted to latch circuit CDL2.

[0650] Next, the memory controller 200 sends an instruction "1Ah" to the memory 100 to notify the data input of the next logical page. Then, the memory controller 200 sends the instruction "80h" and the logical page address "AD-P3" for the third logical page to the memory 100. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P3" into a physical page address.

[0651] Next, the memory controller 200 sends the data of the third logical page to the memory 100. The first cluster of the third logical page is saved to latch circuit XDL3 and then transmitted to latch circuit ADL3. The second cluster of the third logical page is saved to latch circuit XDL1. The third cluster of the third logical page is saved to latch circuit XDL2. The fourth cluster of the third logical page is saved to latch circuit XDL3.

[0652] Next, the memory controller 200 sends the instruction "10h" to the memory 100, indicating that the write operation should be performed.

[0653] If the sequencer 123 receives the instruction "10h", it sets both the internal and external RBn signals to "L" level. Furthermore, the sequencer 123 determines the state of the transistors MC of each memory element based on the data stored in the latch circuits ADL1-ADL3, BDL1-BDL3, CDL1-CDL3, and XDL1-XDL3, and performs the write operation. After the write operation is completed, the sequencer 123 sets both the internal and external RBn signals to "H" level.

[0654] 5.6 Effects of this implementation method

[0655] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0656] 6. Sixth Implementation Method

[0657] Next, the sixth embodiment will be described. In the sixth embodiment, 12 examples of QLC encoding that differ from the fifth embodiment are shown. In each example, the allocation of data relative to the Top, Upper, Middle, and Lower bits includes one bit with a boundary number of 1. Furthermore, the boundary number of bits with a boundary number other than 1 is encoded such that the maximum boundary number becomes the minimum. Hereinafter, the description will focus on the differences from the fifth embodiment.

[0658] 6.1 Example 1

[0659] First, use Figure 51 The encoding of the first example will be explained. Figure 51 It is a table showing the allocation of data to each state.

[0660] like Figure 51 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0661] "S0" status: "1111" data

[0662] "S1" status: "0111" data

[0663] "S2" status: "0011" data

[0664] "S3" status: "0001" data

[0665] "S4" status: "0101" data

[0666] "S5" status: "1101" data

[0667] "S6" status: "1001" data

[0668] "S7" status: "1011" data

[0669] "S8" status: "1010" data

[0670] "S9" status: "1000" data

[0671] "S10" status: "0000" data

[0672] "S11" Status: "0010" Data

[0673] "S12" status: "0110" data

[0674] "S13" status: "1110" data

[0675] "S14" status: "1100" data

[0676] "S15" Status: "0100" Data

[0677] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R3, R7, R9, R11, and R14. The Upper page is determined by reading actions R2, R4, R6, and R12. The Top page is determined by reading actions R1, R5, R10, R13, and R15. Therefore, the data allocation in this example is 1-5-4-5 encoded.

[0678] 6.2 Case 2

[0679] Next, use Figure 52 The encoding of example 2 will be explained. Figure 52 It is a table showing the allocation of data to each state.

[0680] like Figure 52 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0681] "S0" status: "1111" data

[0682] "S1" status: "0111" data

[0683] "S2" status: "0011" data

[0684] "S3" status: "0001" data

[0685] "S4" status: "0101" data

[0686] "S5" status: "1101" data

[0687] "S6" status: "1001" data

[0688] "S7" status: "1011" data

[0689] "S8" status: "1010" data

[0690] "S9" status: "1110" data

[0691] "S10" status: "1100" data

[0692] "S11" status: "0100" data

[0693] "S12" status: "0110" data

[0694] "S13" Status: "0010" Data

[0695] "S14" status: "0000" data

[0696] "S15" status: "1000" data

[0697] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R3, R7, R10, R12, and R14. The Upper page is determined by reading actions R2, R4, R6, R9, and R13. The Top page is determined by reading actions R1, R5, R11, and R15. Therefore, the data allocation in this example is 1-5-5-4 encoded.

[0698] 6.3 Example 3

[0699] Next, use Figure 53 The encoding of example 3 will be explained. Figure 53 It is a table showing the allocation of data to each state.

[0700] like Figure 53 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0701] "S0" status: "1111" data

[0702] "S1" status: "0111" data

[0703] "S2" status: "0011" data

[0704] "S3" status: "0001" data

[0705] "S4" status: "0101" data

[0706] "S5" status: "1101" data

[0707] "S6" status: "1001" data

[0708] "S7" status: "1011" data

[0709] "S8" status: "1010" data

[0710] "S9" status: "0010" data

[0711] "S10" status: "0000" data

[0712] "S11" status: "0100" data

[0713] "S12" status: "0110" data

[0714] "S13" status: "1110" data

[0715] "S14" status: "1100" data

[0716] "S15" status: "1000" data

[0717] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R3, R7, R10, R12, and R14. The Upper page is determined by reading actions R2, R4, R6, R11, and R15. The Top page is determined by reading actions R1, R5, R9, and R13. Therefore, the data allocation in this example is 1-5-5-4 encoded.

[0718] 6.4 Case 4

[0719] Next, use Figure 54 The encoding of example 4 will be explained. Figure 54 It is a table showing the allocation of data to each state.

[0720] like Figure 54 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0721] "S0" status: "1111" data

[0722] "S1" status: "0111" data

[0723] "S2" status: "0011" data

[0724] "S3" status: "1011" data

[0725] "S4" status: "1001" data

[0726] "S5" status: "1101" data

[0727] "S6" status: "0101" data

[0728] "S7" status: "0001" data

[0729] "S8" status: "0000" data

[0730] "S9" status: "0010" data

[0731] "S10" status: "0110" data

[0732] "S11" status: "0100" data

[0733] "S12" status: "1100" data

[0734] "S13" status: "1110" data

[0735] "S14" Status: "1010" Data

[0736] "S15" status: "1000" data

[0737] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R4, R9, R11, R13, and R15. The Upper page is determined by reading actions R2, R5, R7, R10, and R14. The Top page is determined by reading actions R1, R3, R6, and R12. Therefore, the data allocation in this example is 1-5-5-4 encoding.

[0738] 6.5 Example 5

[0739] Next, use Figure 55 The encoding of example 5 will be explained. Figure 55 It is a table showing the allocation of data to each state.

[0740] like Figure 55 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0741] "S0" status: "1111" data

[0742] "S1" status: "0111" data

[0743] "S2" status: "0011" data

[0744] "S3" status: "1011" data

[0745] "S4" status: "1001" data

[0746] "S5" status: "1101" data

[0747] "S6" status: "0101" data

[0748] "S7" status: "0001" data

[0749] "S8" status: "0000" data

[0750] "S9" status: "0010" data

[0751] "S10" status: "1010" data

[0752] "S11" status: "1000" data

[0753] "S12" status: "1100" data

[0754] "S13" status: "1110" data

[0755] "S14" status: "0110" data

[0756] "S15" Status: "0100" Data

[0757] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R4, R9, R11, R13, and R15. The Upper page is determined by reading actions R2, R5, R7, and R12. The Top page is determined by reading actions R1, R3, R6, R10, and R14. Therefore, the data allocation in this example is 1-5-4-5 encoded.

[0758] 6.6 Case 6

[0759] Next, use Figure 56 The encoding of example 6 will be explained. Figure 56 It is a table showing the allocation of data to each state.

[0760] like Figure 56As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0761] "S0" status: "1111" data

[0762] "S1" status: "0111" data

[0763] "S2" status: "0011" data

[0764] "S3" status: "1011" data

[0765] "S4" status: "1001" data

[0766] "S5" status: "0001" data

[0767] "S6" status: "0101" data

[0768] "S7" status: "1101" data

[0769] "S8" status: "1100" data

[0770] "S9" status: "1110" data

[0771] "S10" status: "1010" data

[0772] "S11" status: "1000" data

[0773] "S12" status: "0000" data

[0774] "S13" Status: "0010" Data

[0775] "S14" status: "0110" data

[0776] "S15" Status: "0100" Data

[0777] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R4, R9, R11, R13, and R15. The Upper page is determined by reading actions R2, R6, R10, and R14. The Top page is determined by reading actions R1, R3, R5, R7, and R12. Therefore, the data allocation in this example is 1-5-4-5 encoded.

[0778] 6.7 Case 7

[0779] Next, use Figure 57 The encoding of example 7 is explained. Figure 57It is a table showing the allocation of data to each state.

[0780] like Figure 57 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0781] "S0" status: "1111" data

[0782] "S1" status: "0111" data

[0783] "S2" status: "0011" data

[0784] "S3" status: "1011" data

[0785] "S4" status: "1001" data

[0786] "S5" status: "0001" data

[0787] "S6" status: "0101" data

[0788] "S7" status: "1101" data

[0789] "S8" status: "1100" data

[0790] "S9" status: "1000" data

[0791] "S10" status: "1010" data

[0792] "S11" status: "1110" data

[0793] "S12" status: "0110" data

[0794] "S13" status: "0100" data

[0795] "S14" status: "0000" data

[0796] "S15" Status: "0010" Data

[0797] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R4, R10, R13, and R15. The Upper page is determined by reading actions R2, R6, R9, R11, and R14. The Top page is determined by reading actions R1, R3, R5, R7, and R12. Therefore, the data allocation in this example is 1-4-5-5 encoded.

[0798] 6.8 Case 8

[0799] Next, use Figure 58 The encoding of example 8 will be explained. Figure 58 It is a table showing the allocation of data to each state.

[0800] like Figure 58 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0801] "S0" status: "1111" data

[0802] "S1" status: "0111" data

[0803] "S2" status: "0011" data

[0804] "S3" status: "0001" data

[0805] "S4" status: "0101" data

[0806] "S5" status: "1101" data

[0807] "S6" status: "1001" data

[0808] "S7" status: "1011" data

[0809] "S8" status: "1010" data

[0810] "S9" status: "1000" data

[0811] "S10" status: "0000" data

[0812] "S11" status: "0100" data

[0813] "S12" status: "1100" data

[0814] "S13" status: "1110" data

[0815] "S14" status: "0110" data

[0816] "S15" Status: "0010" Data

[0817] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R3, R7, R9, and R13. The Upper page is determined by reading actions R2, R4, R6, R11, and R14. The Top page is determined by reading actions R1, R5, R10, R12, and R14. Therefore, the data allocation in this example is 1-4-5-5 encoded.

[0818] 6.9 Case 9

[0819] Next, use Figure 59 The encoding of example 9 will be explained. Figure 59 It is a table showing the allocation of data to each state.

[0820] like Figure 59 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0821] "S0" status: "1111" data

[0822] "S1" status: "0111" data

[0823] "S2" status: "0011" data

[0824] "S3" status: "1011" data

[0825] "S4" status: "1001" data

[0826] "S5" status: "0001" data

[0827] "S6" status: "0101" data

[0828] "S7" status: "1101" data

[0829] "S8" status: "1100" data

[0830] "S9" status: "1110" data

[0831] "S10" status: "1010" data

[0832] "S11" status: "1000" data

[0833] "S12" status: "0000" data

[0834] "S13" status: "0100" data

[0835] "S14" status: "0110" data

[0836] "S15" Status: "0010" Data

[0837] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R4, R9, R11, and R14. The Upper page is determined by reading actions R2, R6, R10, R13, and R15. The Top page is determined by reading actions R1, R3, R5, R7, and R12. Therefore, the data allocation in this example is 1-4-5-5 encoded.

[0838] 6.10 Case 10

[0839] Next, use Figure 60 The encoding of example 10 is explained. Figure 60 It is a table showing the allocation of data to each state.

[0840] like Figure 60 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0841] "S0" status: "1111" data

[0842] "S1" status: "0111" data

[0843] "S2" status: "0011" data

[0844] "S3" status: "0001" data

[0845] "S4" status: "0101" data

[0846] "S5" status: "1101" data

[0847] "S6" status: "1001" data

[0848] "S7" status: "1011" data

[0849] "S8" status: "1010" data

[0850] "S9" status: "0010" data

[0851] "S10" status: "0000" data

[0852] "S11" status: "1000" data

[0853] "S12" status: "1100" data

[0854] "S13" status: "1110" data

[0855] "S14" status: "0110" data

[0856] "S15" Status: "0100" Data

[0857] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R3, R7, R10, R13, and R15. The Upper page is determined by reading actions R2, R4, R6, and R12. The Top page is determined by reading actions R1, R5, R9, R11, and R14. Therefore, the data allocation in this example is 1-5-4-5 encoded.

[0858] 6.11 Case 11

[0859] Next, use Figure 61 The encoding of example 11 is explained. Figure 61 It is a table showing the allocation of data to each state.

[0860] like Figure 61 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0861] "S0" status: "1111" data

[0862] "S1" status: "0111" data

[0863] "S2" status: "0011" data

[0864] "S3" status: "1011" data

[0865] "S4" status: "1001" data

[0866] "S5" status: "1101" data

[0867] "S6" status: "0101" data

[0868] "S7" status: "0001" data

[0869] "S8" status: "0000" data

[0870] "S9" status: "0100" data

[0871] "S10" status: "0110" data

[0872] "S11" status: "1110" data

[0873] "S12" status: "1100" data

[0874] "S13" status: "1000" data

[0875] "S14" Status: "1010" Data

[0876] "S15" Status: "0010" Data

[0877] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R4, R10, R12, and R14. The Upper page is determined by reading actions R2, R5, R7, R9, and R13. The Top page is determined by reading actions R1, R3, R6, R11, and R15. Therefore, the data allocation in this example is 1-4-5-5 encoded.

[0878] 6.12 Case 12

[0879] Next, use Figure 62 The encoding of example 12 is explained. Figure 62 It is a table showing the allocation of data to each state.

[0880] like Figure 62 As shown, in this example, similar to the fifth embodiment, data is allocated for each state in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0881] "S0" status: "1111" data

[0882] "S1" status: "0111" data

[0883] "S2" status: "0011" data

[0884] "S3" status: "1011" data

[0885] "S4" status: "1001" data

[0886] "S5" status: "1101" data

[0887] "S6" status: "0101" data

[0888] "S7" status: "0001" data

[0889] "S8" status: "0000" data

[0890] "S9" status: "1000" data

[0891] "S10" status: "1010" data

[0892] "S11" status: "1110" data

[0893] "S12" status: "1100" data

[0894] "S13" status: "0100" data

[0895] "S14" status: "0110" data

[0896] "S15" Status: "0010" Data

[0897] Given this data allocation, the Lower page is determined by reading action R8. The Middle page is determined by reading actions R4, R10, R12, and R14. The Upper page is determined by reading actions R2, R5, R7, R11, and R15. The Top page is determined by reading actions R1, R3, R6, R9, and R13. Therefore, the data allocation in this example is 1-4-5-5 encoded.

[0898] 6.13 Effects of this implementation method

[0899] The coding of this embodiment can be applied to the fifth embodiment.

[0900] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0901] 7. Seventh Implementation Method

[0902] Next, the seventh embodiment will be described. In the seventh embodiment, two examples will be given regarding the QLC readout operation that differs from the fifth embodiment. Hereinafter, the description will focus on the differences from the fifth embodiment.

[0903] 7.1 Example 1

[0904] First, let's explain the reading action in the first example. In the first example, the reading action is used... Figures 63-65 The order of the read voltage applied to the select word line WL during the read operation of the first to third logic pages will be explained as different from that in the fifth embodiment. Figure 63 It is the instruction sequence for reading the first page of the logic. Figure 64 It is the instruction sequence for reading the second page of the logic. Figure 65 This is the instruction sequence for reading from page 3 of the logic. Figures 63-65 In the example, for simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. Additionally, in... Figures 63-65 In the example, part of the instruction and the address were also omitted. Furthermore, in Figures 63-65In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[0905] First, let's explain the instruction sequence in the read operation of the first page of logic.

[0906] like Figure 63 As shown, in the read operations of the Lower page (read operation R8) corresponding to the first logical page and the Middle page (read operations R3, R7, R11, and R15), the sequencer 123 executes the read operations in the order of R15, R11, R8, R7, and R3. That is, read voltages V15, V11, V8, V7, and V3 are applied sequentially to the select word line WL. After the read operation R3 is completed, the sequencer 123 sets the external RBn signal and the internal RBn signal to the "H" level. Therefore, after the Middle page read operation is completed, the output of the read data begins.

[0907] Furthermore, the sequencer 123 can also perform the read operation in the order of R3, R7, R8, R11, and R15. That is, the read voltages V3, V7, V8, V11, and V15 can be applied to the select word line WL sequentially. In addition, if the sequencer 123 performs the read operation R8, the data of the Lower page is determined, so the external RBn signal can also be set to the "H" level to output data.

[0908] Next, the instruction sequence in the read operation of the second page of logic will be explained.

[0909] like Figure 64 As shown, in the read operations of the Lower page (read operation R8) corresponding to the second logical page and the Upper page (read operations R2, R4, R6, R9, and R13), the sequencer 123 executes the read operations in the order of R13, R9, R8, R6, R4, and R2. That is, read voltages V13, V9, V8, V6, V4, and V2 are applied sequentially to the select word line WL. After the read operation R2 is completed, the sequencer 123 sets the external RBn signal and the internal RBn signal to the "H" level. Therefore, the output of the read data begins after the read operation of the Upper page is completed.

[0910] Furthermore, the sequencer 123 can also perform the read operation in the order of R2, R4, R6, R8, R9, and R13. That is, the read voltages V2, V4, V6, V8, V9, and V13 can be applied to the select word line WL sequentially. In addition, if the sequencer 123 performs the read operation R8, the data of the Lower page is determined, so the external RBn signal can also be set to the "H" level to output data.

[0911] Next, the instruction sequence in the read operation of the logic page 3 will be explained.

[0912] like Figure 65 As shown, in the read operations of the Lower page (read operation R8) corresponding to the logical 3rd page and the Top page (read operations R1, R5, R10, R12, and R14), the sequencer 123 executes the read operations in the order of R14, R12, R10, R8, R5, and R1. That is, read voltages V14, V12, V10, V8, V5, and V1 are applied sequentially to the select word line WL. After the read operation R1 is completed, the sequencer 123 sets the external RBn signal and the internal RBn signal to the "H" level. Therefore, after the read operation of the Top page is completed, the output of the read data begins.

[0913] Furthermore, the sequencer 123 can also perform the read operation in the order of R1, R5, R8, R10, R12, and R14. That is, the read voltages V1, V5, V8, V10, V12, and V14 can be applied to the select word line WL sequentially. Additionally, if the sequencer 123 performs the read operation R8, the data on the Lower page is determined, so the external RBn signal can be set to "H" level to output data.

[0914] 7.2 Example 2

[0915] Next, the reading action in the second example will be explained. In the second example, the reading action is used... Figure 66 This section explains the case where data from the Lower, Middle, Upper, and Top pages are read together during a sequential read operation. In this example, states "S0" through "S15" are read together during the sequential read operation. Figure 66 It is a sequence of instructions for sequential reading actions. Figure 66 In the example, for simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. Additionally, in... Figure 66 In the example, part of the instruction and its address are also omitted. Furthermore, in Figure 66 In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[0916] like Figure 66As shown, if sequencer 123 receives the instruction "30h", it responds by initiating a read operation. First, sequencer 123 sets both the internal and external RBn signals to the "L" level, indicating a busy state. Next, sequencer 123 performs a sequential read operation. More specifically, sequencer 123 executes read operations R1 to R15 sequentially. During this time, read voltages V1 to V15 are applied sequentially to the select word line WL. If read operation R8 ends, sequencer 123 determines the data for the Lower page and sets the external RBn signal to the "H" level. The data for the Lower page is saved to latch circuits ADL1 to ADL3. The data in latch circuit ADL1 (data for the first cluster of the first logical page) is transferred to latch circuit XDL1. If memory controller 200 receives the external RBn signal at the "H" level, it sends the signal REn (not shown) to memory 100. The input / output circuit 110 starts the output of the data (data of the first cluster of the first page of logic) of the latching circuit XDL1 based on the signal REn.

[0917] If the data output of the latch circuit XDL1 ends during the sequential read operation, the sequencer 123 will temporarily set the external RBn signal to the "L" level until the sequential read operation ends.

[0918] If the process ends up with read operation R13, sequencer 123 determines the data for the Upper page. The data for the Upper page is stored in latch circuits CDL1 to CDL3. Conversely, if the process ends up with read operation R15, sequencer 123 determines the data for the Middle page. The data for the Middle page is stored in latch circuits BDL1 to BDL3. Data from latch circuit BDL2 (data from the second cluster of the first logical page) is transferred to latch circuit XDL2. Data from latch circuit BDL3 (data from the third cluster of the first logical page) is transferred to latch circuit XDL3. Data from latch circuit BDL1 (data from the fourth cluster of the first logical page) is transferred to latch circuit XDL1.

[0919] If the sequential readout operation ends, the sequencer 123 sets the external RBn signal and the internal RBn signal to the "H" level.

[0920] If the memory controller 200 receives an external RBn signal at the "H" level, it restarts the transmission of signal REn (not shown). The input / output circuit 110 outputs data according to the sequence of latch circuits XDL2, XDL3, and XDL1 based on signal REn. When the output of data from latch circuit XDL1 (data from the 4th cluster of logical page 1) ends, the data output for logical page 1 ends.

[0921] Next, the output of data for the second logical page begins. Data from latch circuit ADL2 (data from cluster 1 of the second logical page) is transferred to latch circuit XDL2. Data from latch circuit CDL3 (data from cluster 2 of the second logical page) is transferred to latch circuit XDL3. Data from latch circuit CDL1 (data from cluster 3 of the second logical page) is transferred to latch circuit XDL1. Data is output in the order of latch circuits XDL2, XDL3, and XDL1. If the output of data from latch circuit XDL2 (data from cluster 1 of the second logical page) ends, data from latch circuit CDL2 (data from cluster 4 of the second logical page) is transferred to latch circuit XDL2. If the output of data from latch circuit XDL1 (data from cluster 3 of the second logical page) ends, data from latch circuit XDL2 (data from cluster 4 of the second logical page) is output. If the output of data from latch circuit XDL2 ends, the data output for the second logical page ends.

[0922] Next, the output of data for the third logical page begins. Data from latch circuit ADL3 (data from the first cluster of the third logical page) is transmitted to latch circuit XDL3. Data from sensing circuit SA1 (data from the second cluster of the third logical page) is transmitted to latch circuit XDL1. Data from sensing circuit SA2 (data from the third cluster of the third logical page) is transmitted to latch circuit XDL2. Data is output in the order of latch circuits XDL3, XDL1, and XDL2. If the output of data from latch circuit XDL3 (data from the first cluster of the third logical page) ends, data from sensing circuit SA3 is transmitted to latch circuit XDL3. If the output of data from latch circuit XDL2 (data from the third cluster of the third logical page) ends, data from latch circuit XDL3 (data from the fourth cluster of the third logical page) is output. If the output of data from latch circuit XDL3 ends, the data output for the third logical page ends. Furthermore, in sequential readout operations, data can also be read out in the order of states "S15" to "S0".

[0923] 7.3 Effects of this implementation method

[0924] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0925] 8. Implementation Method 8

[0926] Next, the eighth embodiment will be described. In the eighth embodiment, the allocation of logical page data in the physical page differs from that in the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0927] 8.1 Transformation between logical page address and physical page address

[0928] use Figure 67 and Figure 68 An example illustrating the transformation between logical page addresses and physical page addresses is provided. Figure 67 It is a diagram illustrating the process of changing logical page addresses and physical page addresses. Figure 68 This is a diagram showing the allocation of logical page data relative to physical pages.

[0929] In this embodiment, similar to the first embodiment, the case of allocating data from 2 logical pages to 3 physical pages (i.e., a memory group MG capable of storing 3 pages of data) will be described.

[0930] like Figure 67 As shown, if the instruction user interface circuit 121 receives a logical page address of 2 pages and a write command for the logical page from the memory controller 200, it transforms the logical page address of 2 pages into a physical page address of 3 pages. In this embodiment, the instruction user interface circuit 121 transforms the logical page address of the first logical page into the physical page addresses of the first element region of the Lower page, the first element region of the Middle page, and the first element region of the Upper page. Furthermore, the instruction user interface circuit 121 transforms the logical page address of the second logical page into the physical page addresses of the second element region of the Lower page, the second element region of the Middle page, and the second element region of the Upper page.

[0931] For example, the sequencer 123 writes data of the first logical page to the first element area of ​​the Lower page, the first element area of ​​the Middle page, and the first element area of ​​the Upper page of the memory group MG based on the physical page address transformed in the instruction user interface circuit 121, and writes data of the second logical page to the second element area of ​​the Lower page, the second element area of ​​the Middle page, and the second element area of ​​the Upper page.

[0932] Next, the configuration of logical page data in a memory group MG is described in detail.

[0933] like Figure 68As shown, for example, memory 100 writes the first cluster of logical first page to the first element area of ​​the Lower page, writes the second cluster of logical first page to the first element area of ​​the Middle page, and writes the third cluster of logical first page to the first element area of ​​the Upper page. Additionally, memory 100 writes the first cluster of logical second page to the second element area of ​​the Lower page, writes the second cluster of logical second page to the second element area of ​​the Middle page, and writes the third cluster of logical second page to the second element area of ​​the Upper page.

[0934] 8.2 Effects of this implementation method

[0935] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0936] 9. The 9th implementation method

[0937] Next, the ninth embodiment will be described. In the ninth embodiment, three examples will be described regarding the configuration of the sense amplifier 132 and the page buffer 133, which differ from the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0938] 9.1 Example 1

[0939] First, use Figure 69 The configuration of the sense amplifier 132 and page buffer 133 in the first example will be described. Figure 69 This is a block diagram of the sense amplifier 132 and the page buffer 133. Furthermore, in Figure 69 In the example, the bit line BL is omitted for simplicity.

[0940] like Figure 69 As shown, in this example, the first element region and the corresponding sense amplifier unit SAU1, and the second element region and the corresponding sense amplifier unit SAU2 are alternately arranged. Therefore, in the memory group MG, for example, the memory element transistor MC connected to the even-numbered bit line BL is included in the first element region, and the memory element transistor MC connected to the odd-numbered bit line BL is included in the second element region. The latch circuits XDL (XDL1 and XDL2) are connected to the serial access controller 126 via the data bus and are used for data transmission and reception between the serial access controller 126 and the sense amplifier 132.

[0941] 9.2 Case 2

[0942] Next, use Figure 70 The configuration of the sense amplifier 132 and page buffer 133 in the second example is described. Figure 70 illustrate. Figure 70 This is a block diagram of the sense amplifier 132 and the page buffer 133. Furthermore, in Figure 70 In the example, the bit line BL is omitted for simplicity.

[0943] like Figure 70 As shown, in this example, latch circuits ADL (ADL1 and ADL2) and XDL (XDL1 and XDL2) are connected to the serial access controller 126 via a data bus and are used for data transmission and reception between the serial access controller 126 and the sense amplifier 132.

[0944] Alternatively, latch circuits BDL (BDL1 and BDL2) and XDL (XDL1 and XDL2) can be connected to the serial access controller 126 via a data bus.

[0945] 9.3 Example 3

[0946] Next, use Figure 71 The configuration of the sense amplifier 132 and page buffer 133 in the third example will be described. Figure 71 This is a block diagram of the sense amplifier 132 and the page buffer 133. Furthermore, in Figure 71 In the example, the bit line BL is omitted for simplicity.

[0947] like Figure 71 As shown, in this example, latch circuits ADL (ADL1 and ADL2), BDL (BDL1 and BDL2), and XDL (XDL1 and XDL2) are connected to the serial access controller 126 via a data bus and are used for data transmission and reception between the serial access controller 126 and the sense amplifier 132.

[0948] 9.4 Effects of this implementation method

[0949] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0950] Furthermore, in the configuration of the first example of this embodiment, the sensing amplifier unit SAU1 and the sensing amplifier unit SAU2 can be arranged alternately. This allows data to be moved between the sensing amplifier unit SAU1 and the sensing amplifier unit SAU2. Such physical separation (configuration) is implemented for various reasons, such as improving circuit response speed, simplifying wiring layout between circuits, and facilitating operations between latching circuits.

[0951] Furthermore, in the configurations of the second and third examples of this embodiment, the latch circuits ADL and / or BDL are connected to the serial access controller 126 via a data bus. Therefore, the latch circuits ADL and / or BDL can transmit and receive data with the serial access controller 126 without using the latch circuit XDL. This improves operating speed. Moreover, the frequency of data transmission can be reduced, thus reducing power consumption. Furthermore, in the case of QLC, the page buffer 133 may also include a latch circuit CDL in addition to the latch circuits ADL, BDL, and XDL.

[0952] In addition, the first example of this embodiment can be combined with the second or third example.

[0953] 10. The 10th Implementation

[0954] Next, the tenth embodiment will be described. In the tenth embodiment, the case where different codes are applied to the first element region and the second element region will be described. Hereinafter, the description will focus on the differences from the first embodiment.

[0955] 10.1 Transformation between logical page address and physical page address

[0956] First, use Figure 27 An example illustrating the transformation between logical page addresses and physical page addresses is provided. Figure 72 This is a diagram showing the allocation of logical page data relative to physical pages.

[0957] In this embodiment, the case of allocating data from 2 logical pages to 3 physical pages (i.e., a memory group MG capable of storing 3 pages of data) will be described.

[0958] like Figure 72 As shown, the data in logical page 1 and logical page 2 are each divided into three clusters, numbered 1 through 3 starting from the beginning of the data. For example, memory 100 writes logical page 1 cluster 1 to logical page 2 cluster 2 to logical page 3 cluster 1 to logical page 3 element area 1 of the Lower page, writes logical page 1 cluster 2 to logical page 2 element area 1 of the Lower page, and writes logical page 1 cluster 3 to logical page 3 element area 1 of the Middle page. Additionally, memory 100 writes logical page 1 cluster 2 to logical page 2 element area 1 of the Middle page, writes logical page 2 cluster 2 to logical page 2 element area 1 of the Upper page, and writes logical page 3 cluster 3 to logical page 2 element area 2 of the Upper page.

[0959] 10.2 Encoding of Memory Element Transistors

[0960] Next, use Figure 73 The encoding of the memory element transistor MC is explained. Figure 73 It is a table that shows the allocation of data to each state.

[0961] like Figure 73 As shown, in this embodiment, different codes are applied in the first element region and the second element region. In this case, each code is selected in the same way in both the first and second element regions, so that the position of the boundary that determines the data of the logical page during the logical page read operation is determined.

[0962] More specifically, in the case of reading the first logical page, the position of the boundary that determines the data of the Lower page and the Middle page in the first element region is the same as the position of the boundary that determines the data of the Lower page in the second element region. Furthermore, in the case of reading the second logical page, the position of the boundary that determines the data of the Upper page in the first element region is the same as the position of the boundary that determines the data of the Middle page and the Upper page in the second element region.

[0963] For example, in the first element region, for the memory element transistor MC, data is allocated to the "Upper bit / Middle bit / Lower bit" as shown below.

[0964] "S0" status: "111" data

[0965] "S1" status: "011" data

[0966] "S2" status: "001" data

[0967] "S3" status: "101" data

[0968] "S4" status: "100" data

[0969] "S5" status: "000" data

[0970] "S6" status: "010" data

[0971] "S7" status: "110" data

[0972] With this data allocation, the Lower page is determined by reading action R4. The Middle page is determined by reading actions R2 and R6. The Upper page is determined by reading actions R1, R3, R5, and R7. Therefore, the data allocation for the first element region is 1-2-4 encoded.

[0973] Additionally, in the second element region, for the memory element transistor MC, data is allocated to the "Upper bit / Middle bit / Lower bit" as shown below.

[0974] "S0" status: "111" data

[0975] "S1" status: "101" data

[0976] "S2" status: "100" data

[0977] "S3" status: "000" data

[0978] "S4" status: "001" data

[0979] "S5" status: "011" data

[0980] "S6" status: "010" data

[0981] "S7" status: "110" data

[0982] With this data allocation, the Lower page is determined by reading actions R2, R4, and R6. The Middle page is determined by reading actions R1 and R5. The Upper page is determined by reading actions R3 and R7. Therefore, the data allocation for the second element region is 3-2-2 encoded.

[0983] When performing a read operation on the first logical page, the objects of the read operation are the first and second element regions of the Lower page and the first element region of the Middle page. In the first region, the data of the Lower page is determined by read operation R4. The data of the Middle page is determined by read operations R2 and R6. Similarly, in the second element region, the data of the Lower page is determined by read operations R2, R4, and R6. Therefore, the data of the first logical page is determined in both the first and second element regions by read operations R2, R4, and R6. Furthermore, during the read operation of the first logical page, read voltages can be applied to the select word line WL in the order of voltages V2, V4, and V6, or in the order of voltages V6, V4, and V2. Additionally, if read operation R4 ends, the data of the first cluster of the first logical page is determined, and the memory 100 can then transmit this data to the latch circuit XDL and output it externally.

[0984] When performing a read operation on the second logical page, the objects of the read operation are the second element area of ​​the Middle page and the first and second element areas of the Upper page. In the first element area, the data of the Upper page is determined by read operations R1, R3, R5, and R7. In the second element area, the data of the Middle page is determined by read operations R1 and R5. The data of the Upper page is determined by read operations R3 and R7. Therefore, the data of the second logical page is determined in both the first and second element areas by read operations R1, R3, R5, and R7. Furthermore, during the read operation of the second logical page, read voltages can be applied to the select word line WL in the order of voltages V1, V3, V5, and V7, or in the order of voltages V7, V5, V3, and V1. For example, when read voltages are applied to the select word line WL in the order of voltages V1, V3, V5, and V7, if read operations R1 and R5 are completed, the data of the first cluster of the second logical page is determined, and therefore the memory 100 can also transmit this data to the latch circuit XDL and output it externally. For example, when read voltages are applied to the select word line WL in the order of voltages V7, V5, V3, and V1, if read operations R7 and R2 are completed, the data of the third cluster of the second logical page is determined, and therefore the memory 100 can also transmit this data to the latch circuit XDL and output it externally. In this case, for example, the memory 100 can also store data that is used... Figure 72 The allocation of the first cluster of the logical second page and the allocation of the third cluster of the logical second page are swapped. By swapping the allocations, the memory 100 is able to output the data of the first cluster of the logical second page to the outside earlier than before the allocation swap.

[0985] 10.3 Effects of this implementation method

[0986] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0987] Furthermore, with this embodiment, different encodings can be applied to each element region. Moreover, the encoding can be selected such that the positions of the boundaries where the data of the logical page is determined are the same in each element region during the logical page read operation. Therefore, when reading data from multiple physical pages during a logical page read operation, the number of boundaries can be minimized. Thus, the increase in the number of read operations can be suppressed, thereby improving processing power. For example, in this embodiment, the first logical page can determine data through 3 read operations, and the second logical page can determine data through 4 read operations.

[0988] 11. Implementation Method 11

[0989] Next, the 11th embodiment will be described. In the 11th embodiment, three examples will be given regarding the case where data from one logical page is distributed to multiple physical pages. Hereinafter, the description will focus on the differences from the 1st to 10th embodiments.

[0990] 11.1 Example 1

[0991] First, use Figure 74 The transformation between logical page address and physical page address in the first example will be explained. Figure 74 This is a diagram showing the allocation of logical page data relative to physical pages.

[0992] In this example, we will explain the allocation of data from 1 logical page to 3 physical pages (i.e., a memory group MG capable of storing 3 pages of data).

[0993] like Figure 74 As shown, the data in the first logical page is divided into three groups, starting from the first group and ending with the third. For example, memory 100 writes the first group of the first logical page to the Lower page, the second group of the first logical page to the Middle page, and the third group of the first logical page to the Upper page.

[0994] 11.2 Example 2

[0995] Next, the transformation between the logical page address and the physical page address in the second example will be explained.

[0996] In this example, we will explain the allocation of data from 1 logical page to 4 physical pages (i.e., a memory group MG capable of storing 4 pages of data).

[0997] First, use Figure 75 An example of the threshold voltage distribution that can be taken for the memory element transistor MC in this example will be explained. Figure 75 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistor MC and the data allocation.

[0998] like Figure 75 As shown, in this example, for the memory element transistors MC included in each threshold voltage distribution, data is allocated to the "Top bit / Upper bit / Middle bit / Lower bit" as follows. For each state, data is allocated in a Gray code manner that results in a 1-bit data change between two adjacent states.

[0999] "S0" status: "1111" data

[1000] "S1" status: "0111" data

[1001] "S2" status: "0101" data

[1002] "S3" status: "1101" data

[1003] "S4" status: "1100" data

[1004] "S5" status: "1000" data

[1005] "S6" status: "1001" data

[1006] "S7" status: "1011" data

[1007] "S8" status: "0011" data

[1008] "S9" status: "0001" data

[1009] "S10" status: "0000" data

[1010] "S11" status: "0100" data

[1011] "S12" status: "0110" data

[1012] "S13" Status: "0010" Data

[1013] "S14" Status: "1010" Data

[1014] "S15" Status: "1110" Data

[1015] Given this data allocation, the Lower page is determined by reading actions R4, R6, and R10. The Middle page is determined by reading actions R2, R7, R9, and R12. The Upper page is determined by reading actions R5, R11, R13, and R15. The Top page is determined by reading actions R1, R3, R8, and R14. Therefore, the data allocation in this example is 3-4-4-4 encoded.

[1016] Furthermore, the allocation of data to states “S0” to “S15” is not limited to 3-4-4-4 encoding. For example, any encoding described in embodiments 5 and 6 can also be applied.

[1017] Next, use Figure 76 The process of converting logical page addresses to physical page addresses is explained. Figure 76 This is a diagram showing the allocation of logical page data relative to physical pages.

[1018] like Figure 76As shown, the data in the first logical page is divided into four groups, starting from the first group and ending with the fourth. For example, memory 100 writes the first group of the first logical page to the Lower page, the second group of the first logical page to the Middle page, the third group of the first logical page to the Upper page, and the fourth group of the first logical page to the Top page.

[1019] 11.3 Example 3

[1020] Next, the transformation between the logical page address and the physical page address in the third example will be explained.

[1021] In this example, we will explain the allocation of data from 2 logical pages to 4 physical pages (i.e., a memory group MG capable of storing 4 pages of data).

[1022] First, use Figure 77 An example of the threshold voltage distribution that can be taken for the memory element transistor MC in this example will be explained. Figure 77 This is a graph showing the relationship between the threshold voltage distribution of the memory element transistor MC and the data allocation.

[1023] like Figure 77 As shown, in this example, for the memory element transistors MC included in each threshold voltage distribution, data is allocated to the "Top bit / Upper bit / Middle bit / Lower bit" as follows. For each state, data is allocated in a Gray code manner that results in a 1-bit data change between two adjacent states.

[1024] "S0" status: "1111" data

[1025] "S1" status: "0111" data

[1026] "S2" status: "0011" data

[1027] "S3" status: "1011" data

[1028] "S4" status: "1001" data

[1029] "S5" status: "1101" data

[1030] "S6" status: "1100" data

[1031] "S7" status: "0100" data

[1032] "S8" status: "0101" data

[1033] "S9" status: "0001" data

[1034] "S10" status: "0000" data

[1035] "S11" status: "1000" data

[1036] "S12" status: "1010" data

[1037] "S13" status: "1110" data

[1038] "S14" status: "0110" data

[1039] "S15" Status: "0010" Data

[1040] Given this data allocation, the Lower page is determined by reading actions R6, R8, and R10. The Middle page is determined by reading actions R4 and R12. The Upper page is determined by reading actions R2, R5, R9, R13, and R15. The Top page is determined by reading actions R1, R3, R7, R11, and R14. Therefore, the data allocation in this example is 3-2-5-5 encoded.

[1041] Furthermore, the allocation of data to states “S0” to “S15” is not limited to 3-2-5-5 encoding. For example, any encoding described in embodiments 5 and 6 can also be applied. Alternatively, 3-4-4-4 encoding described in the second example of embodiment 11 can also be applied.

[1042] Next, use Figure 78 The process of converting logical page addresses to physical page addresses is explained. Figure 78 This is a diagram showing the allocation of logical page data relative to physical pages.

[1043] like Figure 78 As shown, the data in logical pages 1 and 2 are divided into two groups, and the groups are designated as cluster 1 and cluster 2 starting from the beginning of the data. For example, memory 100 writes cluster 1 of logical page 1 to the Lower page, cluster 2 of logical page 1 to the Middle page, cluster 1 of logical page 2 to the Upper page, and cluster 2 of logical page 2 to the Top page.

[1044] 11.4 Effects of this implementation method

[1045] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[1046] 12. Implementation Method 12

[1047] Next, the 12th embodiment will be described. In the 12th embodiment, the case where different codes are applied to the 1st to 3rd element regions will be described. Hereinafter, the description will focus on the differences from the 1st to 11th embodiments.

[1048] 12.1 Transformation between logical page address and physical page address

[1049] First, use Figure 79 An example illustrating the transformation between logical page addresses and physical page addresses is provided. Figure 79 This is a diagram showing the allocation of logical page data relative to physical pages.

[1050] In this embodiment, the case of allocating data from 3 logical pages to 4 physical pages (i.e., a memory group MG capable of storing 4 pages of data) will be described.

[1051] like Figure 79 As shown, the data in logical pages 1 through 3 are divided into four groups, starting from the first data and designated as clusters 1 through 4. For example, memory 100 writes cluster 1 of logical page 1 to element 1 of the Lower page, cluster 2 of logical page 1 to element 2 of the Lower page, and cluster 3 of logical page 1 to element 3 of the Lower page. Memory 100 writes cluster 4 of logical page 1 to element 1 of the Middle page, cluster 1 of logical page 2 to element 2 of the Middle page, and cluster 2 of logical page 2 to element 3 of the Middle page. Memory 100 writes cluster 3 of logical page 2 to element 1 of the Upper page, cluster 4 of logical page 2 to element 2 of the Upper page, and cluster 1 of logical page 3 to element 3 of the Upper page. The memory 100 writes the second cluster of the logical third page to the first element area of ​​the Top page, writes the third cluster of the logical third page to the second element area of ​​the Top page, and writes the fourth cluster of the logical third page to the third element area of ​​the Top page.

[1052] 12.2 Encoding of Memory Element Transistors

[1053] Next, use Figure 80 The encoding of the memory element transistor MC is explained. Figure 80 It is a table that shows the allocation of data to each state.

[1054] like Figure 80As shown, in this embodiment, different codes are applied in the first to third element regions. In this case, each code is selected in the same manner as in the first, second, and third element regions, so that the position of the boundary that determines the data of the logical page during the logical page read operation is the same.

[1055] More specifically, when reading the first logical page, the positions of the boundaries defining the data of the Lower and Middle pages in the first element region, the second element region, and the third element region are the same. Similarly, when reading the second logical page, the positions of the boundaries defining the data of the Upper page in the first element region, the second element region, and the third element region are the same. Furthermore, when reading the third logical page, the positions of the boundaries defining the data of the Top page in the first element region, the second element region, and the third element region are the same.

[1056] For example, in the first element region, for the memory element transistor MC, data is allocated to the "Top bit / Upper bit / Middle bit / Lower bit" as shown below.

[1057] "S0" status: "1111" data

[1058] "S1" status: "1101" data

[1059] "S2" status: "0101" data

[1060] "S3" status: "0100" data

[1061] "S4" status: "0000" data

[1062] "S5" status: "1000" data

[1063] "S6" status: "1100" data

[1064] "S7" status: "1110" data

[1065] "S8" status: "1010" data

[1066] "S9" status: "0010" data

[1067] "S10" status: "0110" data

[1068] "S11" status: "0111" data

[1069] "S12" status: "0011" data

[1070] "S13" status: "1011" data

[1071] "S14" Status: Data "1001"

[1072] "S15" Status: "0001" Data

[1073] With this data allocation, the Lower page is determined by reading actions R3 and R11. The Middle page is determined by reading actions R1, R7, and R14. The Upper page is determined by reading actions R4, R6, R8, R10, and R12. The Top page is determined by reading actions R2, R5, R9, R13, and R15. Therefore, the data allocation for the first element region is 2-3-5-5 encoded.

[1074] In the second element region, relative to the memory element transistor MC, data is allocated to the "Top bit / Upper bit / Middle bit / Lower bit" as shown below.

[1075] "S0" status: "1111" data

[1076] "S1" status: "1110" data

[1077] "S2" status: "0110" data

[1078] "S3" status: "0111" data

[1079] "S4" status: "0011" data

[1080] "S5" status: "1011" data

[1081] "S6" status: "1001" data

[1082] "S7" status: "1000" data

[1083] "S8" status: "1010" data

[1084] "S9" status: "0010" data

[1085] "S10" status: "0000" data

[1086] "S11" Status: "0001" Data

[1087] "S12" status: "0101" data

[1088] "S13" Status: "1101" Data

[1089] "S14" status: "1100" data

[1090] "S15" Status: "0100" Data

[1091] With this data allocation, the Lower page is determined by reading actions R1, R3, R7, R11, and R14. The Middle page is determined by reading actions R6, R8, and R10. The Upper page is determined by reading actions R4 and R12. The Top page is determined by reading actions R2, R5, R9, R13, and R15. Therefore, the data allocation for the second element region is 5-3-2-5 encoded.

[1092] In the third element region, for the memory element transistor MC, data is allocated to the "Top bit / Upper bit / Middle bit / Lower bit" as shown below.

[1093] "S0" status: "1111" data

[1094] "S1" status: "1110" data

[1095] "S2" status: "0110" data

[1096] "S3" status: "0111" data

[1097] "S4" status: "0101" data

[1098] "S5" status: "0001" data

[1099] "S6" status: "0011" data

[1100] "S7" status: "0010" data

[1101] "S8" status: "0000" data

[1102] "S9" status: "1000" data

[1103] "S10" status: "1010" data

[1104] "S11" status: "1011" data

[1105] "S12" status: "1001" data

[1106] "S13" Status: "1101" Data

[1107] "S14" status: "1100" data

[1108] "S15" Status: "0100" Data

[1109] With this data allocation, the Lower page is determined by reading actions R1, R3, R7, R11, and R14. The Middle page is determined by reading actions R4, R6, R8, R10, and R12. The Upper page is determined by reading actions R5 and R13. The Top page is determined by reading actions R2, R9, and R15. Therefore, the data allocation for the third element region is 5-5-2-3 encoded.

[1110] When performing a read operation on the first logical page, the objects of the read operation are the first to third element areas of the Lower page and the first element area of ​​the Middle page. In the first element area, the data of the Lower page is determined by read operations R3 and R11. The data of the Middle page is determined by read operations R1, R7, and R14. In the second element area, the data of the Lower page is determined by R1, R3, R7, R11, and R14. In the third element area, the data of the Lower page is determined by R1, R3, R7, R11, and R14. Therefore, the data of the first logical page is determined in the first, second, and third element areas by read operations R1, R3, R7, R11, and R14. Furthermore, during the read operation of the first logical page, the order in which the read voltages applied to the select word line WL can be either voltages V1, V3, V7, V11, and V14, or voltages V14, V11, V7, V3, and V1. Additionally, if the read operations R11 and R3 are completed, the data for the first cluster of the first logical page is determined, and therefore the memory 100 can also transmit this data to the latch circuit XDL and output it externally.

[1111] When performing a read operation on the second logical page, the objects of the read operation are the second and third element areas of the Middle page and the first and second element areas of the Upper page. In the first element area, the data of the Upper page is determined by read operations R4, R6, R8, R10, and R12. In the second element area, the data of the Middle page is determined by read operations R6, R8, and R10. The data of the Upper page is determined by read operations R4 and R12. In the third element area, the data of the Middle page is determined by read operations R4, R6, R8, R10, and R12. Therefore, the data of the second logical page is determined in the first, second, and third element areas by read operations R4, R6, R8, R10, and R12. Furthermore, during the read operation of the second logical page, the order in which the read voltages applied to the select word line WL can be either voltages V4, V6, V8, V10, and V12, or voltages V12, V10, V8, V6, and V4. Additionally, if read operations R6, R8, and R10 are completed, the data for the first cluster of the second logical page is determined, and therefore the memory 100 can also transmit this data to the latch circuit XDL and output it externally. Furthermore, if read operations R4 and R12 are completed, the data for the fourth cluster of the second logical page is determined, and therefore the memory 100 can also transmit this data to the latch circuit XDL and output it externally. In this case, for example, the memory 100 can also use... Figure 79 The allocation of cluster 1 on logical page 2 and cluster 4 on logical page 2 are swapped. By swapping the allocations, the data of cluster 1 on logical page 2 can be output externally earlier than before the allocation swap.

[1112] When performing a read operation on the logical third page, the objects of the read operation are the third element area of ​​the Upper page and the first to third element areas of the Top page. In the first element area, the data of the Top page is determined by read operations R2, R5, R9, R13, and R15. In the second element area, the data of the Top page is determined by read operations R2, R5, R9, R13, and R15. In the third element area, the data of the Upper page is determined by read operations R5 and R13. The data of the Top page is determined by read operations R2, R9, and R15. Therefore, the data of the logical third page is determined by read operations R2, R5, R9, R13, and R15 in the first, second, and third element areas. Furthermore, during the read operation of the third logical page, the order in which the read voltages applied to the select word line WL can be either voltages V2, V5, V9, V13, and V15, or voltages V15, V13, V9, V5, and V2. If the read operations R13 and R5 are completed, the data for the first cluster of the third logical page is determined, and therefore the memory 100 can also transmit this data to the latch circuit XDL and output it externally.

[1113] 12.3 Effects of this implementation method

[1114] If this embodiment is configured, the same effects as in the first and tenth embodiments can be obtained. For example, in this embodiment, the first logical page can determine data through 5 read operations, the second logical page can determine data through 5 read operations, and the third logical page can determine data through 5 read operations.

[1115] 13. Implementation Method 13

[1116] Next, the 13th embodiment will be described. In the 13th embodiment, the case of using two memory element transistors MC to store 3 bits of data will be described. Hereinafter, the description will focus on the differences from the 1st to 12th embodiments.

[1117] 13.1 Threshold voltage distribution of memory element transistors

[1118] First, use Figure 81 The threshold voltage distribution that can be taken for the transistor MC of the memory element is explained. Figure 81 This is a threshold voltage distribution diagram of the memory element transistor MC.

[1119] like Figure 81As shown, the threshold voltage of each memory element transistor MC takes a value included in one of, for example, three discrete distributions. That is, the memory element transistor MC of the present embodiment is a 1.5 bit / Cell that can hold three-valued data. Hereinafter, the three distributions will be respectively denoted as the "S0" state, the "S1" state, and the "S2" state in ascending order of threshold voltage.

[1120] The "S0" state, for example, corresponds to the erased state of the data. And the "S1" and "S2" states correspond to the states where data is written by injecting charges into the charge storage layer. In the write operation, the verification voltages corresponding to the respective threshold voltage distributions are set as V1 and V2. Then, these voltage values are in the relationship of V1 < V2 < Vread.

[1121] In addition, the set values of the verification voltages corresponding to the respective states and the set value of the read voltage may be the same or different. Hereinafter, for simplicity of explanation, the case where the verification voltage and the read voltage have the same set value will be described.

[1122] Hereinafter, the read operations corresponding to the read operations of the "S1" and "S2" states will be respectively denoted as read operation R1 and read operation R2. Read operation R1 determines whether the threshold voltage of the memory element transistor MC is lower than the voltage V1. Read operation R2 determines whether the threshold voltage of the memory element transistor MC is lower than the voltage V2.

[1123] Hereinafter, the data corresponding to read operation R1 (read voltage V1) will be denoted as "V1 data", and the data corresponding to read operation R2 (read voltage V2) will be denoted as "V2 data".

[1124] As described above, each memory element transistor MC can take three states by having one of the three threshold voltage distributions.

[1125] 13.2 Encoding

[1126] Next, the encoding will be described using Figure 82 is a table showing the allocation of data based on two memory element transistors MC. Figure 82

[1127] ​In this embodiment, two memory element transistors MC are grouped together (hereinafter also referred to as "element cells") to hold 8 values ​​(3 bits) of data. Therefore, the memory element array 130 is configured as a 3-bit / 2-cell (hereinafter also referred to as "D1.5 (3-value)"). Hereinafter, the two memory element transistors MC constituting the element cell will be referred to as "element A" and "element B". In this embodiment, the memory element transistors MC contained in the first element region function as "element A", and the memory element transistors MC contained in the second element region function as "element B". In addition, the unit of data written to multiple element cells at the same time is referred to as a "segment". For example, when writing data in one segment, the size of the segment (data length) is half the number of memory element transistors MC contained in one memory group MG. That is, the size of the segment is half the page size of the physical page.

[1128] By assigning the 8-value state of a component cell to "000" through "111" in binary notation, a component cell can hold 3 bits of data. Hereinafter, the 3 bits of data for a component cell will be denoted as "the first bit of the component cell," "the second bit of the component cell," and "the third bit of the component cell," respectively. Furthermore, the set of the first bits of component cells written to (or read from) the memory bank MG will be denoted as "segment 1," the set of the second bits of component cells as "segment 2," and the set of the third bits of component cells as "segment 3."

[1129] exist Figure 82 In the example, for the combination of states of "Component A / Component B", data is allocated to "Segment 1 (first bit of component unit) / Segment 2 (second bit of component unit) / Segment 3 (third bit of component unit)" as shown below.

[1130] "S0 / S0" status: "111" data

[1131] "S0 / S1" status: "100" data

[1132] "S0 / S2" status: "000" data

[1133] "S1 / S0" status: "110" data

[1134] "S1 / S1" status: "101" data

[1135] "S1 / S2" status: "001" data

[1136] "S2 / S0" status: "010" data

[1137] "S2 / S1" status: "011" data

[1138] In this way, the 3-bit state is represented by the combination of the states of element A and element B. Furthermore, when element A / B = "S2 / S2", it is defined as not being used.

[1139] The bit value of the first segment (the first bit of the element unit) is determined by the readout action R2 (readout voltage V2) in element A (the first element region) and the readout action R2 (readout voltage V2) in element B (the second element region). When element A or element B is in the "S2" state, the bit value of the first segment is assigned "0".

[1140] The bit value of the second segment (the second bit of the element unit) is determined by the readout action R2 (readout voltage V2) in element A (the first element region) and the readout action R1 (readout voltage V1) in element B (the second element region). When element A is in state "S0" or "S1" and element B is in state "S1" or "S2", the bit value of the second segment is assigned to "0".

[1141] The bit value of the third segment (the third bit of the element unit) is determined by the readout action R1 (readout voltage V1) in element A (the first element region) and the readout action R1 (readout voltage V1) in element B (the second element region). When element A is in state "S0" and element B is in state "S1" or "S2", or when element A is in state "S1" or "S2" and element B is in state "S0", the bit value of the third segment is assigned to "0".

[1142] Calculation of the position value of segment 13.3

[1143] Next, use Figure 83 The calculation of the position value of the segment is explained. Figure 83 This is a diagram showing the relationship between the allocation of data to elements A and B and the bit values ​​of the segments. Figure 83 In the example, the logical AND operation is represented by "&", and the negation of data is represented by "~".

[1144] like Figure 83 As shown, in the readout operation R1 of element A or element B, when the threshold voltage is above the readout voltage V1, "0" data is assigned as V1 data; when the threshold voltage is below the readout voltage V1, "1" data is assigned as V1 data. Similarly, in the readout operation R2 of element A or element B, when the threshold voltage is above the readout voltage V2, "0" data is assigned as V2 data; when the threshold voltage is below the readout voltage V2, "1" data is assigned as V2 data. Thus, the bit value of each segment is calculated through the following operation.

[1145] The bit value of the first segment is calculated by performing an exponential OR operation (EXNOR) on the readout result (V2 data) of element A using the readout voltage V2 and the readout result (V2 data) of element B using the readout voltage V2.

[1146] The bit value of the second segment is calculated by performing a negation and NAND operation using the readout result (V2 data) of element A with readout voltage V2 and the readout result (V1 data) of element B with readout voltage V1.

[1147] The bit value of the third segment is calculated by performing an exponential OR operation (EXNOR) on the readout result (V1 data) of element A using the readout voltage V1 and the readout result (V1 data) of element B using the readout voltage V1.

[1148] 13.4 Transformation between Logical Page Address and Physical Page Address

[1149] Next, use Figure 84 and Figure 85 An example illustrating the transformation between logical page addresses and physical page addresses is provided. Figure 84 It is a diagram illustrating the process of changing logical page addresses and physical page addresses. Figure 85 This is a diagram showing the allocation of logical page data relative to physical pages.

[1150] In this embodiment, the case where the data of a logical page of 1 page is allocated to 3 segments in a memory group MG will be described.

[1151] like Figure 84 As shown, for example, if the memory controller 200 receives a write request from the host device 2, it allocates a logical page address "90001" (logical page 1) corresponding to the received logical address "00001".

[1152] If the instruction user interface circuit 121 receives a logical page address and a write command for a logical page from the memory controller 200, it transforms the logical page address into a physical page address consisting of three segments according to a pre-set mapping. At this time, the data length of the logical page is the same as the data length of the three segments.

[1153] Let the page size of a logical page be m (m is a number greater than or equal to 1), and the number of logical pages written (i.e., the number of logical page addresses contained in the command) be a (a is an integer greater than or equal to 1). Furthermore, let the page size of the physical pages of a memory bank MG be n (n is a number less than m), and let the number of segments (i.e., the number of bits that a group of elements A and B can hold) be c (c is an integer greater than a). Thus, the page size n of a physical page is twice the size of a segment (the number of element units), and can therefore be represented by n = m × 2a / c. In this embodiment, a = 1 and c = 3, so the page size of the physical page is n = m × 2 / 3. For example, when the page size of the logical page is 16 [kB], the page size of the physical page is n = 16 × 2 / 3 = 10.67 [kB]. In this case, the number of memory element transistors MC capable of achieving a page size n = 10.67 [kB] for one physical page becomes an integer value that is the same as or larger than the integer value obtained by rounding down 10.67 × 1024. That is, the number of memory element transistors MC becomes an integer value that is the same as or larger than the integer value obtained by rounding down the page size for one physical page.

[1154] Next, the configuration of logical page data in a memory group MG is described in detail.

[1155] like Figure 85 As shown, the data of the logical first page is divided into three groups, starting from the first data and designated as clusters 1 through 3. For example, memory 100 writes data from cluster 1 to segment 1, data from cluster 2 to segment 2, and data from cluster 3 to segment 3. In this embodiment, the data in segment 1 corresponds to the data in cluster 1 of the logical first page, the data in segment 2 corresponds to the data in cluster 2 of the logical first page, and the data in segment 3 corresponds to the data in cluster 3 of the logical first page.

[1156] 13.5 Composition of Sensing Amplifier and Page Buffer

[1157] Next, the configuration of the sense amplifier 132 and the page buffer 133 will be briefly described. In this embodiment, the memory element array 130 is configured as a 3-bit / 2-cell group, with element A of the first element region and element B of the second element region grouped together. Therefore, the configuration of the sense amplifier 132 and the page buffer 133 is preferably as follows: Figure 69 In the first example of the 9th embodiment, the configuration of alternating arrangement of sensing amplifier units SAU1 and SAU2 is described. This is because when processing data from elements A and B, it is easy to design a configuration where the corresponding sensing circuit SA and latch circuits XDL, ADL, and BDL are physically close together.

[1158] 13.6 Reading Action

[1159] Next, the read operation will be explained. In the read operation of this embodiment, if the memory 100 receives a read command based on a logical page from the memory controller 200, it reads data from the corresponding multiple physical pages, calculates segments by performing operations on the read data, and then combines the segments and outputs them as data of the logical page.

[1160] 13.6.1 Reading out the action flow

[1161] First, use Figure 86 and Figure 87 The process of reading from memory 100 is explained. Figure 86 and Figure 87 This is a flowchart of the reading action.

[1162] like Figure 86 and Figure 87 As shown, memory 100 receives a read command for logical page 1 from memory controller 200 (step S1). After the instruction user interface circuit 121 converts the logical page address into a physical page address, it sends the received instruction and the converted physical page address to sequencer 123.

[1163] The sequencer 123 first executes the readout action R2 corresponding to the readout voltage V2 (step S90).

[1164] The sequencer 123 transmits the data (V2 data) read from the sensing circuits SA1 and SA2 to the latching circuits BDL1 and BDL2 respectively (step S91).

[1165] The sequencer 123 performs calculations on the data using latch circuit BDL1 (V2 data of element A) and latch circuit BDL2 (V2 data of element B) to calculate the data of the first segment (data of the first cluster of the first logical page) (step S92).

[1166] The sequencer 123 transmits the calculated data of the first segment to the latch circuit XDL1 (step S93).

[1167] Sequencer 123 executes the readout action R1 corresponding to the readout voltage V1 (step S94).

[1168] The sequencer 123 transmits the data (V1 data) read from the sensing circuits SA1 and SA2 to the latching circuits ADL1 and ADL2 respectively (step S95).

[1169] The sequencer 123 performs calculations on the data using latch circuit BDL1 (V2 data of element A) and latch circuit ADL2 (V1 data of element B) to calculate the data of the second segment (data of the second cluster of the first logical page) (step S96).

[1170] The sequencer 123 transmits the calculated data of the second segment to the latch circuit XDL2 (step S97).

[1171] The sequencer 123 performs calculations on the data using latch circuit ADL1 (V1 data of element A) and latch circuit ADL2 (V1 data of element B) to calculate the data of the third segment (data of the third cluster of the first logical page) (step S98).

[1172] The sequencer 123 transmits the calculated data of the third segment to the latch circuit BDL1 (step S99).

[1173] Sequencer 123 sets the starting address of latch circuit XDL1 as column address CA in column counter 125 (step S100). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL1 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data (data of the first cluster of the first logical page) to latch circuit XDL1 of memory controller 200.

[1174] If the data output of the latch circuit XDL1 has not ended (step S101_No), the sequencer 123 will repeatedly perform the data output confirmation action until the output ends.

[1175] If the data output of latch circuit XDL1 ends (step S101_Yes), then sequencer 123 transmits the data of latch circuit BDL1 to latch circuit XDL1 (step S102). Alternatively, if the data output of latch circuit XDL1 ends, then the output of data from latch circuit XDL2 (data from the second cluster of the first logical page) begins.

[1176] If the data output of the latch circuit XDL2 has not ended (step S103_No), the sequencer 123 repeatedly performs the data output confirmation action until the output ends.

[1177] If the data output of latch circuit XDL2 ends (step S103_Yes), the starting address of latch circuit XDL1 is set as column address CA in column counter 125 (step S104). Serial access controller 126 receives data sequentially from the starting address of latch circuit XDL1 based on column address CA counted by column counter 125 and transmits it to input / output circuit 110. Input / output circuit 110 begins sending (outputting) data (data of the third cluster of the first logical page) of latch circuit XDL1 to memory controller 200. If the data output of latch circuit XDL1 ends, sequencer 123 ends the read operation of the first logical page. Furthermore, after read operation R2 ends, during the execution of read operation R1, the data of the first segment is determined, so memory 100 can also set the external RBn signal to "H" level and output data.

[1178] 13.6.2 Reading the instruction sequence of the action

[1179] Next, use Figure 88 An example of a sequence of instructions for reading out actions is illustrated. Figure 88 This is the instruction sequence for reading the logical first page. Figure 88 In the example, for simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted. Additionally, in... Figure 88 In the example, part of the instruction and the address were also omitted. Furthermore, in Figure 88 In the example, the voltage of the select word line WL when the internal RBn signal is in a busy state is also shown.

[1180] like Figure 88 As shown, if the sequencer 123 receives the instruction "30h", it responds by initiating a read operation. First, the sequencer 123 sets both the internal RBn signal and the external RBn signal to the "L" level, indicating a busy state. Next, the sequencer 123 executes the read operation R2. That is, it applies a read voltage V2 to the select word line WL. The result of the read data (V2 data) is stored in the latch circuits BDL1 (corresponding to element A) and BDL2 (corresponding to element B).

[1181] After the sequencer 123 completes the read operation R2, it executes the read operation R1. That is, it applies the read voltage V1 to the select word line WL. The result of the read data (V1 data) is saved to the latch circuits ADL1 (corresponding to element A) and ADL2 (corresponding to element B).

[1182] During the read operation R1, the sequencer 123 performs calculations on the data using latch circuit BDL1 and latch circuit BDL2 to calculate the data for the first segment. The calculated data is then stored in latch circuit XDL1.

[1183] If the read operation R1 ends, the sequencer 123 sets both the internal and external RBn signals to the "H" level, indicating a ready state. Additionally, the sequencer 123 performs calculations on the data using latch circuit BDL1 and latch circuit ADL2 to calculate the data for the second segment. The calculated data is then stored in latch circuit XDL2.

[1184] If the memory controller 200 receives an external RBn signal at the "H" level, it sends a signal REn (not shown) to the memory 100. The input / output circuit 110 begins outputting data based on the signal REn. First, the input / output circuit 110 outputs the data from the latch circuit XDL1 (the data from the first cluster of the first logical page).

[1185] During the period when the data of latch circuit XDL1 is output, sequencer 123 performs calculations using the data from latch circuit ADL1 and latch circuit ADL2 to calculate the data for the third segment. The calculated data is then stored in latch circuit BDL1.

[1186] If the data output of latch circuit XDL1 ends, the data of latch circuit BDL1 is transferred to latch circuit XDL1. Input / output circuit 110 is connected after latch circuit XDL1 and outputs the data of latch circuit XDL2 (data of the second cluster of the first logical page). Furthermore, input / output circuit 110 is connected after latch circuit XDL2 and outputs the data of latch circuit XDL1 (data of the third cluster of the first logical page). If the data output of latch circuit XDL1 ends, the read operation of the first logical page ends.

[1187] Furthermore, the order in which the read voltages V1 and V2 are applied can be interchanged. Additionally, if the data output of latch circuit XDL2 is completed before the data of the third segment is saved to latch circuit BDL1, the sequencer 123 can temporarily set the external RBn signal to "L" level to interrupt data output. Furthermore, after the read operation R2 is completed, the data of the first segment is determined during the execution of read operation R1, therefore the memory 100 can also set the external RBn signal to "H" level to output data.

[1188] 13.7 Write Action

[1189] Next, the write operation will be explained. In this embodiment, a full-sequence write operation is performed, in which data from segments 1 to 3 are written to the memory group MG. That is, in the full-sequence write operation of this embodiment, the write operations in states "S1" and "S2" are performed.

[1190] 13.7.1 Write operation process

[1191] Next, use Figure 89 and Figure 90 The process of writing operations in memory 100 is described. Figure 89 and Figure 90 This is a flowchart of the write operation.

[1192] like Figure 89 and Figure 90 As shown, during the receipt of a write command, memory 100 receives the logical page address of the logical first page from memory controller 200 (step S280). Instruction user interface circuit 121 converts the logical page address of the logical first page into a physical page address.

[1193] The sequencer 123 sets the starting address of the latch circuit XDL1 as the column address CA in the column counter 125 (step S281).

[1194] In page buffer 133, data input to the first cluster of the first logical page of latch circuit XDL1 begins based on the column address CA received from column counter 125 (step S282).

[1195] If the data input to the latch circuit XDL1 has not ended (step S283_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[1196] If the data input to latch circuit XDL1 ends (step S283_Yes), then sequencer 123 transmits the data from latch circuit XDL1 to latch circuit BDL1 (step S284). Alternatively, if the data input to latch circuit XDL1 ends, then data input to the second cluster of the first logical page of latch circuit XDL2 begins. Furthermore, if step S283_Yes, then data input to the second cluster of the first logical page of latch circuit XDL2 begins, and during this data input, sequencer 123 may also execute step S284.

[1197] If the data input to the latch circuit XDL2 has not ended (step S285_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[1198] If the data input to latch circuit XDL2 is completed (step S285_Yes), then sequencer 123 will transmit the data from latch circuit XDL2 to latch circuit BDL2 (step S286).

[1199] In column counter 125, sequencer 123 sets the starting address of latch circuit XDL1 as column address CA (step S287). In page buffer 133, based on column address CA received from column counter 125, data input to the third cluster of the logical first page of latch circuit XDL1 begins. Furthermore, if step S285 is true, data input to the third cluster of the logical first page of latch circuit XDL1 then begins, and during this data input, sequencer 123 may also execute step S286.

[1200] If the data input to the latch circuit XDL1 has not ended (step S288_No), the sequencer 123 will repeatedly perform the data input confirmation action until the input ends.

[1201] If the data input to latch circuit XDL1 ends (step S288_Yes), then the data input to the first logic page of latch circuits XDL1 and XDL2 ends. Sequencer 123 sets the external RBn signal and the internal RBn signal to the "L" level.

[1202] The sequencer 123 calculates the V1 data of element A and element B using the data from latch circuits BDL1, BDL2, and XDL1, which are the data of segments 1, 2, and 3 respectively (step S289). The calculated V1 data of element A and element B are then transmitted to latch circuits ADL1 and ADL2 respectively (step S290).

[1203] Sequencer 123 operates on the data from latch circuits BDL1, BDL2, and XDL1, i.e., the data of segments 1, 2, and 3, to calculate the V2 data of element A and element B (step S291). The calculated V2 data of element A and element B are transmitted to latch circuits XDL1 and XDL2 respectively (step S292). At this time, the data of segment 3 is stored in latch circuit XDL1, but the V2 data of element A can also be overwritten. Sequencer 123 determines the state of transistor MC of each memory element based on the combination of data from latch circuits ADL1, ADL2, XDL1, and XDL2.

[1204] The sequencer 123 executes program actions based on the determined state (step S293).

[1205] After the program action is completed, the sequencer 123 performs the program verification action (step S294).

[1206] If the verification fails (step S295_No), the sequencer 123 checks whether the number of program loops has reached the preset upper limit (step S296).

[1207] If the program loop count has not reached the upper limit (step S296_No), the sequencer 123 executes the program action (step S293). That is, the sequencer 123 repeatedly performs the program loop.

[1208] If the program loop count reaches the upper limit (step S296_Yes), the sequencer 123 ends the write operation and reports to the memory controller 200 that the write operation has not ended normally.

[1209] If the verification is successful (step S295_Yes), that is, if the writing of states "S1" and "S2" is completed, the sequencer 123 sets the external RBn signal to the "H" level and ends the full sequence writing operation.

[1210] 13.7.2 Command sequence for write operation

[1211] Next, use Figure 91 An example of a sequence of instructions for a write operation is illustrated. Figure 91 It is a sequence of instructions for a full-sequence write operation. Figure 91 In the example, for the sake of simplicity, signals CEn, CLE, ALE, WEn, and REn are omitted.

[1212] like Figure 91 As shown, firstly, the memory controller 200 sends the instruction "80h" to the memory 100. Next, the memory controller 200 sends the logical page address "AD-P1" of the first logical page. In the memory 100, the instruction user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address. Then, the memory controller 200 sends the data of the first logical page to the memory 100. The first cluster of the first logical page is saved to latch circuit XDL1 and then transferred to latch circuit BDL1. Next, the second cluster of the first logical page is saved to latch circuit XDL2 and then transferred to latch circuit BDL2. The third cluster of the first logical page is saved to latch circuit XDL1.

[1213] Next, the memory controller 200 sends the instruction "10h" to the memory 100.

[1214] If sequencer 123 receives the instruction "10h", it will set the internal RBn signal and the external RBn signal to the "L" level.

[1215] Sequencer 123 performs calculations on data V1 based on the data stored in latch circuits BDL1, BDL2, and XDL1, and saves the result to latch circuits ADL1 and ADL2. Sequencer 123 also performs calculations on data V2 based on the data stored in latch circuits BDL1, BDL2, and XDL1, and saves the result to latch circuits XDL1 and XDL2. Sequencer 123 determines the state of each memory element transistor MC based on the combination of data from latch circuits ADL1, ADL2, XDL1, and XDL2, and performs the write operation. After the write operation is completed, sequencer 123 sets both the internal RBn signal and the external RBn signal to the "H" level.

[1216] 13.8 Effects of this implementation method

[1217] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[1218] For example, the memory 100 may contain a memory region with multiple values ​​(2 to 4 bits / cell) and a memory region for high speed and high reliability. For example, the memory region for high speed and high reliability is used to store data as 2 values ​​(1 bit / cell) for high-speed access and high data reliability. It is also possible to set the high-speed and high-reliability memory region of the first to 12 embodiments as 2 values ​​(1 bit / cell), but since the physical page size of the memory region with multiple values ​​is smaller than the logical page size, the logical page size of the high-speed and high-reliability memory region will be smaller. In this case, the first to 12 embodiments can be applied to the memory region with multiple values, and this embodiment can be applied to the high-speed / high-reliability memory region. Therefore, the page size of the logical page of the memory region with multiple values ​​and the page size of the logical page of the high-speed / high-reliability memory region can be the same.

[1219] Furthermore, the allocation of storing 3 bits of data using 2 elements and 3 values ​​is described, for example, in U.S. Patent Application No. 16 / 123,162, filed September 6, 2018, entitled "SEMICONDUCTOR MEMORY". The entire patent application is incorporated herein by reference.

[1220] Furthermore, in this embodiment, the case where the memory element transistor MC stores 3 bits of data in 3-value 2-element configuration (1.5 bits / cell) is described, but it is not limited to this. For example, the memory element transistor MC can also store 5 bits of data in 6-value 2-element configuration (2.5 bits / cell), 7 bits of data in 12-value 2-element configuration (3.5 bits / cell), or 9 bits of data in 23-value or 24-value 2-element configuration (4.5 bits / cell).

[1221] 14. Examples of variations, etc.

[1222] The semiconductor memory of the above embodiment includes: a memory bank (MG) including multiple memory elements (MC) capable of holding multiple bits of data in three or more states; word lines (WL) connected to the multiple memory elements; and a first circuit (121) that transforms a single external address (logical page address) received from an external controller (200) into multiple internal addresses (physical page addresses). The size of the first page of the page data (physical page data) that the memory bank can hold is smaller than the size of the second page of the input data (logical page data) corresponding to the external address.

[1223] By applying the above-described embodiments, a semiconductor memory capable of suppressing the increase in chip area can be provided.

[1224] Furthermore, the implementation method is not limited to the manner described above and can be varied in various ways.

[1225] For example, in various encodings, it is also possible to reverse the "0" data and the "1" data.

[1226] For example, in embodiments 1 to 12 described above, examples of memory element transistor MC being 2 to 4 bits / cell were described, but this is not a limitation. For example, memory element transistor MC could also be 5 bits / cell. Furthermore, memory element transistor MC could also store 5 bits of data using a 6-value 2-element configuration (2.5 bits / cell), 7 bits of data using a 12-value 2-element configuration (3.5 bits / cell), or 9 bits of data using a 23-value or 24-value 2-element configuration (4.5 bits / cell).

[1227] For example, memory 100 is not limited to NAND flash memory. Memory 100 can be any non-volatile memory that performs read and write operations by selecting only a portion of the word lines within the address space of the memory element array. For example, memory 100 can also be PCM (Phase Change Memory), MRAM (Magnetoresistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

[1228] Furthermore, in the embodiments 1 to 12 described above, the state with 8 or 16 values ​​is written in a single write operation. However, to suppress the influence of adjacent elements, the write operation can be performed in two steps, for example. In this case, if the influence of adjacent elements is significant, after the write operation of the first page of the first word line (WLn), the write operation of the first page of the adjacent second word line (WLn+1) is performed, followed by the write operation of the second page of the first word line (WLn). For example, in the case of the 10th embodiment, as... Figure 92 As shown, during a write operation on the first logical page, the memory element transistor MC in the first element region writes data to states S0, S2, S4, or S6 by writing data to the first cluster of the first logical page in the Lower page and the third cluster of the first logical page in the Middle page. Conversely, the memory element transistor MC in the second element region writes data to states S0 or S2 by writing data to the second cluster of the first logical page in the Lower page. Furthermore, the state of the write operation on the first logical page can be lowered than the state of the write operation on the second logical page. Additionally, the boost voltage for the write operation on the first logical page can be greater than the boost voltage for the write operation on the second logical page. Subsequently, during the write operation on the second logical page, the data written during the write operation on the first logical page is read out through an internal read operation. The memory element transistor MC of the first element region writes data to the second cluster of the second logical page of the Upper page. When writing in state S0, it writes to state S0 or S1; when writing in state S2, it writes to state S2 or S3; when writing in state S4, it writes to state S4 or S5; and when writing in state S6, it writes to state S6 or S7. Similarly, the memory element transistor MC of the second element region writes data to the first cluster of the second logical page of the Middle page and the third cluster of the second logical page of the Upper page. When writing in state S0, it writes to states S0, S1, S4, or S5; and when writing in state S2, it writes to states S2, S3, S6, or S7. Furthermore, if a read operation is performed before a write operation on logical page 2 and after a write operation on logical page 1, the data will be erroneous because it will not be written to the Vth distribution following the write operation on logical page 2. Therefore, a separate read command can be set for this situation, or a flag element can be prepared for each page to change the read level.

[1229] For example, the above-described embodiments can be combined as much as possible.

[1230] Furthermore, the "connection" in the above embodiments includes a state in which the connection is indirectly formed by interleaving something such as a transistor or resistor in between.

[1231] The embodiments are illustrative, and the scope of the invention is not limited thereto.

[1232] Label Explanation

[1233] 1…Memory system, 2…Host device, 30…Semiconductor substrate, 32, 33, 41, 53, 55…Wiring layers, 34…Block insulating film, 35…Charge storage layer, 36…Tunnel insulating film, 37…Semiconductor layer, 38…Core layer, 39…Cap layer, 40, 51, 54, 56, 57…Contact plugs, 52…Gate electrode, 100…NAND flash memory, 110…Input / output circuit, 120…Control unit, 121…Command user interface circuit 122… Oscillator, 123… Sequencer, 124… Voltage generation circuit, 125… Column counter, 126… Serial access controller, 130… Memory element array, 131… Row decoder, 132… Sensing amplifier, 133… Page buffer, 200… Memory controller, 210… Host interface circuit, 220… RAM, 230… Processor, 240… Buffer memory, 250… Memory interface circuit, 260… ECC circuit.

Claims

1. A non-volatile memory, comprising: Multiple memory elements, each capable of storing 3 bits of data, which can be represented by the 1st bit, the 2nd bit, and the 3rd bit, through 8 threshold regions. The 8 threshold regions are a combination of the 1st threshold region, which represents the erased state, and the 2nd to 8th threshold regions, which represent the write state, where the threshold voltage is higher than the 1st threshold region. The threshold voltage of the gth threshold region is higher than the threshold voltage of the (g-1)th threshold region, where g is a natural number greater than 2 and less than 8. Word lines are connected to the plurality of memory elements; and The control unit executes read operations relative to the plurality of memory elements based on read instructions received from an external controller. The number of voltages used in determining the value of the data in the first bit among the first to seventh voltages existing between adjacent threshold regions in the first to eighth threshold regions is 1, the number of voltages used in determining the value of the data in the second bit is p, and the number of voltages used in determining the value of the data in the third bit is (6-p), where p is a natural number greater than 2 and less than 4. The address specified by the read instruction received from the external controller is an address corresponding to either the first page address or the second page address. When the specified address corresponds to the first page address, the control unit uses the voltage used in determining the value of the data in the first bit and the p voltages used in determining the value of the data in the second bit to read data from the plurality of memory elements. When the specified address corresponds to the second page address, the control unit uses the voltage used in determining the value of the data in the first bit and the (6-p) voltages used in determining the value of the data in the third bit to read data from the plurality of memory elements.

2. The non-volatile memory according to claim 1, The h-th voltage is higher than the (h-1)-th voltage, where h is a natural number greater than 2 and less than 7, and the 4th voltage is the voltage used to determine the value of the data in the 1st position.

3. The non-volatile memory according to claim 2, The value of p is 3.

4. The non-volatile memory according to claim 3, The first voltage, the third voltage, and the sixth voltage are the voltages used to determine the value of the data in the second bit. The second, fifth, and seventh voltages are the voltages used to determine the value of the data in the third bit.

5. The non-volatile memory according to claim 2, The value of p is 4.

6. The non-volatile memory according to claim 5, The first voltage, the third voltage, the fifth voltage, and the seventh voltage are the voltages used to determine the value of the data in the second bit. The second and sixth voltages are the voltages used to determine the value of the data in the third bit.

7. The non-volatile memory according to claim 2, The value of p is 2.

8. The non-volatile memory according to claim 7, The second and sixth voltages are the voltages used to determine the value of the data in the second bit. The first voltage, the third voltage, the fifth voltage, and the seventh voltage are the voltages used to determine the value of the data in the third bit.

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