Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate comprising a first device region for forming a first device and a second device region for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device; forming a polysilicon gate layer on the substrate, wherein the polysilicon gate layer in the first device region comprises a bottom polysilicon gate layer and multiple top polysilicon gate layers protruding from the bottom polysilicon gate layer; forming an interlayer dielectric layer on the substrate at the side of the polysilicon gate layer, wherein the interlayer dielectric layer also covers the bottom polysilicon gate layer and exposes the top of the polysilicon gate layer in the second device region; removing the polysilicon gate layer in the second device region to form a gate opening; and forming a metal gate layer in the gate opening. The present invention forms a finger-shaped polysilicon gate layer in the first device region, thereby facilitating improvement of the problem of top surface depression of the polysilicon gate layer in the first device region during the formation of the metal gate layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In existing semiconductor devices, devices with different operating voltages, such as low voltage (LV) devices, high voltage (HV) devices, and medium voltage (MV) devices, are generally formed on a substrate.

[0003] With the advancement of semiconductor process technology, the critical dimensions of semiconductor devices continue to shrink, leading to increasingly severe gate depletion effects. To better overcome these issues, high-k gate dielectric layer followed by a gate electrode layer (high-k last metal gate last) and replacement gate processes have become common processes.

[0004] Among them, compared with low-voltage devices, high-voltage devices and medium-voltage devices have higher operating voltages and correspondingly larger sizes. Therefore, high-voltage devices and medium-voltage devices still use polysilicon gates, while low-voltage devices use metal gates. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region for forming a first device and a second device region for forming a second device, the channel length of the first device being greater than the channel length of the second device; a first gate layer, located on the substrate of the second device region, the first gate layer being a metal gate material; a finger-shaped second gate layer, located on the substrate of the first device region, the second gate layer including a bottom polysilicon gate layer and a plurality of top gate layers protruding from the bottom polysilicon gate layer; an interlayer dielectric layer, located on the substrate on the sides of the first gate layer and the second gate, the interlayer dielectric layer covering the sidewalls of the first gate layer and the second gate, and covering the top of the bottom polysilicon gate layer exposed by the top gate layer.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region for forming a first device and a second device region for forming a second device, the channel length of the first device being greater than the channel length of the second device; forming a polysilicon gate layer on the substrate of the first device region and the second device region, wherein in the first device region, the polysilicon gate layer is finger-shaped, comprising a bottom polysilicon gate layer and a plurality of top polysilicon gate layers protruding from the bottom polysilicon gate layer; forming an interlayer dielectric layer on the substrate on the side of the polysilicon gate layer, wherein the interlayer dielectric layer also covers the bottom polysilicon gate layer exposed by the top polysilicon gate layer and exposes the top of the polysilicon gate layer of the second device region; removing the polysilicon gate layer of the second device region to form a gate opening in the interlayer dielectric layer; and forming a metal gate layer in the gate opening.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by an embodiment of the present invention, the first device region is used to form a first device, and the second device region is used to form a second device, the channel length of the first device is greater than the channel length of the second device, and a finger-shaped second gate layer is formed on the substrate of the first device region, the second gate layer includes a bottom polysilicon gate layer and a plurality of top gate layers protruding from the bottom polysilicon gate layer, wherein the first gate layer is a metal gate material, and the process of forming the first gate layer includes a planarization treatment step. The embodiment of the present invention arranges a discrete top gate layer on the bottom polysilicon gate layer so that the line width of the top gate layer and the spacing between adjacent top gate layers are smaller, thereby improving the top surface dishing problem generated by the second gate layer when forming the first gate layer, which is beneficial to improving the structural integrity of the second gate layer, and thus improving the performance of the semiconductor structure.

[0010] In the formation method provided by an embodiment of the present invention, a finger-shaped polysilicon gate layer is formed on the substrate of the first device area, and the polysilicon gate layer includes a bottom polysilicon gate layer and multiple top polysilicon gate layers protruding from the bottom polysilicon gate layer. After the polysilicon gate layer of the second device area is subsequently removed, a metal gate layer is formed in the gate opening, and the process of forming the metal gate layer usually includes a planarization step. Since the top polysilicon gate layer is separated from the bottom polysilicon gate layer, the line width of the top polysilicon gate layer and the spacing between adjacent top polysilicon gate layers are relatively small. Therefore, in the process of planarizing the metal gate layer, it is beneficial to improve the top surface dishing problem of the polysilicon gate layer in the first device area, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 5 to 14 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0013] Figures 15 to 17 1 is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figure 18 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Figure 19 FIG. 1 is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0016] As known from the background art, currently high-voltage devices and medium-voltage devices use polysilicon gates, while low-voltage devices use metal gates. However, the performance of the current semiconductor structure is poor.

[0017] The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure. Figures 1 to 4 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0018] refer to Figure 1 , providing a substrate 10, including a first device region 10M for forming a first device and a second device region 10L for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device.

[0019] Specifically, the operating voltage of the first device is greater than the operating voltage of the second device, the first device includes one or both of a high-voltage device and a medium-voltage device, and the second device is a low-voltage device. The operating voltages of the low-voltage device, the medium-voltage device, and the high-voltage device increase in sequence.

[0020] Continue to refer Figure 1 A gate oxide material layer 20 is formed on the surface of the substrate 10 in the first device region 10M; a high-k gate dielectric material layer 21 covering the gate oxide material layer 20 and the substrate 10, a metal barrier material layer 22 covering the high-k gate dielectric material layer 21, and a polysilicon material layer 23 covering the metal barrier material layer 22 are formed.

[0021] It should be noted that, according to process requirements, before forming the high-k gate dielectric material layer 21, another gate oxide material layer (not shown) can also be formed on the surface of the substrate 10 in the second device area 10L, and compared with the gate oxide material layer 20 of the first device area 10M, the thickness of the gate oxide material layer located in the second device area 10L is smaller.

[0022] refer to Figure 2 , the polysilicon material layer 23, the metal barrier material layer 22, the high-k gate dielectric material layer 21 and the gate oxide material layer 20 are etched to form a gate oxide layer 33 on the substrate 10 of the first device area 10M, a high-k gate dielectric layer 34 is formed on the gate oxide layer 33 and on the substrate 10 of the second device area 10L, a metal barrier layer 35 is formed on the high-k gate dielectric layer 34, and a polysilicon gate layer 36 is formed on the metal barrier layer 35.

[0023] In the first device region 10M, the stacked gate oxide layer 33 , high-k gate dielectric layer 34 , metal barrier layer 35 and polysilicon gate layer 36 constitute a polysilicon gate structure 31 .

[0024] It should be noted that when another gate oxide material layer is formed on the surface of the substrate 10 in the second device area 10L, the gate oxide material layer in the second device area 10L is also etched accordingly to form a gate oxide layer at the bottom of the high-k gate dielectric layer 34 in the second device area 10L.

[0025] refer to Figure 3 An interlayer dielectric layer 40 is formed on the substrate 10 at the side of the polysilicon gate layer 36 , and the interlayer dielectric layer 40 exposes the top of the polysilicon gate layer 36 in the second device region 10L.

[0026] refer to Figure 4 , the polysilicon gate layer 36 of the second device region 10L is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 40 to expose the metal barrier layer 35 ; and a metal gate layer 37 is formed in the gate opening.

[0027] In the second device region 10L, the stacked high-k gate dielectric layer 34 , metal barrier layer 35 and metal gate layer 37 form a metal gate structure 32 .

[0028] By forming a high-k gate dielectric layer 34 in the first device area 10M and the second device area 10L, forming a polysilicon gate structure 31 in the first device area 10M, and forming a metal gate structure 32 in the second device area 10L, the performance of the second device is maintained while the critical dimensions of the semiconductor device are continuously reduced. At the same time, the formation process of the first device still uses polysilicon gate technology.

[0029] Specifically, the step of forming the metal gate layer 37 in the gate opening includes: filling the gate opening with metal gate material, the metal gate material also covering the interlayer dielectric layer 40; flattening the metal gate material, removing the metal gate material above the top of the interlayer dielectric layer 40, and retaining the remaining metal gate material in the gate opening as the metal gate layer 37.

[0030] However, since the channel length of the first device is greater than the channel length of the second device, the line width of the polysilicon gate layer 36 of the first device region 10M is correspondingly larger. Figure 4 As shown, in the process of planarizing the metal gate material, it is easy to cause over-polishing problem to the polysilicon gate layer 36 of the first device area 10M, resulting in serious top surface depression problem of the polysilicon gate layer 36 of the first device area 10M. In severe cases, the metal barrier layer 35 may even be exposed.

[0031] In particular, a gate oxide layer 33 is also formed on the substrate 10 of the first device area 10M, and since the operating voltage of the first device is greater than the operating voltage of the second device, the gate oxide layer 33 of the first device area 10M is thicker than the gate oxide layer at the bottom of the high-k gate dielectric layer 34 located in the second device area 10L, which makes the top surface of the polysilicon gate layer 36 of the first device area 10M higher than the top surface of the polysilicon gate layer 36 of the second device area 10L. Therefore, the probability of the polysilicon gate layer 36 of the first device area 10M having a top surface depression problem is higher.

[0032] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region for forming a first device and a second device region for forming a second device, the channel length of the first device being greater than the channel length of the second device; forming a polysilicon gate layer on the substrate of the first device region and the second device region, wherein in the first device region, the polysilicon gate layer is finger-shaped, comprising a bottom polysilicon gate layer and a plurality of top polysilicon gate layers protruding from the bottom polysilicon gate layer; forming an interlayer dielectric layer on the substrate on the side of the polysilicon gate layer, the interlayer dielectric layer also covering the bottom polysilicon gate layer exposed by the top polysilicon gate layer and exposing the top of the polysilicon gate layer in the second device region; removing the polysilicon gate layer in the second device region, forming a gate opening in the interlayer dielectric layer; and forming a metal gate layer in the gate opening.

[0033] In the formation method provided by an embodiment of the present invention, a finger-shaped polysilicon gate layer is formed on the substrate of the first device area, and the polysilicon gate layer includes a bottom polysilicon gate layer and multiple top polysilicon gate layers protruding from the bottom polysilicon gate layer. After the polysilicon gate layer of the second device area is subsequently removed, a metal gate layer is formed in the gate opening, and the process of forming the metal gate layer usually includes a planarization step. Since the top polysilicon gate layer is separated from the bottom polysilicon gate layer, the line width of the top polysilicon gate layer and the spacing between adjacent top polysilicon gate layers are relatively small. Therefore, in the process of planarizing the metal gate layer, it is beneficial to improve the top surface dishing problem of the polysilicon gate layer in the first device area, thereby improving the performance of the semiconductor structure.

[0034] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 5 to 14 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0036] refer to Figure 5 , providing a substrate 100, including a first device region 100M for forming a first device and a second device region 100L for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device.

[0037] The substrate 100 is used to provide a process platform for subsequent process steps.

[0038] In this embodiment, the substrate 100 is used to form a planar field effect transistor as an example. The substrate 100 is a planar substrate. In other embodiments, the substrate is used to form a fin field effect transistor (FinFET). Accordingly, the substrate includes a substrate and a fin protruding from the substrate.

[0039] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be a substrate of other materials. For example, the substrate may be made of germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0040] In this embodiment, the substrate is a P-type substrate (Psub), that is, the substrate is doped with P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0041] In this embodiment, the substrate 100 includes a first device region 100M for forming a first device and a second device region 100L for forming a second device. The channel length of the first device is greater than the channel length of the second device.

[0042] As an example, the operating voltage of the first device is greater than the operating voltage of the second device, so that the channel length of the first device is greater than the channel length of the second device.

[0043] In this embodiment, the first device includes one or both of a medium-voltage device and a high-voltage device, and the second device is a low-voltage device. The operating voltages of the low-voltage, medium-voltage, and high-voltage devices increase in sequence. As an example, the operating voltage of the low-voltage device is less than 1V, the operating voltage of the medium-voltage device is between 1V and 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0044] It should be noted that, when the first device includes a medium-voltage device and a high-voltage device, the first device region 100M for forming the medium-voltage device and the first device region 100M for forming the high-voltage device are isolated.

[0045] The first device may be an NMOS device or a PMOS device. Similarly, the second device may also be an NMOS device or a PMOS device.

[0046] As an example, the first device region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the first sub-region 100MN and the second sub-region 100MP are used to form first devices of different channel conductivity types. For example, the first device formed in the first sub-region 100MN is an NMOS device, and the first device formed in the second sub-region 100MP is a PMOS device.

[0047] In this embodiment, taking the example of the first device area 100M being used to form a medium-voltage device and the second device area 100L being used to form a low-voltage device, a deep N-type well (DNW) area (not shown) is further formed in the substrate 100, a first well area (not marked) is formed in the deep N-type well area of ​​the first device area 100M, and a second well area (not marked) is formed in the deep N-type well area of ​​the second device area 100L.

[0048] The deep N-type well region is used to isolate the first well region from the P-type substrate, and is also used to isolate the second well region from the P-type substrate, thereby reducing substrate coupling noise.

[0049] The dopant ion type in the first well region is opposite to the channel conductivity type of the first device formed above it. When the first device is an NMOS device, the dopant ions in the first well region are P-type ions; when the first device is a PMOS device, the dopant ions in the first well region are N-type ions. Similarly, the dopant ion type in the second well region is opposite to the channel conductivity type of the second device formed above it.

[0050] In other embodiments, when the first device region is used to form a high-voltage device, a high-voltage well region is formed in the substrate, and accordingly, no deep N-type well region is formed in the substrate. Similarly, the dopant ion type in the high-voltage well region is opposite to the channel conductivity type of the first device formed thereover.

[0051] In this embodiment, an isolation structure 101 is further formed in the substrate 100. Specifically, the isolation structure 101 is formed in the substrate 100 at the junction of the first device region 100M and the second device region 100L.

[0052] The first device region 100M includes a first sub-region 100MN and a second sub-region 100MP. Therefore, the isolation structure 101 is also formed in the substrate 100 at the junction of the first sub-region 100MN and the second sub-region 100MP.

[0053] The isolation structure 101 is used to isolate adjacent devices. In this embodiment, the isolation structure 101 is shallow trench isolation (STI), which provides good isolation. In this embodiment, the isolation structure 101 is made of an insulating material, including silicon oxide.

[0054] Continue to refer Figure 5 The formation method further includes: forming a gate oxide layer 210 on the substrate 100 in the first device region 100M.

[0055] Subsequently, a polysilicon gate layer is formed on the gate oxide layer 210 of the first device area 100M. The polysilicon gate layer is used to control the opening or closing of the channel of the first device. The gate oxide layer 210 serves as the gate dielectric layer of the first device. The gate oxide layer 210 is used to electrically isolate the polysilicon gate layer from the channel of the first device.

[0056] In this embodiment, the gate oxide layer 210 exposes the substrate 100 in the second device region 100L, thereby preparing for the subsequent formation of a high-k gate dielectric layer on the substrate 100 in the second device region 100L.

[0057] In this embodiment, the gate oxide layer 210 is made of silicon oxide.

[0058] It should be noted that, according to process requirements, the formation method may also include: forming another gate oxide layer (not shown) on the surface of the substrate 100 in the second device area 100L, and compared with the gate oxide layer 210 in the first device area 100M, the thickness of the gate oxide layer located in the second device area 100L is smaller.

[0059] Combined with reference Figures 6 to 9 A polysilicon gate layer 330 (eg, Figure 9 As shown), in the first device region 100M, the shape of the polysilicon gate layer 330 is finger-shaped, and the polysilicon gate layer 330 includes a bottom polysilicon gate layer 331 (as shown Figure 9 ) and a plurality of top polysilicon gate layers 332 protruding from the bottom polysilicon gate layer 331 (as shown Figure 9 shown).

[0060] The adjacent top polysilicon gate layer 332 and the bottom polysilicon gate layer 331 form a first groove 333 (eg, Figure 9 shown).

[0061] The polysilicon gate layer 330 of the first device region 100M is used as a device gate structure of the first device, thereby controlling the opening or closing of the channel of the first device. The polysilicon gate layer 330 of the second device region 100L is used to occupy space for the subsequent formation of a metal gate layer.

[0062] After forming an interlayer dielectric layer on the substrate 100 on the side of the polysilicon gate layer 330, the polysilicon gate layer 330 in the second device region 100L is removed to form a gate opening. A metal gate layer is then formed in the gate opening. The process for forming the metal gate layer generally includes a step of planarizing the metal gate material. The larger the line width of the metal gate layer, the higher the probability of a top surface dishing problem occurring on the metal gate layer during the planarization process. Since the first device region 100M is used to form the first device, the first device has a longer channel length. Therefore, by using the polysilicon gate layer 330 in the first device, the step of planarizing the metal gate material over a large area is omitted in the first device region 100M, thereby avoiding the top surface dishing problem of the metal gate layer caused by the larger size.

[0063] Moreover, since the top polysilicon gate layer 332 is separated from the bottom polysilicon gate layer 331, the line width of the top polysilicon gate layer 332 and the interval between adjacent top polysilicon gate layers 332 (i.e., the line width of the first groove 333) are relatively small. Therefore, in the process of flattening the metal gate layer, the probability of over-grinding the polysilicon gate layer 330 of the first device area 100M is low, which is beneficial to improving the top surface depression problem of the polysilicon gate layer 330 of the first device area 100M. For example, it is beneficial to reduce the probability of the polysilicon gate layer 330 of the first device area 100M being ground to expose the metal barrier layer 320, thereby improving the structural integrity of the polysilicon gate layer 330 of the first device area 100M, and further beneficial to improving the performance of the semiconductor structure.

[0064] In this embodiment, the material of the polysilicon gate layer 330 is polysilicon.

[0065] It should be noted that the distance H (e.g. Figure 9 If the distance H from the top of the top polysilicon gate layer 332 to the top of the bottom polysilicon gate layer 331 is too small, then in the subsequent planarization process of forming the metal gate layer, the top polysilicon gate layer 332 is likely to be completely removed, thereby causing over-grinding of the bottom polysilicon gate layer 331, and further increasing the probability of the polysilicon gate layer 330 in the first device area 100M having a top surface depression problem; if the distance H from the top of the top polysilicon gate layer 332 to the top of the bottom polysilicon gate layer 331 is too large, then the thickness of the bottom polysilicon gate layer 331 is likely to be too small. Considering the influence of etching uniformity and load effect, in the process of forming the first groove 333, the bottom polysilicon gate layer 331 exposed by the top polysilicon gate layer 332 is likely to be etched through, thereby affecting the performance of the polysilicon gate layer in the first device area 100M. Therefore, in this embodiment, the distance H from the top of the top polysilicon gate layer 332 to the top of the bottom polysilicon gate layer 331 is to For example, the distance H from the top of the top polysilicon gate layer 332 to the top of the bottom polysilicon gate layer 331 is or

[0066] In this embodiment, the polysilicon gate layer 330 further includes an edge polysilicon gate layer 335 that protrudes from the surface of the edge region of the bottom polysilicon gate layer 331 and surrounds the top polysilicon gate layer 332 .

[0067] Specifically, the edge polysilicon gate layer 335 includes relative outer side walls 335b and inner side walls 335a, the inner side walls 335a are in contact with the side walls of the outermost top polysilicon gate layer 332, the outer side walls 335b are flush with the side walls of the bottom polysilicon gate layer 331, and the top of the edge polysilicon gate layer 335 is lower than the top of the top polysilicon gate layer 332.

[0068] The outermost top polysilicon gate layer 332 refers to the top polysilicon gate layer 332 closest to the sidewall of the bottom polysilicon gate layer 331 .

[0069] In addition, the total thickness of the edge polysilicon gate layer 335 and the bottom polysilicon gate layer 331 in the first device region 100M is equal to the thickness of the polysilicon gate layer 330 in the second device region 100N.

[0070] By forming the edge polysilicon gate layer 335 , the process window of the photolithography process when forming the polysilicon gate layer 330 in the first device region 100M is increased.

[0071] like Figure 9 As shown, it should be noted that, for the convenience of illustration, for the polysilicon gate layer 330 in the first device region 100M, dotted lines are used to represent the interfaces between the edge polysilicon gate layer 335, the top polysilicon gate layer 332 and the bottom polysilicon gate layer 331.

[0072] The steps of forming the polysilicon gate layer 330 are described in detail below with reference to the accompanying drawings.

[0073] Combined with reference Figure 6 and Figure 7 A polysilicon material layer 243 (eg, Figure 7 shown).

[0074] The polysilicon material layer 243 is used to prepare for the subsequent formation of a polysilicon gate layer.

[0075] Specifically, the steps of forming the polysilicon material layer 243 include: Figure 6 As shown, an initial polysilicon material layer 240 is formed on the substrate 100 in the first device region 100M and the second device region 100L; Figure 7As shown, in the second device area 100L and a partial area of ​​the first device area 100M, a partial thickness of the initial polysilicon material layer 240 is etched to form a bottom residual layer 241 covering the substrate 100 and a protruding portion 242 protruding from the bottom residual layer 241 of the first device area 100M, and the bottom residual layer 241 and the protruding portion 242 serve as a polysilicon material layer 243.

[0076] In this embodiment, the polysilicon gate layer of the second device region 100L has a target thickness. Therefore, the thickness T2 of the bottom residual layer 241 (e.g. Figure 7 is set to be equal to the target thickness.

[0077] In this embodiment, the initial polysilicon material layer 240 is used to form a polysilicon gate layer.

[0078] Specifically, the polysilicon material layer 243 is subsequently etched to form a polysilicon gate layer. In order to form a finger-shaped polysilicon gate layer in the first device region 100M, during the etching of the polysilicon material layer 243, the protrusion 242 and the bottom residual layer 241 with a partial thickness at the bottom of the protrusion 242 are sequentially etched to form a first groove. Therefore, the thickness T1 of the initial polysilicon material layer 240 (such as Figure 6 shown) is greater than the target thickness of the polysilicon gate layer.

[0079] By making the thickness T1 of the initial polysilicon material layer 240 greater than the target thickness of the polysilicon gate layer, a thickness margin is provided for forming the protrusion 242. Accordingly, a single etching step can be used subsequently to etch the entire thickness of the bottom residual layer 241 on the side of the protrusion 242 while etching the protrusion 242 and the bottom residual layer 241 with a partial thickness located at the bottom of the protrusion 242. This allows a first groove to be formed in the protrusion 242 and the bottom residual layer 241 located at the bottom of the protrusion 242, so that the shape of the polysilicon gate layer of the first device area 100 is finger-shaped.

[0080] In the process of forming the bottom residual layer 241 and the protrusion 242, the initial polysilicon material layer 240 covers the entire substrate 100, which facilitates the photolithography process and the etching process, thereby reducing the process difficulty of forming the bottom residual layer 241 and the protrusion 242.

[0081] It should be noted that the difference between the thickness T1 of the initial polysilicon material layer 240 and the target thickness will affect the thickness T2 of the bottom residual layer 241 , and the thickness T2 of the bottom residual layer 241 is the actual thickness of the polysilicon gate layer of the second device region 100L. If the difference between the thickness T1 of the initial polysilicon material layer 240 and the target thickness is too small, considering the influence of etching uniformity and load effect, when the protrusion 242 and the bottom residual layer 241 of a partial thickness located at the bottom of the protrusion 242 are subsequently etched, it is easy to etch through the bottom residual layer 241 below the protrusion 242, thereby affecting the performance of the polysilicon gate layer of the first device area 100M; if the difference between the thickness T1 of the initial polysilicon material layer 240 and the target thickness is too large, the thickness T1 of the initial polysilicon material layer 240 is too large. In order to enable the polysilicon gate layer of the second device area 100L to reach its target thickness, accordingly, in the process of etching the initial polysilicon material layer 240 to form the protrusion 242, the initial polysilicon gate layer is damaged. The etching amount of the silicon material layer 240 is large, thereby increasing the process time required for forming the initial polysilicon material layer 240 and etching the initial polysilicon material layer 240, which is not conducive to improving production capacity. Moreover, this may easily lead to the distance from the bottom of the subsequent first groove to the top of the edge polysilicon gate layer being too small, and it may even happen that the top of the first groove is higher than the top of the edge polysilicon gate layer, that is, the depth of the first groove is too small. Accordingly, in the subsequent flattening process of forming the metal gate layer, it is easy to cause the part of the top polysilicon gate layer that is higher than the top of the edge polysilicon gate layer to be completely removed, thereby easily causing over-grinding of the edge polysilicon gate layer or the bottom polysilicon gate layer, thereby increasing the probability of the polysilicon gate layer in the first device area 100M having a top surface depression problem.

[0082] Therefore, in this embodiment, the difference between the thickness T of the initial polysilicon material layer 240 and the target thickness is to For example, the difference between the thickness T of the initial polysilicon material layer 240 and the target thickness is or

[0083] In this embodiment, the initial polysilicon material layer 240 is formed by a furnace process or a chemical vapor deposition process.

[0084] In this embodiment, an anisotropic dry etching process is used to etch the initial polysilicon material layer 240. The anisotropic etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate is much greater than the lateral etching rate, thereby obtaining a better etching profile, thereby improving the morphology quality and dimensional accuracy of the protrusion 242, and facilitating precise control of the longitudinal etching amount of the initial polysilicon material layer 240.

[0085] In this embodiment, after the protrusion 242 is formed, the line width of the protrusion 242 is smaller than the preset line width of the polysilicon gate layer of the first device area 100M, so that an edge polysilicon gate layer can be formed in the subsequent process of etching the polysilicon material layer 243 to form a polysilicon gate layer.

[0086] Combined with reference Figure 8 and Figure 9 , etching the polysilicon material layer 243 (such as Figure 8 As shown), the polysilicon gate layer 330 is formed.

[0087] Specifically, the raised portion 242 and the bottom residual layer 241 with a partial thickness at the bottom of the raised portion 242 are etched to form a first groove 333 in the raised portion 242 and the bottom residual layer 241 at the bottom of the raised portion 242, and the bottom residual layer 241 with the entire thickness of the side of the raised portion 242 is etched at the same time. The raised portion 242 and the bottom residual layer 241 remaining after etching are used as the polysilicon gate layer 330.

[0088] In this embodiment, in the first device region 100M, the protrusion 242 and the bottom residual layer 241 remaining after etching serve as the polysilicon gate layer 330 , and in the second device region 100L, the bottom residual layer 241 remaining after etching serves as the polysilicon gate layer 330 .

[0089] Specifically, in the first device area 100M, the polysilicon gate layer 330 includes a bottom polysilicon gate layer 331 and multiple top polysilicon gate layers 332 protruding from the bottom polysilicon gate layer 331, and the adjacent top polysilicon gate layers 332 and bottom polysilicon gate layers 331 form a first groove 333.

[0090] In this embodiment, since the initial polysilicon material layer 240 (such as Figure 6 The thickness T1 (as shown) Figure 6 As shown) is greater than the target thickness of the polysilicon gate layer 330 of the second device region 100L, which makes the total thickness of the top polysilicon gate layer 332 and the bottom polysilicon gate layer 331 greater than the thickness of the polysilicon gate layer 330 of the second device region 100L.

[0091] Correspondingly, compared with the top surface of the polysilicon gate layer 330 of the second device area 100L, the top surface of the top polysilicon gate layer 332 is higher. Therefore, after the subsequent planarization process, the thickness of the polysilicon gate layer 330 of the first device area 100M is still relatively large, which is beneficial to improving the top surface depression problem of the polysilicon gate layer 330 of the first device area 100M.

[0092] In this embodiment, the distance H from the top of the top polysilicon gate layer 332 to the top of the bottom polysilicon gate layer 331 is to

[0093] It should be noted that, in the actual process, due to the etching of the protrusion 242 and the bottom residual layer 241 with a partial thickness at the bottom of the protrusion 242, a first groove 333 is formed in the protrusion 242 and the bottom participating layer 241 at the bottom of the protrusion 242, and at the same time, the bottom residual layer 241 with the entire thickness of the side of the protrusion 242 is etched to form a polysilicon gate layer 330. Therefore, the distance H from the top of the top polysilicon gate layer 332 to the top of the bottom polysilicon gate layer 331 depends on the target thickness of the polysilicon gate layer 330 of the second device area 100L.

[0094] Among them, the thickness of the bottom polysilicon gate layer 331 is equal to the difference between the thickness T1 of the initial polysilicon material layer 240 and the target thickness. The smaller the thickness T1 of the initial polysilicon material layer 240, the smaller the thickness of the bottom polysilicon gate layer 331 is, and the greater the probability that the bottom polysilicon gate layer 331 will be etched through during the formation of the first groove.

[0095] In this embodiment, an anisotropic dry etching process is used to etch the polysilicon material layer 243 , thereby improving the morphology quality and dimensional accuracy of the polysilicon gate layer 330 .

[0096] It should be noted that if Figure 8 As shown, before etching the polysilicon material layer 243 , the forming method further includes: forming a gate mask layer 340 on the polysilicon material layer 243 .

[0097] The gate mask layer 340 is used as a mask when etching the polysilicon material layer 243 .

[0098] Specifically, the gate mask layer 340 is formed by sequentially performing a deposition process, a photolithography process, and an etching process.

[0099] In this embodiment, in the first device region 100M, the gate mask layer 340 covers the sidewalls and a portion of the top of the protrusion 242 , and also extends to cover a portion of the bottom residual layer 241 on the side of the protrusion 242 .

[0100] Compared with the solution in which the sidewalls of the gate mask layer are flush with the protrusion, this embodiment enables the gate mask layer 340 to extend to cover part of the bottom residual layer 241 on the side of the protrusion 242, thereby increasing the process window of the photolithography process during the formation of the gate mask layer 340.

[0101] Moreover, the line width dimension of the protrusion 242 is smaller than the preset line width dimension of the polysilicon gate layer of the first device area 100M. Therefore, by extending the gate mask layer 340 of the first device area 100M to cover part of the bottom residual layer 241 on the side of the protrusion 242, the line width dimension of the polysilicon gate layer 330 of the first device area 100M can reach the preset line width dimension.

[0102] In other embodiments, depending on actual conditions, in the first device region, the gate mask layer may be located only on top of the protrusion. Accordingly, the line width of the protrusion is equal to the preset line width of the polysilicon gate layer 330 in the first device region 100M.

[0103] In this embodiment, the gate mask layer 340 is made of silicon nitride.

[0104] like Figure 9 As shown, the gate mask layer 340 is used as a mask to etch the polysilicon material layer 243 .

[0105] Therefore, in this embodiment, the polysilicon gate layer 330 further includes an edge polysilicon gate layer 335 protruding from the bottom polysilicon gate layer 331 and surrounding the top polysilicon gate layer 332 .

[0106] Accordingly, the gate mask layer 340 is formed on the top of the top polysilicon gate layer 332 and the top of the edge polysilicon gate layer 335 of the first device region 100M, and on the top of the polysilicon gate layer 330 of the second device region 100L.

[0107] refer to Figure 9 In this embodiment, a high-k gate dielectric layer 310 and a metal barrier layer 320 stacked in sequence from bottom to top are further formed on the substrate 100 of the first device area 100M and the second device area 100L; the polysilicon gate layer 330 is correspondingly formed on the metal barrier layer 320.

[0108] In this embodiment, a high-K first process in a gate-last process is used to form the metal gate structure. Therefore, a stacked high-k gate dielectric layer 310 and a metal barrier layer 320 are first formed on the substrate 100.

[0109] The high-k gate dielectric layer 310 is used to constitute the gate dielectric layer of the second device, that is, the gate dielectric layer of the second device includes the high-k gate dielectric layer 310 .

[0110] The high-k gate dielectric layer 310 is made of a high-k dielectric material, where a high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 310 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. As an example, the material of the high-k gate dielectric layer 310 is HfO2.

[0111] The metal barrier layer 320 is used to isolate the high-k gate dielectric layer 310 and the metal gate layer to protect the high-k gate dielectric layer 310. At the same time, in the subsequent etching process of removing the polysilicon gate layer 330 in the second device area 100L, the metal barrier layer 320 serves as an etching stop layer, thereby reducing the probability of damage to the high-k gate dielectric layer 310. Moreover, after the metal gate layer is subsequently formed, the metal barrier layer 320 is also used to prevent easily diffusible ions (for example, aluminum ions) in the metal gate layer from diffusing into the high-k gate dielectric layer 310.

[0112] Specifically, the material of the metal barrier layer 320 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 320 is titanium nitride.

[0113] The metal barrier layer 320 also has a certain influence on the gate work function of the second device.

[0114] In the actual process, by reasonably setting the thickness of the metal barrier layer 320, the metal barrier layer 320 can be used as an etching stop layer in the subsequent etching process to remove the polysilicon gate layer 330 of the second device area 100L. At the same time, the metal barrier layer 320 has a better blocking effect on the easily diffusible ions in the metal gate layer.

[0115] Correspondingly, such as Figure 6 As shown, before forming the polysilicon material layer 240 , a high-k gate dielectric material layer 220 and a metal barrier material layer 230 are sequentially stacked from bottom to top on the substrate 100 in the first device region 100M and the second device region 100L.

[0116] The high-k gate dielectric material layer 220 is used to form a high-k gate dielectric layer, and the metal barrier material layer 230 is used to form a metal barrier layer.

[0117] Specifically, the high-k gate dielectric material layer 220 covers the substrate 100 in the second device region 100L, and extends to cover the gate oxide layer 210 in the first device region 100M.

[0118] It should be noted that, when another gate oxide layer (not shown) is formed on the surface of the substrate 100 in the second device region 100L, the high-k gate dielectric material layer 220 correspondingly covers the gate oxide layer in the second device region 100L.

[0119] In this embodiment, the high-k gate dielectric material layer 220 and the metal barrier material layer 230 are formed using a deposition process. Specifically, the deposition process is an atomic layer deposition process. The use of the atomic layer deposition process improves the step coverage and thickness uniformity of the high-k gate dielectric material layer 220 and the metal barrier material layer 230. In other embodiments, the deposition process may also be a physical vapor deposition process.

[0120] Correspondingly, such as Figure 9 As shown, after etching the polysilicon material layer 243 , the process further includes: etching the high-k gate dielectric material layer 220 and the metal barrier material layer 230 exposed by the polysilicon gate layer 330 to form a stacked high-k gate dielectric layer 310 and a metal barrier layer 320 .

[0121] In this embodiment, the forming method further includes: etching the gate oxide layer 210 exposed by the polysilicon gate layer 330 to expose the substrate 100 on both sides of the polysilicon gate layer 330 .

[0122] By exposing the substrate 100 on both sides of the polysilicon gate layer 330 , the influence on the subsequent process of forming the source and drain doped regions is reduced, and preparation is made for the subsequent formation of the source and drain silicide layer.

[0123] When another gate oxide layer (not shown) is formed on the surface of the substrate 100 in the second device region 100L, the forming method further comprises: etching and removing the gate oxide layer exposed by the polysilicon gate layer 330 in the second device region 100L.

[0124] It should be noted that, in other embodiments, the gate oxide layer partially exposed by the polysilicon gate layer may also be removed in the first device region. For example, another gate oxide layer (not shown) is formed on the substrate surface of the second device region, and the gate oxide layer in the second device region is thinner than the gate oxide layer in the first device region. Therefore, the time required to remove the gate oxide layer in the second device region is correspondingly shorter. Therefore, while the stacked polysilicon gate layer 330, metal barrier layer 320, high-k gate dielectric layer 310, and gate oxide layer (not shown) are removed sequentially from top to bottom in the second device region, the gate oxide layer in the first device region may not be completely removed.

[0125] refer to Figure 10 After forming the polysilicon gate layer 330 , the forming method further includes: forming source-drain doped regions 350 in the substrate 100 on both sides of the polysilicon gate layer 330 .

[0126] The source-drain doped region 350 serves as the source region or drain region of the formed device.

[0127] The conductivity type of the doped ions in the source / drain doping regions 350 is the same as the conductivity type of the corresponding device. When the device formed is an NMOS device, the doped ions in the source / drain doping regions 350 are N-type ions, including P ions, As ions, or Sb ions. When the device formed is a PMOS device, the doped ions in the source / drain doping regions 350 are P-type ions, including B ions, Ga ions, or In ions.

[0128] Continue to refer Figure 10 After forming the polysilicon gate layer 330 , the forming method further includes: doping conductive ions 351 into the bottom polysilicon gate layer 331 exposed from the top polysilicon gate layer 332 .

[0129] By doping the conductive ions 351 into the bottom polysilicon gate layer 331 exposed by the top polysilicon gate layer 332, the resistance of the polysilicon gate layer 330 in the first device area 100M is reduced, thereby reducing the gate resistance of the first device and reducing the contact resistance between the polysilicon gate layer 330 and the gate silicide layer, which is correspondingly beneficial to improving the performance of the semiconductor structure.

[0130] In this embodiment, the conductive ions 351 may be N-type ions or P-type ions. Specifically, the conductive ions 351 include B ions, Ga ions, In ions, P ions, As ions, or Sb ions.

[0131] The conductivity type of the conductive ions 351 may be the same as or different from the channel conductivity type of the corresponding device.

[0132] In this embodiment, during the process of forming the source / drain doping region 350 , the conductive ions 351 are doped into the bottom polysilicon gate layer 331 exposed from the top polysilicon gate layer 332 .

[0133] The conductive ions 351 are doped into the bottom polysilicon gate layer 331 exposed from the top polysilicon gate layer 332 using the process used to form the source / drain doped regions 350, thereby simplifying the process steps. Accordingly, the conductive ions 351 doped into the bottom polysilicon gate layer 331 have the same conductivity type as the channel conductivity type of the corresponding device.

[0134] Specifically, the first device region 100M includes a first sub-region 100MN and a second sub-region 100MP. Therefore, during the process of forming the source / drain doped region 350 in the substrate 100 of the first sub-region 100MN, the conductive ions 351 are doped into the bottom polysilicon gate layer 331 of the first sub-region 100MN. Similarly, during the process of forming the source / drain doped region 350 in the substrate 100 of the second sub-region 100MP, the conductive ions 351 are doped into the bottom polysilicon gate layer 331 of the second sub-region 100MP.

[0135] Specifically, the conductive ions 351 are doped into the substrate 100 on both sides of the polysilicon gate layer 330 and the bottom polysilicon gate layer 331 exposed from the top polysilicon gate layer 332 by ion implantation.

[0136] It should be noted that after ion implantation, since the conductive ions 351 will diffuse, the conductive ions 351 may also diffuse laterally into the bottom polysilicon gate layer 331 below the top polysilicon gate layer 332 in a direction parallel to the surface of the substrate 100 .

[0137] refer to Figure 11 After forming the polysilicon gate layer 330 , the forming method further includes: forming a gate silicide layer 361 on the surface of the bottom polysilicon gate layer 331 exposed by the top polysilicon gate layer 332 .

[0138] By forming a gate silicide layer 361 on the surface of the bottom polysilicon gate layer 331 exposed by the top polysilicon gate layer 332, current can flow through the gate silicide layer 361 when the first device is working, thereby reducing the gate resistance.

[0139] In this embodiment, the material of the gate silicide layer 361 can be nickel silicon compound, cobalt silicon compound or titanium silicon compound.

[0140] It should be noted that a gate mask layer 340 is formed on the top of the polysilicon gate layer 330. Therefore, in the process of forming the gate silicide layer 361, the gate mask layer 340 is used as a protective layer to avoid the formation of the gate silicide layer 361 on the top surface of the polysilicon gate layer 330. Therefore, in the subsequent planarization process of forming the metal gate layer, the gate silicide layer 361 will not be polished, thereby avoiding metal contamination of the machine.

[0141] In this embodiment, the formation method further includes: forming a source-drain silicide layer 360 on the surface of the source-drain doped region 350 , and forming the gate silicide layer 361 during the process of forming the source-drain silicide layer 360 .

[0142] Subsequently, source / drain contact plugs are formed on top of the source / drain doped regions 350. The source / drain silicide layer 360 is formed to reduce the contact resistance between the source / drain doped regions 350 and the source / drain contact plugs. Furthermore, in this embodiment, the source / drain silicide layer 360 and the gate silicide layer 361 are formed in the same step, thereby simplifying the process steps.

[0143] Specifically, a metal layer is formed on the surface of the source / drain doped region 350 and the bottom polysilicon gate layer 331, and an annealing treatment is performed to allow the metal layer to react with the materials of the source / drain doped region 350 and the bottom polysilicon gate layer 331, thereby converting the metal layer located on the surface of the source / drain doped region 350 into a source / drain silicide layer 360, and converting the metal layer located on the surface of the bottom polysilicon gate layer 331 into a gate silicide layer 361. After the source / drain silicide layer 360 and the gate silicide layer 361 are formed, the remaining unreacted metal layer is removed.

[0144] It should be noted that a step of forming a silicide block (SAB) layer (not shown) is also included before forming the source / drain silicide layer 360 and the gate silicide layer 361. By forming the silicide block layer, the regions where the source / drain silicide layer 360 and the gate silicide layer 361 are to be formed are exposed, and regions where the source / drain silicide layer 360 and the gate silicide layer 361 are not to be formed are protected.

[0145] In addition, before forming the source / drain silicide layer 360, it also includes: removing the oxide layer (for example, the natural oxide layer) on the surface of the source / drain doped region 350 or the gate oxide layer 210 remaining in the first device region 100M, thereby exposing the surface of the source / drain doped region 350, and preparing for the formation of the source / drain silicide layer 360.

[0146] refer to Figure 12An interlayer dielectric (ILD) layer 370 is formed on the substrate 100 on the side of the polysilicon gate layer 330. The interlayer dielectric layer 370 also covers the bottom polysilicon gate layer 331 exposed by the top polysilicon gate layer 332 and exposes the top of the polysilicon gate layer 330 of the second device area 100L.

[0147] The interlayer dielectric layer 370 is used to isolate adjacent devices and exposes the top of the polysilicon gate layer 330 of the second device region 100L, thereby preparing for the subsequent removal of the polysilicon gate layer 330 of the second device region 100L.

[0148] The material of the interlayer dielectric layer 370 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. As an example, the material of the interlayer dielectric layer 370 is silicon oxide.

[0149] Specifically, the interlayer dielectric layer 370 is formed by a deposition and planarization process (eg, a chemical mechanical polishing process), such that the interlayer dielectric layer 370 exposes the top of the polysilicon gate layer 330 of the second device region 100L.

[0150] It should be noted that the operating voltage of the first device is relatively high. Therefore, the thickness of the gate oxide layer 210 of the first device area 100M is usually larger. Accordingly, the top of the polysilicon gate layer 330 of the first device area 100M is usually higher than the top of the polysilicon gate layer 330 of the second device area 100L. Therefore, after the interlayer dielectric layer 370 is formed, the interlayer dielectric layer 370 usually also exposes the top of the polysilicon gate layer 330 of the first device area 100M (that is, the top of the top polysilicon gate layer 332).

[0151] It should also be noted that, during the process of forming the interlayer dielectric layer 370 , the gate mask layer 340 located on top of the top polysilicon gate layer 332 is removed.

[0152] In this embodiment, during the process of forming the gate mask layer 340, in the first device area 100M, the gate mask layer 340 covers the side walls of the protrusion 242, and also extends to cover part of the bottom residual layer 241 on the side of the protrusion 242, so that the top of the edge polysilicon gate layer 335 is lower than the top of the top polysilicon gate layer 332. Therefore, a partial thickness of the gate mask layer 340 is retained on the top of the edge polysilicon gate layer 335.

[0153] In other embodiments, according to actual conditions, the gate mask layer in the first device region may also be completely removed.

[0154] refer to Figure 13 , the polysilicon gate layer 330 of the second device region 100L is removed, and a gate opening 381 is formed in the interlayer dielectric layer 370 .

[0155] The gate opening 381 is used to provide a space for forming a metal gate layer.

[0156] In this embodiment, one or both of a dry etching process and a wet etching process are used to remove the polysilicon gate layer 330 of the second device region 100L.

[0157] In this embodiment, during the process of removing the polysilicon gate layer 330 of the second device region 100L, the top polysilicon gate layer 332 is removed to form a second groove 382 exposing the bottom polysilicon gate 331 .

[0158] The second groove 382 is used to provide a space for forming a metal gate layer in the first device region 100M. Accordingly, the metal gate layer is formed in the second groove 382 in the subsequent process.

[0159] After a metal gate layer is subsequently formed in the second groove 382 , the gate oxide layer 210 , the high-k gate dielectric layer 310 , the metal barrier layer 320 , the remaining polysilicon gate layer 330 and the metal gate layer in the first device region 100M are used to constitute a first gate structure.

[0160] In the first device region 100M, by replacing part of the polysilicon gate layer 330 with a metal gate layer, current can flow through the metal gate layer when the first device is operating, thereby reducing the gate resistance of the first device. Furthermore, when a gate contact plug is subsequently formed on top of the first gate structure in the first device region 100M, the gate contact plug can be electrically connected to the metal gate layer, thereby reducing contact resistance.

[0161] In this embodiment, the gate opening 381 and the second groove 382 are formed in the same step, thereby simplifying the process steps, saving masks, and reducing process costs.

[0162] In which, the total thickness of the top polysilicon gate layer 332 and the bottom polysilicon gate layer 331 is greater than the thickness of the polysilicon gate layer 330 of the second device area 100L. Therefore, even if the polysilicon gate layer 330 of the second device area 100L and the top polysilicon gate layer 332 are removed in the same step, the bottom polysilicon gate layer 331 can still be retained.

[0163] refer to Figure 14 , in the gate opening 381 (such as Figure 13A metal gate layer 380 is formed in the embodiment shown in FIG.

[0164] The high-k gate dielectric layer 310, metal barrier layer 320, and metal gate layer 380 in the second device region 100L form a second gate structure, and the second gate structure is a metal gate structure. Because the operating voltage of the second device is relatively low, the use of a metal gate structure is beneficial for improving short channel effects as device critical dimensions continue to shrink.

[0165] The metal gate layer 380 is used to electrically lead out the second gate structure.

[0166] Specifically, the step of forming a metal gate layer 380 in the gate opening 381 includes: filling the gate opening 381 with metal gate material, wherein the metal gate material also covers the interlayer dielectric layer 370; performing a planarization process (for example, a chemical mechanical polishing process) on the metal gate material, removing the metal gate material above the top of the interlayer dielectric layer 370, and retaining the remaining metal gate material in the gate opening 381 as the metal gate layer 380.

[0167] The material of the metal gate layer 380 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the metal gate layer 380 is Al.

[0168] In this embodiment, in the step of forming the metal gate layer 380 in the gate opening 381 , the metal gate layer 380 is also formed in the second groove 382 .

[0169] In this embodiment, the gate oxide layer 210 , the high-k gate dielectric layer 310 , the metal barrier layer 320 , the polysilicon gate layer 330 and the metal gate layer 380 in the first device region 100M are used to form a first gate structure.

[0170] It should be noted that, in the second device region 100L, when a gate oxide layer is formed between the high-k gate dielectric layer 310 and the substrate 100 , the metal gate structure further includes the gate oxide layer.

[0171] It should also be noted that before filling the gate opening 381 with metal gate material, a work function layer is formed in the gate opening 381 , which will not be described in detail in this embodiment.

[0172] In addition, in other embodiments, according to process requirements, in the process of removing the polysilicon gate layer of the second device area, a mask can also be used to define the etching area of ​​the polysilicon gate layer to block the first device area, thereby retaining the top polysilicon gate layer.

[0173] Figures 15 to 17 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

[0174] The similarities between the embodiment of the present invention and the aforementioned embodiment are not repeated here. The difference between the embodiment of the present invention and the aforementioned embodiment lies in that the method of forming the polysilicon gate layer 440 is different.

[0175] refer to Figure 15 , a polysilicon material layer 410 is formed on the substrate 400 in the first device region 400M and the second device region 400L.

[0176] The polysilicon material layer 410 is used to prepare for forming a polysilicon gate layer.

[0177] In this embodiment, the thickness of the polysilicon material layer 410 is equal to the target thickness of the polysilicon gate layer subsequently formed in the second device region 400L.

[0178] refer to Figure 16 , performing a first etching on the polysilicon material layer 410 to form a separate initial polysilicon gate layer 420 .

[0179] By first forming a discrete initial polysilicon gate layer 420 , preparation is made for subsequently etching the initial polysilicon gate layer 420 of the first device region 400M to form a finger-shaped polysilicon gate layer.

[0180] In this embodiment, before etching the polysilicon material layer 410 , the process further includes forming a gate mask layer 430 on the polysilicon material layer 410 . Accordingly, the polysilicon material layer 410 is first etched using the gate mask layer 430 as a mask to form an initial polysilicon gate layer 420 .

[0181] In this embodiment, an anisotropic dry etching process is used to perform a first etching on the polysilicon material layer 410 , thereby improving the morphology quality and dimensional accuracy of the initial polysilicon gate layer 420 .

[0182] It should be noted that after the first etching of the polysilicon material layer 410, the metal barrier material layer, the high-k gate dielectric material layer and the gate oxide layer are further etched, and the remaining metal barrier material layer at the bottom of the initial polysilicon gate layer 420 is retained as a metal barrier layer, and the remaining high-k gate dielectric material layer at the bottom of the initial polysilicon gate layer 420 is retained as a high-k gate dielectric layer.

[0183] refer to Figure 17, the initial polysilicon gate layer 410 in the first device area 400M is subjected to a second etching to form a first groove 443 located in a partial thickness of the initial polysilicon gate layer 410. After the second etching, the remaining initial polysilicon gate layer 410 serves as the polysilicon gate layer 440.

[0184] In this embodiment, after the second etching, the remaining initial polysilicon gate layer 410 includes a bottom polysilicon gate layer 441 and a top polysilicon gate layer 442 protruding from the top surface of the bottom polysilicon gate layer 441, the top surface of the bottom polysilicon gate layer 441 is flush with the bottom surface of the first groove 443, and the adjacent top polysilicon gate layer 442 and bottom polysilicon gate layer 441 form a first groove 443.

[0185] In this embodiment, the gate mask layer 430 is first etched, and then the initial polysilicon gate layer 410 in the first device region 400M is subjected to a second etching using the etched gate mask layer 430 as a mask.

[0186] In this embodiment, an anisotropic dry etching process is used to perform a second etching on the polysilicon material layer 410 , thereby precisely controlling the etching amount of the initial polysilicon gate layer 410 in the first device region 400M and the sidewall morphology quality of the first groove 443 .

[0187] In this embodiment, during the second etching of the initial polysilicon gate layer 410 in the first device region 400M, a mask is used to define the positions to be etched in the initial polysilicon gate layer 410. Accordingly, the initial polysilicon gate layer 420 in the second device region 400L is protected.

[0188] It should be noted that, as an example, after performing a first etching on the polysilicon material layer 410 to form a discrete initial polysilicon gate layer 420, and before performing a second etching, the formation method may further include: forming sidewalls (not shown) on the sidewalls of the initial polysilicon gate layer 420. By forming the sidewalls first, the sidewalls protect the high-k gate dielectric layer, the metal barrier layer, and the gate oxide layer, thereby reducing the probability of contamination of the high-k gate dielectric layer or the metal barrier layer due to prolonged exposure, and reducing the probability of adverse effects on the quality of the gate oxide layer.

[0189] In some other embodiments, after the second etching is performed, sidewall spacers may be formed on the sidewalls of the polysilicon gate layer. Correspondingly, the sidewall spacers may also be formed on the sidewalls of the first groove.

[0190] It should also be noted that, in this embodiment, when the polysilicon gate layer 440 of the second device region 400L is subsequently removed, the top polysilicon gate layer 442 in the first device region 400M is retained.

[0191] Among them, since the total thickness of the top polysilicon gate layer and the bottom polysilicon gate layer is equal to the thickness of the polysilicon gate layer of the second device area, if the top polysilicon gate layer 442 is also removed in the process of removing the polysilicon gate layer 440 of the second device area 400L, the probability of the bottom polysilicon gate layer 441 being etched through is high. Therefore, in this embodiment, the top polysilicon gate layer 442 in the first device area 400M is retained.

[0192] For the specific description of the forming method described in this embodiment, reference can be made to the corresponding description of the aforementioned embodiment, which will not be repeated here.

[0193] Accordingly, the present invention also provides a semiconductor structure. Figure 18 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0194] The semiconductor structure includes: a substrate 500, including a first device area 500M for forming a first device and a second device area 500L for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device; a first gate layer 780, located on the substrate 500 in the second device area 500L, the first gate layer 780 being a metal gate material; a finger-shaped second gate layer 730, located on the substrate 500 in the first device area 500M, the second gate layer 730 including a bottom polysilicon gate layer 731 and a plurality of top gate layers 732 protruding from the bottom polysilicon gate layer 731; an interlayer dielectric layer 770, located on the substrate 500 on the side of the first gate layer 780 and the second gate layer 730, the interlayer dielectric layer 770 covering the sidewalls of the first gate layer 780 and the second gate layer 730, and covering the bottom polysilicon gate layer 731 exposed by the top gate layer 732.

[0195] In the semiconductor structure provided by an embodiment of the present invention, the first device region 500M is used to form a first device, and the second device region 500L is used to form a second device. The channel length of the first device is greater than the channel length of the second device, and a finger-shaped second gate layer 730 is formed on the substrate 500 of the first device region 500M. The second gate layer 730 includes a bottom polysilicon gate layer 731 and multiple top gate layers 732 protruding from the bottom polysilicon gate layer 731. The first gate layer 780 is a metal gate material, and the process of forming the first gate layer 780 includes a planarization step. In the embodiment of the present invention, a discrete top gate layer 732 is provided on the bottom polysilicon gate layer 731, so that the line width of the top gate layer 732 and the spacing between adjacent top gate layers 732 are both small, thereby improving the top surface dishing problem of the second gate layer 730 generated in the process of forming the first gate layer 780, which is beneficial to improving the structural integrity of the second gate layer 730, and thus improving the performance of the semiconductor structure.

[0196] In this embodiment, the semiconductor structure is a planar field effect transistor as an example, and the substrate 500 is a planar substrate. In other embodiments, the semiconductor structure is a fin field effect transistor (FinFET), and accordingly, the substrate includes a substrate and a fin protruding from the substrate.

[0197] In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the substrate may be a substrate of other materials. For example, the substrate may be made of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or may be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0198] In this embodiment, the substrate is a P-type substrate (Psub), that is, the substrate is doped with P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0199] In this embodiment, the substrate 500 includes a first device region 500M for forming a first device and a second device region 500L for forming a second device. The channel length of the first device is greater than the channel length of the second device.

[0200] In this embodiment, the first device includes one or both of a medium-voltage device and a high-voltage device, and the second device is a low-voltage device. The operating voltages of the low-voltage, medium-voltage, and high-voltage devices increase in sequence. As an example, the operating voltage of the low-voltage device is less than 1V, the operating voltage of the medium-voltage device is between 1V and 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0201] The first device may be an NMOS device or a PMOS device. Similarly, the second device may also be an NMOS device or a PMOS device.

[0202] It should be noted that, when the first device includes a medium-voltage device and a high-voltage device, the first device region 500M for forming the medium-voltage device and the first device region 500M for forming the high-voltage device are isolated.

[0203] As an example, the first device region 500M includes a first sub-region 500MN and a second sub-region 500MP, and the first sub-region 500MN and the second sub-region 500MP are used to form first devices of different channel conductivity types. For example, the first device formed in the first sub-region 500MN is an NMOS device, and the first device formed in the second sub-region 500MP is a PMOS device.

[0204] In this embodiment, taking the example of the first device area 500M being used to form a medium-voltage device and the second device area 500L being used to form a low-voltage device, a deep N-type well (DNW) area (not shown) is also formed in the substrate 500, a first well area (not marked) is formed in the deep N-type well area of ​​the first device area 500M, and a second well area (not marked) is formed in the deep N-type well area of ​​the second device area 500L.

[0205] The deep N-type well region is used to isolate the first well region from the P-type substrate, and is also used to isolate the second well region from the P-type substrate, thereby reducing substrate coupling noise.

[0206] The dopant ion type in the first well region is opposite to the channel conductivity type of the first device formed above it. When the first device is an NMOS device, the dopant ions in the first well region are P-type ions; when the first device is a PMOS device, the dopant ions in the first well region are N-type ions. Similarly, the dopant ion type in the second well region is opposite to the channel conductivity type of the second device formed above it.

[0207] In other embodiments, when the first device region is used to form a high-voltage device, a high-voltage well region is formed in the substrate, and accordingly, no deep N-type well region is formed in the substrate. Similarly, the dopant ion type in the high-voltage well region is opposite to the channel conductivity type of the first device formed thereover.

[0208] In this embodiment, the semiconductor structure further includes an isolation structure 501 located in the substrate 500. Specifically, the isolation structure 501 is located in the substrate 500 at the junction of the first device region 500M and the second device region 500L. The first device region 500M includes a first sub-region 500MN and a second sub-region 500MP. Therefore, the isolation structure 501 is also located in the substrate 500 at the junction of the first sub-region 500MN and the second sub-region 500MP.

[0209] The isolation structure 501 is used to isolate adjacent devices. In this embodiment, the isolation structure 501 is a shallow trench isolation, so that the isolation structure 501 has a good isolation effect. In this embodiment, the isolation structure 501 is made of an insulating material, and the insulating material includes silicon oxide.

[0210] The first gate layer 780 of the second device region 500L is made of a metal gate material and is used as a part of the second gate structure to electrically lead out the second gate structure. Accordingly, the second gate structure is a metal gate structure.

[0211] Since the operating voltage of the second device is relatively low, as the critical dimensions of the device continue to shrink, the use of a metal gate structure is beneficial to improving the short channel effect.

[0212] The material of the first gate layer 780 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the first gate layer 780 is Al.

[0213] It should be noted that the semiconductor structure further includes a work function layer covering the sidewalls and bottom of the first gate layer 780 , which will not be described in detail in this embodiment.

[0214] In this embodiment, the semiconductor structure further includes: a stacked structure (not shown) located between the first gate layer 780 and the substrate 500, and the stacked structure includes a high-k gate dielectric layer 710 and a metal barrier layer 720 stacked in sequence from bottom to top.

[0215] In the second device region 500L, the high-k gate dielectric layer 710 , the metal barrier layer 720 and the first gate layer 780 are used to form a second gate structure.

[0216] The high-k gate dielectric layer 710 serves as the gate dielectric layer of the second device. The material of the high-k gate dielectric layer 710 is a high-k dielectric material. Specifically, the material of the high-k gate dielectric layer 710 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. As an example, the material of the high-k gate dielectric layer 710 is HfO2.

[0217] The metal barrier layer 720 is used to isolate the high-k gate dielectric layer 710 from the first gate layer 780 to protect the high-k gate dielectric layer 710. Furthermore, the metal barrier layer 720 is used to prevent easily diffusible ions (e.g., aluminum ions) in the first gate layer 780 from diffusing into the high-k gate dielectric layer 710. Specifically, the material of the metal barrier layer 720 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 720 is titanium nitride.

[0218] The second gate layer 730 is used as a device gate structure of the first device, thereby controlling the opening or closing of the channel of the first device. Specifically, the second gate layer 730 serves as a part of the first gate structure.

[0219] In this embodiment, the second gate layer 730 includes a bottom polysilicon gate layer 731 and a plurality of top gate layers 732 protruding from the bottom polysilicon gate layer 731 .

[0220] Therefore, the material of the bottom polysilicon gate layer 731 is polysilicon.

[0221] In this embodiment, the total thickness of the top gate layer 732 and the bottom polysilicon gate layer 731 is greater than the thickness of the first gate layer 780 .

[0222] In this embodiment, the material of the top gate layer 732 is the same as the material of the first gate 780 , that is, the material of the top gate layer 732 is also a metal gate material.

[0223] By making the top gate layer 732 also a metal gate material, current can flow through the top gate layer 732 of the metal gate material when the first device is operating, thereby reducing the gate resistance of the first device. Furthermore, when a gate contact plug is subsequently formed on top of the first gate structure in the first device region 500M, the gate contact plug can be electrically connected to the top gate layer 732 of the metal gate material, thereby reducing contact resistance.

[0224] In which, during the formation of the semiconductor structure, a top polysilicon gate layer is formed at the position of the top gate layer 732, and the first gate 780 is formed by a high-K first process in a gate last process, that is, before the top gate layer 732 is formed, the top polysilicon gate layer is formed at the position of the top gate layer 732, and before the first gate 780 is formed, a polysilicon gate layer is formed at the position of the first gate 780. Therefore, in the process of removing the polysilicon gate layer of the second device area 500L, the top polysilicon gate layer of the first device area 500M can be removed at the same time, and in the process of forming the first gate 780 at the position of the polysilicon gate layer of the second device area 500L, the top gate layer 732 is formed at the position of the top polysilicon gate layer.

[0225] It should be noted that the total thickness of the top gate layer 732 and the bottom polysilicon gate layer 731 is greater than the thickness of the first gate layer 780. Therefore, even if the polysilicon gate layer of the second device area 500L and the top polysilicon gate layer are removed in the same step, the bottom polysilicon gate layer 731 can still be retained.

[0226] In other embodiments, the material of the top gate layer may also be the same as that of the bottom polysilicon gate layer. Specifically, the top gate layer and the bottom polysilicon gate layer are an integrated structure.

[0227] It should be noted that the distance H between the top of the top gate layer 732 and the top of the bottom polysilicon gate layer 731 should not be too small or too large. If the distance H between the top of the top gate layer 732 and the top of the bottom polysilicon gate layer 731 is too small, the top gate layer 732 may be completely removed during the planarization process to form the first gate layer 780, resulting in over-polishing of the bottom polysilicon gate layer 731 and an increased probability of top surface depression in the second gate layer 730 of the first device region 500M. If the distance H between the top of the top gate layer 732 and the top of the bottom polysilicon gate layer 731 is too large, the thickness of the bottom polysilicon gate layer 731 may be too small. Considering the influence of etching uniformity and loading effect, the bottom polysilicon gate layer 731 at the bottom of the first groove may be more likely to be etched through during the formation of the first groove, thereby affecting the performance of the second gate layer 730 of the first device region 500M. Therefore, in this embodiment, the distance H from the top of the top gate layer 732 to the top of the bottom polysilicon gate layer 731 is to For example, the distance H from the top of the top gate layer 732 to the top of the bottom polysilicon gate layer 731 is or

[0228] In this embodiment, the finger-shaped second gate layer 730 further includes an edge polysilicon gate layer 735 protruding from the bottom polysilicon gate layer 731 and surrounding the top gate layer 732 .

[0229] Specifically, the edge polysilicon gate layer 735 includes relative outer side walls 735b and inner side walls 735a, the inner side walls 735a are in contact with the side walls of the outermost top gate layer 732, the outer side walls 735b are flush with the side walls of the bottom polysilicon gate layer 731, and the top of the edge polysilicon gate layer 735 is lower than the top of the top gate layer 732.

[0230] The outermost top gate layer 732 refers to the top gate layer 732 closest to the sidewall of the bottom polysilicon gate layer 731 .

[0231] In this embodiment, the total thickness of the edge polysilicon gate layer 735 and the bottom polysilicon gate layer 731 in the first device region 500M is equal to the thickness of the polysilicon gate layer 780 in the second device region 500L.

[0232] During the formation of the semiconductor structure, the polysilicon material layer is etched and grooves are formed in the polysilicon material layer, so that the final top gate layer 732 can protrude from the top surface of the bottom polysilicon gate layer 731. Therefore, by making the second gate layer 730 also include an edge polysilicon gate layer 735, the process window of the lithography process can be increased during the formation of the groove.

[0233] In some other embodiments, when the total thickness of the top gate layer and the bottom polysilicon gate layer is greater than the thickness of the first gate layer, the edge polysilicon gate layer may not be included.

[0234] In other embodiments, the second gate layer does not include the edge polysilicon gate layer, and the total thickness of the top gate layer and the bottom polysilicon gate layer may also be equal to the thickness of the first gate.

[0235] In this embodiment, the semiconductor structure further includes a gate oxide layer 610 located between the second gate layer 730 and the substrate 500 .

[0236] The gate oxide layer 610 serves as a gate dielectric layer of the first device, and is used to electrically isolate the second gate layer 730 from the channel of the first device.

[0237] In this embodiment, the gate oxide layer 610 is made of silicon oxide.

[0238] It should be noted that, depending on process requirements, a gate oxide layer (not shown) may also be formed between the high-k gate dielectric layer 710 and the substrate 500 in the second device region 500L. The gate oxide layer in the second device region 500L is thinner than the gate oxide layer 610 in the first device region 500M. Accordingly, the gate oxide layer in the second device region 500L also serves as part of the metal gate structure, and the gate oxide layer in the second device region 500L and the high-k gate dielectric layer 610 together serve as the gate dielectric layer of the second device.

[0239] In this embodiment, during the formation of the semiconductor structure, a metal gate structure is formed using a high-K first process in a gate last process. Therefore, the stacked high-k gate dielectric layer 710 and the metal barrier layer 720 are also located between the second gate layer 730 and the substrate 500.

[0240] Specifically, in the first device region 500M, the stacked high-k gate dielectric layer 710 and the metal barrier layer 720 are located between the second gate layer 730 and the gate oxide layer 610 .

[0241] In this embodiment, the gate oxide layer 610 , the high-k gate dielectric layer 710 , the metal barrier layer 720 and the second gate layer 730 in the first device region 500M are used to form a first gate structure.

[0242] In this embodiment, the semiconductor structure further includes: source and drain doped regions 750, respectively located in the substrate 500 on both sides of the second gate layer 730 and in the substrate 500 on both sides of the first gate layer 780; and a source and drain silicide layer 760, located on the surface of the source and drain doped regions 750.

[0243] The conductivity type of the doped ions in the source / drain doping regions 750 is the same as the conductivity type of the corresponding device. When the device is an NMOS device, the doped ions in the source / drain doping regions 750 are N-type ions, including P ions, As ions, or Sb ions. When the device is a PMOS device, the doped ions in the source / drain doping regions 750 are P-type ions, including B ions, Ga ions, or In ions.

[0244] Subsequently, source / drain contact plugs are formed on top of the source / drain doped regions 750, and the contact resistance between the source / drain doped regions 750 and the source / drain contact plugs is reduced through the source / drain silicide layer 760. In this embodiment, the material of the source / drain silicide layer 760 can be nickel-silicon compound, cobalt-silicon compound, or titanium-silicon compound.

[0245] In this embodiment, the bottom polysilicon gate layer 731 is doped with conductive ions 751 .

[0246] By doping the bottom polysilicon gate layer 731 with conductive ions 751, the resistance of the bottom polysilicon gate layer 731 of the first device region 500M is reduced, thereby reducing the gate resistance of the first device and reducing the contact resistance between the bottom polysilicon gate layer 731 and the gate silicide layer. In addition, the device threshold voltage can be adjusted by adjusting the concentration of the conductive ions 751, which is correspondingly beneficial to improving the performance of the semiconductor structure.

[0247] In this embodiment, the conductive ions 751 may be N-type ions or P-type ions. Specifically, the conductive ions 751 include B ions, Ga ions, In ions, P ions, As ions, or Sb ions.

[0248] A high-k gate dielectric layer 710 and a metal barrier layer 720 are formed below the bottom polysilicon gate layer 731 . Therefore, the conductivity type of the conductive ions 751 may be the same as or different from the channel conductivity type of the corresponding device.

[0249] In this embodiment, the conductivity type of the conductive ions 751 in the bottom polysilicon gate layer 731 is the same as the ion conductivity type in the source-drain doping region 750 on both sides of the bottom polysilicon gate layer 731, so that the conductive ions 751 can be doped into the bottom polysilicon gate layer 731 by utilizing the process of forming the source-drain doping region 750.

[0250] In this embodiment, the semiconductor structure further includes a gate silicide layer 761 located on the surface of the bottom polysilicon gate layer 731 exposed by the top gate layer 732 .

[0251] The gate silicide layer 761 allows current to flow through the gate silicide layer 761 when the first device is operating, thereby reducing gate resistance.

[0252] In this embodiment, the material of the gate silicide layer 761 can be nickel silicon compound, cobalt silicon compound or titanium silicon compound.

[0253] The interlayer dielectric layer 770 is used to isolate adjacent devices. The material of the interlayer dielectric layer 770 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. As an example, the material of the interlayer dielectric layer 770 is silicon oxide.

[0254] In this embodiment, the interlayer dielectric layer 770 covers the sidewalls of the first gate layer 780 and the second gate layer 730, and exposes the top of the first gate layer 780. Specifically, the interlayer dielectric layer 770 covers the top of the bottom polysilicon gate layer 731 exposed by the top gate layer 732. In other words, the interlayer dielectric layer 770 also fills the space between adjacent top gate layers 732.

[0255] It should be noted that the semiconductor structure further includes a gate mask layer 740 located on top of the edge polysilicon gate layer 735. Specifically, the interlayer dielectric layer 770 also exposes the top of the gate mask layer 740.

[0256] The gate mask layer 740 serves as an etching mask when forming the second gate layer 730. During the process of forming the interlayer dielectric layer 770, since the top of the edge polysilicon gate layer 735 is lower than the top of the top gate layer 732, the gate mask layer 740 on the top of the edge polysilicon gate layer 735 is retained.

[0257] In other embodiments, the semiconductor structure may not include the gate mask layer.

[0258] The semiconductor structure can be formed by the formation method described in the first embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the first embodiment, which will not be repeated here.

[0259] Figure 19 A schematic structural diagram of another embodiment of the semiconductor structure of the present invention.

[0260] The similarities between the embodiment of the present invention and the aforementioned embodiment are not repeated here. The differences between the embodiment of the present invention and the aforementioned embodiment are as follows:

[0261] The second gate layer 840 only includes the bottom polysilicon gate layer 841 and the top gate layer 842 , and the total thickness of the top gate layer 842 and the bottom polysilicon gate layer 841 is equal to the thickness of the first gate layer 840 .

[0262] In this embodiment, the material of the top gate layer 842 is the same as that of the bottom polysilicon gate layer 841 .

[0263] Specifically, the material of the top gate layer 842 is an integrated structure with the bottom polysilicon gate layer 841 , so that the bottom polysilicon gate layer 841 and the top gate layer 842 can be formed by etching the polysilicon material layer.

[0264] The semiconductor structure can be formed by the formation method described in the second embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the second embodiment, which will not be repeated in this embodiment.

[0265] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a first device region for forming a first device and a second device region for forming a second device, wherein a channel length of the first device is greater than a channel length of the second device; an isolation structure located in the substrate; a first gate layer, located on the substrate of the second device region, wherein the first gate layer is made of a metal gate material; a finger-shaped second gate layer, located on the substrate of the first device region and between the isolation structures, the second gate layer comprising a bottom polysilicon gate layer and a plurality of top gate layers protruding from the bottom polysilicon gate layer; An interlayer dielectric layer is located on the substrate at the sides of the first and second gate layers, and covers the sidewalls of the first and second gate layers and the top of the bottom polysilicon gate layer exposed by the top gate layer.

2. The semiconductor structure according to claim 1, wherein The total thickness of the top gate layer and the bottom polysilicon gate layer is equal to the thickness of the first gate layer.

3. The semiconductor structure according to claim 1, wherein: The total thickness of the top gate layer and the bottom polysilicon gate layer is greater than the thickness of the first gate layer.

4. The semiconductor structure according to claim 3, wherein: The finger-shaped second gate layer further includes an edge polysilicon gate layer protruding from the bottom polysilicon gate layer and surrounding the top gate layer; The edge polysilicon gate layer includes relative outer side walls and inner side walls, the inner side walls are in contact with the side walls of the outermost top gate layer, the outer side walls are flush with the side walls of the bottom polysilicon gate layer, and the top of the edge polysilicon gate layer is lower than the top of the top gate layer.

5. The semiconductor structure according to any one of claims 1 to 3, wherein: The material of the top gate layer is the same as that of the bottom polysilicon gate layer.

6. The semiconductor structure according to claim 3, wherein: The material of the top gate layer is the same as that of the first gate layer.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a gate silicide layer located on a top surface of the bottom polysilicon gate layer exposed by the top gate layer.

8. The semiconductor structure according to claim 1, wherein: The bottom polysilicon gate layer is doped with conductive ions.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a stacked structure located between the first gate layer and the substrate, wherein the stacked structure includes a high-k gate dielectric layer and a metal barrier layer stacked in sequence from bottom to top.

10. The semiconductor structure according to claim 1, wherein: The distance from the top of the top gate layer to the top of the bottom polysilicon gate layer is to 11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a first device region for forming a first device and a second device region for forming a second device, wherein a channel length of the first device is greater than a channel length of the second device, and an isolation structure is further formed in the substrate; forming a polysilicon gate layer on the substrate of the first device region and the second device region, wherein in the first device region, the polysilicon gate layer is located between the isolation structures and has a finger shape, including a bottom polysilicon gate layer and a plurality of top polysilicon gate layers protruding from the bottom polysilicon gate layer; forming an interlayer dielectric layer on the substrate at the side of the polysilicon gate layer, wherein the interlayer dielectric layer also covers the bottom polysilicon gate layer exposed by the top polysilicon gate layer and exposes the top of the polysilicon gate layer in the second device region; removing the polysilicon gate layer of the second device region and forming a gate opening in the interlayer dielectric layer; A metal gate layer is formed in the gate opening.

12. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming the polysilicon gate layer includes: forming a polysilicon material layer on the substrate of the first device region and the second device region; The polysilicon material layer is etched to form the polysilicon gate layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming the polysilicon material layer includes: forming an initial polysilicon material layer on the substrate of the first device region and the second device region; etching a partial thickness of the initial polysilicon material layer in the second device region and a partial area of ​​the first device region to form a bottom residual layer covering the substrate and a protruding portion protruding from the bottom residual layer of the first device region, wherein the bottom residual layer and the protruding portion serve as the polysilicon material layer; The step of etching the polysilicon material layer to form the polysilicon gate layer includes: etching the protrusion and a bottom residual layer with a partial thickness at the bottom of the protrusion, forming a first groove in the protrusion and the bottom residual layer at the bottom of the protrusion, and simultaneously etching the bottom residual layer with the entire thickness of the side of the protrusion, and the protrusion and bottom residual layer remaining after etching are used as the polysilicon gate layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: Before etching the polysilicon material layer, the forming method further comprises: forming a gate mask layer on the polysilicon material layer, wherein, in the first device region, the gate mask layer covers the sidewalls and a portion of the top of the protrusion, and further extends to cover a portion of the bottom residual layer on the side of the protrusion; In the step of etching the polysilicon material layer, the gate mask layer is used as an etching mask.

15. The method for forming a semiconductor structure according to claim 13, wherein: The polysilicon gate layer of the second device region has a target thickness, the thickness of the initial polysilicon material layer is greater than the target thickness, and the difference between the thickness of the initial polysilicon material layer and the target thickness is to 16. The method for forming a semiconductor structure according to claim 12, wherein: The step of etching the polysilicon material layer includes: performing a first etching on the polysilicon material layer to form a discrete initial polysilicon gate layer; The initial polysilicon gate layer in the first device region is subjected to a second etching to form a first groove located in a partial thickness of the initial polysilicon gate layer. After the second etching, the remaining initial polysilicon gate layer serves as a polysilicon gate layer.

17. The method for forming a semiconductor structure according to claim 12, wherein: Before forming the polysilicon material layer, the forming method further comprises: forming a high-k gate dielectric material layer and a metal barrier material layer stacked sequentially from bottom to top on the substrate of the second device region; After etching the polysilicon material layer, the forming method further comprises: etching the high-k gate dielectric material layer and the metal barrier material layer to form a stacked high-k gate dielectric layer and metal barrier layer.

18. The method for forming a semiconductor structure according to claim 11, wherein: After forming the polysilicon gate layer and before forming the interlayer dielectric layer, the forming method further comprises: forming a gate silicide layer on the top surface of the bottom polysilicon gate layer exposed by the top polysilicon gate layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: In the step of forming the polysilicon gate layer, a gate mask layer is formed on the top of the polysilicon gate layer in the first device region and the top of the polysilicon gate layer in the second device region; The gate silicide layer is formed by using the gate mask layer as a protection layer.

20. The method for forming a semiconductor structure according to claim 11, wherein: After forming the polysilicon gate layer and before forming the interlayer dielectric layer, the forming method further comprises: doping conductive ions into the bottom polysilicon gate layer exposed from the top polysilicon gate layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: After forming the polysilicon gate layer and before forming the interlayer dielectric layer, the formation method further includes: forming source-drain doping regions in the substrate on both sides of the polysilicon gate layer, and in the process of forming the source-drain doping regions, doping the conductive ions into the bottom polysilicon gate layer exposed by the top polysilicon gate layer.

22. The method for forming a semiconductor structure according to claim 21, wherein: After forming the source / drain doped regions and before forming the interlayer dielectric layer, the formation method further includes: forming a source / drain silicide layer on the surface of the source / drain doped regions, and in the process of forming the source / drain silicide layer, forming a gate silicide layer on the surface of the bottom polysilicon gate layer exposed by the top polysilicon gate layer.

23. The method for forming a semiconductor structure according to claim 13, wherein: In the process of removing the polysilicon gate layer of the second device region, the top polysilicon gate layer is also removed to form a second groove exposing the bottom polysilicon gate; In the step of forming a metal gate layer in the gate opening, the metal gate layer is also formed in the second groove.

24. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a metal gate layer in the gate opening includes: filling the gate opening with a metal gate material, wherein the metal gate material also covers the interlayer dielectric layer; The metal gate material is planarized to remove the metal gate material above the top of the interlayer dielectric layer, and the remaining metal gate material in the gate opening is retained as a metal gate layer.

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