A back-illuminated silicon-based single-photon avalanche diode structure and photodetector

Abstract

The invention discloses a back-illuminated silicon-based single-photon avalanche diode structure and a photodetector, wherein the diode structure comprises: a P-type epitaxial layer and a wiring layer; a plurality of isolation structures, each of which comprises a shallow trench isolation layer, an isolation N well and a deep trench isolation layer stacked in the P-type epitaxial layer; an electrode protection ring, which is arranged in the wiring layer and close to the shallow trench isolation layer; a plurality of light source sensing regions, which are spaced and distributed between adjacent isolation structures; each light source sensing region comprises: an active P+ layer, an active region P well, a deep N well and an N-type buried layer stacked; a P well protection ring, which is arranged on both sides of the active P+ layer and the active region P well; an anode electrode, which is arranged in the wiring layer below the active P+ layer; a reflective metal plate, which is arranged in the wiring layer opposite to the active P+ layer; a shared cathode, which comprises an electrode N well, which is arranged in the P-type epitaxial layer and connected to the deep N well; and a cathode electrode, which is arranged in the wiring layer close to the electrode N well. The invention can improve detection efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of microelectronic optoelectronic devices, and in particular relates to a back-illuminated silicon-based single-photon avalanche diode structure and a photodetector. Background Art

[0002] Avalanche diodes (SPADs) have attracted increasing attention due to their high sensitivity at the single-photon level and high resolution of more than 100ps. Recently, SPADs made using complementary metal oxide semiconductor (CMOS) technology have been used in various fields, such as fluorescence lifetime imaging microscopy, time-gated Raman spectroscopy, radiation temperature measurement, as well as photodetectors and ranging radars. In these applications, high sensitivity and high resolution are very necessary, so SPADs with high fill rate and high detection efficiency have received widespread attention. Existing SPADs use a certain pixel array to achieve the detection effect of SPADs.

[0003] However, due to the limitation of device performance for large pixel arrays, existing SPADs have poor detection efficiency and a high dark count rate. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a back-illuminated silicon-based single-photon avalanche diode structure and a photodetector. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a back-illuminated silicon-based single-photon avalanche diode structure, comprising:

[0006] A plurality of isolation structures, each of which comprises: a shallow trench isolation layer, an isolation N well and a deep trench isolation layer stacked from bottom to top in the P-type epitaxial layer; an electrode guard ring, which is arranged in the wiring layer and close to the shallow trench isolation layer;

[0007] A plurality of light source sensing regions are spaced and distributed between adjacent isolation structures; wherein each of the light source sensing regions comprises: an active P+ layer, an active region P well, a deep N well and an N-type buried layer stacked from bottom to top; a P well protection ring is arranged on both sides of the active P+ layer and the active region P well, and is connected to the shallow trench isolation layer and the isolated N well; the deep N well is also arranged on the P well protection ring, on part of the isolated N well, and wraps the outermost shallow trench isolation layer and the isolated N well; an anode electrode is arranged in the wiring layer below the active P+ layer; a reflective metal plate is arranged in the wiring layer opposite to the active P+ layer;

[0008] The shared cathode includes: an electrode N-well, which is arranged in the P-type epitaxial layer and connected to the deep N-well; and a cathode electrode, which is arranged in the wiring layer close to the electrode N-well.

[0009] In one embodiment of the present invention, the deep N-well is a retrograde doped well.

[0010] In one embodiment of the present invention, the doping concentration of the active region P-well is higher than the doping concentration of the P-well guard ring.

[0011] In one embodiment of the present invention, the junction depth of the active region P-well is smaller than the junction depth of the P-well guard ring.

[0012] In one embodiment of the present invention, the width of the active P+ layer is equal to the width of the reflective metal plate.

[0013] In one embodiment of the present invention, a plurality of light source sensing areas are distributed in an array, and the shared cathode is disposed in an area surrounded by the top corners of each of four adjacent light source sensing areas.

[0014] In one embodiment of the present invention, each of the light source sensing areas is a rounded structure.

[0015] In a second aspect, the present invention provides a photodetector comprising a plurality of back-illuminated silicon-based single-photon avalanche diode structures as described above distributed in an array.

[0016] Beneficial effects of the present invention:

[0017] The back-illuminated silicon-based single-photon avalanche diode structure provided by the present invention is a new structure based on a compatible high-voltage CMOS process. The structure can ensure that the diode has a large filling rate and has a high detection efficiency in a wide spectral response range, thereby improving the detection efficiency and having a low dark count rate. Specifically: an isolated N-well in an isolation structure forms a reverse-biased PN junction structure with a P-well protection ring in a light source sensing area to avoid crosstalk between adjacent light source sensing areas caused by carrier drift or tunneling; an electrode protection ring in the isolation structure introduces the electric field peak at the interface of a shallow trench isolation layer into the interior of the shallow trench isolation layer, thereby effectively reducing dark counts and after-pulses caused by trapped charges on the surface of the shallow trench isolation layer under strong field application; an N-type buried layer is located at a position closest to the surface of the device to provide electrons for a deep N-well to avoid electric field enhancement at a shared cathode position caused by full depletion of a P-type epitaxial layer.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1It is a cross-sectional schematic diagram of a back-illuminated silicon-based single-photon avalanche diode structure provided by an embodiment of the present invention;

[0020] Figure 2 It is a cross-sectional schematic diagram of a shared cathode in a back-illuminated silicon-based single-photon avalanche diode structure provided by an embodiment of the present invention;

[0021] Figure 3 It is a top view of a back-illuminated silicon-based single-photon avalanche diode structure provided by an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of the filling rates of pixel areas at different sizes and spacings provided by an embodiment of the present invention;

[0023] Figure 5 (a)~ Figure 5 (b) is a schematic diagram of the electric field distribution and avalanche ionization rate distribution of the back-illuminated silicon-based single-photon avalanche diode structure provided by an embodiment of the present invention;

[0024] Figure 6 (a)~ Figure 6 (b) is a schematic diagram of the electric field distribution of the electrode guard ring at different positions in the back-illuminated silicon-based single-photon avalanche diode structure provided in an embodiment of the present invention.

[0025] Description of reference numerals:

[0026] 1-P-type epitaxial layer; 2-wiring layer; 3-shallow trench isolation layer; 4-isolation N-well; 5-deep trench isolation layer; 6-electrode guard ring; 7-active P+ layer; 8-active area P-well; 9-deep N-well; 10-N-type buried layer; 11-P-well guard ring; 12-anode electrode; 13-reflective metal plate; 14-electrode N-well; 15-cathode electrode. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0028] In view of the problems of low detection efficiency and high dark counts of traditional SPADs, the embodiments of the present invention take into account both improving the detection probability and reducing the dark count rate, and provide a back-illuminated silicon-based single-photon avalanche diode structure and a photodetector.

[0029] First, see Figure 1 , an embodiment of the present invention provides a back-illuminated silicon-based single-photon avalanche diode structure, comprising:

[0030] P-type epitaxial layer 1 and wiring layer 2;

[0031] A plurality of isolation structures are arranged in the P-type epitaxial layer 1 and the wiring layer 2; wherein each isolation structure comprises a shallow trench isolation layer 3, an isolation N well 4 and a deep trench isolation layer 5 stacked from bottom to top and arranged in the P-type epitaxial layer 1; an electrode protection ring 6 is arranged in the wiring layer 1 and close to the shallow trench isolation layer 3;

[0032] A plurality of light source sensing regions are arranged in the P-type epitaxial layer 1 and the wiring layer 2, and are distributed between adjacent isolation structures at intervals; wherein each light source sensing region includes: an active P+ layer 7, an active region P well 8, a deep N well 9 and an N-type buried layer 10 stacked from bottom to top; a P well protection ring 11, arranged on both sides of the active P+ layer 7 and the active region P well 8, and connected to the shallow trench isolation layer 3 and the isolation N well 4; the deep N well 9 is also arranged on the P well protection ring 8, on part of the isolation N well 4, and wraps the outermost shallow trench isolation layer 3 and the isolation N well 4; an anode electrode 12 is arranged in the wiring layer 1 below the active P+ layer 7; a reflective metal plate 13 is arranged in the wiring layer 2 opposite to the active P+ layer 7;

[0033] The shared cathode is arranged in the P-type epitaxial layer 1 and the wiring layer 2; wherein the shared cathode includes an electrode N well 14 arranged in the P-type epitaxial layer 1 and connected to the deep N well 9; and a cathode electrode 15 arranged in the wiring layer 2 close to the electrode N well 14.

[0034] In the embodiment of the present invention, the P-type epitaxial layer 1 is a ready-made silicon (Si)-based substrate doped with phosphorus, arsenic or antimony, and the doping concentration is about 5×10 15 cm -3 , the ready-made Si-based substrate is thinned to form the thickness required by the embodiment of the present invention as the P-type epitaxial layer 1; the doping concentration of the P-type epitaxial layer 1 in the embodiment of the present invention is low, and the depletion region width is wide, which helps to improve the device detection probability and spectral response range.

[0035] For wiring layer 2, which is a wiring layout layer with electrical characteristics, there are no strict requirements here, and it only needs to meet the wiring layout requirements.

[0036] In each isolation structure of the embodiment of the present invention, the shallow trench isolation layer 3, the isolation N well 4 and the deep trench isolation layer 5 are used to isolate two adjacent light source sensing areas. In order to avoid electrical crosstalk, a PN junction isolation is formed between the two adjacent light source sensing areas. The isolation N well 4 is arranged on the upper surface of the shallow trench isolation layer 3 in the vertical direction, and the deep trench isolation layer 5 is arranged on the upper surface of the isolation N well 4 in the vertical direction. In the process implementation, preferably, the shallow trench isolation layer 3 is a narrow-upper-wide-lower structure, and the width of the upper side of the shallow trench isolation layer 3 is equal to the width of the isolation N well 4; the deep trench isolation layer 5 is a wide-upper-narrow-lower structure, and the width of the lower side of the deep trench isolation layer 5 is less than the width of the isolation N well 4; the width of the deep trench isolation layer 5 is less than the width of the isolation N well 4, so that the deep trench isolation layer 5 leaves a sufficient safety distance for the light source sensing area, which can prevent the traps caused by the etching and filling processes from having a negative impact on the dark count rate and the after pulse;

[0037] An electrode guard ring 6 is arranged in the wiring layer 2 below the shallow trench isolation layer 3. The material may be polycrystalline silicon, and the electric field peak at the interface of the shallow trench isolation layer 3 may be introduced into the interior of the shallow trench isolation layer 3. This may effectively reduce the dark counts and after-pulses caused by the trapped charges on the surface of the shallow trench isolation layer 3 under strong field conditions.

[0038] In the embodiment of the present invention, the active P+ layer 7 is arranged at the center of each light source sensing area, the active area P well 8 coincides with the center of the active P+ layer 7, the outer diameter is equal to the active P+ layer 7, and the active area P well 8 is arranged directly above the active P+ layer 7 in the vertical direction; the size of the light source sensing area and the spacing between the light source sensing areas are very critical to the entire device structure. Appropriate size and spacing can ensure a high filling rate. The size of the light source sensing area in the embodiment of the present invention is mainly determined by the size of the active P+ layer 7. Therefore, in the preparation process of the light source sensing area, the size of the active P+ layer 7 can be pre-designed to determine the spacing between adjacent light source sensing areas. Preferably, each light source sensing area in the implementation of the present invention is a rounded structure. The rounded structure can be a circle, a rounded square, a rounded regular octagon, a rounded rectangle, a rounded hexagon, etc. The specific shape is not limited. The outer vertex angle formed by this shape is rounded to avoid the curvature effect and the electric field peak caused by the sharp corner. For example, the active P+ layer 7 can be selected as a rounded square structure, and the size of the active P+ layer 7 is the length of the side length of the square structure. In the experiment, the size of the active P+ layer 7 is preferably 2μm to 6μm, and the spacing between adjacent light source sensing areas can be designed differently according to actual needs;

[0039] The deep N-well 9 is arranged above the active region P-well 8, which is a retrograde doped well, that is, the doping concentration is low on the surface and increases with the doping depth, and because its concentration increases continuously, the width of its depletion region becomes wider, further improving the device detection probability and spectral response range; the deep N-well 9 is shared by all light source sensing regions, forming a whole continuous area, and the shallow trench isolation layer 3 and the isolation N-well 4 in the isolation structure are wrapped on the outermost side, forming a multiplied main junction with the active region P-well, forming a strong electric field, and sensing the arrival of photons;

[0040] The N-type buried layer 10 is arranged at the position closest to the surface of the device structure. The N-type buried layer 10 is shared by all light source sensing areas, forming a whole continuous area, forming a multiplication main junction with the P-type epitaxial layer 1, and forming a strong electric field to sense the arrival of photons, thereby providing a bias voltage for the deep N well 9. The N-type buried layer 10 and the P-type epitaxial layer 1 form an avalanche multiplication region, and the electric field points from the P-type epitaxial layer 1 to the N-type buried layer 10. In the high field absorption region, electrons mainly participate in the avalanche, and the electron avalanche ionization rate is relatively high, which can further improve the quantum efficiency and avoid the full depletion of the P-type epitaxial layer 1, which leads to the enhancement of the electric field at the shared cathode 40. In addition, the doping concentration of the N-type buried layer 10 in the embodiment of the present invention is relatively high, for example, the doping concentration is about 5×10 18 cm -3 , which can provide a smaller cathode series resistance for each light source sensing area;

[0041] The P-well protection ring 11 surrounds the active area P-well 8 and the active P+ layer 7 in the light source sensing area to form a physical epitaxial protection ring, and the isolation N-well 4 forms a reverse biased PN junction structure with the P-well protection ring 11 to avoid carrier drift or tunneling to form adjacent pixel crosstalk; under the action of the deep N-well 9, it is helpful to reduce the doping concentration required to form the P-well protection ring 11; wherein, it is preferred that the doping concentration of the active area P-well 8 in the embodiment of the present invention is higher than the doping concentration of the P-well protection ring 11, and the junction depth of the active area P-well 8 is smaller than the P-well protection ring 11, so that the central electric field of the light source sensing area can be effectively made higher than the side electric field, thereby inhibiting the side from breaking down in advance;

[0042] The anode electrode 12 is arranged at the center of the active P+ layer 7, which is a floating potential and is connected to the subsequent circuit. The large current generated by the avalanche multiplication effect causes the potential change of the fixed node of the subsequent circuit, thereby reflecting the arrival of the photon;

[0043] The reflective metal plate 13 is disposed directly below the anode electrode 12, and its width is equal to the width of the active P+ layer to ensure that the photons irradiated thereon are reflected back into the device, thereby increasing the utilization rate of the photons and enhancing the device detection probability at a longer wavelength.

[0044] For further information, see Figure 2In the embodiment of the present invention, the cathode electrode 15 in the shared cathode forms an electrical contact with the N-type buried layer 10 through the electrode N-well 14 and the deep N-well 9, and provides a bias voltage for the deep N-well 9 in each light source sensing area. In order to avoid the potential inconsistency caused by the lateral resistance loss of the N-well buried layer 10, the shared cathode is provided with a bias voltage by four adjacent light source sensing areas.

[0045] See also Figure 3 , a top view of a back-illuminated silicon-based single-photon avalanche diode structure proposed in an embodiment of the present invention, the diode is an array structure of 2 rows and 2 columns, each light source sensing area is a rounded square structure, and the shared cathode is located in the area surrounded by the rounded corners of the four light source sensing areas. Among them, Figure 1 The cross-sectional structure with xx′ as the cut plane corresponds to Figure 2 It also has a similar cross-sectional structure.

[0046] The back-illuminated silicon-based single-photon avalanche diode structure proposed in the embodiment of the present invention can also be applied to a photoelectric detection chip based on a back-illuminated three-dimensional architecture. The chip is divided into two layers, and its photosensitive device layer can adopt the diode structure proposed in the embodiment of the present invention and be manufactured on the top chip to maximize the fill rate, improve the detection efficiency and have a lower dark count rate. Other circuits are manufactured on the bottom chip, and the two layers can be bonded by copper-copper.

[0047] In order to verify the effectiveness of the back-illuminated silicon-based single-photon avalanche diode structure proposed in the embodiment of the present invention, the following experiment is used to illustrate.

[0048] For the light source sensing area, a larger filling rate means higher photon utilization and detection efficiency, and a smaller light source sensing area spacing means better image fineness. Based on the device structure corresponding to one of the above optional solutions, please refer to Figure 4 , Figure 4 The filling rate changes corresponding to different sizes and spacings of the light source sensing area show that for the back-illuminated silicon-based single-photon avalanche diode structure proposed in the embodiment of the present invention, when the size of the active P+ layer 7 in the light source sensing area is in the range of 2μm to 6μm, for silicon-based SPADs, smaller spacings between light source sensing areas all achieve higher filling rates. For example, when the size of the active P+ layer 7 in the light source sensing area is 2μm and the spacing between the light source sensing areas is 2.5μm, the filling rate reaches 0.25%; when the size of the active P+ layer 7 in the light source sensing area is 6μm and the spacing between the light source sensing areas is 17μm, the filling rate reaches more than 0.5%.

[0049] See also Figure 5 (a) to 5(b), Figure 5(a) is a schematic diagram of the electric field distribution of the back-illuminated silicon-based single-photon avalanche diode structure provided by an embodiment of the present invention. When the reverse bias breakdown voltage of the device reaches 2V, it can be seen that the device structure of the embodiment of the present invention can lock the strong electric field in the middle position of the light source sensing area, wherein the polysilicon electrode guard ring 6 plays a good protective role, and the electric field at the edge of the pixel is significantly lower than the electric field in the central area of ​​the light source sensing area, which effectively suppresses edge breakdown; Figure 5 (b) is the avalanche ionization rate distribution diagram of the back-illuminated silicon-based single-photon avalanche diode structure provided in an embodiment of the present invention. It can be seen that the avalanche ionization mainly occurs in the middle position of the light source sensing area and maintains a large value in a wide range, reflecting that the device structure proposed in the embodiment of the present invention can efficiently realize the avalanche nose multiplication process.

[0050] See also Figure 6 (a) to 6(b), Figure 6 (a) is the electric field distribution simulation result of the polysilicon electrode guard ring 6 disposed in the middle of the shallow trench isolation layer 3 in the back-illuminated silicon-based single-photon avalanche diode structure proposed in the embodiment of the present invention, Figure 6 (b) is the simulation result of the electric field distribution of the polysilicon electrode guard ring 6 disposed at the boundary of the shallow trench isolation layer 3 in the back-illuminated silicon-based single-photon avalanche diode structure proposed in the embodiment of the present invention. Figure 6 It can be seen from (a) to 6(b) that although the polysilicon electrode guard ring 6 is also used to suppress edge breakdown, when the polysilicon electrode guard ring 6 is set in the middle of the shallow trench isolation layer 3, the electric field at the edge of the shallow trench isolation layer 3 is significantly lower than the electric field when the polysilicon electrode guard ring 6 is set at the boundary of the shallow trench isolation layer 3. It can be seen that the polysilicon electrode guard ring 6 plays a good protective role, effectively suppressing edge breakdown, and the electric field near the shallow trench isolation layer 3 is significantly reduced, which effectively reduces the dark count rate of the device caused by trap capture.

[0051] It should be noted that the P-type doping in the embodiment of the present invention refers to doping with group V elements, such as boron and aluminum, and the N-type doping refers to doping with group III elements, such as phosphorus and antimony.

[0052] In summary, the back-illuminated silicon-based single-photon avalanche diode structure proposed in the embodiment of the present invention is a new structure based on a compatible high-voltage CMOS process. The structure can ensure that the diode has a large filling rate and has a high detection efficiency within a wide spectral response range, thereby improving the detection efficiency and having a low dark count rate. Specifically: the isolation N-well 4 in the isolation structure forms a reverse-biased PN junction structure with the P-well protection ring 11 in the light source sensing area to avoid crosstalk between adjacent light source sensing areas caused by carrier drift or tunneling; the electrode protection ring 6 in the isolation structure introduces the electric field peak at the interface of the shallow trench isolation layer 3 into the shallow trench isolation layer 3, which can effectively reduce the dark counts and after-pulses caused by the trapped charges on the surface of the shallow trench isolation layer 3 under strong field application; the N-type buried layer 10 is located at the position closest to the surface of the device to provide electrons for the deep N-well 9 to avoid the electric field enhancement at the shared cathode position caused by the full depletion of the P-type epitaxial layer 1.

[0053] At the same time, the deep N-well 9 in the embodiment of the present invention is a retrograde doped well. Controlling the doping concentration of the deep N-well 9 helps to reduce the doping concentration required to form the P-well guard ring 11, and because its concentration continues to decrease, its depletion region width is wider, which helps to improve the device detection probability and spectral response range.

[0054] In the second aspect, an embodiment of the present invention provides a photodetector, comprising a plurality of the above-mentioned back-illuminated silicon-based single-photon avalanche diode structures distributed in an array. The photodetector proposed in the embodiment of the present invention is formed based on the above-mentioned back-illuminated silicon-based single-photon avalanche diode structure, and the SPAD implementation is not described in detail here. By adopting the above-mentioned back-illuminated silicon-based single-photon avalanche diode structure, the photodetector also has a large filling rate and a high detection probability within a wider spectral response range, thereby achieving the purpose of improving the detection efficiency and having a lower dark count rate.

[0055] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0056] In the description of the embodiments of the present invention, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0057] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0058] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the present application for which protection is sought, a person skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims.

[0059] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A back-illuminated silicon-based single-photon avalanche diode structure, characterized in that: include: P-type epitaxial layer and wiring layer; A plurality of isolation structures, each of which comprises: a shallow trench isolation layer, an isolation N well and a deep trench isolation layer stacked from bottom to top in the P-type epitaxial layer; an electrode guard ring, which is arranged in the wiring layer and close to the shallow trench isolation layer; A plurality of light source sensing regions are spaced and distributed between adjacent isolation structures; wherein each of the light source sensing regions comprises: an active P+ layer, an active region P well, a deep N well and an N-type buried layer stacked from bottom to top; a P well protection ring is arranged on both sides of the active P+ layer and the active region P well, and is connected to the shallow trench isolation layer and the isolated N well; the deep N well is also arranged on the P well protection ring, on part of the isolated N well, and wraps the outermost shallow trench isolation layer and the isolated N well; an anode electrode is arranged in the wiring layer below the active P+ layer; a reflective metal plate is arranged in the wiring layer opposite to the active P+ layer; The shared cathode includes: an electrode N-well, which is arranged in the P-type epitaxial layer and connected to the deep N-well; and a cathode electrode, which is arranged in the wiring layer close to the electrode N-well.

2. The back-illuminated silicon-based single-photon avalanche diode structure according to claim 1, characterized in that: The deep N-well is a retrograde doped well.

3. The back-illuminated silicon-based single-photon avalanche diode structure according to claim 1, characterized in that: The doping concentration of the active region P-well is higher than the doping concentration of the P-well guard ring.

4. The back-illuminated silicon-based single-photon avalanche diode structure according to claim 1, characterized in that: The junction depth of the active region P-well is smaller than the junction depth of the P-well guard ring.

5. The back-illuminated silicon-based single-photon avalanche diode structure according to claim 1, characterized in that: The width of the active P+ layer is equal to the width of the reflective metal plate.

6. The back-illuminated silicon-based single-photon avalanche diode structure according to claim 1, characterized in that: The plurality of light source sensing areas are distributed in an array, and the shared cathode is arranged in an area surrounded by the top corners of each of four adjacent light source sensing areas.

7. The back-illuminated silicon-based single-photon avalanche diode structure according to claim 1, characterized in that: Each of the light source sensing areas is a rounded structure.

8. A photoelectric detector, characterized in that: The invention comprises a plurality of back-illuminated silicon-based single-photon avalanche diode structures as described in any one of claims 1 to 7 distributed in an array.

Images