An adaptive bootstrap charging circuit suitable for GaN driving chip

Abstract

The application discloses a self-adaptive bootstrap charging circuit suitable for a GaN driving chip and belongs to the integrated circuit field. The voltage of a switch node SW is subjected to zero-crossing detection, whether to start or shut down a bootstrap charging path is determined, the voltage on a bootstrap capacitor is clamped at a fixed voltage, bootstrap voltage overcharging is prevented, the bootstrap voltage is ensured to be within the safe working voltage range of a GaN power device, and the problem that a GaN power device is damaged due to excessive bootstrap voltage when a traditional driving chip drives the GaN power device is solved. The scheme can be integrated into a converter chip, the complexity of a peripheral circuit is reduced, the system performance is improved, and the cost is saved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an adaptive bootstrap charging circuit suitable for GaN driver chips. Background Technology

[0002] As power electronic devices continue to evolve towards higher power, higher efficiency, smaller size, and lighter weight, the performance requirements for power switching devices are becoming increasingly demanding, making it increasingly difficult for traditional Si power devices to meet these requirements. Gallium nitride (GaN), as a representative of third-generation semiconductor materials, possesses superior electrical properties compared to traditional Si materials, such as a larger bandgap, higher breakdown field strength, higher thermal conductivity, higher electron saturation velocity, lower dielectric constant, stronger radiation resistance, and higher chemical temperature and power density. Devices fabricated using GaN materials will exhibit lower conduction losses and higher frequency response performance, meaning that GaN power devices have significant advantages in fabricating small-size, high-efficiency power modules and have promising application prospects. However, there are some factors that require special attention when driving GaN power devices, such as low gate breakdown voltage, narrow gate safe operating voltage range, low threshold voltage, high reverse conduction voltage, and sensitivity to parasitic factors. These factors pose new requirements for the design of drive circuits for GaN power devices.

[0003] For half-bridge drive circuits, a bootstrap circuit is required to provide a bootstrap voltage to the high side to drive the upper transistor, such as... Figure 1 As shown. When the downside diode is turned on, the low-side supply voltage VDD flows through the bootstrap diode D. BOOT For bootstrap capacitor C BOOT Charging is performed; when the upper transistor is turned on, the bootstrap diode D... BOOT Blocking the low-side supply voltage VDD, while the bootstrap capacitor C BOOT It provides the energy required for high-side gate drive. In a half-bridge drive circuit, to prevent shoot-through between the upper and lower transistors, a dead time is required. During the dead time, both HO and LO are low, and both the upper and lower transistors are turned off. During the level transition, when the upper transistor is turned off, since the current in inductor L cannot change abruptly, it needs to conduct through the lower transistor in reverse to freewheel. The voltage at point HS will rapidly drop below 0 potential. At this time, the voltage across the bootstrap capacitor will be charged to V. BOOT =VDD-V F +V SD V F It is the forward voltage drop of the bootstrap diode, V SDThis refers to the reverse conduction voltage of the GaN power device. For GaN power devices, the reverse conduction voltage increases rapidly with increasing load current. When the load current is 20A, its value reaches 2.2V, which is much higher than the reverse conduction voltage of traditional power devices. This causes the voltage across the bootstrap capacitor to be rapidly charged to greater than 6V (VDD is typically 5V), exceeding the gate withstand voltage of the GaN power device and causing damage. This is a problem that needs to be considered and addressed in the design of the drive circuit for GaN power devices.

[0004] For the problems of excessive reverse conduction voltage drop and high-side transistor bootstrap overvoltage in GaN power devices, the main solutions from academia and industry include: controlling the dead time of the upper and lower transistors within a few nanoseconds to reduce the overlap time of reverse conduction current and reverse conduction voltage in GaN power devices, thereby reducing reverse conduction losses. However, this introduces larger parasitic capacitance and reverse recovery charge, limiting the improvement of switching frequency; and using anti-parallel diodes across the low-side GaN power devices to act as body diodes, thereby clamping the reverse conduction voltage to a lower voltage level. However, anti-parallel diodes will carry a certain current and generate losses. Studies have shown that this can increase current loss by 40% and may also cause undervoltage lockout in the high-side circuit. Summary of the Invention

[0005] The purpose of this invention is to provide an adaptive bootstrap charging circuit suitable for GaN driver chips, so as to solve the problem of overcharging of the bootstrap capacitor during the dead time in traditional bootstrap circuits, prevent gate breakdown of GaN power devices, and improve the reliability of driver chips.

[0006] To address the aforementioned technical problems, this invention provides an adaptive bootstrap charging circuit suitable for GaN driver chips, comprising a zero-crossing detection module, a low-voltage control module, and a bootstrap diode D. BOOT and bootstrap capacitor C BOOT ;

[0007] The zero-crossing detection module performs zero-crossing detection on the switching node SW, and the low-voltage control module controls the opening and closing of the bootstrap charging circuit to prevent overcharging of the bootstrap voltage and damage to the GaN power devices.

[0008] Optionally, the zero-crossing detection module includes a first bias current I. BIAS1 Second bias current I BIAS2 The components are: first diode D1, second diode D2, resistor R1, and voltage comparator COMP.

[0009] The first bias current I BIAS1One end of the resistor R1 is connected to VDD, and the other end is connected to node V1; one end of the resistor R1 is connected to node V1, and the other end is connected to the anode of the first diode D1; the cathode of the first diode D1 is connected to the switch node SW, wherein the voltage at node V1 is determined by the first bias current I. BIAS1 The voltage is determined by resistor R1, the forward voltage of the first diode D1, and the voltage at point SW.

[0010] The second bias current I BIAS2 One end is connected to VDD, and the other end is connected to node V2; the anode of the second diode D2 is connected to node V2, and the cathode is grounded, wherein the voltage of node V2 is determined by the forward conduction voltage of the second diode D2;

[0011] The positive input terminal of the voltage comparator COMP is connected to node V2, the negative input terminal is connected to node V1, and the output terminal is connected to the low-voltage control module.

[0012] Optionally, both the first diode D1 and the second diode D2 are reverse-biased high-voltage resistant devices, and their forward conduction voltages are equal.

[0013] Optionally, the low-voltage control module includes a drive buffer and a PMOS switch MP1. The input terminal of the drive buffer is connected to the output terminal of the voltage comparator COMP, and the output terminal of the drive buffer is connected to the gate terminal of the PMOS switch MP1 and node V. P The drain of the PMOS switch MP1 is connected to VDD, and the source is connected to the bootstrap diode D. BOOT The anode of the bootstrap capacitor is turned on or off according to the gate signal.

[0014] Optionally, the PMOS switch MP1 is a single-sided high-voltage resistant device.

[0015] Optionally, the bootstrap diode D BOOT It is a reverse-biased high-voltage resistant device.

[0016] In the adaptive bootstrap charging circuit for GaN driver chips provided by this invention, zero-crossing detection of the switching node SW voltage determines whether the bootstrap charging path is turned on or off. This clamps the voltage on the bootstrap capacitor to a fixed voltage, preventing overcharging and ensuring the bootstrap voltage remains within the safe operating voltage range of the GaN power device. This solves the problem of traditional driver chips damaging GaN power devices due to excessive bootstrap voltage. This solution can be integrated into the converter chip, reducing the complexity of peripheral circuits, improving system performance, and saving costs. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the bootstrap charging circuit topology of a traditional half-bridge drive circuit.

[0018] Figure 2 This is a schematic diagram of the adaptive bootstrap charging circuit topology for GaN driver chips provided by the present invention;

[0019] Figure 3 This is a schematic waveform diagram illustrating the working principle of the adaptive bootstrap charging circuit for GaN driver chips provided by the present invention. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of an adaptive bootstrap charging circuit suitable for GaN driver chips proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0021] This invention provides an adaptive bootstrap charging circuit suitable for GaN driver chips, the structure of which is as follows: Figure 2 As shown. Figure 1 The diagram shows the bootstrap circuit of a traditional drive circuit. During the dead time, due to the reverse conduction of the lower transistor MN11, the reverse conduction voltage is V. SD VDD forms a loop to ground through the bootstrap diode, bootstrap capacitor, and lower transistor. The voltage across the bootstrap capacitor will be charged to V. BOOT =VDD-V F +V SD V F It is the forward voltage drop of the bootstrap diode, V SD This is the reverse conduction voltage of the GaN power device below. Because GaN power devices have a laterally symmetrical structure and lack an internal body diode, they achieve reverse freewheeling of the switching power supply through reverse conduction. Therefore, their reverse conduction voltage is much greater than the diode's conduction voltage, approximately 2V. When VDD is 5V and the diode's conduction voltage is 0.7V, the voltage across the bootstrap capacitor V... BOOT A voltage exceeding 6V is outside the safe operating voltage range of GaN power devices, potentially causing the upper GaN power transistor to break down and affecting system reliability. Compared to traditional bootstrap circuits, the bootstrap circuit of this invention clamps the bootstrap voltage by detecting zero-crossing of the switching node SW to determine whether to turn the bootstrap charging path on or off. This prevents the bootstrap voltage from becoming too high, ensuring that the voltage across the bootstrap capacitor remains within the safe operating range of the GaN power devices and improving system performance.

[0022] The adaptive bootstrap charging circuit for GaN driver chips provided by the invention mainly consists of a zero-crossing detection module, a low-voltage control module, and a bootstrap diode D. BOOT and bootstrap capacitor C BOOTComposition, including bootstrap diode D BOOT It is a reverse-biased high-voltage withstand device. The zero-crossing detection module is based on the first bias current I. BIAS1 Second bias current I BIAS2 The system consists of a first diode D1, a second diode D2, a resistor R1, and a voltage comparator COMP. Diodes D1 and D2 are reverse-biased high-voltage devices with equal forward conduction voltages. The low-voltage control module consists of a drive buffer and a PMOS switch MP1, where MP1 is a single-sided high-voltage device. The first bias current I... BIAS1 One end of resistor R1 is connected to VDD, and the other end is connected to node V1. One end of resistor R1 is connected to node V1, and the other end is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to the switch node SW. The voltage at node V1 is determined by the first bias current I. BIAS1 The second bias current I is determined by the resistance value of R1, the forward conduction voltage of D1, and the voltage at point SW. BIAS2 One end of the circuit is connected to VDD, and the other end is connected to node V2. The anode of the second diode D2 is connected to node V2, and the cathode is grounded. The voltage at node V2 is determined by the forward conduction voltage of the second diode D2. The positive input of the voltage comparator COMP is connected to node V2, the negative input is connected to node V1, and the output is connected to the input of the drive buffer. Its main function is to compare nodes V1 and V2. When V1 is greater than V2, the output is high; otherwise, the output is low. The input of the drive buffer is connected to the output port of the comparator COMP, and the output port is connected to the gate of the PMOS switch MP1 and node VDD. P Its main function is to increase the driving capability of the output signal of the voltage comparator COMP. The drain of the PMOS switch MP1 is connected to VDD, and the source is connected to the bootstrap diode D. BOOT The anode of the gate capacitor is mainly used to turn the charging circuit of the bootstrap capacitor on or off according to the gate signal.

[0023] Figure 3 The diagram shown illustrates the working principle of this invention. When the upper transistor is turned off, the circuit enters the dead time, and the voltage at terminal SW begins to drop. During the 0-t1 phase, the voltage at terminal SW has not yet dropped to VDD-I. BIAS1 *R1-V F Previously, because the first diode D1 was not conducting, the voltage at point V1 was clamped at 5V, which was greater than the voltage at point V2. F V P When the voltage level is low, PMOS transistor MP1 is in the ON state. Simultaneously, during this stage, bootstrap diode D... BOOTReverse cutoff, bootstrap charging path shut down. During the t1-t2 phase, the voltage at the SW terminal drops to 0V. During this process, the voltage at point V1 will decrease along with the voltage at the SW terminal, but the voltage at point V1 will still be greater than the voltage at point V2. F V P The voltage level is low, and PMOS transistor MP1 is in the on state. During the t2-t3 phase, the voltage at the SW terminal gradually decreases from 0V to V. t2 V t2 =-I BIAS1 *R1, during this process, the voltage at point V1 still has not dropped to V. F V P The voltage level remains low, and PMOS transistor MP1 remains on. This is due to the bootstrap diode D... BOOT The presence of this clamps the voltage at the HB terminal to VDD-V. F Because the voltage at terminal SW is less than 0V, the bootstrap capacitor C... BOOT Voltage V on BOOT A slight rise will occur. During the t3-t4 phase, the voltage at the SW terminal will first decrease and then increase, but during this phase, the voltage at point V1 will always be less than V. F The output of the voltage comparator COMP reverses, V P When the signal transitions to a high level, PMOS transistor MP1 is turned off, blocking the bootstrap capacitor C. BOOT The charging circuit prevents the voltage V on the bootstrap capacitor from being applied. BOOT Further increases lead to overcharging. After stage t4, the voltage at terminal SW rises to V. t2 Above, the voltage at point V1 begins to be greater than the voltage at point V2. F The output of the voltage comparator COMP reverses again, V P When the voltage transitions to low, PMOS transistor MP1 turns on, opening the charging circuit of the bootstrap capacitor and maintaining the voltage V across the bootstrap capacitor. BOOT In VDD-V F +I BIAS1 *R1 ensures that the bootstrap voltage remains within the safe operating range of GaN power devices.

[0024] This implementation can also be used in other GaN HEMT drive circuits, such as full-bridge drive circuits. By detecting the voltage at point SW, it automatically adjusts the opening and closing of the bootstrap capacitor charging circuit, clamping the bootstrap voltage within the safe operating voltage range of the GaN power device. This solves the problem of damage to the GaN power device caused by overcharging of the bootstrap voltage due to excessive reverse conduction voltage of the GaN power device.

[0025] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An adaptive bootstrap charging circuit suitable for GaN driver chips, characterized in that, Includes a zero-crossing detection module, a low-voltage control module, and a bootstrap diode D. BOOT and bootstrap capacitor C BOOT ; The zero-crossing detection module performs zero-crossing detection on the switching node SW, and the low-voltage control module controls the opening and closing of the bootstrap charging circuit to prevent overcharging of the bootstrap voltage and damage to the GaN power device; wherein the switching node SW is the node connecting the upper power transistor and the lower power transistor. The zero-crossing detection module includes a first bias current I. BIAS1 Second bias current I BIAS2 The components are: first diode D1, second diode D2, resistor R1, and voltage comparator COMP. The first bias current I BIAS1 One end of the resistor R1 is connected to VDD, and the other end is connected to node V1; one end of the resistor R1 is connected to node V1, and the other end is connected to the anode of the first diode D1; the cathode of the first diode D1 is connected to the switch node SW, wherein the voltage at node V1 is determined by the first bias current I. BIAS1 The voltage is determined by resistor R1, the forward conduction voltage of the first diode D1, and the voltage of the switching node SW. The second bias current I BIAS2 One end is connected to VDD, and the other end is connected to node V2; the anode of the second diode D2 is connected to node V2, and the cathode is grounded, wherein the voltage of node V2 is determined by the forward conduction voltage of the second diode D2; The positive input terminal of the voltage comparator COMP is connected to node V2, the negative input terminal is connected to node V1, and the output terminal is connected to the low-voltage control module. The low-voltage control module includes a drive buffer and a PMOS switch MP1. The input terminal of the drive buffer is connected to the output terminal of the voltage comparator COMP, and the output terminal of the drive buffer is connected to the gate terminal of the PMOS switch MP1. The drain terminal of the PMOS switch MP1 is connected to VDD, and the source terminal is connected to the bootstrap diode D. BOOT The anode of diode D BOOT The cathode is connected to the bootstrap capacitor C BOOT One end, the bootstrap capacitor C BOOT The other end is connected to the switching node SW, and the charging circuit of the bootstrap capacitor is turned on or off according to the gate signal of the PMOS switching transistor MP1.

2. The adaptive bootstrap charging circuit for GaN driver chips as described in claim 1, characterized in that, Both the first diode D1 and the second diode D2 are reverse-biased high-voltage devices, and their forward conduction voltages are equal.

3. The adaptive bootstrap charging circuit for GaN driver chips as described in claim 1, characterized in that, The PMOS switch MP1 is a single-sided high-voltage resistant device.

4. The adaptive bootstrap charging circuit for GaN driver chips as described in any one of claims 1-3, characterized in that, The bootstrap diode D BOOT It is a reverse-biased high-voltage resistant device.

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