Circuit and method for controlled discharge of high (positive or negative) voltage charge pumps

Abstract

Embodiments of the present disclosure relate to circuits and methods for controlled discharge of high (positive or negative) voltage charge pumps. A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes a first switch circuit coupled to a first output of the first charge pump stage circuit and configured to discharge the first output when actuated, and a second switch circuit coupled to a second output of the second charge pump stage circuit and configured to discharge the second output when actuated. A discharge control circuit actuates the first switch discharge circuit to discharge the first output, and then after the first output is fully discharged, actuates the second switch discharge circuit to discharge the second output.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 115,725, filed November 19, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to a circuit for controlled discharge of a multi-stage high (positive or negative) voltage charge pump. Background Technology

[0004] Many circuits require relatively high supply voltages (e.g., equal to or greater than 12V). Non-volatile memory is an example of such circuits. Programming and erasing operations in such memory are performed using the Fowler-Nordeim tunneling effect, which requires such high voltages. It is common practice to generate these high voltages on-chip from relatively low supply voltages (e.g., 3V, 3.3V, or 5V) using high-voltage charge pump circuits.

[0005] A typical multi-stage high (positive) voltage charge pump circuit 10 in Figure 1 The charge pump circuit 10 is shown in the figure. It includes N pump stage circuits 12(1) to 12(N) connected in series. Each pump stage circuit 12 includes an input configured to receive a first voltage and an output configured to generate a second voltage higher than the first voltage. In the series connection of the pump stage circuits 12, the output of the first pump stage circuit 12(1) is connected to the input of the second pump stage circuit 12(2), the output of the second pump stage circuit 12(2) is connected to the input of the third pump stage circuit 12(3), and so on, until the input of the Nth pump stage circuit 12(N) is connected to the output of the (N-1)th pump stage circuit 12(N-1).

[0006] The internal circuitry of each pump stage circuit 12 is well known to those skilled in the art and is not illustrated in the figures, nor described in detail herein. However, as an example, each pump stage circuit 12 may utilize clock-controlled charge transfer between capacitors used as charge accumulation elements. In such a pump stage circuit, opposite-phase clock signals CLK and CLKb are used to control switches (e.g., MOSFET devices) to selectively transfer charge to and between capacitors.

[0007] The overall charge pump circuit 10 has an input 14 configured to receive an input voltage Vin, the input voltage Vin being applied to the input of the first pump stage circuit 12(1), and also has an output 16 configured to generate an output voltage Vout at the output of the Nth pump stage circuit 12(2). The output 16 is coupled to a load (not shown), and the output voltage Vout has a suitably elevated voltage level relative to the input voltage Vin. As an example, when the input voltage Vin = 3V and each pump stage circuit 12 can provide a voltage boost of approximately 2.2V, the charge pump circuit 10 with N = 6 will generate approximately equal to (N + 1)*Vin (in this case, for example, Vout = 16V).

[0008] The charge pump circuit 10 includes a clock generator circuit 20 configured to generate a set of complementary clock signals CLK and CLKb, the set of complementary clock signals CLK and CLKb being applied to each pump stage circuit 12 to control the clock-controlled charge transfer operation. In an alternative embodiment, the clock signals for driving each pump stage circuit may include more than two phases - for example, some known pump stage circuits use a set of four-phase clock signals. The operation of the clock generator circuit 20 is enabled in response to an enable signal En generated by a comparator circuit 22. An output voltage detection circuit 26 is coupled between the output 16 and ground and is configured to sense the output voltage Vout and generate a feedback voltage Vfb, the feedback voltage Vfb indicating the output voltage Vout (i.e., being a fraction of the output voltage Vout). The output voltage detection circuit 26 may include, for example, a resistive voltage divider circuit including at least two resistors R1, R2 and a tap node T. The comparator circuit 22 operates to compare the feedback voltage Vfb with a reference voltage Vref and, when Vfb < Vref, generates the enable signal En to turn on the clock generator circuit 20, and conversely, when Vref < Vfb, turns off the clock generator circuit 20. For example, the reference voltage Vref may be generated by a bandgap circuit.

[0009] When the charge pump circuit 10 is subsequently turned off, it is important to properly discharge the output of each pump stage circuit 12 to an appropriate low voltage level. More specifically, this discharge operation refers to the discharge of the high-voltage storage capacitors within the pump stage circuit 12. If the capacitor discharge operation is not performed correctly, a number of potential problems may occur, including: ground bounce (due to discharge to the ground node), power supply noise generation (due to discharge to the power supply node), latch-up (if an uncontrolled high current is dumped to the ground / power supply node and the local body is forward biased), fast return (if an uncontrolled high current is dumped to the ground / power supply node and the parasitic bipolar junction transistor is triggered), or device reliability problems (e.g., junction breakdown, oxide-related problems, or aging problems due to violation of safe operating area (SOA) limits in response to uncontrolled current).

[0010] Therefore, there is a need in the art for controlled discharge of pump stage circuits within multi-stage high-voltage charge pump circuits.

[0011] Further reference is made to U.S. Patent Application Publications 2020 / 0195134 and 2020 / 0161966 (incorporated herein by reference), which teach examples of charge pump discharge circuits. Summary of the Invention

[0012] In one embodiment, a circuit includes: a charge pump circuit including a plurality of series-coupled charge pump stage circuits; and a discharge circuit configured to discharge the charge pump circuit; wherein the discharge circuit includes: a plurality of switch discharge circuits, wherein each switch discharge circuit is coupled to the output of a corresponding charge pump stage circuit in the charge pump stage circuit and is configured to discharge the output when actuated; and a discharge control circuit configured to sequentially actuate each of the plurality of switch discharge circuits during a discharge time period.

[0013] In one embodiment, a circuit includes: a charge pump circuit including a first charge pump stage circuit coupled in series with a second charge pump stage circuit; and a discharge circuit configured to discharge the charge pump circuit; wherein the discharge circuit includes: a first switching discharge circuit coupled to a first output of the first charge pump stage circuit and configured to discharge the first output when actuated; a second switching discharge circuit coupled to a second output of the second charge pump stage circuit and configured to discharge the second output when actuated; and a discharge control circuit configured to: actuate the first switching discharge circuit to discharge the first output, and then, after the first output has been fully discharged to a specific voltage level, actuate the second switching discharge circuit to discharge the second output to the specific voltage level. Attached Figure Description

[0014] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:

[0015] Figure 1 A block diagram of a typical multi-stage high-voltage charge pump circuit is shown.

[0016] Figures 2A to 2B Block diagrams of positive and negative multi-stage high-voltage charge pump circuits with discharge circuits are shown respectively.

[0017] Figure 3 It shows Figures 2A to 2B A more generalized block diagram of the circuit in the diagram;

[0018] Figure 4 It is a sequence diagram;

[0019] Figure 5A and Figure 5B The circuit diagram of the switch discharge circuit is shown; and

[0020] Figure 6 It shows having, as Figure 2A The waveform trace of the simulated operation of the charge pump circuit of the discharge circuit shown is illustrated. Detailed Implementation

[0021] Now for reference Figure 2A It shows a block diagram of a positive multi-stage high-voltage charge pump circuit 100 with a discharge circuit 102. It is implemented as a 6-stage charge pump. Figure 2A The circuit diagram is provided by Figure 3 Provided. The charge pump circuit 100 includes N pump stage circuits 112(1) to 112(N) connected in series. Each pump stage circuit 112 includes an input configured to receive a first voltage and an output (Sx, where x = 1 to N) configured to generate a second voltage higher than the first voltage. In the series connection of the pump stage circuits 112, the output S1 of the first pump stage circuit 112(1) is connected to the input of the second pump stage circuit 112(2), the output S2 of the second pump stage circuit 112(2) is connected to the input of the third pump stage circuit 112(3), and so on, until the input of the Nth pump stage circuit 112(N) is connected to the output SN-1 of the (N-1)th pump stage circuit 112(N-1).

[0022] The internal circuitry of each pump stage circuit 112 is well known to those skilled in the art, is not illustrated in the figures, and is not described in detail herein. However, as an example, each pump stage circuit 112 may utilize clock-controlled charge transfer between capacitors used as charge accumulation elements. In such a pump stage circuit, opposite-phase clock signals CLK and CLKb are used to control switches (e.g., MOSFET devices) to selectively transfer charge to and between capacitors. It should be understood that, in alternative embodiments, each pump stage circuit may be driven by a set of clock signals comprising more than two phases (e.g., a four-phase clock signal set).

[0023] Figure 2A The overall charge pump circuit 100 is a positive voltage generator circuit having an input 114 configured to receive an input positive voltage Vin = +Vin, which is applied to the input of a first pump stage circuit 112 (1), and also having an output 116 configured to generate a raised positive output voltage Vpos at the output SN of the Nth pump stage circuit 112 (N). The output 116 is coupled to a load (not shown), and the output voltage Vpos has a suitably raised voltage level relative to the input voltage +Vin. As an example, each pump stage circuit 112 can provide a voltage boost of approximately 2.2V, so an N=6 charge pump circuit 100 with an input voltage +Vin = 3V will generate an output voltage Vpos = V... S6 V S1 =5.2V, V S2 =7.4V, V S3 =9.6V, V S4 =11.8V and V S5 =14V (see Figure 6 ).

[0024] In such Figure 2B In the alternative embodiment shown, the overall charge pump circuit 100 is a negative voltage generator circuit having an input 114 configured to receive an input ground voltage Vin = Gnd, which is applied to the input of the first pump stage circuit 112(1) and generates a raised negative output voltage Vneg at the output SN, 116 of the Nth pump stage circuit 112(N). As an example, each pump stage circuit 112 can provide a voltage boost of approximately 2.2V, so an N=6 charge pump circuit 100 with a ground input voltage and a circuit supply voltage Vdd = 3V will generate an output voltage Vneg = V ≈ -13V. S6 V S1 =-2.2V, V S2 = -4.4V, V S3= -6.6V, V S4 = -8.8V and V S5 = -11.0V.

[0025] The charge pump circuit 100 includes a clock generator circuit 120 configured to generate complementary clock signals CLK and CLKb (again, note the possible embodiments with more than two (such as four) phases for the clock signals). Each of the N clock gating (logic) circuits 104(1) to 104(N) is coupled to receive the complementary clock signals CLK and CLKb. Each clock gating circuit 104 also receives a corresponding one of the N discharge control signals DEn_1 to DEn_N, and the discharge control signal controls the gating operation to selectively transfer the complementary clock signals CLK and CLKb to the corresponding pump stage circuit 112. When the control signal DEn is de-asserted, the complementary clock signals CLK and CLKb are transferred by the clock gating circuit 104. Conversely, when the control signal DEn is asserted, a blocking operation is performed and the complementary clock signals CLK and CLKb are not transferred.

[0026] In response to an enable signal En generated by the comparator circuit 122, the operation of the clock generator circuit 120 is enabled. The output voltage detection circuit 126 is coupled between the output 116 and ground and is configured to sense the output voltage Vout and generate a feedback voltage Vfb that is an indication of the output voltage Vout (i.e., is a portion of the output voltage Vout). The output voltage detection circuit 126 may include, for example, a resistive voltage divider circuit that includes at least two resistors R1, R2 and a tap node T. In Figure 2A embodiments, the comparator circuit 122 operates to compare the feedback voltage Vfb with a reference voltage Vref and generate an enable signal En to turn on the clock generator circuit 120 when Vfb < Vref, and conversely, turn off the clock generator circuit 120 when Vref < Vfb. In Figure 2B embodiments, since the voltage boosting operation is negative, the resistive voltage divider circuit of the output voltage detection circuit 126 is coupled between the output node and the reference voltage Vref, and the comparator circuit 122 operates to compare the feedback voltage Vfb with the ground voltage Gnd. When Gnd < Vfb, the enable signal En turns on the clock generator circuit 120, and conversely, when Vfb < Gnd, the clock generator circuit 120 is turned off. For example, the reference voltage Vref may be generated by a bandgap circuit.

[0027] When the charge pump circuit 100 is subsequently turned off, it is important to properly discharge the output of each pump stage circuit 112 to an appropriate low voltage level (e.g., to the level of the input voltage Vin). More specifically, this discharge operation refers to the discharge of the high-voltage storage capacitor within the pump stage circuit 112. A discharge circuit 102 is coupled to the charge pump circuit 100 and configured to operate in a controlled manner to discharge the voltage at the output Sx of each pump stage circuit 112.

[0028] N switching discharge circuits 106(1) to 106(N) are coupled to charge pump circuit 100 and are selectively controlled to discharge and clamp the output of each pump stage circuit 112 to a specific voltage level (e.g., Vin). Each switching discharge circuit 106 is connected to an input voltage Vin (or the voltage at one of the outputs Sx, or voltage Vdd) and ground to obtain power. The control input of each switching discharge circuit 106 is coupled to receive one of the N control signals DEn_1 to DEn_N. The output Dx of each switching discharge circuit 106 is coupled to the corresponding output Sx of charge pump stage circuit 112. The control signals DEn_1 to DEn_N control the discharge and clamping operations performed by the switching discharge circuit 106 on the output of the corresponding pump stage circuit 112. When the control signal DEn is deasserted, the switching discharge circuit 106 is disabled, and the output Dx of the switching discharge circuit 106 is tri-state. Conversely, when the control signal DEn is asserted (as described above, when the complementary clock signals CLK and CLKb are not passed by the clock gating circuit 104), the switching discharge circuit 106 is enabled to perform a discharge and clamping operation at its output Dx. Specifically, the enabled switching discharge circuit 106 clamps the output Sx of the pump stage circuit 112 to the voltage level at the power supply node (the input voltage Vin or the voltage at a specific node Sx).

[0029] Discharge control circuit 103 operates to control the discharge and clamping operations of discharge circuit 102. Discharge control circuit 103 includes controller circuit 101, which generates a first control signal DEn_1, which is applied to the corresponding first clock gate circuit 104(1) and first switch discharge circuit 106(1). Discharge control circuit 103 also includes delay circuit 105, which generates second to Nth control signals DEn_2 to DEn_N. The first control signal DEn_1 is applied to the input of delay circuit 105. The second control signal DEn_2 is applied to the corresponding second clock gate circuit 104(2) and second switch discharge circuit 106(2), ..., and the Nth control signal DEn_N is applied to the corresponding Nth clock gate circuit 104(N) and Nth switch discharge circuit 106(N).

[0030] The delay circuit 105 includes N-1 flip-flop circuits 107(2) to 107(N) coupled in series. The data input of the first flip-flop circuit 107(2) receives a first control signal DEn_1. In the series connection of the flip-flop circuits 107, the output of the first flip-flop circuit 107(2) providing the second control signal DEn_2 is connected to the input of the second flip-flop circuit 107(3), the output of the second flip-flop circuit 107(3) providing the third control signal DEn_3 is connected to the input of the third flip-flop circuit 107(4), and so on, until the input of the Nth flip-flop circuit 107(N) is connected to the output of the (N-1)th flip-flop circuit 107(N-1), and the output of the Nth flip-flop circuit 107(N) provides the Nth control signal DEn_N.

[0031] It should be understood that the circuit system shown for delay circuit 105 is merely an example. In an alternative configuration, delay circuit 105 may instead be formed by a resistor-capacitor (RC) circuit system with logic gates that provide control signals DEn with the desired delay timing relationship.

[0032] The reset inputs of N-1 flip-flop circuits 107(2) to 107(N) all receive a reset signal (reset) generated by the discharge controller circuit 101. In response to the assertion of the reset signal, the output of each flip-flop circuit 107 is placed in the reset logic state, and the corresponding control signal DEn is deasserted. In other words, when the discharge controller circuit 101 asserts the reset signal, this action, along with the simultaneous deassertion of the first control signal DEn_1, disables all N switching discharge circuits 106(1) to 106(N). Furthermore, because all control signals DEn are deasserted, the N clock gate circuits 104(1) to 104(N) are enabled, and the complementary clock signals CLK and CLKb are passed to the corresponding pump stage circuits 112(1) to 112(N). In this case, the normal operation of the charge pump circuit 100 for boosting the input voltage Vin and generating the output voltage Vout is supported.

[0033] The clock inputs of N-1 flip-flop circuits 107(2) to 107(N) all receive the discharge clock signal DisClk generated by the discharge controller circuit 101. In response to the reset signal's de-assertion, along with the simultaneous assertion of the first control signal DEn_1, due to the operation of the delay circuit 105, in response to each cycle of the discharge clock signal DisClk (with a period of Tdel) (see...) Figure 4The remaining control signals DEn_2 to DEn_N will have a series of sequential assertions. Each assertion of the control signal DEn will cause the corresponding clock gating circuit 104 to block the transmission of complementary clock signals CLK and CLKb to the corresponding pump stage circuit 112, and will also enable the corresponding switch discharge circuit 106 to discharge and clamp the output of the corresponding pump stage circuit 112.

[0034] The frequency of the discharge clock signal DisClk is selected such that the period Tdel is long enough to ensure that the discharge and clamping operations at the output of each charge pump stage circuit 112 are completed, regardless of the level of the increased voltage at the output.

[0035] Now for reference Figure 5A The diagram illustrates a circuit diagram of an embodiment of the switch-discharge circuit 106. A first p-channel MOSFET device 200 and a second p-channel MOSFET device 202 have source-drain paths connected in series between a positive power supply node 204 and a first intermediate node 206. The sources of transistors 200 and 202 are interconnected at an output node Dx. The gate of transistor 200 is coupled to the first intermediate node 206, and the gate of transistor 202 is coupled to the positive power supply node 204. The switch-discharge circuit 106 also includes a first n-channel MOSFET device 208 and a second n-channel MOSFET device 210, having source-drain paths connected in series between the first intermediate node 206 and a ground power supply node 212. The source of transistor 208 and the drain of transistor 210 are interconnected at a second intermediate node 214. The gate of transistor 208 is coupled to the positive power supply node 204. The gate of transistor 210 is coupled to receive a control signal DEn_x. The switching discharge circuit 106 also includes a third p-channel MOSFET device 216, which has a source coupled to the positive power supply node 204, a drain coupled to the second intermediate node 214, and a gate coupled to receive the control signal DEn_x.

[0036] In response to the de-assertification of the control signal DEn_x (e.g., at ground voltage), transistors 200, 208, and 210 are turned off, and transistors 202 and 216 are turned on. Output node Dx is placed in a tri-state state. Conversely, in response to the assertion of the control signal DEn_x (e.g., at voltage Vin), transistors 200, 208, and 210 are turned on, and transistors 202 and 216 are turned off. In this case, the voltage at output node Dx is discharged and then clamped to the voltage at positive power supply node 204.

[0037] In the multi-stage charge pump circuit 100 with N>2, the positive power supply nodes 204 of the first two switching discharge circuits 106(1) and 106(2) are coupled to receive the input voltage Vin. However, the remaining switching discharge circuits 106 have positive power supply nodes 204 that are coupled to receive the voltage at one (or more) selected outputs of the charge pump stage circuit 112. As an example, in the case of N=4, the positive power supply nodes 204 of the third switching discharge circuit 106(1) and the fourth switching discharge circuit 106(2) are coupled to receive the voltage at the output S1 of the first charge pump stage circuit 112(1).

[0038] As another example, in the case of N=5, the positive power supply node 204 of the fifth switch discharge circuit 106(5) is coupled to receive the voltage at the output S2 of the second charge pump stage circuit 112(2).

[0039] Furthermore, in the case of N=6, the positive power supply node 204 of the sixth switch discharge circuit 106(6) is coupled to receive the voltage at the output S4 of the fourth charge pump stage circuit 112(4).

[0040] This connection from the positive power supply node 204 of the high-order switching discharge circuit 106 to the output Sx is necessary because when the switching discharge circuit 106 is disabled, the voltage at node Dx will be pumped high, and the presence of this voltage will stress the p-channel transistor 200. By connecting the source of the transistor 200 at the positive power supply node 204 to receive the voltage at the output Sx, unwanted stress on the transistor 200 is avoided.

[0041] Furthermore, due to the potential need for the switching discharge circuit 106 to handle higher voltages, such as Figure 5A The circuit 106 shown has been modified to provide, as Figure 5BThe embodiment shown is for higher voltage operation. A first p-channel MOSFET device 200 and a second p-channel MOSFET device 202 have source-drain paths connected in series between a positive power supply node 204 and a first intermediate node 206. The sources of transistors 200 and 202 are interconnected at an output node Dx. The gate of transistor 200 is coupled to the first intermediate node 206, and the gate of transistor 202 is coupled to the positive power supply node 204. The switch-discharge circuit 106 also includes a first n-channel MOSFET device 208, a second n-channel MOSFET device 210, and a third n-channel MOSFET device 218, having source-drain paths connected in series between the first intermediate node 206 and a ground power supply node 212. The source of transistor 208 and the drain of transistor 210 are interconnected at a second intermediate node 214, and the source of transistor 210 and the drain of transistor 218 are interconnected at a third intermediate node 220. The gate of transistor 208 is coupled to the positive power supply node 204. The gates of transistors 210 and 218 are coupled to receive the control signal DEn_x. The switch-discharge circuit 106 also includes a third p-channel MOSFET device 216, having a source coupled to the positive power supply node 204, a drain coupled to the second intermediate node 214, and a gate coupled to receive the control signal DEn_x. Furthermore, a fourth p-channel MOSFET device 222 has a source coupled to the positive power supply node 204, a drain coupled to the third intermediate node 220, and a gate coupled to receive the control signal DEn_x.

[0042] Figure 5B The operation of the circuit is similar to Figure 5A Circuit operation.

[0043] Now for reference Figure 6 The diagram shows the waveform trace of simulated operation of a charge pump circuit 100 with the discharge circuit 102 shown in Figure 2. In this case, N = 6. The time period before time t0 shows the standby operation of the charge pump circuit 100. The time period between time t0 and t1 shows the normal operation of the charge pump circuit 100. In this example, where each pump stage circuit 112 provides a voltage boost of approximately 2.2V, the voltage level at the output of the charge pump stage circuit 112 is: V S1 =5.2V, V S2 =7.4V, V S3 =9.6V, V S4 =11.8V, V S5 =14V and V S6 =Vout=16V. During this normal operating period, the discharge circuit 102 is disabled.

[0044] At time t1, discharge circuit 102 is activated, and discharge control circuit 103 begins discharge and clamping operations. Discharge controller circuit 101 is given a first control signal DEn_1 (reference numeral 300, see also figure) applied to the corresponding first clock gate circuit 104(1) and first switch discharge circuit 106(1). Figure 4 Assume that the pumping operation of the first charge pump stage circuit 112(1) is disabled because the clock is blocked by the first clock gate circuit 104(1). The first switch discharge circuit 106(1) is enabled to operate, and the voltage at the output of the first charge pump stage circuit 112(1) is discharged and clamped to be equal to the input voltage Vin = 3V.

[0045] At the next leading edge of the discharge clock signal DisClk, which occurs at time t2, the second control signal DEn_2 (reference numeral 302) is asserted and applied to the corresponding second clock gate circuit 104(2) and the second switch discharge circuit 106(2). Because the clock is blocked by the second clock gate circuit 104(2), the pumping operation of the second charge pump stage circuit 112(2) is disabled. The second switch discharge circuit 106(2) is enabled, and the voltage at the output of the second charge pump stage circuit 112(2) is discharged and clamped to be equal to the input voltage Vin = 3V. Since the voltage at the output of the second charge pump stage circuit 112(2) is the input voltage of the remaining series-coupled charge pump stage circuits 112, and since each of these charge pump stage circuits 112 continues to receive its complementary clock signal, it should be noted that the output voltages of the remaining charge pump stage circuits 112 will all drop (reference numeral 312) to the extent that depends on the input voltage at the third charge pump stage circuit 112(3).

[0046] At the next leading edge of the discharge clock signal DisClk, which occurs at time t3, the third control signal DEn_3 (reference numeral 304) is asserted and applied to the corresponding third clock gate circuit 104(3) and the third switch discharge circuit 106(3). Because the clock is blocked by the third clock gate circuit 104(3), the pumping operation of the third charge pump stage circuit 112(3) is disabled. The third switch discharge circuit 106(3) is enabled, and the voltage at the output of the third charge pump stage circuit 112(3) is discharged and clamped to be equal to the input voltage Vin = 3V. Since the voltage at the output of the third charge pump stage circuit 112(3) is the input voltage of the remaining series-coupled charge pump stage circuits 112, and since each of these charge pump stage circuits 112 continues to receive its complementary clock signal, it should be noted that the output voltages of the remaining charge pump stage circuits 112 will all drop (reference numeral 314) to the extent that depends on the input voltage at the fourth charge pump stage circuit 112(4).

[0047] At the next leading edge of the discharge clock signal DisClk, which occurs at time t4, the fourth control signal DEn_4 (reference numeral 306) is asserted and applied to the corresponding fourth clock gate circuit 104(4) and fourth switch discharge circuit 106(4). Because the clock is blocked by the fourth clock gate circuit 104(4), the pumping operation of the fourth charge pump stage circuit 112(4) is disabled. The fourth switch discharge circuit 106(4) is enabled, and the voltage at the output of the fourth charge pump stage circuit 112(4) is discharged and clamped to be equal to the input voltage Vin = 3V. Since the voltage at the output of the fourth charge pump stage circuit 112(4) is the input voltage of the remaining series-coupled charge pump stage circuits 112, and since each of these charge pump stage circuits 112 continues to receive its complementary clock signal, it should be noted that the output voltages of the remaining charge pump stage circuits 112 will all drop (reference numeral 316) to the extent that depends on the input voltage at the fifth charge pump stage circuit 112(5).

[0048] The fifth control signal DEn_5 (see attached figure 308, also referencing the previous one) appears at time t5, following the next leading edge of the discharge clock signal DisClk. Figure 4 The clock signal is asserted and applied to the corresponding fifth clock gate circuit 104(5) and fifth switch discharge circuit 106(5). Because the clock is blocked by the fifth clock gate circuit 104(1), the pumping operation of the fifth charge pump stage circuit 112(5) is disabled. The fifth switch discharge circuit 106(5) is enabled, and the voltage at the output of the fifth charge pump stage circuit 112(5) is discharged and clamped to be equal to the input voltage Vin = 3V. Because the voltage at the output of the fifth charge pump stage circuit 112(5) is the input voltage of the sixth charge pump stage circuit 112(6), and because the charge pump stage circuit 112 continues to receive the complementary clock signal, it should be noted that the output voltage of the sixth charge pump stage circuit 112 drops (reference numeral 318) to a degree dependent on the input voltage at the sixth charge pump stage circuit 112(6).

[0049] The sixth control signal DEn_6 (see attached figure 310, also referencing the next leading edge of the discharge clock signal DisClk, which appears at time t6) is generated at the next leading edge of the discharge clock signal DisClk. Figure 4The clock signal is asserted and applied to the corresponding sixth clock gate circuit 104(6) and sixth switch discharge circuit 106(6). Because the clock is blocked by the sixth clock gate circuit 104(6), the pumping operation of the sixth charge pump stage circuit 112(6) is disabled. The sixth switch discharge circuit 106(6) is enabled, and the voltage at the output of the sixth charge pump stage circuit 112(6) is discharged and clamped to be equal to the input voltage Vin = 3V. At this time, the complete discharge of the charge pump circuit 100 is completed, in which the output voltage at all charge pump stage circuits 112 is clamped to the level of the input voltage Vin.

[0050] While the invention has been illustrated and described in detail in the accompanying drawings and foregoing description, such illustrations and descriptions are intended to be illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention upon study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit for controlled discharge, comprising: A charge pump circuit includes multiple charge pump stages coupled in series, wherein each charge pump stage is controlled by a clock signal; as well as A discharge circuit is configured to discharge the charge pump circuit. The discharge circuit includes: Multiple switch-discharge circuits, wherein each switch-discharge circuit is coupled to the output of a corresponding charge pump stage circuit in the charge pump stage circuit, and is configured to discharge the output when actuated; as well as The discharge control circuit is configured to sequentially actuate each of the plurality of switching discharge circuits during a discharge time period, and is configured to block the clock signal for the corresponding charge pump stage circuit in the charge pump stage circuit, while actuating the switching discharge circuit for the same corresponding charge pump stage circuit in the charge pump stage circuit.

2. The circuit according to claim 1, wherein the sequential actuation of each switch discharge circuit in the switch discharge circuit is controlled by a discharge clock signal.

3. The circuit of claim 2, wherein the discharge clock signal has a period of sufficient length to ensure that the output of a given charge pump stage circuit in the charge pump stage circuit is fully discharged to the input voltage level before a subsequent charge pump stage circuit in the charge pump stage circuit is sequentially actuated by the switching discharge circuit.

4. The circuit of claim 1, wherein the discharge circuit further comprises a plurality of clock gating circuits, wherein each clock gating circuit is configured to selectively transmit a charge pump clock signal to a corresponding charge pump stage circuit in the charge pump stage circuit, and wherein the discharge control circuit is configured to control the clock gating circuit to block the charge pump clock signal for the corresponding charge pump stage circuit in the charge pump stage circuit, while actuating the switching discharge circuit for the same corresponding charge pump stage circuit in the charge pump stage circuit.

5. The circuit of claim 4, wherein the discharge control circuit controls the sequential actuation of the switching discharge circuit during the discharge time period, such that the output of a given charge pump stage circuit in the charge pump stage circuit is fully discharged to the input voltage level before a subsequent charge pump stage circuit in the charge pump stage circuit is discharged.

6. The circuit according to claim 4, wherein the charge pump circuit is a positive voltage charge pump.

7. The circuit according to claim 4, wherein the charge pump circuit is a negative voltage charge pump.

8. The circuit according to claim 4, further comprising: A clock generator circuit is configured to generate the charge pump clock signal; A sensing circuit is configured to sense the voltage at the output of the last charge pump stage circuit in the plurality of charge pump stage circuits, and to generate a feedback voltage from the sensed voltage. The clock generator circuit is activated to operate when the feedback voltage is less than the reference voltage.

9. The circuit according to claim 8, wherein the reference voltage is a bandgap voltage.

10. The circuit of claim 1, wherein each switch discharge circuit comprises: First power supply node; Second power supply node; Multiple transistors having a source-drain path coupled in series between the first power supply node and the second power supply node, wherein the multiple transistors include: A first p-channel transistor and a second p-channel transistor are coupled in series between the first power supply node and the first intermediate node, wherein the sources of the first p-channel transistor and the second p-channel transistor are connected to the output of a corresponding charge pump stage circuit in the charge pump stage circuit, and wherein the gate of the first p-channel transistor is connected to the first intermediate node, and the gate of the second p-channel transistor is connected to the first power supply node. A first n-channel transistor is coupled between the first intermediate node and the second intermediate node, and has a gate connected to the first power supply node; and A second n-channel transistor is coupled between the second intermediate node and the second power supply node, and has a gate connected to receive an actuation control signal output by the discharge control circuit; and A third p-channel transistor is coupled between the first power supply node and the second intermediate node, and has a gate connected to receive the actuation control signal output by the discharge control circuit.

11. The circuit of claim 10, wherein the discharge control circuit controls the sequential actuation of the switching discharge circuit during the discharge time period, such that the output of a given charge pump stage circuit in the charge pump stage circuit is fully discharged to the input voltage level before a subsequent charge pump stage circuit in the charge pump stage circuit is discharged.

12. The circuit of claim 10, wherein the charge pump circuit is a positive voltage charge pump.

13. The circuit of claim 10, wherein the charge pump circuit is a negative voltage charge pump.

14. The circuit of claim 1, wherein each switch discharge circuit comprises: First power supply node; Second power supply node; Multiple transistors having a source-drain path coupled in series between the first power supply node and the second power supply node, wherein the multiple transistors include: A first p-channel transistor and a second p-channel transistor are coupled in series between the first power supply node and the first intermediate node, wherein the sources of the first p-channel transistor and the second p-channel transistor are connected to the output of a corresponding charge pump stage circuit in the charge pump stage circuit, and wherein the gate of the first p-channel transistor is connected to the first intermediate node, and the gate of the second p-channel transistor is connected to the first power supply node. A first n-channel transistor is coupled between the first intermediate node and the second intermediate node, and has a gate that is connected to the first power supply node. A second n-channel transistor, coupled between the second intermediate node and the third intermediate node, and having a gate connected to receive an actuation control signal output by the discharge control circuit; and A third n-channel transistor is coupled between the third intermediate node and the second power supply node, and has a gate connected to receive the actuation control signal output by the discharge control circuit. A third p-channel transistor is coupled between the first power supply node and the second intermediate node, and has a gate connected to receive the actuation control signal output by the discharge control circuit; and A fourth p-channel transistor is coupled between the first power supply node and the third intermediate node, and has a gate connected to receive the actuation control signal output by the discharge control circuit.

15. The circuit of claim 14, wherein the discharge control circuit controls the sequential actuation of the switching discharge circuit during the discharge time period, such that the output of a given charge pump stage circuit in the charge pump stage circuit is fully discharged to the input voltage level before a subsequent charge pump stage circuit in the charge pump stage circuit is discharged.

16. The circuit of claim 14, wherein the charge pump circuit is a positive voltage charge pump.

17. The circuit of claim 14, wherein the charge pump circuit is a negative voltage charge pump.

18. The circuit of claim 1, wherein the discharge control circuit controls the sequential actuation of the switching discharge circuit during the discharge time period, such that the output of a given charge pump stage circuit in the charge pump stage circuit is fully discharged to the input voltage level before a subsequent charge pump stage circuit in the charge pump stage circuit is discharged.

19. The circuit of claim 1, wherein the sequential actuation of the switching discharge circuit is controlled by a discharge clock signal, and wherein the discharge control circuit comprises: A control circuit is configured to generate a first actuation signal and the discharge clock signal, wherein the first actuation signal is applied to control the actuation of a first switching discharge circuit in the switching discharge circuit; as well as The trigger circuit is clock-controlled by the discharge clock signal and has an input configured to receive the first actuation signal and an output configured to generate a second actuation signal, which is applied to control the actuation of the second switching discharge circuit in the switching discharge circuit.

20. The circuit of claim 19, wherein the discharge control circuit controls the sequential actuation of the switching discharge circuit during the discharge time period, such that the output of a given charge pump stage circuit in the charge pump stage circuit is fully discharged to the input voltage level before a subsequent charge pump stage circuit in the charge pump stage circuit is discharged.

21. The circuit of claim 19, wherein the charge pump circuit is a positive voltage charge pump.

22. The circuit of claim 19, wherein the charge pump circuit is a negative voltage charge pump.

23. The circuit of claim 19, wherein the first switch discharge circuit in the switch discharge circuit is coupled to the output of the corresponding first charge pump stage circuit in the charge pump stage circuit, and wherein the second switch discharge circuit in the switch discharge circuit is coupled to the output of the corresponding second charge pump stage circuit in the charge pump stage circuit, the corresponding second charge pump stage circuit being connected in series with the first charge pump stage circuit in the charge pump stage circuit.

24. The circuit according to claim 1, wherein the charge pump circuit is a positive voltage charge pump.

25. The circuit according to claim 1, wherein the charge pump circuit is a negative voltage charge pump.

26. A circuit for controlled discharge, comprising: A charge pump circuit, including a first charge pump stage circuit that is coupled in series with a second charge pump stage circuit; as well as A discharge circuit is configured to discharge the charge pump circuit. The discharge circuit includes: A first switching discharge circuit is coupled to a first output of the first charge pump stage circuit and is configured to discharge the first output when actuated. A second switching discharge circuit is coupled to the second output of the second charge pump stage circuit and configured to discharge the second output when actuated; and A discharge control circuit is configured to actuate the first switch discharge circuit to discharge the first output, and then, after the first output has been fully discharged to the input voltage level, actuate the second switch discharge circuit to discharge the second output to the input voltage level. The discharge circuit further includes: The first clock gating circuit is configured to selectively pass the charge pump clock signal to the first charge pump stage circuit. The second clock gating circuit is configured to selectively pass the charge pump clock signal to the second charge pump stage circuit; and The discharge control circuit is further configured to control the first clock gating circuit to block the charge pump clock signal when the first switch discharge circuit is actuated, and to control the second clock gating circuit to block the charge pump clock signal when the second switch discharge circuit is actuated.

27. The circuit of claim 26, wherein the charge pump circuit is a positive voltage charge pump.

28. The circuit of claim 26, wherein the charge pump circuit is a negative voltage charge pump.

29. The circuit according to claim 26, wherein the time length between the actuation of the first switch discharge circuit and the actuation of the second switch discharge circuit is controlled by the period of the discharge clock signal.

30. The circuit according to claim 26, further comprising: A clock generator circuit is configured to generate the charge pump clock signal; The sensing circuit is configured to sense the voltage at the output of the last charge pump stage circuit and generate a feedback voltage from the sensed voltage. The clock generator circuit is activated to operate when the feedback voltage is less than the reference voltage.

31. The circuit of claim 30, wherein the reference voltage is a bandgap voltage.

32. The circuit of claim 26, wherein each of the first switch discharge circuit and the second switch discharge circuit comprises: First power supply node; Second power supply node; Multiple transistors having a source-drain path coupled in series between the first power supply node and the second power supply node, wherein the multiple transistors include: A first p-channel transistor and a second p-channel transistor are coupled in series between the first power supply node and the first intermediate node, wherein the source of the first p-channel transistor and the second p-channel transistor are connected to the output of a corresponding charge pump stage circuit in the charge pump stage circuit, and wherein the gate of the first p-channel transistor is connected to the first intermediate node, and the gate of the second p-channel transistor is connected to the first power supply node. A first n-channel transistor is coupled between the first intermediate node and the second intermediate node, and has a gate connected to the first power supply node; and A second n-channel transistor is coupled between the second intermediate node and the second power supply node, and has a gate connected to receive an actuation control signal output by the discharge control circuit; and A third p-channel transistor is coupled between the first power supply node and the second intermediate node, and has a gate connected to receive the actuation control signal output by the discharge control circuit.

33. The circuit of claim 26, wherein each of the first switch discharge circuit and the second switch discharge circuit comprises: First power supply node; Second power supply node; Multiple transistors having a source-drain path coupled in series between the first power supply node and the second power supply node, wherein the multiple transistors include: A first p-channel transistor and a second p-channel transistor are coupled in series between the first power supply node and the first intermediate node, wherein the source of the first p-channel transistor and the second p-channel transistor are connected to the output of a corresponding charge pump stage circuit in the charge pump stage circuit, and wherein the gate of the first p-channel transistor is connected to the first intermediate node, and the gate of the second p-channel transistor is connected to the first power supply node. A first n-channel transistor is coupled between the first intermediate node and the second intermediate node, and has a gate that is connected to the first power supply node. A second n-channel transistor, coupled between the second intermediate node and the third intermediate node, and having a gate connected to receive an actuation control signal output by the discharge control circuit; and A third n-channel transistor is coupled between the third intermediate node and the second power supply node, and has a gate connected to receive the actuation control signal output by the discharge control circuit. A third p-channel transistor is coupled between the first power supply node and the second intermediate node, and has a gate connected to receive the actuation control signal output by the discharge control circuit; and A fourth p-channel transistor is coupled between the first power supply node and the third intermediate node, and has a gate connected to receive the actuation control signal output by the discharge control circuit.

34. The circuit of claim 26, wherein the discharge control circuit comprises: A control circuit is configured to generate a first actuation signal, wherein the first actuation signal is applied to control the actuation of the first switch discharge circuit; A delay circuit is configured to generate a second actuation signal by delaying the first actuation signal, wherein the second actuation signal is applied to control the actuation of the second switch discharge circuit.

35. The circuit of claim 34, wherein the delay circuit is a trigger circuit.

36. The circuit of claim 34, wherein the charge pump circuit is a positive voltage charge pump.

37. The circuit of claim 34, wherein the charge pump circuit is a negative voltage charge pump.

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