Two-stage DC-DC converter for pulse load and control method thereof

Abstract

The present invention discloses a two-stage DC-DC converter applied to pulse loads and its control method. The main circuit topology includes a front-stage synchronous rectifier TL-Buck converter, a rear-stage DCX-LLC converter, and a pulse load circuit. Starting from the DC converter under pulse load conditions, a steady-state controller based on voltage decoupling double closed-loop control is designed under steady-state load conditions, and a transient controller based on duty cycle extension mode is designed under pulse load conditions. Taking the output voltage v C3 and the inductor current i L1 of the converter as the comparison with the preset critical state value as the switching condition of the steady / transient controller, and comparing the energy storage capacitor capacity expressions of the single-stage and two-stage architecture pulse load DC converters to illustrate the power density advantage of the two-stage architecture. The present invention can simultaneously control the output voltage of the synchronous rectifier TL-Buck and the flying capacitor voltage, and has more advantages in efficiency and power density.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, in particular to a two-stage DC-DC converter applied to pulse loads and a control method thereof. Background Art

[0002] In power supply systems such as radars and transmitters, more load devices exhibit pulse characteristics, which places higher requirements on the dynamic response performance of the power supply. The output voltage over / undershoot amplitude of the power supply under pulse load conditions must be as low as possible, and the dynamic recovery time must be as short as possible to ensure the normal operation and safety of the circuit. Existing pulse load DC converters have the following three deficiencies:

[0003] (1) The existing method of controlling the pulse load DC converter is a single control method, that is, the same control strategy is used when the load is in a steady state and in a pulse load transient state. The change rate of the inductor current is consistent, and no corresponding controller is designed for the characteristics of the pulse load. The dynamic response performance of the pulse load DC converter needs to be optimized;

[0004] (2) The pulse load DC converter of the existing method uses a single-stage architecture, and the energy storage capacitor is located on the output low voltage side. Since the voltage is low, the energy storage capacitor has a large capacity, and the power density of the pulse load DC converter needs to be improved;

[0005] (3) The pulse-loaded DC converter of the existing method uses a single-stage architecture. As the voltage difference between the input and output increases, the efficiency of the converter will further decrease. The efficiency of the pulse-loaded DC converter needs to be improved. Summary of the invention

[0006] The present invention proposes a two-stage DC-DC converter for pulse load and a control method thereof, which can not only realize voltage stabilization of the intermediate bus voltage and the flying capacitor voltage under steady-state load conditions to ensure the normal operation of the converter, but also realize the improvement of the inductor current change rate of the front-stage converter under pulse load transient conditions; while reducing the over / undershoot amplitude of the energy storage capacitor voltage, shorten the dynamic recovery time, and optimize the dynamic response performance of the converter.

[0007] The technical solution to achieve the purpose of the present invention is: a two-stage DC-DC converter applied to pulse loads, the main circuit topology includes a front-stage synchronous rectification TL-Buck converter, a rear-stage DCX-LLC converter and a pulse load circuit, wherein:

[0008] The front-stage synchronous TL-Buck converter is used to provide power to the intermediate bus energy storage capacitor and provide average power to the output load; the sampling v C3 Control Q1~Q4; Under pulse load conditions, according to vC3 and i L1 Switch control mode in real time;

[0009] The rear-stage DCX-LLC converter is used for electrical isolation and voltage conversion, and transmits the average power and pulse power provided by the front-stage converter and the intermediate bus energy storage capacitor to the output load;

[0010] The pulse load circuit simulates steady-state load and pulse load conditions through a Q7 with a given preset switching frequency and duty cycle and two power resistors R1 and R2. The load resistor at the simulated output end switches between full load and half load to achieve a pulse load effect.

[0011] Among them, v C3 is the intermediate bus voltage between the front-stage and rear-stage converters, Q1 and Q2 are the main power switches of the front-stage converter, Q3 and Q4 are the synchronous rectification switches of the front-stage converter, and i L1 It is the filter inductor current of the previous converter, Q7 is the pulse switch, R1 is the steady-state load, and R2 is the pulse load.

[0012] A control method for a two-stage DC-DC converter applied to a pulse load, based on the two-stage DC-DC converter applied to a pulse load, comprises the following steps:

[0013] Step 1: According to the voltage decoupling dual closed-loop control small signal model of TL-Buck, the output voltage duty cycle command-output voltage transfer function and the flying capacitor voltage duty cycle command-flying capacitor voltage transfer function are given;

[0014] Step 2: Sample v C3 and i L1 , according to the comparison between the two and the critical state value, determine the scheme of switching between the steady-state / transient controller and the control logic of the transient controller;

[0015] Step 3: Determine the energy storage capacitor capacity expression of the pulse load DC converter of the single-stage and two-stage architectures, and explain the power density advantage of the two-stage architecture.

[0016] Compared with the prior art, the present invention has the following significant advantages: (1) the two control schemes can not only stabilize the intermediate bus voltage and the flying capacitor voltage under steady-state load conditions to ensure the normal operation of the converter, but also improve the rate of change of the inductor current of the front-stage converter under pulse load transient conditions, thereby reducing the over / undershoot amplitude of the energy storage capacitor voltage and shortening its dynamic recovery time, thereby optimizing the dynamic response performance of the converter; (2) the two-stage type has a higher power density than the pulse load DC converter with a single-stage architecture; (3) the two-stage type has a higher efficiency than the pulse load DC converter with a single-stage architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The invention is a main circuit structure of a two-stage DC-DC converter applied to pulse loads.

[0018] Figure 2 This is the block diagram of voltage decoupling dual closed-loop control for a two-stage converter.

[0019] Figure 3 This is a diagram showing the effect of closed-loop control on the flying capacitor voltage regulation when the input voltage fluctuates.

[0020] Figure 4 This is the steady / transient switching control block diagram of the two-stage converter.

[0021] Figure 5 This is the key waveform timing during the load loading process of the two-stage converter.

[0022] Figure 6 This is the key waveform timing during the load unloading process of the two-stage converter.

[0023] Figure 7 Effect of the steady-state controller on the dynamic response of the converter at a pulse repetition frequency of 1kHz.

[0024] Figure 8 Effect of transient controller on the dynamic response of converter at 1kHz pulse repetition frequency.

[0025] Fig. 9 Figure 2 shows the efficiency-input voltage relationship for single-stage and two-stage architectures. DETAILED DESCRIPTION

[0026] The present invention discloses a two-stage DC-DC converter for pulse load and a control method thereof. The invention takes the DC converter under pulse load condition as the starting point, designs a steady-state controller based on voltage decoupling double closed-loop control under steady-state load condition, designs a transient controller based on duty cycle expansion mode under pulse load condition, and outputs a voltage v of the previous converter. C3 and the inductor current i L1 The result obtained by comparing with the size of the preset critical state value is used as the switching condition of the steady / transient controller. The energy storage capacitor capacity expression of the pulse load DC converter of the single-stage and two-stage architectures is compared to illustrate the power density advantage of the two-stage architecture.

[0027] The present invention discloses a two-stage DC-DC converter for pulse loads, wherein the main circuit topology includes a front-stage synchronous rectification TL-Buck converter, a rear-stage DCX-LLC converter and a pulse load circuit, wherein:

[0028] The front-stage synchronous TL-Buck converter is used to provide power to the intermediate bus energy storage capacitor and provide average power to the output load; the sampling v C3 Control Q1~Q4; Under pulse load conditions, according to v C3 and i L1 Switch control mode in real time;

[0029] The rear-stage DCX-LLC converter is used for electrical isolation and voltage conversion, and transmits the average power and pulse power provided by the front-stage converter and the intermediate bus energy storage capacitor to the output load;

[0030] The pulse load circuit simulates steady-state load and pulse load conditions through a Q7 with a given preset switching frequency and duty cycle and two power resistors R1 and R2. The load resistor at the simulated output end switches between full load and half load to achieve a pulse load effect.

[0031] Among them, v C3 is the intermediate bus voltage between the front-stage and rear-stage converters, Q1 and Q2 are the main power switches of the front-stage converter, Q3 and Q4 are the synchronous rectification switches of the front-stage converter, and i L1 is the filter inductor current of the previous converter, Q7 is a pulse switch, R1 is a steady-state load, and R2 is a pulse load

[0032] As a specific embodiment, the front-stage synchronous TL-Buck converter includes an input voltage source V in , input capacitor C1, front-stage flying capacitor C2, front-stage main power switches Q1, Q2, front-stage synchronous rectification switches Q3, Q4, front-stage filter inductor L1, intermediate bus energy storage capacitor C3; the drain of Q1 and one end of C1 are connected to V in The source of Q1 and the drain of Q2 are connected to one end of C2, the source of Q2 and the drain of Q3 are connected to one end of L1, the source of Q3 and the drain of Q4 are connected to the other end of C2, the other end of L1 and one end of C3 are connected to the output end of the previous converter, and the other end of C3 is connected to the source of Q4 and V in The other end of C1 and the other end of C1 are connected to a common ground PGND of the converter; in one switching cycle of the front-stage synchronous TL-Buck converter, V in C2 is charged through Q1~Q4 and the chopped voltage is transmitted to the output end. The LC filter circuit composed of L1 and C3 filters the chopped voltage into a steady-state DC voltage with ripple and provides it to C3 and the output end of the previous converter.

[0033] As a specific embodiment, the rear-stage DCX-LLC converter includes rear-stage main power switches Q5 and Q6, a rear-stage resonant inductor L2, a rear-stage resonant capacitor C4, a rear-stage transformer T1, rear-stage rectifier diodes D1-D4, and a rear-stage filter capacitor C5; the Q5 drain is connected to one end of the front-stage converter C3, the Q5 source and the Q6 drain are commonly connected to one end of C4, the Q6 source and one end of L2 are commonly connected to a common ground PGND of the converter, the other end of C4 is connected to one end of the primary side of T1, the other end of L2 is connected to the other end of the primary side of T1, the D1 anode and the D2 cathode are commonly connected to one end of the secondary side of T1, the D3 anode and the D4 cathode are commonly connected to the other end of the secondary side of T1, the D1 cathode and the D3 cathode are commonly connected to one end of C5, the D2 anode and the D4 anode and the other end of C5 are commonly connected to another common ground SGND of the converter; the rear-stage DCX-LLC The converter uses the energy transmitted from the previous synchronous TL-Buck converter to form a 1 / 2 gain through the half-bridge composed of Q5 and Q6, and then forms a resonant cavity gain through the resonant circuit composed of C4, L2 and the primary side of T1. The AC signal passes through the rectifier tube composed of D1~D4, and then is filtered by C5 to transmit the energy to the pulse load circuit.

[0034] As a specific embodiment, the pulse load circuit includes the steady-state load R1, the pulse load R2, and the pulse switch Q7; one end of R1 and the drain of Q7 are commonly connected to one end of the output end of the subsequent converter, the source of Q7 is connected to one end of R2, and the other end of R2 and the other end of R1 are commonly connected to the other end of the output end of the subsequent converter and another common ground SGND of the converter; under steady-state conditions, Q7 is in an off state, and the load in the circuit only contains R1; under pulse load conditions, Q7 performs switching operation with a fixed pulse frequency and duty cycle, and when Q7 is in an on state, the equivalent resistance of the pulse load circuit switches between R1 and R1 in parallel with R2.

[0035] The present invention provides a control method for a two-stage DC-DC converter applied to a pulse load, based on the two-stage DC-DC converter applied to a pulse load, comprising the following steps:

[0036] Step 1: According to the voltage decoupling dual closed-loop control small signal model of TL-Buck, the output voltage duty cycle command-output voltage transfer function and the flying capacitor voltage duty cycle command-flying capacitor voltage transfer function are given;

[0037] Step 2: Sample v C3 and i L1 , according to the comparison between the two and the critical state value, determine the scheme of switching between the steady-state / transient controller and the control logic of the transient controller;

[0038] Step 3: Determine the energy storage capacitor capacity expression of the pulse load DC converter of the single-stage and two-stage architectures, and explain the power density advantage of the two-stage architecture.

[0039] As a specific embodiment, in step 1, the TL-Buck output voltage duty cycle instruction-output voltage transfer function and the flying capacitor voltage duty cycle instruction-flying capacitor voltage transfer function are respectively:

[0040] (1.1) The TL-Buck output voltage duty cycle command-output voltage transfer function is:

[0041]

[0042]

[0043] Said is the output voltage duty cycle command-output voltage transfer function of the previous converter, is the output voltage closed-loop weight, V in is the input voltage source, V C3 is the intermediate bus capacitor voltage, M is the impedance coefficient of the previous converter, Z in_DCX-LLC is the input impedance of the subsequent converter, C3 is the intermediate bus capacitor, R C3 is the equivalent series resistance of the intermediate bus capacitor, L1 is the pre-filter inductor, R L1 is the equivalent DC resistance of the front-stage filter inductor;

[0044] (1.2) TL-Buck flying capacitor voltage duty cycle command - flying capacitor voltage transfer function:

[0045]

[0046] Said is the flying capacitor voltage duty cycle instruction-flying capacitor voltage transfer function of the previous converter, is the closed-loop weight of the flying capacitor voltage, C2 is the voltage of the previous flying capacitor, V s is the sawtooth wave amplitude at the inverting input of the comparator.

[0047] As a specific embodiment, the scheme of switching the controller between the steady-state controller and the transient controller in step 2, and the control logic of the transient controller are respectively:

[0048] (2.1) Scheme for switching between steady-state and transient controllers:

[0049] ① During the load loading process, the start and end conditions of the duty cycle extended mode transient control are:

[0050]

[0051] Said is the intermediate bus voltage critical value for the start of transient load control, i L1 is the inductor current of the previous converter, I L1_over is the critical value of the inductor current of the preceding converter at the end of the loading transient control; after the loading start condition is met, the control mode of the converter is switched from the voltage decoupling double closed-loop control mode to the transient control mode based on the duty cycle extension mode; after the loading end condition is met, the control mode of the converter is switched from the transient control mode based on the duty cycle extension mode to the voltage decoupling double closed-loop control mode;

[0052] ② During load unloading, the start and end conditions of the duty cycle extended mode transient control are:

[0053]

[0054] Said is the intermediate bus voltage critical value for the start of unloading transient control, I L1_under is the critical value of the inductor current of the preceding converter at the end of the unloading transient control; after the unloading start condition is met, the control mode of the converter is switched from the voltage decoupling double closed-loop control mode to the transient control mode based on the duty cycle extension mode; after the unloading end condition is met, the control mode of the converter is switched from the transient control mode based on the duty cycle extension mode to the voltage decoupling double closed-loop control mode;

[0055] (2.2) Control logic of transient controller:

[0056] ① During the load loading process, when the converter meets the loading start condition but does not meet the loading end condition, under the transient control based on the duty cycle extended mode, the switching logic of Q1~Q4 is:

[0057]

[0058] Said To load the Q1 drive logic signal during transient control, To load the Q2 drive logic signal during transient control, To load the Q3 drive logic signal during transient control, is the Q4 driving logic signal during the loading transient process; during the loading transient control process, the switching logic of Q1 to Q4 is that Q1 and Q2 remain turned on, and Q3 and Q4 remain turned off;

[0059] ② During load unloading, when the converter meets the unloading start condition and does not meet the unloading end condition, under transient control based on the duty cycle extended mode, the switching logic of Q1~Q4 is:

[0060]

[0061] Said To unload the Q1 drive logic signal during the transient process, To unload the Q2 drive logic signal during transient control, To unload the Q3 drive logic signal during transient control, It is the Q4 driving logic signal in the unloading transient control process; in the unloading transient process, the switching logic of Q1 to Q4 is that Q1 and Q2 remain off, and Q3 and Q4 remain on.

[0062] As a specific embodiment, the expressions of energy storage capacitor capacity of pulse load DC converters of single-stage and two-stage architectures in step 3, and the comparison of the two capacities are respectively:

[0063] (3.1) Expression of single-stage and two-stage energy storage capacitor capacity:

[0064]

[0065]

[0066] The C o_s For the single-stage architecture output end energy storage capacitor, I o_peak is the peak value of the load current, D pulse is the pulse duty cycle, Δv o is the output voltage ripple, f pulse is the pulse repetition frequency, V o is the output voltage, is the intermediate bus voltage ripple;

[0067] (3.2) Comparison of energy storage capacitor capacity of pulse load DC converters with two-stage and single-stage architectures:

[0068]

[0069] The K is the ratio of the energy storage capacitor capacity of the pulse load DC converter of the two-stage structure to that of the single-stage structure, and n is the transformer ratio of the rear-stage converter of the two-stage structure.

[0070] The two-stage DC-DC converter topology for pulse loads has the following three advantages:

[0071] (1) The control method of the two-stage DC-DC converter applied to the pulse load uses voltage decoupling dual closed-loop control when the load is in a steady state, and simultaneously stabilizes the intermediate bus voltage and the flying capacitor voltage of the front-stage converter. When the load is in a pulse load transient state, transient control based on the duty cycle expansion mode is used, thereby improving the inductor current change rate of the front-stage converter, achieving a reduction in the over / undershoot amplitude of the energy storage capacitor voltage and a shortening of the dynamic recovery time, thereby optimizing the dynamic response performance of the pulse load DC converter;

[0072] (2) In the two-stage architecture of the two-stage DC-DC converter applied to pulse loads, the energy storage capacitor is located on the high-voltage side of the intermediate bus. Since the voltage is higher than the output end, the energy storage capacitor has a smaller capacity, thereby improving the power density of the pulse load DC converter;

[0073] (3) The two-stage architecture of the two-stage DC-DC converter applied to pulse loads improves the efficiency of pulse load DC converters in power supply systems such as radars and transmitters where the input and output voltage difference is ten times or more.

[0074] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0075] Example

[0076] The present invention provides a solution for optimizing the dynamic response performance of a DC converter under pulse load conditions. The steady-state controller can simultaneously control the output voltage and flying capacitor voltage of the synchronous rectifier TL (Three Level)-Buck. The transient controller can reduce the voltage fluctuation amplitude of the energy storage capacitor and accelerate its dynamic recovery time when the pulse load is in action. The design scheme of the synchronous rectifier TL-Buck + DCX (DC Transformer)-LLC steady-state and transient controller is provided. In applications where the input and output voltage difference is large, the two-stage architecture has a greater efficiency advantage than the single-stage architecture. At the same time, the two-stage architecture transfers the energy storage capacitor to the high-voltage side of the intermediate bus, which has a greater power density advantage.

[0077] Figure 1 The main circuit structure of the two-stage DC-DC converter applied to pulse loads. The main circuit topology mainly includes the front-stage synchronous rectification TL-Buck converter, the rear-stage DCX-LLC converter and the pulse load circuit. The front-stage converter adopts synchronous rectification technology to improve the overall efficiency. The intermediate bus voltage v is sampled under steady-state conditions. C3 To control the switch tubes Q1~Q4, under the transient condition of pulse load, according to v C3 、i L1The steady / transient controller is switched to improve the rate of change of the inductor current of the front-stage converter to optimize the dynamic response performance of the converter. The rear-stage converter adopts open-loop fixed-frequency control. The intermediate bus voltage is raised through the transformer ratio to reduce the energy storage capacitor capacity and improve the power density. The DCX-LLC converter selected in the rear stage can achieve soft switching in the full range of service, which can improve the overall efficiency. In the pulse load circuit, the pulse repetition frequency and pulse duty cycle are preset for Q7, and the output load resistance changes between R1, R1 / / R2 to achieve the effect of pulse load.

[0078] According to the S-domain equivalent model of TL-Buck, the TL-Buck output voltage duty cycle command-output voltage transfer function is:

[0079]

[0080]

[0081] Said is the output voltage duty cycle command-output voltage transfer function of the previous converter, is the output voltage closed-loop weight, V in is the input voltage source, V C3 is the intermediate bus capacitor voltage, M is the impedance coefficient of the previous converter, Z in_DCX-LLC is the input impedance of the subsequent converter, C3 is the intermediate bus capacitor, R C3 is the equivalent series resistance of the intermediate bus capacitor, L1 is the pre-filter inductor, R L1 is the equivalent DC resistance of the pre-stage filter inductor.

[0082] According to the S-domain equivalent model of TL-Buck, the TL-Buck flying capacitor voltage duty cycle command-flying capacitor voltage transfer function can also be obtained:

[0083]

[0084] Said is the flying capacitor voltage duty cycle instruction-flying capacitor voltage transfer function of the previous converter, is the closed-loop weight of the flying capacitor voltage, C2 is the voltage of the previous flying capacitor, V s is the sawtooth wave amplitude at the inverting input of the comparator.

[0085] The block diagram of the TL-Buck converter voltage decoupling dual closed-loop control small signal model including the output voltage closed-loop and the flying capacitor voltage closed-loop is as follows: Figure 2 After voltage decoupling double closed-loop control, not only can the intermediate bus voltage v C3 Stable, flying capacitor voltage vC2 Stable. Figure 3 As shown in the figure, when the input voltage changes from 300V to 320V, the flying capacitor voltage can be stabilized at V within 1ms using closed-loop control. in / 2, that is, 160V, and the flying capacitor voltage without closed-loop control needs 40ms to stabilize at 160V.

[0086] During the load loading process, the start and end conditions of the duty cycle extended mode transient control are:

[0087]

[0088] Said is the intermediate bus voltage critical value for the start of transient load control, i L1 is the inductor current of the previous converter, I L1_over It is the critical value of the inductor current of the preceding converter at which the transient loading control ends.

[0089] During load unloading, the start and end conditions of the duty cycle extended mode transient control are:

[0090]

[0091] Said is the intermediate bus voltage critical value for the start of unloading transient control, I L1_under is the critical value of the inductor current of the preceding converter at the end of the unloading transient control. The steady / transient switching control block diagram during the above load loading and unloading process is shown in Figure 4 As shown, during the process of load loading or unloading, the intermediate bus voltage v C3 All of them determine the moment when the controller switches from steady state to transient state. The inductor current i L1 All of them determine the moment when the controller switches from transient state to steady state. Accordingly, during the process of load loading or unloading, the specific switching logic of Q1 to Q4 of the front-stage converter is as follows.

[0092] During the load loading process, when the converter meets the loading start condition but does not meet the loading end condition, under the transient control based on the duty cycle extended mode, the switching logic of Q1 to Q4 is:

[0093]

[0094] Said To load the Q1 drive logic signal during transient control, To load the Q2 drive logic signal during transient control, To load the Q3 drive logic signal during transient control, It is the logic signal that drives Q4 during the loading transient process.

[0095] During load unloading, when the converter meets the unloading start condition and does not meet the unloading end condition, under transient control based on the duty cycle extended mode, the switching logic of Q1 to Q4 is:

[0096]

[0097] Said To unload the Q1 drive logic signal during the transient process, To unload the Q2 drive logic signal during transient control, To unload the Q3 drive logic signal during transient control, It is the logic signal for driving Q4 during the unloading transient control process.

[0098] Figure 5 and Figure 6 The key waveform timing of the two-stage converter during loading and unloading are shown respectively, including the intermediate bus voltage v C3 , the inductor current i of the previous converter L1 As well as the switching logic signals of Q1~Q4, during load loading, Q1 and Q2 are turned on, and Q3 and Q4 are turned off; during load unloading, Q1 and Q2 are turned off, and Q3 and Q4 are turned on. Figure 7 and Figure 8 The v without and with transient control are shown respectively. C3 and i L1 In the simulation waveform under the pulse load transient condition, when the load is loaded, the inductor current change rate increases, the intermediate bus voltage drop amplitude decreases, and its dynamic recovery time is accelerated; when the load is unloaded, the intermediate bus voltage overshoot amplitude decreases, and its dynamic recovery time is accelerated.

[0099] The two-stage architecture also has a greater advantage in power density than the single-stage architecture. The energy storage capacitor capacity expression of the single-stage and two-stage architectures is:

[0100]

[0101]

[0102] The C o_s For the single-stage architecture output end energy storage capacitor, I o_peak is the peak value of the load current, D pulse is the pulse duty cycle, Δv o is the output voltage ripple, f pulse is the pulse repetition frequency, V o is the output voltage, is the intermediate bus voltage ripple.

[0103] Comparison of energy storage capacitor capacity of pulse load DC converters with two-stage and single-stage architectures:

[0104]

[0105] K is the ratio of the energy storage capacitor capacity of the pulse load DC converter of the two-stage and single-stage architectures, and n is the transformer ratio of the rear-stage converter of the two-stage architecture. The rear-stage converter adopts DCX-LLC, that is, the rear stage has a fixed input and output voltage gain n. By comparing the energy storage capacitor expressions of the single-stage and two-stage architectures, it can be seen that the energy storage capacitor capacity of the two-stage architecture can be set to 1 / n of that of the single-stage architecture. 2 , greatly improving the converter power density.

[0106] Finally, through Fig. 9 It can be seen that when the input voltage is close to the output voltage, the duty cycle of the pulse load DC converter of the single-stage architecture is relatively large, and its efficiency is higher than that of the two-stage architecture. As the input voltage increases, the efficiency of the single-stage architecture will gradually be surpassed by the two-stage architecture due to the limited duty cycle, and will be lower and lower than the two-stage architecture. In pulse load power supply applications such as radars and transmitters where the input and output voltage difference is large, the two-stage architecture has higher efficiency, and the front-stage TL-Buck is more suitable for high input voltage applications than other Buck family converters.

[0107] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A two-stage DC-DC converter for pulse loads, characterized in that: The main circuit topology includes a front-stage synchronous rectification TL-Buck converter, a rear-stage DCX-LLC converter and a pulse load circuit, where: The front-stage synchronous TL-Buck converter is used to provide power to the intermediate bus energy storage capacitor and provide average power to the output load; the sampling v C3 Control Q1~Q4; Under pulse load conditions, according to v C3 and i L1 Switch control mode in real time; The rear-stage DCX-LLC converter is used for electrical isolation and voltage conversion, and transmits the average power and pulse power provided by the front-stage converter and the intermediate bus energy storage capacitor to the output load; The pulse load circuit simulates steady-state load and pulse load conditions through a Q7 with a given preset switching frequency and duty cycle and two power resistors R1 and R2. The load resistor at the simulated output end switches between full load and half load to achieve a pulse load effect. Among them, v C3 is the intermediate bus voltage between the front-stage and rear-stage converters, Q1 and Q2 are the main power switches of the front-stage converter, Q3 and Q4 are the synchronous rectification switches of the front-stage converter, and i L1 is the filter inductor current of the previous converter, Q7 is a pulse switch, R1 is a steady-state load, and R2 is a pulse load; The two-stage DC-DC converter applied to pulse loads has the following working steps: Step 1: According to the voltage decoupling dual closed-loop control small signal model of TL-Buck, the output voltage duty cycle command-output voltage transfer function and the flying capacitor voltage duty cycle command-flying capacitor voltage transfer function are given; Step 2: Sample v C3 and i L1 , according to the comparison between the two and the critical state value, determine the scheme of switching between the steady-state / transient controller and the control logic of the transient controller; Step 3, determine the energy storage capacitor capacity expression of the pulse load DC converter of the single-stage and two-stage architectures, and explain the power density advantage of the two-stage architecture; The controller switching scheme between steady-state / transient controller in step 2 and the control logic of transient controller are: (2.1) Scheme for switching between steady-state and transient controllers: ① During the load loading process, the start and end conditions of the duty cycle extended mode transient control are: Said is the intermediate bus voltage critical value for the start of transient load control, i L1 is the inductor current of the previous converter, I L1_over is the critical value of the inductor current of the preceding converter at the end of the loading transient control; after the loading start condition is met, the control mode of the converter is switched from the voltage decoupling double closed-loop control mode to the transient control mode based on the duty cycle extension mode; after the loading end condition is met, the control mode of the converter is switched from the transient control mode based on the duty cycle extension mode to the voltage decoupling double closed-loop control mode; ② During load unloading, the start and end conditions of the duty cycle extended mode transient control are: Said is the intermediate bus voltage critical value for the start of unloading transient control, I L1_under is the critical value of the inductor current of the preceding converter at the end of the unloading transient control; after the unloading start condition is met, the control mode of the converter is switched from the voltage decoupling double closed-loop control mode to the transient control mode based on the duty cycle extension mode; after the unloading end condition is met, the control mode of the converter is switched from the transient control mode based on the duty cycle extension mode to the voltage decoupling double closed-loop control mode; (2.2) Control logic of transient controller: ① During the load loading process, when the converter meets the loading start condition but does not meet the loading end condition, under the transient control based on the duty cycle extended mode, the switching logic of Q1~Q4 is: Said To load the Q1 drive logic signal during transient control, To load the Q2 drive logic signal during transient control, To load the Q3 drive logic signal during transient control, is the Q4 driving logic signal during the loading transient process; during the loading transient control process, the switching logic of Q1 to Q4 is that Q1 and Q2 remain turned on, and Q3 and Q4 remain turned off; ② During load unloading, when the converter meets the unloading start condition and does not meet the unloading end condition, under transient control based on the duty cycle extended mode, the switching logic of Q1~Q4 is: Said To unload the Q1 drive logic signal during the transient process, To unload the Q2 drive logic signal during transient control, Drive Q3_light To unload the Q3 drive logic signal during transient control, Drive Q4_light It is the Q4 driving logic signal in the unloading transient control process; in the unloading transient process, the switching logic of Q1 to Q4 is that Q1 and Q2 remain off, and Q3 and Q4 remain on.

2. The two-stage DC-DC converter for pulse loads according to claim 1, characterized in that: The front-stage synchronous TL-Buck converter includes an input voltage source V in , input capacitor C1, front-stage flying capacitor C2, front-stage main power switches Q1, Q2, front-stage synchronous rectification switches Q3, Q4, front-stage filter inductor L1, intermediate bus energy storage capacitor C3; the drain of Q1 and one end of C1 are connected to V in The source of Q1 and the drain of Q2 are connected to one end of C2, the source of Q2 and the drain of Q3 are connected to one end of L1, the source of Q3 and the drain of Q4 are connected to the other end of C2, the other end of L1 and one end of C3 are connected to the output end of the previous converter, and the other end of C3 is connected to the source of Q4 and V in The other end and the other end of C1 are connected to a common ground PGND of the converter; The front-stage synchronous TL-Buck converter has a switching cycle, V in C2 is charged through Q1~Q4 and the chopped voltage is transmitted to the output end. The LC filter circuit composed of L1 and C3 filters the chopped voltage into a steady-state DC voltage with ripple and provides it to C3 and the output end of the previous converter.

3. The two-stage DC-DC converter for pulse loads according to claim 1, characterized in that: A rear-stage DCX-LLC converter comprises rear-stage main power switch tubes Q5 and Q6, a rear-stage resonant inductor L2, a rear-stage resonant capacitor C4, a rear-stage transformer T1, rear-stage rectifier diodes D1-D4, and a rear-stage filter capacitor C5; the drain of Q5 is connected to one end of the front-stage converter C3, the source of Q5 and the drain of Q6 are commonly connected to one end of C4, the source of Q6 and one end of L2 are commonly connected to a common ground PGND of the converter, the other end of C4 is connected to one end of the primary side of T1, the other end of L2 is connected to the other end of the primary side of T1, the anode of D1 and the cathode of D2 are commonly connected to one end of the secondary side of T1, the anode of D3 and the cathode of D4 are commonly connected to the other end of the secondary side of T1, the cathode of D1 and the cathode of D3 are commonly connected to one end of C5, and the anode of D2, the anode of D4 and the other end of C5 are commonly connected to another common ground SGND of the converter; The subsequent DCX-LLC converter uses the energy transmitted from the previous synchronous TL-Buck converter to form a 1 / 2 gain through the half-bridge composed of Q5 and Q6, and then forms a resonant cavity gain through the resonant circuit composed of C4, L2 and the primary side of T1. The AC signal passes through the rectifier tube composed of D1~D4, and then is filtered by C5 to transmit the energy to the pulse load circuit.

4. The two-stage DC-DC converter for pulse loads according to claim 1, characterized in that: The pulse load circuit includes the steady-state load R1, the pulse load R2, and the pulse switch Q7; one end of the R1 and the drain of Q7 are connected to one end of the output of the subsequent converter, the source of Q7 is connected to one end of R2, and the other end of R2 and the other end of R1 are connected to the other end of the output of the subsequent converter and another common ground SGND of the converter; Under steady-state conditions, Q7 is in the off state, and the load in the circuit only contains R1; under pulse load conditions, Q7 switches at a fixed pulse frequency and duty cycle. When Q7 is in the on state, the equivalent resistance of the pulse load circuit switches between R1 and R1 in parallel with R2.

5. A control method for a two-stage DC-DC converter applied to a pulse load, characterized in that: The two-stage DC-DC converter for pulse loads according to any one of claims 1 to 4 comprises the following steps: Step 1: According to the voltage decoupling dual closed-loop control small signal model of TL-Buck, the output voltage duty cycle command-output voltage transfer function and the flying capacitor voltage duty cycle command-flying capacitor voltage transfer function are given; Step 2: Sample v C3 and i L1 , according to the comparison between the two and the critical state value, determine the scheme of switching between the steady-state / transient controller and the control logic of the transient controller; Step 3: Determine the energy storage capacitor capacity expression of the pulse load DC converter of the single-stage and two-stage architectures, and explain the power density advantage of the two-stage architecture.

6. The control method of a two-stage DC-DC converter for pulse loads according to claim 5, characterized in that: In step 1, the TL-Buck output voltage duty cycle command-output voltage transfer function and the flying capacitor voltage duty cycle command-flying capacitor voltage transfer function are: (1.1) The TL-Buck output voltage duty cycle command-output voltage transfer function is: Said is the output voltage duty cycle command-output voltage transfer function of the previous converter, is the output voltage closed-loop weight, V in is the input voltage source, V C3 is the intermediate bus capacitor voltage, M is the impedance coefficient of the previous converter, Z in_DCX-LLC is the input impedance of the subsequent converter, C3 is the intermediate bus capacitor, R C3 is the equivalent series resistance of the intermediate bus capacitor, L1 is the pre-filter inductor, R L1 is the equivalent DC resistance of the front-stage filter inductor; (1.2) TL-Buck flying capacitor voltage duty cycle command - flying capacitor voltage transfer function: Said is the flying capacitor voltage duty cycle instruction-flying capacitor voltage transfer function of the previous converter, is the closed-loop weight of the flying capacitor voltage, C2 is the voltage of the previous flying capacitor, V s is the sawtooth wave amplitude at the inverting input of the comparator.

7. The control method of a two-stage DC-DC converter for pulse loads according to claim 5, characterized in that: The controller switching scheme between steady-state / transient controller in step 2 and the control logic of transient controller are: (2.1) Scheme for switching between steady-state and transient controllers: ① During the load loading process, the start and end conditions of the duty cycle extended mode transient control are: Said is the intermediate bus voltage critical value for the start of transient load control, i L1 is the inductor current of the previous converter, I L1_over is the critical value of the inductor current of the preceding converter at the end of the loading transient control; after the loading start condition is met, the control mode of the converter is switched from the voltage decoupling double closed-loop control mode to the transient control mode based on the duty cycle extension mode; after the loading end condition is met, the control mode of the converter is switched from the transient control mode based on the duty cycle extension mode to the voltage decoupling double closed-loop control mode; ② During load unloading, the start and end conditions of the duty cycle extended mode transient control are: Said is the intermediate bus voltage critical value for the start of unloading transient control, I L1_under is the critical value of the inductor current of the preceding converter at the end of the unloading transient control; after the unloading start condition is met, the control mode of the converter is switched from the voltage decoupling double closed-loop control mode to the transient control mode based on the duty cycle extension mode; after the unloading end condition is met, the control mode of the converter is switched from the transient control mode based on the duty cycle extension mode to the voltage decoupling double closed-loop control mode; (2.2) Control logic of transient controller: ① During the load loading process, when the converter meets the loading start condition but does not meet the loading end condition, under the transient control based on the duty cycle extended mode, the switching logic of Q1~Q4 is: Said To load the Q1 drive logic signal during transient control, To load the Q2 drive logic signal during transient control, To load the Q3 drive logic signal during transient control, is the Q4 driving logic signal during the loading transient process; during the loading transient control process, the switching logic of Q1 to Q4 is that Q1 and Q2 remain turned on, and Q3 and Q4 remain turned off; ② During load unloading, when the converter meets the unloading start condition and does not meet the unloading end condition, under transient control based on the duty cycle extended mode, the switching logic of Q1~Q4 is: Said To unload the Q1 drive logic signal during the transient process, To unload the Q2 drive logic signal during transient control, To unload the Q3 drive logic signal during transient control, It is the Q4 driving logic signal in the unloading transient control process; in the unloading transient process, the switching logic of Q1 to Q4 is that Q1 and Q2 remain off, and Q3 and Q4 remain on.

8. The control method of a two-stage DC-DC converter for pulse loads according to claim 5, characterized in that: The expressions of energy storage capacitor capacity of pulse load DC converters with single-stage and two-stage architectures in step 3, as well as the comparison of their capacities are: (3.1) Expression of single-stage and two-stage energy storage capacitor capacity: The C o_s For the single-stage architecture output end energy storage capacitor, I o_peak is the peak value of the load current, D pulse is the pulse duty cycle, Δv o is the output voltage ripple, f pulse is the pulse repetition frequency, V o is the output voltage, is the intermediate bus voltage ripple; (3.2) Comparison of energy storage capacitor capacity of pulse load DC converters with two-stage and single-stage architectures: The K is the ratio of the energy storage capacitor capacity of the pulse load DC converter of the two-stage structure to that of the single-stage structure, and n is the transformer ratio of the rear-stage converter of the two-stage structure.

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