Low-loss power supply

Abstract

A low-loss power supply includes an input switching circuit, a transformer, a first capacitor, an output stage circuit, and a detection and control circuit. The input switching circuit can generate a switching level based on an input level. The output stage circuit can generate an output level, wherein the output stage circuit includes a first rectifier switch and a second rectifier switch. The detection and control circuit can detect a first output current passing through the first rectifier switch and then generate a first control level based on it, and can detect a second output current passing through the second rectifier switch and then generate a second control level based on it. The first rectifier switch is selectively turned on or off based on the first control level. The second rectifier switch is selectively turned on or off based on the second control level.

Description

Technical Field

[0001] The present invention relates to a power supply, and in particular to a low-loss power supply. Background Art

[0002] In traditional power supplies, when the output diode switches from the on state to the off state, the output current through the output diode often has not yet dropped to zero. This non-ideal characteristic easily increases the switching loss of the power supply and reduces the overall efficiency of the power supply. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies. Summary of the Invention

[0003] In a preferred embodiment, the present invention provides a low-loss power supply, comprising: an input switching circuit for generating a switching level according to an input level; a transformer comprising a main winding, a first secondary winding, and a second secondary winding, wherein the transformer has a built-in leakage inductor and an excitation inductor, and the main winding receives the switching level via the leakage inductor; a first capacitor, wherein the excitation inductor is coupled to ground via the first capacitor; an output stage circuit coupled to the first secondary winding and the second secondary winding and configured to generate an output level, wherein The output stage circuit includes a first rectifier switch and a second rectifier switch; and a detection and control circuit coupled to the output stage circuit, wherein the detection and control circuit is used to detect a first output current passing through the first rectifier switch and then generate a first control level, and detect a second output current passing through the second rectifier switch and then generate a second control level; wherein the first rectifier switch is selectively turned on or off according to the first control level; wherein the second rectifier switch is selectively turned on or off according to the second control level. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention.

[0005] Figure 2 FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention.

[0006] Figure 3 FIG. 1 is a signal waveform diagram showing a power supply according to an embodiment of the present invention.

[0007] The description of the accompanying drawings is as follows:

[0008] 100, 200: Power supply

[0009] 110, 210: Input switching circuit

[0010] 120, 220: Transformer

[0011] 121, 221: Main coil

[0012] 122, 222: First secondary coil

[0013] 123, 223: Second secondary coil

[0014] 130, 230: Output stage circuit

[0015] 141, 241: First rectifier switch

[0016] 142, 242: Second rectifier switch

[0017] 150, 250: Detection and control circuit

[0018] 190, 290: Earth

[0019] 212: Pulse Width Modulation Integrated Circuit

[0020] 252: First subtractor

[0021] 254: First Drive

[0022] 256: Second subtractor

[0023] 258: Second Drive

[0024] 360: First dotted box

[0025] 370: Second dotted box

[0026] C1: First capacitor

[0027] C2: Second capacitor

[0028] IOUT1: first output current

[0029] IOUT2: Second output current

[0030] LM: Magnetizing Inductor

[0031] LR: Leakage Inductor

[0032] M1: first transistor

[0033] M2: Second transistor

[0034] M3: the third transistor

[0035] M4: the fourth transistor

[0036] M5: fifth transistor

[0037] M6: sixth transistor

[0038] M7: Seventh transistor

[0039] M8: eighth transistor

[0040] N1: first node

[0041] N2: Second node

[0042] N3: The third node

[0043] N4: The fourth node

[0044] N5: Fifth node

[0045] N6: Sixth node

[0046] N7: Seventh node

[0047] N8: Node 8

[0048] N9: Ninth Node

[0049] NC1: First control node

[0050] NC2: Secondary control node

[0051] NIN: Input Node

[0052] NOUT: output node

[0053] R1: First resistor

[0054] R2: Second resistor

[0055] R3: The third resistor

[0056] R4: fourth resistor

[0057] R5: fifth resistor

[0058] R6: Sixth resistor

[0059] V4, V5, V8, V9: Level

[0060] VC1: First control level

[0061] VC2: Second control level

[0062] VD1: First level difference

[0063] VD2: Second level difference

[0064] VD3: third level difference

[0065] VD4: fourth level difference

[0066] VG1: First drive level

[0067] VG2: Second drive level

[0068] VIN: input level

[0069] VM1: First pulse width modulation level

[0070] VM2: Second pulse width modulation level

[0071] VOUT: output level

[0072] VS1: First specific level

[0073] VS2: Second specific level

[0074] VSS: Ground level

[0075] VW: Switching Level DETAILED DESCRIPTION

[0076] In order to make the objects, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are given below and described in detail with reference to the accompanying drawings.

[0077] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components by name, but rather by functional differences. The words "include" and "comprising" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

[0078] Figure 1 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. Figure 1 As shown, the power supply 100 includes: an input switching circuit 110, a transformer 120, a first capacitor C1, an output stage circuit 130, and a detection and control circuit 150. It should be noted that although not shown in FIG. Figure 1 However, the power supply 100 may further include other components, such as a voltage regulator and / or a negative feedback circuit.

[0079] The input switching circuit 110 can generate a switching level VW based on an input level VIN. The input level VIN can come from an external input power source, where the input level VIN can be a DC level of any level. For example, the DC level can be between 380V and 400V, but is not limited thereto. The transformer 120 includes a main winding 121, a first secondary winding 122, and a second secondary winding 123. The transformer 120 has a built-in leakage inductor LR and a magnetizing inductor LM. The main winding 121, the leakage inductor LR, and the magnetizing inductor LM can all be located on the same side of the transformer 120, while the first secondary winding 122 and the second secondary winding 123 can both be located on opposite sides of the transformer 120. The main winding 121 can receive the switching level VW via the leakage inductor LR, and the first secondary winding 122 and the second secondary winding 123 can both operate based on the switching level VW. The magnetizing inductor LM can be coupled to ground 190 via a first capacitor C1. Ground 190 can refer to the Earth or any ground path coupled to the Earth and is not an internal component of the power supply 100. The output stage circuit 230 is coupled to the first and second secondary windings 122 and 123 and can be configured to generate an output level VOUT. For example, the output level VOUT can be another DC level, ranging from 18V to 20V, but is not limited thereto. The output stage circuit 130 includes a first rectifier switch 141 and a second rectifier switch 142. The detection and control circuit 150 is coupled to the output stage circuit 130. The detection and control circuit 150 can be configured to detect a first output current IOUT1 passing through the first rectifier switch 141 and generate a first control level VC1 accordingly, and to detect a second output current IOUT2 ​​passing through the second rectifier switch 142 and generate a second control level VC2 accordingly. Next, the first rectifier switch 141 and the second rectifier switch 142 can be controlled by the detection and control circuit 150. The first rectifier switch 141 can be selectively turned on or off according to the first control level VC1. For example, if the first control level VC1 is at a high logic level, the first rectifier switch 141 will be turned on (i.e., the first rectifier switch 141 can be considered as a short circuit path), and if the first control level VC1 is at a low logic level, the first rectifier switch 141 will be turned off (i.e., the first rectifier switch 141 can be considered as an open circuit path). The second rectifier switch 142 can be selectively turned on or off according to the second control level VC2. For example, if the second control level VC2 is a high logic level, the second rectifier switch 142 will be turned on (i.e., the second rectifier switch 142 can be regarded as a short-circuit path), and if the second control level VC2 is a low logic level, the second rectifier switch 142 will be turned off (i.e., the second rectifier switch 142 can be regarded as an open-circuit path).In some embodiments, when the first output current IOUT1 is exactly equal to zero, the first rectifier switch 141 is disconnected, and otherwise, it is connected. Conversely, when the second output current IOUT2 ​​is exactly equal to zero, the second rectifier switch 142 is disconnected, and otherwise, it is connected. With this design, the first rectifier switch 141 and the second rectifier switch 142 of the output stage circuit 130 experience virtually no non-ideal switching losses, thereby significantly improving the overall efficiency of the power supply 100.

[0080] The following embodiments will introduce the detailed structure and operation of the power supply 100. It should be understood that these drawings and descriptions are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0081] Figure 2 FIG. 1 is a schematic diagram showing a power supply 200 according to an embodiment of the present invention. Figure 2 In the embodiment of the present invention, the power supply 200 has an input node NIN and an output node NOUT, and includes an input switching circuit 210, a transformer 220, a first capacitor C1, an output stage circuit 230, and a detection and control circuit 250. The input node NIN of the power supply 200 can receive an input voltage level VIN from an external input power source, and the output node NOUT of the power supply 200 can be used to output an output voltage level VOUT to an electronic device (not shown).

[0082] The input switching circuit 210 includes a pulse width modulation integrated circuit 212, a first transistor M1, and a second transistor M2. The pulse width modulation integrated circuit 212 can generate a first pulse width modulation level VM1 and a second pulse width modulation level VM2. The first pulse width modulation level VM1 and the second pulse width modulation level VM2 can be maintained at a fixed level during initialization of the power supply 200 and can provide a periodic clock waveform after the power supply 200 enters normal operation. In some embodiments, the first pulse width modulation level VM1 and the second pulse width modulation level VM2 can have the same waveform but with a phase difference so that they are not simultaneously at a high logic level. The first transistor M1 and the second transistor M2 can each be an N-type metal oxide semiconductor field effect transistor. The control terminal of the first transistor M1 is used to receive the first pulse width modulation level VM1. The first terminal of the first transistor M1 is coupled to a first node N1 to output a switching level VW. The second terminal of the first transistor M1 is coupled to the input node NIN. The control terminal of the second transistor M2 is configured to receive the second pulse-width modulation level VM2. A first terminal of the second transistor M2 is coupled to ground 290, and a second terminal of the second transistor M2 is coupled to the first node N1. Ground 290 may refer to the earth or any ground path coupled to the earth and is not an internal component of the power supply 200.

[0083] Transformer 220 includes a primary winding 221, a first secondary winding 222, and a second secondary winding 223. Transformer 220 also includes a leakage inductor LR and a magnetizing inductor LM. Leakage inductor LR and magnetizing inductor LM can be inherent components generated during the manufacture of transformer 220 and are not external, independent components. Leakage inductor LR, primary winding 221, and magnetizing inductor LM can all be located on the same side of transformer 220, while first secondary winding 222 and second secondary winding 223 can be located on opposite sides of transformer 220. A first end of leakage inductor LR is coupled to a first node N1 to receive a switching voltage VW, while a second end of leakage inductor LR is coupled to a second node N1. A first end of primary winding 221 is coupled to a second node N2, while a second end of primary winding 221 is coupled to a third node N3. A first end of the magnetizing inductor LM is coupled to a second node N2, and a second end of the magnetizing inductor LM is coupled to a third node N3. A first end of the first capacitor C1 is coupled to the third node N3, and a second end of the first capacitor C1 is coupled to ground 290. In some embodiments, the leakage inductor LR, the magnetizing inductor LM, and the first capacitor C1 together form a resonant tank, which can be used to determine the resonant frequency and corresponding gain value of the power supply 200. A first end of the first secondary winding 222 is coupled to a fourth node N4, and a second end of the first secondary winding 222 is coupled to a ground level VSS (e.g., 0V). A first end of the second secondary winding 223 is coupled to a fifth node N5, and a second end of the second secondary winding 223 is coupled to the ground level VSS.

[0084] The output stage circuit 230 includes a first rectifier switch 241, a second rectifier switch 242, a first resistor R1, a second resistor R2, and a second capacitor C2. The first rectifier switch 241 includes a third transistor M3, and the second rectifier switch 242 includes a fourth transistor M4. The third transistor M3 and the fourth transistor M4 can each be an N-type metal oxide semiconductor field effect transistor.

[0085] The control terminal of the third transistor M3 is coupled to a first control node NC1 to receive a first control level VC1. The first terminal of the third transistor M3 is coupled to a sixth node N6 to output a first specific level VS1. The second terminal of the third transistor M3 is coupled to a fourth node N4. The control terminal of the fourth transistor M4 is coupled to a second control node NC2 to receive a second control level VC2. The first terminal of the fourth transistor M4 is coupled to a seventh node N7 to output a second specific level VS2. The second terminal of the fourth transistor M4 is coupled to a fifth node N5. The first terminal of the first resistor R1 is coupled to the sixth node N6, and the second terminal of the first resistor R1 is coupled to the output node NOUT. A first output current IOUT1 may flow through the third transistor M3 and the first resistor R1. The first terminal of the second resistor R2 is coupled to the seventh node N7, and the second terminal of the second resistor R2 is coupled to the output node NOUT. A second output current IOUT2 ​​may flow through the fourth transistor M4 and the second resistor R2. A first terminal of the second capacitor C2 is coupled to the output node NOUT, and a second terminal of the second capacitor C2 is coupled to the ground level VSS.

[0086] The detection and control circuit 250 includes a first subtractor 252, a first driver 254, a second subtractor 256, a second driver 258, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can each be an N-type metal oxide semiconductor field effect transistor.

[0087] The first subtractor 252 may subtract the output level VOUT from the first specific level VS1 at the sixth node N6 to generate a first level difference VD1. According to Ohm's law, the first level difference VD1 is also equal to the product of the current value of the first output current IOUT1 and the resistance value of the first resistor R1. The first driver 254 may then amplify the first level difference VD1 to generate a first drive level VG1. The operation of the first subtractor 252 and the first driver 254 may be described according to the following equations (1), (2), and (3).

[0088] VD1=VS1-VOUT (1)

[0089] VD1=IOUT1·R1 (2)

[0090] VG1=VD1·K1 (3)

[0091] Wherein "VD1" represents the first level difference VD1, "VS1" represents the first specific level VS1, "VOUT" represents the output level VOUT, "IOUT1" represents the current value of the first output current IOUT1, "R1" represents the resistance value of the first resistor R1, "VG1" represents the first drive level VG1, and "K1" represents the amplification factor of the first driver 254 (which can be an arbitrary positive value).

[0092] The fifth transistor M5 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fifth transistor M5 is used to receive the first driving level VG1, the first terminal of the fifth transistor M5 is coupled to the ground level VSS, and the second terminal of the fifth transistor M5 is coupled to an eighth node N8. The first terminal of the third resistor R3 is coupled to the output node NOUT, and the second terminal of the third resistor R3 is coupled to the eighth node N8. The control terminal of the sixth transistor M6 is coupled to the eighth node N8, the first terminal of the sixth transistor M6 is coupled to the ground level VSS, and the second terminal of the sixth transistor M6 is coupled to the first control node NC1 to output the first control level VC1. The first terminal of the fourth resistor R4 is coupled to the output node NOUT, and the second terminal of the fourth resistor R4 is coupled to the first control node NC1.

[0093] The second subtractor 256 can subtract the output level VOUT from the second specific level VS2 at the seventh node N7 to generate a second level difference VD2. According to Ohm's law, the second level difference VD2 is also equal to the product of the current value of the second output current IOUT2 ​​and the resistance value of the second resistor R2. Then, the second driver 258 can amplify the second level difference VD2 to generate a second drive level VG2. The operation of the second subtractor 256 and the second driver 258 can be described according to the following equations (4), (5), and (6).

[0094] VD2=VS2-VOUT (4)

[0095] VD2=IOUT2·R2 (5)

[0096] VG2=VD2·K2 (6)

[0097] Wherein, "VD2" represents the second level difference VD2, "VS2" represents the second specific level VS2, "VOUT" represents the output level VOUT, "IOUT2" represents the current value of the second output current IOUT2, "R2" represents the resistance value of the second resistor R2, "VG2" represents the second drive level VG2, and "K2" represents the amplification factor of the second driver 258 (which can be an arbitrary positive value).

[0098] A control terminal of the seventh transistor M7 is configured to receive the second drive level VG2. A first terminal of the seventh transistor M7 is coupled to the ground level VSS, and a second terminal of the seventh transistor M7 is coupled to a ninth node N9. A first terminal of the fifth resistor R5 is coupled to the output node NOUT, and a second terminal of the fifth resistor R5 is coupled to the ninth node N9. A control terminal of the eighth transistor M8 is coupled to the ninth node N9. A first terminal of the eighth transistor M8 is coupled to the ground level VSS, and a second terminal of the eighth transistor M8 is coupled to the second control node NC2 to output the second control level VC2. A first terminal of the sixth resistor R6 is coupled to the output node NOUT, and a second terminal of the sixth resistor R6 is coupled to the second control node NC2.

[0099] In some embodiments, the power supply 200 can alternately operate in a first mode and a second mode, and its operating principle can be described as follows.

[0100] In the first mode, the first pulse-width modulation level VM1 is at a high logic level to enable the first transistor M1, while the second pulse-width modulation level VM2 is at a low logic level to disable the second transistor M2. Depending on the variation in the first output current IOUT1, the first rectifier switch 241 of the output stage circuit 250 can perform different operations. When the first output current IOUT1 is not equal to zero, the first voltage difference VD1 of the first subtractor 252 is a positive value, and the first drive voltage VG1 of the first driver 254 is at a high logic level to enable the fifth transistor M5. At this time, the voltage level V8 at the eighth node N8 is almost pulled down to the ground level VSS, disabling the sixth transistor M6. Since the sixth transistor M6 is disabled, the first control voltage VC1 at the first control node NC1 is indirectly pulled up by the output voltage VOUT, enabling the third transistor M3 (i.e., the first rectifier switch 241 is in the on state).

[0101] In the first mode, when the first output current IOUT1 is exactly equal to zero, the first voltage difference VD1 of the first subtractor 252 is also equal to zero, and the first drive voltage VG1 of the first driver 254 is at a low logic level, thereby disabling the fifth transistor M5. Since the fifth transistor M5 is disabled, the voltage level V8 at the eighth node N8 is indirectly pulled up by the output voltage VOUT, thereby enabling the sixth transistor M6. At this time, the first control voltage VC1 at the first control node NC1 is almost pulled down to the ground level VSS, thus disabling the third transistor M3 (i.e., the first rectifier switch 241 is in the off state). It should be noted that in the first mode, the second sub-coil 223, the fourth transistor M4, the second subtractor 256, and the second driver 258 are all in a disabled state.

[0102] In the second mode, the first pulse-width modulation level VM1 is at a low logic level to disable the first transistor M1, while the second pulse-width modulation level VM2 is at a high logic level to enable the second transistor M2. Depending on the variation in the second output current IOUT2, the second rectifier switch 242 of the output stage circuit 250 can perform different operations. When the second output current IOUT2 ​​is not equal to zero, the second voltage difference VD2 of the second subtractor 256 is a positive value, and the second drive level VG2 of the second driver 258 is at a high logic level to enable the seventh transistor M7. At this time, the voltage level V9 at the ninth node N9 is almost pulled down to the ground level VSS, disabling the eighth transistor M8. Since the eighth transistor M8 is disabled, the second control level VC2 at the second control node NC2 is indirectly pulled up by the output voltage VOUT, enabling the fourth transistor M4 (i.e., the second rectifier switch 242 is in the on state).

[0103] In the second mode, when the second output current IOUT2 ​​is exactly equal to zero, the second voltage difference VD2 of the second subtractor 256 is also equal to zero, and the second drive level VG2 of the second driver 258 is at a low logic level, thereby disabling the seventh transistor M7. Since the seventh transistor M7 is disabled, the voltage level V9 at the ninth node N9 is indirectly pulled up by the output voltage VOUT, thereby enabling the eighth transistor M8. At this time, the second control level VC2 at the second control node NC2 is almost pulled down to the ground level VSS, thus disabling the fourth transistor M4 (i.e., the second rectifier switch 242 is in the off state). It should be noted that in the second mode, the first sub-coil 222, the third transistor M3, the first subtractor 252, and the first driver 254 are all in a disabled state.

[0104] Figure 3 : is a signal waveform diagram of a power supply 200 according to an embodiment of the present invention, wherein the horizontal axis represents time and the vertical axis represents the level or current value. A third level difference VD3 is formed between the second terminal and the first terminal of the third transistor M3, which can be equal to the level V4 at the fourth node N4 minus the first specific level VS1 at the sixth node N6. In addition, a fourth level difference VD4 is formed between the second terminal and the first terminal of the fourth transistor M4, which can be equal to the level V5 at the fifth node N5 minus the first specific level VS2 at the seventh node N7. According to Figure 3According to the measurement results, when the third transistor M3 switches from an enabled state to a disabled state, the first output current IOUT1 flowing through the third transistor M3 drops to zero (as shown by a first dashed box 360). In addition, when the fourth transistor M4 switches from an enabled state to a disabled state, the second output current IOUT2 ​​flowing through the fourth transistor M4 also drops to zero (as shown by a second dashed box 370). In other words, under the design of the present invention, the first rectifier switch 241 and the second rectifier switch 242 of the output stage circuit 230 have almost no non-ideal switching losses, thereby significantly improving the overall efficiency of the power supply 200.

[0105] In some embodiments, the component parameters of the power supply 200 may be as described below. The capacitance value of the first capacitor C1 may be between 42.3nF and 51.7nF, preferably approximately 47nF. The capacitance value of the second capacitor C2 may be between 376μF and 564μF, preferably approximately 470μF. The inductance value of the leakage inductor LR may be between 27μH and 33μH, preferably approximately 30μH. The inductance value of the excitation inductor LM may be between 252μH and 308μH, preferably approximately 280μH. The resistance value of the first resistor R1 may be between 19.8mΩ and 20.2mΩ, preferably approximately 20mΩ. The resistance value of the second resistor R2 may be between 19.8mΩ and 20.2mΩ, preferably approximately 20mΩ. The resistance value of the third resistor R3 may be between 9kΩ and 11kΩ, preferably approximately 10kΩ. The resistance value of the fourth resistor R4 may be between 9Ω and 11Ω, preferably approximately 10Ω. The resistance value of the fifth resistor R5 may be between 9KΩ and 11KΩ, preferably approximately 10KΩ. The resistance value of the sixth resistor R6 may be between 9Ω and 11Ω, preferably approximately 10Ω. The turns ratio of the main coil 221 to the first secondary coil 222 may be between 1 and 100, preferably approximately 20. The turns ratio of the main coil 221 to the second secondary coil 223 may be between 1 and 100, preferably approximately 20. The above parameter ranges are obtained based on multiple experimental results, which help minimize the switching loss of the power supply 200.

[0106] The present invention proposes a novel power supply including a low-loss rectifier switch. According to actual measurement results, the overall efficiency of the power supply using the above design can be greatly improved, making it very suitable for application in various devices.

[0107] It is worth noting that the above-mentioned voltage level, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to Figure 1-Figure 3 The present invention may only include Figure 1-Figure 3 any one or more features of any one or more embodiments. In other words, not all illustrated features need to be implemented simultaneously in the power supply of the present invention. Although the embodiments of the present invention use metal oxide semiconductor field effect transistors as an example, the present invention is not limited thereto. Those skilled in the art may use other types of transistors, such as junction field effect transistors or fin field effect transistors, without affecting the effects of the present invention.

[0108] Although the present invention is disclosed above with reference to preferred embodiments, they are not intended to limit the scope of the invention. Anyone skilled in the art may make slight changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A low-loss power supply, comprising: an input switching circuit generating a switching level according to an input level; A transformer comprising a main winding, a first secondary winding, and a second secondary winding, wherein the transformer has a built-in leakage inductor and an excitation inductor, and the main winding receives the switching level via the leakage inductor; a first capacitor, wherein the magnetizing inductor is coupled to ground via the first capacitor; an output stage circuit coupled to the first secondary winding and the second secondary winding and configured to generate an output level, wherein the output stage circuit comprises a first rectifier switch and a second rectifier switch; and a detection and control circuit coupled to the output stage circuit, wherein the detection and control circuit is configured to detect a first output current passing through the first rectifier switch and generate a first control level accordingly, and to detect a second output current passing through the second rectifier switch and generate a second control level accordingly; wherein the first rectifier switch is selectively turned on or off according to the first control level; wherein the second rectifier switch is selectively turned on or off according to the second control level; Wherein, the input switching circuit includes: a pulse width modulation integrated circuit generating a first pulse width modulation level and a second pulse width modulation level; a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first pulse width modulation level, the first terminal of the first transistor is coupled to a first node to output the switching level, and the second terminal of the first transistor is coupled to an input node to receive the input level; and a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is configured to receive the second pulse width modulation level, the first terminal of the second transistor is coupled to the ground, and the second terminal of the second transistor is coupled to the first node; The leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the first node to receive the switching level, and the second end of the leakage inductor is coupled to a second node. The main coil has a first end and a second end, the first end of the main coil is coupled to the second node, and the second end of the main coil is coupled to a third node. The excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the second node, and the second end of the excitation inductor is coupled to the third node. point, the first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the third node, the second terminal of the first capacitor being coupled to the ground, the first secondary coil having a first terminal and a second terminal, the first terminal of the first secondary coil being coupled to a fourth node, the second terminal of the first secondary coil being coupled to a ground level, the second secondary coil having a first terminal and a second terminal, the first terminal of the second secondary coil being coupled to a fifth node, and the second terminal of the second secondary coil being coupled to the ground level; The first rectifier switch includes a third transistor having a control terminal, a first terminal, and a second terminal. The control terminal of the third transistor is coupled to a first control node to receive the first control level, the first terminal of the third transistor is coupled to a sixth node, and the second terminal of the third transistor is coupled to the fourth node. The second rectifier switch includes a fourth transistor having a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor is coupled to a second control node to receive the second control level, the first terminal of the fourth transistor is coupled to a seventh node, and the second terminal of the fourth transistor is coupled to the fifth node. The output stage circuit further includes: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the sixth node, and the second end of the first resistor is coupled to an output node to output the output level; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the seventh node, and the second end of the second resistor is coupled to the output node; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the ground level; The detection and control circuit includes: a first subtractor for subtracting the output level from a first specific level at the sixth node to generate a first level difference; a first driver, amplifying the first level difference to generate a first driving level; a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is configured to receive the first driving level, the first terminal of the fifth transistor is coupled to the ground level, and the second terminal of the fifth transistor is coupled to an eighth node; a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the output node, and the second end of the third resistor is coupled to the eighth node; a sixth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is coupled to the eighth node, the first terminal of the sixth transistor is coupled to the ground level, and the second terminal of the sixth transistor is coupled to the first control node to output the first control level; and A fourth resistor has a first end and a second end, wherein the first end of the fourth resistor is coupled to the output node, and the second end of the fourth resistor is coupled to the first control node.

2. The power supply according to claim 1, wherein: When the first output current is exactly equal to 0, the first rectifier switch is disconnected, and when the second output current is exactly equal to 0, the second rectifier switch is disconnected.

3. The power supply according to claim 1, wherein: The detection and control circuit also includes: a second subtractor for subtracting the output level from a second specific level at the seventh node to generate a second level difference; and A second driver amplifies the second level difference to generate a second driving level.

4. The power supply according to claim 3, wherein: The detection and control circuit also includes: a seventh transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the seventh transistor is configured to receive the second driving level, the first terminal of the seventh transistor is coupled to the ground level, and the second terminal of the seventh transistor is coupled to a ninth node; a fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the output node, and the second end of the fifth resistor is coupled to the ninth node; an eighth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighth transistor is coupled to the ninth node, the first terminal of the eighth transistor is coupled to the ground level, and the second terminal of the eighth transistor is coupled to the second control node to output the second control level; and A sixth resistor has a first end and a second end, wherein the first end of the sixth resistor is coupled to the output node, and the second end of the sixth resistor is coupled to the second control node.

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