vibrating device

Abstract

A vibration device capable of suppressing deterioration of oscillation characteristics due to capacitive coupling. The vibration device (1) includes: a base (2) including a semiconductor substrate (20) and a through electrode (40) that penetrates between a first surface (21) and a second surface of the semiconductor substrate (20); a vibration element (5) disposed on the first surface (21) side; and an external connection terminal (91) disposed on the second surface (22) side via an insulating layer (80). An oscillation circuit (11) and an output buffer circuit (12) are disposed on the second surface (22). The oscillation circuit (11) is electrically connected to the vibration element (5) via the through electrode (40) to oscillate the vibration element (5) to generate an oscillation signal. The output buffer circuit (12) outputs a clock signal based on the oscillation signal, and outputs the clock signal from the output buffer circuit (12) from the external connection terminal (91). The through electrode (40) and the external connection terminal (91) are disposed so as not to overlap when viewed from a direction orthogonal to the first surface (21).

Description

TECHNICAL FIELD

[0001] The present application relates to a vibrating device or the like. BACKGROUND

[0002] In the past, as a device using a vibrating element, a vibrating device such as an oscillator is known. For example, Patent Document 1 discloses an oscillator which mounts a piezoelectric vibration piece as a vibrating element on a semiconductor substrate such as a silicon substrate on which a circuit pattern of an integrated circuit is formed, and seals the piezoelectric vibration piece with the semiconductor substrate and a lid. Further, the oscillator of Patent Document 1 has a through-hole which is a through-hole connecting the piezoelectric vibration piece and the circuit pattern, and a mounting electrode as an external connection terminal.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-214787

[0004] It is known that in such a vibrating device such as an oscillator, due to capacitive coupling between a through-hole which is a wiring electrically connecting an oscillation circuit possessed by an integrated circuit and a vibrating element, and an external connection terminal for output of a clock signal based on an oscillation signal, there are problems such as deterioration in precision of an oscillation frequency, or an increase in a noise component contained in the oscillation signal. SUMMARY

[0005] One embodiment of the present application relates to a vibrating device including: a base including a semiconductor substrate having a first surface and a second surface in a front-rear relationship with the first surface, and a through electrode which penetrates between the first surface and the second surface; a vibrating element disposed on the first surface side; and an external connection terminal disposed on the second surface side through an insulating layer, an oscillation circuit which is electrically connected to the vibrating element via the through electrode and generates an oscillation signal by oscillating the vibrating element, and an output buffer circuit which outputs a clock signal based on the oscillation signal are disposed on the second surface, and the through electrode and the external connection terminal are disposed so as not to overlap when viewed from a direction orthogonal to the first surface. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a cross-sectional view showing a structure example of the vibrating device of the present embodiment.

[0007] Figure 2 is a cross-sectional view showing a detailed structure example of the vibrating device of the present embodiment.

[0008] Figure 3 is a plan view showing an example of the vibrating element of the vibrating device.

[0009] Figure 4FIG. 1 is a diagram showing a structure example of an integrated circuit.

[0010] Figure 5 FIG. 2 is a diagram showing a detailed structure example of the integrated circuit.

[0011] Figure 6 FIG. 3 is a diagram showing a structure example of an oscillation circuit.

[0012] Figure 7 FIG. 4 is a diagram showing a structure example of an output buffer circuit.

[0013] Figure 8 FIG. 5 is a manufacturing process diagram showing an example of a manufacturing method of a vibration device.

[0014] Figure 9 FIG. 6 is a plan view showing a configuration example of a through electrode, an external connection terminal, an integrated circuit, and the like.

[0015] Figure 10 FIG. 7 is a plan view showing a configuration example of the external connection terminal.

[0016] Figure 11 FIG. 8 is a cross-sectional view showing another example of the through electrode.

[0017] Figure 12 FIG. 9 is a diagram showing another structure example of an output driver of the output buffer circuit.

[0018] Figure 13 FIG. 10 is a diagram showing another structure example of an output driver of the output buffer circuit.

[0019] Figure 14 FIG. 11 is a plan view showing another configuration example of the external connection terminal.

[0020] Figure 15 FIG. 12 is a diagram showing another structure example of an integrated circuit.

[0021] Figure 16 FIG. 13 is a plan view showing another configuration example of the external connection terminal.

[0022] Label Explanation

[0023] 1: vibration device; 2: base; 5: vibration element; 7: cover; 8: reconfiguration wiring layer; 10: integrated circuit; 11: oscillation circuit; 12: output buffer circuit; 13: logic circuit; 14: power supply circuit; 15: temperature compensation circuit; 16: temperature sensor circuit; 17: memory; 18: PLL circuit; 19: interface circuit; 20: semiconductor substrate; 21: first surface; 22: second surface; 23, 24: transistor; 25: element separation film; 30: wiring layer; 31, 32: metal layer; 33, 34, 35: insulating layer; 36, 37, 38, 39: contact pad; 40, 41: through electrode; 44: insulating layer; 45: resin layer; 50: vibration substrate; 52, 53: excitation electrode; 54, 55: wiring; 56, 57: terminal; 60, 61: joining member; 62: bump; 64: terminal; 68, 69: contact pad; 71, 72: joining member; 80: insulating layer; 82: wiring; 91, 91a, 91b, 92, 93, 94, 95, 96, 97, 98, 99: external connection terminal; 101: first metal layer; 102: second metal layer; CK, CKX: clock signal; CL: center line; CV1, CV2: variable capacitance circuit; DV1, DV2: inverter circuit; IV1, IV2, IV3: inverter circuit; LA, LB: wiring; NA: NAND circuit; OE: output enable signal; OSC: oscillation signal; SCL: clock signal; SD1, SD2, SD3, SD4: side; SDA: data signal; SP: accommodation space; TCK, TGND, TOE, TVC, TVDD, TXA, TXB: terminal. DETAILED DESCRIPTION

[0024] Hereinafter, the present embodiment will be described. Note that the present embodiment described below is not intended to limit the recitations of the claims. Furthermore, all the structures described in the present embodiment are not necessarily essential structural elements. Furthermore, in each of the following drawings, a part of the structural elements is sometimes omitted for convenience of explanation. Furthermore, in each of the drawings, the dimensional ratios of the structural elements are different from the actual ones for easy understanding.

[0025] 1. Vibration device

[0026] Figure 1 is a cross-sectional view showing a structure example of the vibration device 1 of the present embodiment. As shown in FIG. 1, the vibration device 1 includes a vibration substrate 50, a cover 7, and a base 2. The vibration substrate 50 is a substrate that is provided with a vibration element 5 and a reconfiguration wiring layer 8. The vibration element 5 is a vibration element that is provided with an excitation electrode 52 and an excitation electrode 53. The cover 7 is a cover that is provided with a joining member 60 and a joining member 61. The base 2 is a base that is provided with a terminal 64 and a terminal 68. Figure 1As illustrated, the vibration device 1 of the present embodiment includes the base 2, the vibration element 5, and the external connection terminals 91, 92. Further, the vibration device 1 can include the lid 7, the redistribution wiring layer 8. The base 2 includes the semiconductor substrate 20 and the through electrode 40. The semiconductor substrate 20 has a first surface 21 and a second surface 22 that is in an opposite relationship to the first surface 21. The first surface 21 is, for example, an upper surface of the semiconductor substrate 20, and the second surface 22 is, for example, a lower surface of the semiconductor substrate 20. The through electrode 40 is an electrode that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. The vibration element 5 is disposed on the first surface 21 side of the semiconductor substrate 20. For example, the vibration element 5 is disposed at a position separated by a given separation distance from the first surface 21 of the semiconductor substrate 20. Specifically, the vibration element 5 is fixed to the first surface 21 of the semiconductor substrate 20, for example, via a conductive bonding member 60. The external connection terminals 91, 92 are provided on the second surface 22 side of the semiconductor substrate 20 via an insulating layer 80 or the like. The insulating layer 80 is, for example, an insulating layer that constitutes the redistribution wiring layer 8.

[0027] In addition, in each of the drawings described in the present embodiment, an X axis, a Y axis, and a Z axis are illustrated as three axes orthogonal to each other. A direction along the X axis is referred to as an “X axis direction”, a direction along the Y axis is referred to as a “Y axis direction”, and a direction along the Z axis is referred to as a “Z axis direction”. Further, the arrow end side of each axis direction is referred to as a “positive side”, and the base end side is referred to as a “negative side”. The Z axis direction positive side is referred to as “up”, and the Z axis direction negative side is referred to as “down”. For example, the Z axis direction is along a vertical direction, and the XY plane is along a horizontal plane. Figure 1 is a cross-sectional view of the vibration device 1 as viewed in the Y axis direction. Further, the first surface 21 and the second surface 22 of the semiconductor substrate 20 are surfaces along the XY plane, and are surfaces orthogonal to the Z axis. In addition, “orthogonal” includes not only cases where the axes intersect at 90°, but also cases where the axes intersect at an angle that is slightly inclined with respect to 90°.

[0028] The vibration device 1 is, for example, an oscillator. Specifically, the vibration device 1 is an oscillator such as a simple package quartz oscillator (SPXO), a voltage-controlled quartz oscillator (VCXO), a temperature-compensated quartz oscillator (TCXO), a quartz oscillator with an oven (OCXO), a SAW (Surface Acoustic Wave) oscillator, a voltage-controlled SAW oscillator, a MEMS (Micro Electro Mechanical Systems) oscillator, or the like. The MEMS oscillator can be implemented by a MEMS vibration element in which a piezoelectric film and an electrode are disposed on a substrate such as a silicon substrate. However, the vibration device 1 can also be an inertial sensor such as an acceleration sensor or an angular velocity sensor, a force sensor such as a tilt sensor, or the like.

[0029] The base 2 is composed of a semiconductor substrate 20. The semiconductor substrate 20 is, for example, a silicon substrate. However, the semiconductor substrate 20 is not limited to a silicon substrate, and can be a semiconductor substrate of Ge, GaP, GaAs, InP, or the like.

[0030] Further, the base 2 includes an integrated circuit 10. The semiconductor circuit, that is, the integrated circuit 10 is formed on the second face 22 of the semiconductor substrate 20. The integrated circuit 10 is composed of a plurality of circuit elements. The circuit elements are, for example, active elements such as transistors, or passive elements such as capacitors, resistors, or the like. Specifically, the integrated circuit 10 is composed of a plurality of circuit blocks each of which includes a plurality of circuit elements. Further, the integrated circuit 10 is formed of a diffusion region that is formed by doping an impurity to the semiconductor substrate 20, and a wiring layer that is formed by laminating a metal layer and an insulating layer. The source region and the drain region of the transistor, which is the circuit element of the integrated circuit 10, are formed by the diffusion region, and the wiring that connects between the circuit elements is formed by the wiring region.

[0031] Further, the base 2 includes a through electrode 40. The through electrode 40 is composed of a conductive material that penetrates the first face 21 and the second face 22 of the semiconductor substrate 20. For example, a through hole is formed with respect to the semiconductor substrate 20, and the through hole is filled with the conductive material, whereby the through electrode 40 is formed. The conductive material can be a metal such as copper, or can be a conductive polysilicon or the like. The conductive polysilicon is, for example, polysilicon to which an impurity such as phosphorus (P), boron (B), arsenic (As), or the like is doped to impart conductivity. When polysilicon is used as the conductive material, the through electrode 40 that is resistant to heat applied in a formation process of the integrated circuit 10 can be realized.

[0032] One end of the through electrode 40 is electrically connected to the vibration element 5 via a conductive bonding member 60. In the present embodiment, the conductive bonding member 60 is realized by a bump 62 or the like that electrically connects one end to the vibration element 5 and the other end to the through electrode 40. Specifically, the other end of the bump 62 is connected to the through electrode 40 via a terminal 64. The bump 62 is a conductive bump, and specifically, a metal bump. Alternatively, the conductive bonding member 60 can be realized by a conductive adhesive material or the like. Figure 1

[0033] The other end of the through electrode 40 is electrically connected to the integrated circuit 10. Specifically, the other end of the through electrode 40 is connected to a circuit element of the integrated circuit 10 via a contact pad 36 formed in the integrated circuit 10. Thus, the vibration element 5 and the integrated circuit 10 can be electrically connected via the through electrode 40.

[0034] ​The lid 7 is joined to the base 2 via the joining members 71, 72. Furthermore, a housing space SP having an airtightness is formed by the base 2 and the lid, i.e., the lid 7, and the vibration element 5 is housed in the housing space SP. The housing space SP is airtightly sealed, and the inside of the housing space SP is, for example, in a reduced pressure state. Thus, the vibration element 5 can be stably driven. Note that the state of the inside of the housing space SP is not limited to the reduced pressure state, and, for example, the inside of the housing space SP can be an inert gas environment.

[0035] The reconfiguration wiring layer 8 is provided on the side of the second surface 22 of the semiconductor substrate 20, and includes an insulating layer 80 and a wiring 82 for reconfiguration. The insulating layer 80 is implemented by, for example, a resin layer of polyimide or the like, and the wiring 82 is implemented by, for example, a metal wiring of a copper foil or the like. The insulating layer 80 needs to have heat resistance against soldering at the time of mounting of the vibration device 1, and polyimide is preferably used. In addition, as the material of the wiring 82, a metal material such as silver can be used in addition to copper. Furthermore, the thickness of the wiring layer and the terminal in the reconfiguration wiring layer 8 is, for example, about 50 μm. By providing the reconfiguration wiring layer 8, the contact pads 38, 39 formed in the integrated circuit 10 and the external connection terminals 91, 92 can be electrically connected. Furthermore, by mounting the external connection terminals 91, 92 of the vibration device 1 to terminals or wirings of a circuit substrate or the like on which the vibration device 1 is mounted, the vibration device 1 can be embedded in an electronic device. Furthermore, by providing such a reconfiguration wiring layer 8, mechanical protection of a part of the integrated circuit 10 can be performed, and the integrated circuit 10 or the like can be protected from heat in a soldering process at the time of mounting of the vibration device 1.

[0036] Figure 2 is a sectional view showing a specific example of the structure of the vibration device 1, Figure 3 is a plan view showing an example of the vibration element 5 of the vibration device 1. First, the vibration element 5 is described using Figure 3 The vibration element 5 is described in detail.

[0037] The vibration element 5 is an element that generates mechanical vibration by an electric signal. For example, as shown in FIG. 1, the vibration element 5 is a piezoelectric element that generates mechanical vibration by an electric signal. Figure 3As shown, the vibration element 5 has a vibration substrate 50 and electrodes arranged on a surface of the vibration substrate 50. The vibration substrate 50 has a thickness shear vibration mode, and in the present embodiment, is formed of an AT-cut quartz substrate. The AT-cut quartz substrate has a frequency-temperature characteristic of the third order, and thus becomes a vibration element 5 having an excellent temperature characteristic. Further, the electrodes have an excitation electrode 52 arranged on an upper surface of the vibration substrate 50, and an excitation electrode 53 arranged on a lower surface opposite the excitation electrode 52. The upper surface is a surface on the positive side in the Z-axis direction, and the lower surface is a surface on the negative side in the Z-axis direction. Further, one of the excitation electrodes 52, 53 is a first excitation electrode, and the other of the excitation electrodes 52, 53 is a second excitation electrode. Further, the electrodes have a pair of terminals 56, 57 arranged on the lower surface of the vibration substrate 50, a wiring 54 electrically connecting the terminal 56 and the excitation electrode 52, and a wiring 55 electrically connecting the terminal 57 and the excitation electrode 53.

[0038] Further, the structure of the vibration element 5 is not limited to the above-described structure. For example, the vibration element 5 can be a mesa type in which a vibration region sandwiched by the excitation electrodes 52, 53 protrudes from the periphery thereof, or conversely, a reverse mesa type in which the vibration region is recessed from the periphery thereof. Further, chamfer processing of grinding the periphery of the vibration substrate 50, or convex processing of making the upper surface and the lower surface convex curved surfaces can be performed. Further, the vibration element 5 is not limited to vibrating in the thickness shear vibration mode. For example, the vibration element 5 can be a tuning fork type vibration element in which a plurality of vibration arms bend in the in-plane direction, a tuning fork type vibration element in which a plurality of vibration arms bend in the out-of-plane direction, a gyroscope sensor element having a drive arm that performs a drive vibration and a detection arm that performs a detection vibration, and detects an angular velocity, or an acceleration sensor element having a detection portion that detects an acceleration. Further, the vibration substrate 50 is not limited to being formed of an AT-cut quartz substrate, and can be formed of a quartz substrate other than an AT-cut quartz substrate, such as an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, an ST-cut quartz substrate, or the like. Further, in the present embodiment, the vibration substrate 50 is composed of quartz, but is not limited thereto, and for example, can be composed of lithium niobate, lithium tantalate, lithium tetraborate, potassium niobate, gallium phosphate, or the like, and can be composed of a piezoelectric single crystal other than these. Further, the vibration element 5 is not limited to a piezoelectric drive type vibration element, and can be an electrostatic drive type vibration element that uses electrostatic force.

[0039] Further, as shown in Figure 2 , Figure 3 , the vibration element 5 is fixed to the upper surface, i.e., the first surface 21 of the semiconductor substrate 20 via conductive bonding members 60, 61. Further, although not shown in Figure 2 , as shown in Figure 3As shown, for example, two joining members 60, 61 are provided along the Y-axis direction. Further, as described later Figure 9 As shown, two through electrodes 40, 41 are provided in the semiconductor substrate 20, for example, along the Y-axis direction, and these through electrodes 40, 41 are electrically connected to the vibration element 5 via the electrically conductive joining members 60, 61. One of the through electrodes 40, 41 is a first through electrode, and the other of the through electrodes 40, 41 is a second through electrode. Specifically, one end of the through electrode 40 is electrically connected to the excitation electrode 52 of the vibration element 5 via the joining member 60, the terminal 56 of the vibration element 5, and the wiring 54. Further, one end of the through electrode 41 is electrically connected to the excitation electrode 53 of the vibration element 5 via the joining member 61, the terminal 57 of the vibration element 5, and the wiring 55. Moreover, the other ends of the through electrodes 40, 41 are electrically connected to the integrated circuit 10. Thus, the vibration element 5 and the integrated circuit 10 are electrically connected via the through electrodes 40, 41. Specifically, the other ends of the through electrodes 40, 41 are electrically connected to the oscillation circuit 11 of the integrated circuit 10 via the contact pads 36, 37. Figure 2 、 Figure 9 The contact pads 36, 37 shown are electrically connected to the oscillation circuit 11 of the integrated circuit 10. Thus, the vibration element 5 and the oscillation circuit 11 are electrically connected via the through electrodes 40, 41.

[0040] The joining members 60, 61 are not particularly limited as long as they have both electrical conductivity and joining properties, and can be implemented by various electrically conductive bumps 62 such as gold bumps, silver bumps, copper bumps, solder bumps, resin core bumps, and the like. Alternatively, the joining members 60, 61 can use an electrically conductive adhesive or the like in which an electrically conductive filler such as a silver filler is dispersed in various adhesives such as polyimide-based, epoxy-based, silicone-based, and acrylic-based adhesives. If the electrically conductive bumps 62 are used as the joining members 60, 61, gas generation from the joining members 60, 61 can be suppressed, and the environmental changes, particularly the increase in pressure, of the accommodation space SP can be effectively suppressed. On the other hand, if the electrically conductive adhesive is used as the joining members 60, 61, the joining members 60, 61 are softer and stress is less likely to be transmitted to the vibration element 5 compared to the case where the joining members 60, 61 are the electrically conductive bumps 62.

[0041] Furthermore, after the through-hole is formed, the semiconductor substrate 20 is thermally oxidized, thereby forming an insulating film, i.e., an insulating layer 44, made of, for example, silicon oxide (SiO2), on the first surface 21 of the semiconductor substrate 20 or the inner surface of the through-hole. By forming the insulating layer 44 through thermal oxidation, a dense and homogeneous insulating layer 44 can be formed on the surface of the semiconductor substrate 20. Furthermore, the difference in the coefficients of linear expansion between the insulating layer 44 and the semiconductor substrate 20 can be reduced. Therefore, a vibrating device 1 that is less prone to thermal stress and has excellent oscillation characteristics can be realized. The material constituting the insulating layer 44 is not particularly limited; for example, it can be made of silicon nitride (SiN) or resin. Furthermore, the method for forming the insulating layer 44 is not limited to thermal oxidation; for example, it can also be formed by CVD (Chemical Vapor Deposition).

[0042] Furthermore, conductive materials such as copper or conductive polysilicon are filled inside the insulating layer 44 of the through-hole to form through electrodes 40 and 41. That is, conductive materials are used to fill the through-hole to form through electrodes 40 and 41. One end of the through electrodes 40 and 41 is electrically connected to the vibrating element 5. Specifically, one end of the through electrodes 40 and 41 is electrically connected to the excitation electrodes 52 and 53 of the vibrating element 5. On the other hand, the other end of the through electrodes 40 and 41 is electrically connected to the integrated circuit 10. Specifically, the other end of the through electrodes 40 and 41 is electrically connected to the oscillation circuit 11 of the integrated circuit 10 via contact pads 36 and 37.

[0043] like Figure 2 As shown, the integrated circuit 10 is composed, for example, of an N-type transistor 23 or a P-type transistor 24. These transistors 23 and 24 are formed from a diffusion region (source and drain regions), a gate electrode, and a gate oxide film formed on the semiconductor substrate 20. Furthermore, the transistors 23 and 24 are separated by a device separation film 25 called LOCOS (Local Oxidation of Silicon). In addition, the integrated circuit 10 includes a wiring layer 30 that implements the interconnections between multiple circuit elements such as transistors 23 and 24. For example, Figure 2The wiring layer 30 includes metal layers 31, 32, and insulating layers 33, 34, 35. The metal layers 31, 32 are a first metal layer and a second metal layer, respectively, and the insulating layers 33, 34, 35 are a first insulating layer, a second insulating layer, and a third insulating layer, respectively. The metal layers 31, 32 are formed of, for example, aluminum or the like. Further, a passivation film is formed by the uppermost insulating layer 35. Further, the metal layer 31 and the metal layer 32 are electrically connected by a contact called a via contact, and the metal layer 31 and the source region or the drain region of the transistors 23, 24 are electrically connected by a contact. Also, as shown in Figure 2 the other end of the through electrodes 40, 41 is formed of the lower metal layer 31. Further, the contact pads 38, 39 electrically connected to the external connection terminals 91, 92 are formed of the upper metal layer 32. In addition, in the wiring layer 30, the layer on the side close to the transistors 23, 24 in the integrated circuit 10 is set as the lower layer, and the layer on the side away from the transistors 23, 24 is set as the upper layer. Further, in Figure 2 the present embodiment, a case where the wiring layer 30 has two metal layers 31, 32 is shown, but the present embodiment is not limited thereto, and the wiring layer 30 can have three or more metal layers. In this case, the contact pads 36, 37 are formed of the lowermost metal layer among the plurality of metal layers, and the contact pads 38, 39 are formed of the uppermost metal layer. Further, the passivation film is formed by the uppermost insulating layer.

[0044] Further, the wiring layer 8 further includes an insulating layer 80 formed of a resin layer such as polyimide, and a wiring 82 formed of a copper foil or the like. Also, the contact pad 38 is electrically connected to the external connection terminal 91, and the contact pad 39 is electrically connected to the external connection terminal 92 via the wiring 82.

[0045] Further, in Figure 2 the present embodiment, the external connection terminals 91, 92 each have a two-layer structure including a first metal layer 101 and a second metal layer 102. As the first metal layer 101 on the side of the insulating layer 80 of polyimide, a titanium tungsten layer is used, for example, to improve adhesion to polyimide. As the second metal layer 102, a metal layer of copper or gold or the like that is easily soldered to a terminal or a wiring of the outside is used, for example.

[0046] Figure 4 A configuration example of the integrated circuit 10 is shown. The integrated circuit 10 includes an oscillation circuit 11 and an output buffer circuit 12. Further, the integrated circuit 10 can include a logic circuit 13 and a power supply circuit 14.

[0047] The oscillation circuit 11 is a circuit that oscillates the vibration element 5. For example, the oscillation circuit 11 is electrically connected to the terminals TXA and TXB, and generates an oscillation signal OSC. Specifically, the oscillation circuit 11 is electrically connected to the vibration element 5 via the wires LA and LB, the terminals TXA and TXB, and oscillates the vibration element 5, thereby generating the oscillation signal OSC. One of the terminals TXA and TXB is a first terminal, and the other of the terminals TXA and TXB is a second terminal. For example, the oscillation circuit 11 can be implemented by an oscillation drive circuit, a capacitor, or a passive element such as a resistor, which are provided between the terminal TXA and the terminal TXB. The drive circuit can be implemented by, for example, an inverter circuit of CMOS or a bipolar transistor. The drive circuit is a core circuit of the oscillation circuit 11, and the drive circuit voltage-drives or current-drives the vibration element 5, thereby oscillating the vibration element 5. As the oscillation circuit 11, various types of oscillation circuits such as an Invert type, a Pierce type, a Colpitts type, or a Hartley type can be used. In addition, the oscillation circuit 11 is provided with a variable capacitance circuit, and by adjusting the capacitance of the variable capacitance circuit, the oscillation frequency can be adjusted. The variable capacitance circuit can be implemented by, for example, a variable capacitance element such as a varicap diode. Alternatively, the variable capacitance circuit can be implemented by a capacitor array and a switch array connected to the capacitor array. For example, the variable capacitance circuit can be constituted by a capacitor array having a plurality of capacitors that weight the capacitance values in a binary manner, and a switch array having a plurality of switches, each of which performs on / off of connection between each of the capacitors of the capacitor array and the terminal TXA or TXB. Note that the connection in the present embodiment is electrical connection. The electrical connection is connection in a manner that can transmit an electric signal, and is connection that can transmit information using an electric signal. The electrical connection can be connection via an active element or the like.

[0048] The output buffer circuit 12 outputs a clock signal CK based on the oscillation signal OSC. For example, the output buffer circuit 12 buffers the oscillation signal OSC and outputs the clock signal CK to the terminal TCK. Then, the clock signal CK is output to the outside via the external connection terminal 91 of the vibration device 1. For example, the output buffer circuit 12 outputs the clock signal CK in the form of a signal of a single-ended CMOS. For example, in a case where the output enable signal OE from the terminal TOE is active, the enable signal from the logic circuit 13 becomes active, and the output buffer circuit 12 outputs the clock signal CK in which the oscillation signal OSC is buffered. On the other hand, in a case where the output enable signal OE is inactive, the output buffer circuit 12 sets the clock signal CK to a fixed voltage level such as a low level. Thus, the voltage level of the terminal TCK is set to the fixed voltage level. Note that signal active means, for example, a high level in the case of positive logic and a low level in the case of negative logic. Further, signal inactive means, for example, a low level in the case of positive logic and a high level in the case of negative logic. In addition, the output buffer circuit 12 can output the clock signal CK in a form other than CMOS.

[0049] The logic circuit 13 is a control circuit and performs various control processes. For example, the logic circuit 13 performs control of the entire integrated circuit 10 or performs control of the operation sequence of the integrated circuit 10. Further, the logic circuit 13 can perform various processes for control of the oscillation circuit 11 or perform control of the power supply circuit 14. The logic circuit 13 can be implemented by an ASIC (Application Specific Integrated Circuit) circuit based on automatic configuration wiring such as a gate array, for example.

[0050] The power supply circuit 14 is supplied with a power supply voltage VDD from the terminal TVDD and a ground voltage GND from the terminal TGND. Further, the power supply circuit 14 supplies the power supply voltage to each internal circuit of the integrated circuit 10. The power supply circuit 14 can also generate a reference voltage or a reference current or the like used in the integrated circuit 10. For example, the power supply circuit 14 has a regulator and supplies a regulated voltage generated by the regulator to the oscillation circuit 11, the output buffer circuit 12, and the logic circuit 13. In this case, the power supply circuit 14 can have a regulator that generates the regulated voltage supplied to the oscillation circuit 11 and a regulator that generates the regulated voltage supplied to the output buffer circuit 12 and the logic circuit 13.

[0051] Figure 5 A detailed configuration example of the integrated circuit 10 is shown. In Figure 5 A temperature compensation circuit 15, a temperature sensor circuit 16, and a memory 17 are further provided.

[0052] The temperature compensation circuit 15 performs temperature compensation of the oscillation signal OSC of the oscillation circuit 11. The temperature compensation of the oscillation signal OSC is temperature compensation of the oscillation frequency of the oscillation circuit 11. Further, the output buffer circuit 12 outputs a clock signal CK based on the temperature-compensated oscillation signal OSC. Specifically, the temperature compensation circuit 15 performs temperature compensation in accordance with temperature detection information from the temperature sensor circuit 16. For example, the temperature compensation circuit 15 generates a temperature compensation voltage in accordance with a temperature detection voltage from the temperature sensor circuit 16, and outputs the generated temperature compensation voltage to the oscillation circuit 11, whereby temperature compensation of the oscillation signal OSC of the oscillation circuit 11 is performed. For example, the temperature compensation circuit 15 outputs, to a variable capacitance circuit of the oscillation circuit 11, a temperature compensation voltage that becomes a capacitance control voltage of the variable capacitance circuit, whereby temperature compensation is performed. In this case, the variable capacitance circuit of the oscillation circuit 11 is implemented by a variable capacitance element such as a varactor diode. Temperature compensation is processing that suppresses variation in the oscillation frequency due to temperature variation and performs compensation. For example, the temperature compensation circuit 15 performs temperature compensation in an analog manner based on polynomial approximation. For example, in a case where a temperature compensation voltage that compensates for the frequency-temperature characteristic of the vibration element 5 is approximated by a polynomial, the temperature compensation circuit 15 performs temperature compensation in an analog manner in accordance with coefficient information of the polynomial. Temperature compensation in an analog manner is, for example, temperature compensation implemented by addition processing of analog signals, i.e., current signals, voltage signals, and the like. Specifically, coefficient information of a polynomial for temperature compensation is stored in the memory 17, and the logic circuit 13 reads out the coefficient information from the memory 17, for example, and sets it in a register of the temperature compensation circuit 15. Then, the temperature compensation circuit 15 performs temperature compensation in an analog manner in accordance with the coefficient information set in the register.

[0053] In addition, the temperature compensation circuit 15 can also perform temperature compensation in a digital manner. In this case, the temperature compensation circuit 15 is implemented by, for example, a logic circuit. Specifically, the temperature compensation circuit 15 performs digital temperature compensation processing in accordance with temperature detection information, i.e., temperature detection data, of the temperature sensor circuit 16. For example, the temperature compensation circuit 15 calculates frequency adjustment data in accordance with the temperature detection data. Then, the capacitance value of the variable capacitance circuit of the oscillation circuit 11 is adjusted in accordance with the calculated frequency adjustment data, whereby temperature compensation processing of the oscillation frequency of the oscillation circuit 11 is implemented. In this case, the variable capacitance circuit of the oscillation circuit 11 is implemented by a capacitor array having a plurality of capacitors weighted in a binary manner and a switch array. Further, the memory 17 stores a lookup table indicating a correspondence relationship between temperature detection data and frequency adjustment data, and the temperature compensation circuit 15 performs temperature compensation processing of calculating frequency adjustment data in accordance with temperature data using the lookup table read out from the memory 17 by the logic circuit 13.

[0054] Temperature sensor circuit 16 is a sensor circuit for detecting temperature. Specifically, temperature sensor circuit 16 outputs a temperature-dependent voltage that varies according to the ambient temperature as a temperature detection voltage. For example, temperature sensor circuit 16 generates the temperature detection voltage using circuit elements with temperature dependence. Specifically, temperature sensor circuit 16 outputs a temperature detection voltage whose voltage value varies with temperature by utilizing the temperature dependence of the forward voltage of a PN junction. The forward voltage of the PN junction can be, for example, the base / emitter voltage of a bipolar transistor.

[0055] In addition, when performing digital temperature compensation processing, the temperature sensor circuit 16 measures the ambient temperature and other temperatures, and outputs the result as temperature detection data. The temperature detection data is data that increases or decreases monotonically relative to temperature, for example. As the temperature sensor circuit 16 in this case, a temperature sensor circuit utilizing the temperature-dependent characteristics of the oscillation frequency of a ring oscillator can be used. Specifically, the temperature sensor circuit 16 includes a ring oscillator and a counter circuit. The counter circuit counts the oscillation signal of the ring oscillator, i.e., the output pulse signal, during a counting period defined by a clock signal based on the oscillation signal OSC from the oscillation circuit 11, and outputs its count value as temperature detection data.

[0056] Memory 17 stores various information used in integrated circuit 10. Memory 17 can be implemented, for example, using non-volatile memory. Non-volatile memory is an EEPROM such as FAMOS (Floating Gate Avalanche Injection MOS) memory or MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory, but is not limited to these; it can also be an OTP (One Time Programmable) memory or a fuse-type ROM. Alternatively, memory 17 can also be implemented using volatile memory such as RAM.

[0057] and, Figure 4 , Figure 5 Terminals TXA and TXB are connected via Figure 2 , Figure 9 The contact plates 36 and 37 are used for connection. Specifically, the oscillation circuit 11 is electrically connected to the vibrating element 5 via terminals TXA and TXB, which are implemented through contact plates 36 and 37. Furthermore, terminal TCK is implemented through contact plate 38. That is, the clock signal CK from the output buffer circuit 12 is output to the outside via terminal TCK, which is implemented through contact plate 38, from external connection terminal 91. Additionally, terminals TVDD and TGND are implemented through... Figure 2 , Figure 9The contact pads 39, 68 are implemented. That is, the power supply voltages VDD, GND are supplied to the integrated circuit 10 via the terminals TVDD, TGND implemented by the contact pads 39, 68. Specifically, VDD, GND are supplied to the power supply circuit 14. Further, the terminal TOE is implemented by the contact pad 69. That is, the output enable signal OE is input to the integrated circuit 10 via the terminal TOE implemented by the contact pad 69. For example, to the logic circuit 13.

[0058] Figure 6 A configuration example of the oscillation circuit 11 is shown. As shown in Figure 6 the oscillation circuit 11 includes the inverter circuits DV1, DV2 and the variable capacitance circuits CV1, CV2. The inverter circuit DV1 is a drive circuit of the vibration element 5, and the input node is connected to one end of the vibration element 5 and the output node is connected to the other end of the vibration element 5. The inverter circuit DV2 buffers the output signal of the inverter circuit DV1 and outputs it as the oscillation signal OSC. The inverter circuits DV1, DV2 are supplied with the regulated power supply voltage VREG1 and GND and operate. The regulated power supply voltage VREG1 is generated by a regulator possessed by the power supply circuit 14.

[0059] One end of the variable capacitance circuit CV1 is connected to one end of the vibration element 5 and the other end is connected to the GND node. One end of the variable capacitance circuit CV2 is connected to the other end of the vibration element 5 and the other end is connected to GND. As described above, these variable capacitance circuits CV1, CV2 can be implemented by a variable capacitance element such as a varactor diode whose capacitance is controlled by a temperature compensation voltage, i.e., a capacitance control voltage, or by a circuit having a capacitor array and a switch array and whose capacitance value is controlled by frequency control data.

[0060] Figure 7 A configuration example of the output buffer circuit 12 is shown. As shown in Figure 7 the output buffer circuit 12 includes the NAND circuit NA and the inverter circuits IV1, IV2, IV3. Thus, the output buffer circuit 12 is configured by, for example, a plurality of signal inversion circuits or the like. Further, the oscillation clock signal, i.e., the oscillation signal OSC from the oscillation circuit 11 is input to the 1st input node of the NAND circuit NA and the enable signal EN from the logic circuit 13 is input to the 2nd input node. For example, when the output enable signal OE input from the terminal TOE is the active level, i.e., the high level, the enable signal EN becomes the high level, the oscillation signal OSC is buffered by the NAND circuit NA and the inverter circuits IV1, IV2, IV3 and output as the clock signal CK. On the other hand, when the output enable signal OE input from the terminal TOE is the inactive level, i.e., the low level, the enable signal EN becomes the low level and the output of the output buffer circuit 12 is fixed to the low level.

[0061] Next, the manufacturing method of the vibration device 1 in this embodiment will be described. Figure 8 This is a manufacturing process diagram illustrating an example of a method for manufacturing the vibrating device 1.

[0062] In the integrated circuit formation process (S11), a semiconductor substrate 20 is prepared, such as... Figure 1 , Figure 2 As shown, an integrated circuit 10 is formed on the lower surface, or second surface 22, of the semiconductor substrate 20. In the redistribution wiring layer formation process (S12), for example, a redistribution wiring layer 8 is formed, having an insulating layer 80, wiring 82, external connection terminals 91, 92, etc., so that the contact pads 38, 39, etc. of the integrated circuit 10 are electrically connected to the external connection terminals 91, 92, etc. In the base thinning process (S13), the mounting surface side of the vibration element 5 of the semiconductor substrate 20, i.e., the first surface 21, is ground to thin the base 2. That is, the base 2 is thinned.

[0063] In the hole formation process (S14), through holes are formed. Specifically, holes are formed on the semiconductor substrate 20 by dry etching, and then formed into the substrate by wet etching. Figure 2 The process continues until the first metal layer, i.e., metal layer 31, of the wiring layer 30. In the insulating layer formation process (S15), the semiconductor substrate 20 is thermally oxidized to form an insulating film, i.e., insulating layer 44, based on silicon oxide (SiO2) or resin layer, on the surface of the semiconductor substrate 20, especially on the inner surface of the through holes. In the through electrode formation process (S16), through electrodes 40 and 41 are formed by filling the through holes with a conductive material such as copper. In the vibration element placement process (S17), the vibration element 5 is prepared and bonded to the first surface 21 of the semiconductor substrate 20 via bonding members 60 and 61. In the cover bonding process (S18), the cover 7 is prepared and bonded to the base 2 via bonding members 71 and 72 under reduced pressure. In the monolithization process (S19), the vibration device 1 is monolithized using a cutting machine or the like. Through the above processes, the vibration device 1 is obtained.

[0064] As described above, in this embodiment, a first semiconductor wafer having multiple bases 2, each having a vibration element 5 and an integrated circuit 10, is bonded to a second semiconductor wafer having multiple covers 7, thereby joining the multiple bases 2 and the multiple covers 7. Then, the vibration device 1 is monolithically packaged, thereby manufacturing multiple vibration devices 1. For example, a small vibration device 1 with a length and width of about 1 mm to a few mm and a thickness of less than 1 mm is manufactured. In this way, a wafer-level packaged (WLP) vibration device 1 can be realized, enabling the manufacture of high-volume, low-cost vibration devices 1. That is, vibration devices 1 having vibration elements 5 and integrated circuits 10 can be manufactured simultaneously through wafer-level batch processing.

[0065] 2. Configuration relationship between through electrodes and external connection terminals

[0066] Figure 9 is a plan view showing a configuration example of the through electrodes 40, 41, the external connection terminals 91, 92, 93, 94, the integrated circuit 10, and the like in the vibration device 1 of the present embodiment. In Figure 9 , the relationship between the configuration positions of the respective circuits of the integrated circuit 10 and the configuration positions of the through electrodes 40, 41, the external connection terminals 91, 92, 93, 94 is shown. Figure 9 is a plan view when the base 2 is viewed from the negative side in the Z-axis direction, and the outer shapes of the through electrodes 40, 41 located on the positive side in the Z-axis direction with respect to the base 2 on which the integrated circuit 10 is formed, and the outer shapes of the external connection terminals 91, 92, 93, 94 located on the negative side in the Z-axis direction with respect to the base 2 are shown by broken lines. Figure 10 shows the configuration positions of the external connection terminals 91, 92, 93, 94 in the bottom surface of the vibration device 1, and is a plan view when the bottom surface of the vibration device 1 is viewed from the negative side in the Z-axis direction. In Figure 9 , Figure 10 , the external connection terminals 91, 92, 93, 94 are rectangular in shape, but these terminals can not be strictly rectangular in shape, and can be, for example, a shape in which the corners are chamfered, or a shape other than a rectangular shape. Further, in Figure 9 , the layout configuration is shown in a case where the integrated circuit 10 has the temperature compensation circuit 15, the temperature sensor circuit 16, and the like, but, as Figure 4 explained, the integrated circuit 10 can also be configured not to have the temperature compensation circuit 15, the temperature sensor circuit 16, and the like. In this case, in Figure 9 , the layout configuration in which the configuration of the temperature compensation circuit 15, the temperature sensor circuit 16, and the like is canceled and the blank area thereof is filled up can be adopted.

[0067] As described above, the vibration device 1 of the present embodiment includes the base 2 including the semiconductor substrate 20 and the through electrodes 40, 41 that pass through between the first surface 21 and the second surface 22 of the semiconductor substrate 20, the vibration element 5 that is disposed on the first surface 21 side of the semiconductor substrate 20, and the external connection terminals 91, 92, 93, 94 that are disposed on the second surface 22 side of the semiconductor substrate 20 through the insulating layer 80. Further, as Figure 9As shown, the semiconductor substrate 20 has an oscillation circuit 11 and an output buffer circuit 12 arranged on the second surface 22. The oscillation circuit 11 is electrically connected to the vibration element 5 via the through electrodes 40, 41, and causes the vibration element 5 to oscillate to generate an oscillation signal OSC. The output buffer circuit 12 outputs a clock signal CK based on the oscillation signal OSC. For example, the oscillation circuit 11 causes the vibration element 5 to oscillate, thereby generating the oscillation signal OSC, which is buffered by the output buffer circuit 12 and output as the clock signal CK. Further, the clock signal CK from the output buffer circuit 12 is output from the terminal TCK realized by the contact pad 38. Moreover, as shown, the contact pad 38 is electrically connected to the external connection terminal 91, and thus the clock signal CK from the output buffer circuit 12 is output from the external connection terminal 91 to the outside of the vibration device 1. Figure 4 、 Figure 5 Figure 1 、 Figure 2

[0068] Figure 9 Moreover, as shown, in the vibration device 1 of the present embodiment, the through electrodes 40, 41 and the external connection terminal 91 are arranged so as not to overlap when viewed from the direction orthogonal to the first surface 21. For example, the through electrodes 40, 41 that electrically connect the vibration element 5 and the integrated circuit 10, and the external connection terminal 91 that outputs the clock signal CK are arranged so as not to overlap when viewed from the Z-axis direction. In this way, in the vibration device 1 of the present embodiment, in the WLP (Wafer Level Package) that contains the integrated circuit 10 having the oscillation circuit 11 and the output buffer circuit 12, and the vibration element 5, the through electrodes 40, 41 that electrically connect the vibration element 5 and the oscillation circuit 11 of the integrated circuit 10, and the external connection terminal 91 that outputs the clock signal CK are arranged so as not to overlap when viewed from above. That is, the through electrodes 40, 41 that are part of the wiring that is electrically connected to the vibration element 5, and the external connection terminal 91 that outputs the clock signal CK based on the oscillation signal OSC, which are external connection terminals through which AC signals flow, are arranged so as not to overlap when viewed from above, and thus the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91 can be reduced.

[0069] ​​​For example, in the present embodiment, unlike the case of using the existing ceramic package, the vibration element 5 is directly mounted on the semiconductor substrate 20, and the vibration device 1 is configured, and thus the following unique problem occurs. In the packaging of the small vibration device 1 based on WLP, the through electrodes 40, 41 called via holes or through holes, which are electrically connected to the vibration element 5, are formed in the semiconductor substrate 20 on the lower surface, that is, the second surface 22 of the semiconductor substrate 20 that constitutes a part of the hermetic package. Further, the through electrodes 40, 41 electrically connected to the vibration element 5 particularly have an adverse effect on the oscillation characteristics such as the oscillation frequency when a terminal or an electrode of an alternating current signal, that is, an AC signal is disposed in the vicinity to capacitively couple. Further, a thin insulating layer 80 formed of a resin layer such as polyimide is formed on the second surface 22 side of the semiconductor substrate 20, and further, for example, four external connection terminals 91 to 94 are formed on the lower surface of the insulating layer 80. Here, the insulating layer 80 is thinner than the semiconductor substrate 20, and for example, is 0.1 mm or less. Further, as shown in Figure 2 the surrounding of the through electrodes 40, 41, a thin insulating layer 44 is also formed. Further, unlike the existing ceramic package, the semiconductor substrate 20, which can be a dielectric or a conductor, is interposed between the through electrodes 40, 41 and the external connection terminals 91 to 94. Therefore, when it is assumed that the through electrodes 40, 41 and the external connection terminal 91 for outputting the clock signal CK of the AC signal are disposed in overlap when viewed from above, since they are disposed with the thin insulating layers 80, 44 and the like interposed therebetween, the capacitive coupling increases, and an adverse effect on the oscillation characteristics occurs. That is, the capacitance value is inversely proportional to the distance between the electrodes, and thus the capacitance based on the thin insulating layers 80, 44 increases. Further, when the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91 increases, the signal component of the clock signal CK in the external connection terminal 91 is transmitted to the vibration element 5 or the oscillation circuit 11 via the through electrodes 40, 41 as noise, and a problem such as degradation of the oscillation characteristics occurs.

[0070] Therefore, in the present embodiment, as shown in Figure 9 the through electrodes 40, 41 electrically connected to the vibration element 5 and the external connection terminal 91 outputting the clock signal CK of the AC signal are disposed not to overlap when viewed from above. In this way, if the through electrodes 40, 41 and the external connection terminal 91 are disposed not to overlap when viewed from above, the distance between the through electrodes 40, 41 and the external connection terminal 91 can be pulled apart compared to the case where the through electrodes 40, 41 and the external connection terminal 91 are disposed to overlap when viewed from above. Thereby, the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91 can be reduced, and degradation of the oscillation characteristics of the vibration element 5 and the like can be effectively suppressed.

[0071] In addition, the external connection terminals 91 to 94 of the vibration device 1 are mounted by being connected to terminals or wiring of a circuit board or the like on which the vibration device 1 is mounted, by soldering or the like. Therefore, as the external connection terminals 91 to 94, terminals suitable for mounting by soldering or the like are preferable, and heat resistance and strength that do not break at the time of mounting are also required.

[0072] In this regard, in the above-described Patent Document 1, connection pads of an integrated circuit are used as the external connection terminals. For example, connection pads formed of a metal layer of an uppermost layer of a wiring layer are used as the external connection terminals. However, the connection pads of the integrated circuit are not terminals suitable for mounting by soldering or the like, have a small area, and have low heat resistance and strength, and thus, there is a possibility that problems such as breakage at the time of mounting occur.

[0073] In contrast to this, in the vibration device 1 of the present embodiment, the external connection terminals 91 to 94 provided on the side of the second surface 22 of the semiconductor substrate 20 through the insulating layer 80 are used. That is, instead of using the contact pads 38, 39, 68, 69 of the integrated circuit 10, the external connection terminals 91 to 94 provided separately from these connection pads, for example, formed in a manufacturing process of the reconfigured wiring layer 8 are used. Therefore, terminals suitable for mounting based on soldering or the like can be used as the external connection terminals 91 to 94. For example, the external connection terminals 91 to 94 can be made large in area, and the strength can be ensured by increasing the film thickness, as compared with the contact pads 38, 39, 68, 69. Therefore, the external connection terminals 91 to 94 can be easily mounted by being connected to terminals or wiring of the outside, and breakage or the like at the time of mounting can also be suppressed.

[0074] On the other hand, when the external connection terminals 91 to 94 become large in area, for example, the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminals 91 can increase. In this regard, in the present embodiment, the through electrodes 40, 41 and the external connection terminals 91 are arranged so as not to overlap in plan view, and thus, even when the external connection terminals 91 become large in area, the deterioration of the oscillation characteristics due to the capacitive coupling can be suppressed. Therefore, according to the present embodiment, the provision of the external connection terminals 91 to 94 that are easy to mount based on connection to terminals or wiring of the outside, have high heat resistance and strength, and are not likely to break, and the suppression of the deterioration of the oscillation characteristics due to the capacitive coupling between the through electrodes 40, 41 and the external connection terminals 91 can be simultaneously achieved.

[0075] Further, in the present embodiment, as described above, Figure 9As shown, the base 2 has a side SD1 and a side SD2 opposite to the side SD1. The side SD1 is a first side, and the side SD2 is a second side. Further, the base 2 has a side SD3 and a side SD4 opposite to the side SD3. The side SD3 is a third side, and the side SD4 is a fourth side. For example, when viewed from above, the base 2 has a rectangular shape having the sides SD1, SD2, SD3, and SD4. Note that the rectangular shape need not be a strict rectangular shape, and can be a shape in which the corners are rounded, for example.

[0076] Further, as shown in FIG. 1, the through electrode 40 is electrically connected to the through electrode 41. For example, the through electrode 40 is electrically connected to the through electrode 41 via a wiring layer 30 formed by a semiconductor manufacturing process. For example, the wiring layer 30 is formed by a metal layer 31 of the wiring layer 30 being patterned at a position corresponding to the lower end of the through electrode 40. Thus, the through electrode 40 is electrically connected to the through electrode 41. Figure 9 As shown, when viewed from above, the through electrodes 40, 41 are disposed closer to the first side, i.e., the side SD1, than to the second side, i.e., the side SD2. On the other hand, when viewed from above, the external connection terminal 91 outputting the clock signal CK is disposed closer to the side SD2 than to the side SD1. For example, a center line between the side SD1 and the side SD2 is set as CL. For example, the distance of the side SD1 from the center line CL is equal to the distance of the side SD2 from the center line CL. In this case, the through electrodes 40, 41 are disposed in a first region between the side SD1 and the center line CL, for example. On the other hand, the external connection terminal 91 is disposed in a second region between the side SD2 and the center line CL, for example. In this way, the through electrodes 40, 41 are disposed closer to the side SD1 side, and the external connection terminal 91 is disposed closer to the side SD2 side. Thus, the distance between the through electrodes 40, 41 and the external connection terminal 91 can be pulled apart. As a result, the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91 can be reduced, and the generation of deterioration of the oscillation characteristics of the vibration element 5 can be suppressed, and the like.

[0077] Further, as shown in FIG. 1, the through electrode 40 is electrically connected to the through electrode 41. For example, the through electrode 40 is electrically connected to the through electrode 41 via a wiring layer 30 formed by a semiconductor manufacturing process. For example, the wiring layer 30 is formed by a metal layer 31 of the wiring layer 30 being patterned at a position corresponding to the lower end of the through electrode 40. Thus, the through electrode 40 is electrically connected to the through electrode 41. Figure 1 Figure 2 Figure 9 As shown, in the present embodiment, the through electrode contact pads 36, 37 electrically connected to the through electrodes 40, 41 are disposed on the second surface 22 of the semiconductor substrate 20. For example, the through electrode contact pads 36, 37 are formed by the metal layer 31 of the wiring layer 30 being patterned at positions corresponding to the lower ends of the through electrodes 40, 41. Further, as shown in FIG. 1, the through electrode contact pads 36, 37 are electrically connected to the through electrodes 40, 41 via the metal layer 31 of the wiring layer 30. Figure 9 ​​As shown, in top view, the contact pads 36 and 37 for the through electrodes are positioned closer to side SD1 than side SD2. For example, contact pads 36 and 37 are positioned in the first region between side SD1 and center line CL, and are electrically connected to the through electrodes 40 and 41. This not only increases the distance between the through electrodes 40 and 41 and the external connection terminal 91, but also increases the distance between the contact pads 36 and 37 for the through electrodes and the external connection terminal 91. As a result, not only can the capacitive coupling capacitance between the through electrodes 40 and 41 and the external connection terminal 91 be reduced, but also the capacitive coupling capacitance between the contact pads 36 and 37 and the external connection terminal 91 can be reduced, thus suppressing the deterioration of the oscillation characteristics of the vibration element 5.

[0078] Furthermore, wiring LA and LB are provided on the second surface 22 of the semiconductor substrate 20 to electrically connect the contact pads 36 and 37 for the through electrodes and the oscillation circuit 11. For example... Figure 4 , Figure 5 As shown, wiring LA and LB are wirings connecting the oscillating circuit 11 and terminals TXA and TXB implemented via contact plates 36 and 37. For example, wiring LA is connected to one of the input and output nodes of the oscillating circuit 11, and wiring LB is connected to the other node. Furthermore, wiring LA and LB are... Figure 2 At least one of the metal layers 31 and 32 of the wiring layer 30 is formed. Furthermore, as... Figure 9 As shown, in top view, wirings LA and LB are positioned closer to side SD1 than side SD2. For example, at least one of wirings LA and LB is positioned closer to side SD1 than side SD2. For example, wirings LA and LB are positioned in the first region between side SD1 and center line CL, connecting the oscillation circuit 11 and terminals TXA and TXB implemented via contact plates 36 and 37. This not only increases the distance between the through electrodes 40 and 41 and the external connection terminal 91, but also increases the distance between wirings LA and LB and the external connection terminal 91. Consequently, it not only reduces the capacitive coupling capacitance between the through electrodes 40 and 41 and the external connection terminal 91, but also reduces the capacitive coupling capacitance between wirings LA and LB and the external connection terminal 91, thus suppressing the deterioration of the oscillation characteristics of the vibration element 5.

[0079] In addition, such as Figure 1 , Figure 2 As shown, a contact pad 38 for outputting a clock signal CK is disposed on the second surface 22 of the semiconductor substrate 20. For example, as... Figure 4 , Figure 5As shown, the output buffer circuit 12 outputs the clock signal CK to the terminal TCK via the contact pad 38 provided on the second surface 22 of the semiconductor substrate 20. For example, the contact pad 38 for outputting the clock signal is formed of a metal layer 32, which is the uppermost layer of the wiring layer 30 formed by a semiconductor manufacturing process. For example, the contact pad 38 for outputting the clock signal is formed by patterning the metal layer 32. At this time, it is preferable that the contact pad 38 be exposed from the insulating layer 35, which is the passivation film, of the uppermost layer.

[0080] Further, the contact pad 38 for outputting the clock signal and the external connection terminal 91 are electrically connected via the insulating layer 80. For example, the insulating layer 80 is provided between the contact pad 38 and the external connection terminal 91, and the contact pad 38 and the external connection terminal 91 are electrically connected via the insulating layer 80. Specifically, the contact pad 38 and the external connection terminal 91 are electrically connected via the insulating layer 80 that constitutes the redistribution wiring layer 8. That is, they are electrically connected via the insulating layer 80 realized by a resin layer such as polyimide. In this way, by using the external connection terminal 91 provided on the contact pad 38 with the insulating layer 80 interposed therebetween, instead of using the contact pad 38 formed on the second surface 22 of the semiconductor substrate 20, the vibrator 1 can be connected to an external terminal or wiring. For example, in the contact pad 38, it is difficult to realize a large-area and less-breakable external connection terminal suitable for mounting based on soldering or the like. Therefore, when the contact pad 38 is used as the external connection terminal, there can be a problem in that mounting of the vibrator 1 is difficult, or the external connection terminal is broken. In this regard, in the present embodiment, the external connection terminal 91 is provided separately from the contact pad 38, and thus the occurrence of the above-described problem can be suppressed. Further, the distance between the external connection terminal 91 and the through electrodes 40 and 41 can be increased, and thus deterioration of the oscillation characteristics can be prevented.

[0081] Further, in the present embodiment, as shown in Figure 1 , Figure 2 , Figure 9 shown, the area of the external connection terminal 91 is larger than that of the contact pad 38 for outputting the clock signal. Similarly, the areas of the external connection terminals 92, 93, and 94 are also increased. The contact pad 38 has an area of, for example, 70 μm to 100 μm or so on one side. The external connection terminals 91, 92, 93, and 94 have an area of, for example, 0.19 mm or more on one side. As shown in Figure 10 , the large-area external connection terminals 91 and the like are provided on the bottom surface of the vibrator 1, and thus connection between the external connection terminals 91 and the like and an external terminal or wiring at the time of mounting the vibrator 1 can be easily performed.

[0082] Further, in the present embodiment, as shown in Figure 1 , Figure 2 , Figure 9As shown, the contact plate 38 for clock signal output and the external connection terminal 91 are configured to overlap when viewed from above. For example, as Figure 1 , Figure 2 As shown, an external connection terminal 91 is disposed below the contact pad 38, separated by an insulating layer 80. Moreover, for example, the contact pad 38 and the external connection terminal 91 disposed below it are electrically connected via a passage contact of the reconfigured wiring layer 8.

[0083] In this way, the shortest path can be used to transport goods from... Figure 4 , Figure 5 The clock signal CK of the output buffer circuit 12 is output to the outside via the contact plate 38 and the external connection terminal 91. As a result, the parasitic capacitance and parasitic resistance in the output path of the clock signal CK can be reduced, and a clock signal CK with good signal characteristics can be output to the outside.

[0084] Furthermore, in this embodiment, such as Figure 9 As shown, in top view, the oscillation circuit 11 is positioned closer to side SD1 than side SD2. For example, the oscillation circuit 11 is positioned in the first region between side SD1 and the center line CL. Specifically, in top view, the oscillation circuit 11 is positioned between side SD1 and the through electrodes 40 and 41. That is, the oscillation circuit 11 is positioned in the region between side SD1 and the line connecting the through electrodes 40 and 41. For example, the oscillation circuit 11 is positioned along side SD1, with its length direction along side SD1. Furthermore, the oscillation circuit 11 is electrically connected to the vibration element 5 via wiring LA and LB, which are also positioned in the first region, and terminals TXA and TXB, implemented through contact pads 36 and 37, causing the vibration element 5 to oscillate.

[0085] For example, the circuit elements constituting the oscillation circuit 11, such as transistors, capacitors, and resistors, have conductive layers, such as metal layers or diffusion layers, that have an area when viewed from above. Therefore, through the capacitive coupling between the conductive layers in the oscillation circuit 11 and the external connection terminal 91, the signal component of the clock signal CK output from the external connection terminal 91 is transmitted to the oscillation circuit 11 as noise, which may adversely affect the oscillation characteristics. In this embodiment, the oscillation circuit 11 is positioned closer to edge SD1 when viewed from above, thus increasing the distance between it and the external connection terminal 91, which is positioned closer to edge SD2 when viewed from above. Therefore, the capacitance of the capacitive coupling between the oscillation circuit 11 and the external connection terminal 91 can be reduced, thereby suppressing the deterioration of the oscillation characteristics of the oscillation circuit 11.

[0086] Furthermore, in this embodiment, such as Figure 9As shown, the output buffer circuit 12 is disposed closer to the side SD2 than to the side SD1 in plan view. For example, the output buffer circuit 12 is disposed in the second region between the side SD2 and the center line CL. Specifically, the output buffer circuit 12 is disposed in the vicinity of the corner where the side SD2 and the side SD3 intersect.

[0087] For example, the circuit elements such as transistors that constitute the output buffer circuit 12 have a conductive layer such as a metal layer or a diffusion layer having an area in plan view. Therefore, due to the capacitive coupling between the conductive layer in the output buffer circuit 12 and the through electrodes 40, 41, the signal component of the clock signal CK in the output buffer circuit 12 is transmitted as noise to the vibration element 5 and the oscillation circuit 11 via the through electrodes 40, 41, and thus, it is possible to adversely affect the oscillation characteristics. In this regard, in the present embodiment, the output buffer circuit 12 is disposed closer to the side SD2 in plan view, and thus, it is possible to pull apart the distance between the through electrodes 40, 41 disposed closer to the side SD1 in plan view. Therefore, it is possible to reduce the capacitance of the capacitive coupling between the output buffer circuit 12 and the through electrodes 40, 41, and thus, it is possible to suppress the generation of degradation of the oscillation characteristics and the like.

[0088] Further, in the present embodiment, the external connection terminals 92, 94 for constant potential signals are included on the side of the second face 22 of the semiconductor substrate 20, which are provided across the insulating layer 80. Here, the constant potential signal is a signal that is not an AC signal, and is, for example, a signal whose potential does not dynamically change. The constant potential signal can also be a power supply signal. For example, the external connection terminal 92 is a terminal to which a power supply signal, that is, a power supply voltage VDD, is supplied. Further, the external connection terminal 94 is a terminal to which a constant potential signal, that is, an output enable signal OE, is input at a fixed low level or high level at the time of operation of the vibration device 1. Moreover, as shown in FIG. 1, the external connection terminal 92 for the power supply voltage VDD and the external connection terminal 94 for the output enable signal OE are disposed in the vicinity of the corner where the side SD1 and the side SD2 intersect. Figure 9 As shown, the through electrode 40 is disposed so as to overlap the external connection terminal 92 for the power supply voltage VDD in plan view. Further, the through electrode 41 is disposed so as to overlap the external connection terminal 94 for the output enable signal OE in plan view. In addition, the external connection terminal for the constant potential signal is not limited to the external connection terminal for the power supply voltage VDD or the external connection terminal for the output enable signal OE, and can be, for example, an external connection terminal for GND or the like.

[0089] For example, as shown in FIG. 1, the external connection terminal 92 for the power supply voltage VDD and the external connection terminal 94 for the output enable signal OE are disposed in the vicinity of the corner where the side SD1 and the side SD2 intersect. Figure 10As shown, the external connection terminals 91 to 94 are terminals having a large area, and thus, a large area of the bottom surface of the vibration device 1 is occupied by the external connection terminals 91 to 94. Thus, when the external connection terminals 91 to 94 are arranged without any design, the through electrodes 40, 41 and the external connection terminal 91 for clock signal output overlap each other in plan view, and a situation in which the oscillation characteristics are deteriorated or the like can occur. In this regard, in the present embodiment, the external connection terminals 92, 94 for constant potential signals are arranged so as to overlap the through electrodes 40, 41 in plan view. In this way, if the external connection terminals 92, 94 are arranged so as to overlap the through electrodes 40, 41, the external connection terminal 91 for clock signal output can be arranged in the remaining area of the arrangement area of the external connection terminals 92, 94 in the area of the bottom surface of the vibration device 1. Thus, the through electrodes 40, 41 and the external connection terminal 91 for clock signal output are easily arranged so as not to overlap each other in plan view, and the occurrence of deterioration of the oscillation characteristics or the like can be suppressed.

[0090] Further, in the present embodiment, as shown in FIG. 1, the vibration device 1 includes a lid 7 that is joined to the base 2 in a manner of housing the vibration element 5. For example, the lid 7 is joined to the base 2 by joining members 71, 72. If such a lid 7 is provided, the vibration element 5 can be arranged in a housing space SP formed by joining the base 2 and the lid 7. For example, the vibration element 5 can be arranged in the housing space SP that is hermetically sealed, and the vibration element 5 or the like can be appropriately protected from impacts, dust, heat, humidity, or the like. Figure 1

[0091] Here, as with the base 2, the lid 7 can be implemented by a silicon substrate. Thus, the coefficient of linear expansion of the base 2 and the lid 7 is equal, thermal stress due to thermal expansion is suppressed, and a vibration device 1 having excellent vibration characteristics can be implemented. Further, both the base 2 and the lid 7 can be formed by a semiconductor manufacturing process. Thus, the vibration device 1 can be manufactured with high precision, and miniaturization thereof can be achieved. However, the lid 7 is not limited to a silicon substrate, and can be implemented by a semiconductor substrate such as Ge, GaP, GaAs, InP, or the like.

[0092] In addition, the vibration device 1 can be configured not to include the lid 7 that is joined to the base 2. For example, the base 2 in which the vibration element 5 is arranged on the first surface 21 side and the integrated circuit 10 is formed on the second surface 22 can be housed in another package or in a container that becomes a thermostat tank in a quartz oscillator (OCXO) with a thermostat tank.

[0093] Further, in the present embodiment, as shown in FIG. 1, the vibration device 1 includes a lid 7 that is joined to the base 2 in a manner of housing the vibration element 5. For example, the lid 7 is joined to the base 2 by joining members 71, 72. If such a lid 7 is provided, the vibration element 5 can be arranged in a housing space SP formed by joining the base 2 and the lid 7. For example, the vibration element 5 can be arranged in the housing space SP that is hermetically sealed, and the vibration element 5 or the like can be appropriately protected from impacts, dust, heat, humidity, or the like. Figure 9 ​In the present embodiment, the direction from the side SD1 toward the side SD2 is set as the first direction, and the direction from the side SD3 toward the side SD4 is set as the second direction. The first direction is the direction along the X axis, and the second direction is the direction along the Y axis. Further, the opposite direction of the first direction is set as the third direction, and the opposite direction of the second direction is set as the fourth direction. At this time, the oscillation circuit 11 is arranged on the first direction side of the side SD1, and the through electrodes 40, 41 are arranged on the first direction side of the oscillation circuit 11. Further, the temperature sensor circuit 16 is arranged on the second direction side of the oscillation circuit 11. Further, the output buffer circuit 12, the logic circuit 13, the power supply circuit 14, the temperature compensation circuit 15, and the memory 17 are arranged on the first direction side of the through electrodes 40, 41. That is, the output buffer circuit 12, the logic circuit 13, the power supply circuit 14, the temperature compensation circuit 15, and the memory 17 are arranged in the region between the through electrodes 40, 41 and the side SD2. Furthermore, the temperature compensation circuit 15 is arranged on the second direction side of the output buffer circuit 12, and the logic circuit 13, the power supply circuit 14 are arranged on the second direction side of the temperature compensation circuit 15, and the memory 17 is arranged on the second direction side of the logic circuit 13.

[0094] Further, in the present embodiment, the vibration element 5 is fixed to the semiconductor substrate 20 through the conductive joining members 60, 61, and the temperature sensor circuit 16 is closer to the through electrode 41 than the output buffer circuit 12 is. Thus, in the present embodiment, the vibration element 5 is directly fixed to the semiconductor substrate 20 through the joining members 60, 61, and thus, heat generation in the output buffer circuit 12 is easily transferred to the vibration element 5 compared to the conventional oscillator using a ceramic package. That is, the temperature of the vibration element 5 also immediately rises due to heat generation in the output buffer circuit 12. Further, since there is no ceramic having low thermal conductivity between the output buffer circuit 12 and the vibration element 5, heat generation in the output buffer circuit 12 is also easily transferred to the vibration element 5 as radiant heat. For example, the output buffer circuit 12 is a circuit that drives an external load of the oscillator device 1, and thus, a current of, for example, 10 mA or more sometimes flows at the time of driving the external load, and the amount of heat generation is very large. On the other hand, the temperature sensor circuit 16 is closer to the through electrode 41, and thus, the temperature sensor circuit 16 can immediately detect the actual temperature of the vibration element 5 that rises due to heat generation in the output buffer circuit 12. That is, the actual temperature of the vibration element 5 is transferred to the integrated circuit 10 via the through electrode 41 and the like having high thermal conductivity, and can be immediately detected by the temperature sensor circuit 16 disposed at a position closer to the through electrode 41. For example, at the time of starting the oscillator device 1, heat generation in the output buffer circuit 12 is immediately transferred to the vibration element 5 with a short heat transfer path, and thus, the actual temperature of the vibration element 5 becomes high, and this actual temperature of the vibration element 5 is detected by the temperature sensor circuit 16 disposed near the through electrode 41 via the through electrode 41 and the like. Then, the temperature compensation circuit 15 performs temperature compensation processing in accordance with the detected temperature of the temperature sensor circuit 16, and thus, performs temperature compensation of the oscillation frequency corresponding to the actual temperature of the vibration element 5. Thus, it is possible to effectively suppress generation of deterioration of the oscillation characteristics due to an error between the detected temperature in the temperature sensor circuit 16 and the actual temperature of the vibration element 5.

[0095] 3. Modification

[0096] Next, various modifications of the present embodiment will be described. For example, Figure 11 is another example of the through electrode 40. In addition, the same applies to the through electrode 41, and thus, the description is omitted. In Figure 11In the inner wall of the through-hole of the base 2, an insulating layer 44 is formed, and a resin layer 45 is formed on the inner side of the insulating layer 44. Further, the through-electrode 40 is constituted by a metal layer formed on the inner side of the resin layer 45. By this through-electrode 40, the vibration element 5 and the oscillation circuit 11 of the integrated circuit 10 are electrically connected. That is, the contact pad 36 of the vibration element 5 and the contact pad 36 of the integrated circuit 10 are electrically connected by the bonding member 60 constituted by the bump 62 and the through-electrode 40, and the contact pad 36 functions as a terminal TXA, TXB of the oscillation circuit 11. Thus, the vibration element 5 and the oscillation circuit 11 are electrically connected. Figure 4 、 Figure 5 The terminal TXA, TXB of the oscillation circuit 11 is electrically connected to the contact pad 36, and thus the vibration element 5 and the oscillation circuit 11 are electrically connected.

[0097] Further, the output buffer circuit 12 can output the differential clock signals CK, CKX to the outside in the form of a signal such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed Current Steering Logic), or differential CMOS (Complementary MOS). That is, the output buffer circuit 12 can have an output driver for LVDS, an output driver for PECL, an output driver for HCSL, or an output driver for differential CMOS. For example, Figure 12 is a configuration example of an output driver for LVDS. The output driver has a P-type transistor for a current source which flows a drive current of 3.5 mA, P-type and N-type transistors which constitute a differential section which outputs the differential clock signals CK, CKX which are inputted differentially, and an N-type transistor which is provided on the VSS side. A bias voltage BSP is applied to the gate of the P-type transistor which is a current source. Thus, a drive current of 3.5 mA flows. Figure 13 is a configuration example of an output driver for PECL. The output driver has a P-type transistor which flows a drive current of 15.25 mA, two P-type transistors which constitute a differential section, and two P-type transistors which constitute a bias current circuit which flows a bias current of 5.7 mA at the node of the clock signals CK, CKX.

[0098] Figure 14 is an example of the configuration of the external connection terminals in the case where the clock signals CK, CKX which are outputted differentially are as Figure 12 、 Figure 13 Figure 14 ​In this case, the oscillator device 1 becomes an external connection terminal having six terminals of the external connection terminals 91a, 91b, 92, 93, 94, 95. The external connection terminals 91a, 91b are terminals for outputting differential clock signals CK, CKX. The external connection terminals 92, 93 are terminals for VDD, GND, and the external connection terminal 94 is a terminal for outputting an enable signal OE. The external connection terminal 95 is an NC (Non Connection) terminal. Figure 14 The external connection terminals 91a, 91b, 92, 93, 94, 95 are also provided on the second surface 22 side of the semiconductor substrate 20 of the base 2 through the insulating layer 80 in the oscillator device 1. Further, the through electrodes 40, 41 and the external connection terminals 91a, 91b for outputting differential clock signals CK, CKX are arranged so as not to overlap in plan view.

[0099] Figure 15 is another example of the structure of the integrated circuit 10, for example, an example of the structure of the integrated circuit 10 used in a programmable voltage controlled quartz oscillator (VCXO). In Figure 15 , a PLL circuit 18 is provided. For example, by providing a PLL circuit 18 of the fractional-N type, it is possible to output clock signals CK, CKX of an arbitrary frequency after multiplying the frequency of the oscillation signal of the oscillation circuit 11. Further, in Figure 15 , a terminal TVC for inputting a frequency control voltage VC is provided. Furthermore, in Figure 15 , a digital interface circuit 19 is also provided. The interface circuit 19 is a circuit that performs interface processing between the oscillator device 1 and an external device, and by this interface circuit 19, it is possible to realize serial data transfer using a data signal SDA, a clock signal SCL. As the interface circuit 19, for example, a circuit that performs I2C (Inter Integrated Circuit), SPI (Serial Peripheral Interface) or the like interface processing can be used. By setting the register of the logic circuit 13 using this interface circuit 19, for example, it is possible to perform setting of the frequency of the clock signals CK, CKX or the like. In addition, in Figure 15 , a temperature compensation circuit 15 that performs digital temperature compensation processing is provided to the logic circuit 13.

[0100] Figure 16 is an example of the external connection terminal arrangement of the oscillator device 1 of the integrated circuit 10 using Figure 15 . In Figure 16 , as in Figure 14 , external connection terminals 91a, 91b, 92, 93, 94 for CK, CKX, VDD, GND, OE are provided. Further, in Figure 16In addition, an external connection terminal 96 for a frequency control voltage VC, an external connection terminal 97 for a data signal SDA, and an external connection terminal 98 for a clock signal SCL are provided, and the vibrator 1 has eight external connection terminals. In this case, for example, the external connection terminals for digital signals such as the external connection terminal 98 for the clock signal SCL and the external connection terminal 97 for the data signal SDA, and the through electrodes 40 and 41 are arranged so as not to overlap when viewed from the top. That is, the external connection terminals for AC signals, that is, digital signals, and the through electrodes 40 and 41 do not overlap when viewed from the top. The digital signals include a plurality of signals of approximately rectangular waves, and the rectangular waves include various frequency components. Therefore, when the external connection terminals to which such digital signals are applied are arranged in the vicinity of the wiring of the through electrodes 40 and 41 connected to the vibration element 5, and the like, the oscillation characteristics are adversely affected. For example, the oscillation frequency is shifted, or a noise signal due to the digital signals is superimposed on the oscillation signal, and the like. In this regard, if the external connection terminals for digital signals and the through electrodes 40 and 41 do not overlap when viewed from the top, it is possible to prevent such problems from occurring.

[0101] As described above, the vibrator according to the present embodiment includes a base including a semiconductor substrate having a first surface and a second surface in an inverse relationship to the first surface, and a through electrode that penetrates between the first surface and the second surface, a vibration element arranged on the first surface side, and an external connection terminal arranged on the second surface side via an insulating layer. In addition, an oscillation circuit electrically connected to the vibration element via the through electrode is arranged on the second surface, and generates an oscillation signal by oscillating the vibration element. An output buffer circuit that outputs a clock signal based on the oscillation signal is also arranged on the second surface. The clock signal from the output buffer circuit is output from the external connection terminal, and the through electrode and the external connection terminal are arranged so as not to overlap when viewed from a direction orthogonal to the first surface.

[0102] As described above, the vibrator according to the present embodiment includes a base including a semiconductor substrate having a first surface and a second surface in an inverse relationship to the first surface, and a through electrode that penetrates between the first surface and the second surface, a vibration element arranged on the first surface side, and an external connection terminal arranged on the second surface side via an insulating layer. In addition, an oscillation circuit electrically connected to the vibration element via the through electrode is arranged on the second surface, and generates an oscillation signal by oscillating the vibration element. An output buffer circuit that outputs a clock signal based on the oscillation signal is also arranged on the second surface. The clock signal from the output buffer circuit is output from the external connection terminal, and the through electrode and the external connection terminal are arranged so as not to overlap when viewed from a direction orthogonal to the first surface.

[0103] Further, in the present embodiment, it can also be that the base has a first side and a second side opposite the first side, and the through electrode is disposed closer to the first side than to the second side when viewed from above, and the external connection terminal is disposed closer to the second side than to the first side when viewed from above.

[0104] In this way, the through electrode is disposed closer to the first side than to the second side, and the external connection terminal is disposed closer to the second side than to the first side, so the distance between the through electrode and the external connection terminal can be pulled apart, and the capacitance of the capacitive coupling between the through electrode and the external connection terminal can be reduced.

[0105] Further, in the present embodiment, it can also be that the second face is provided with a contact pad for the through electrode that is electrically connected to the through electrode, and the contact pad for the through electrode is disposed closer to the first side than to the second side when viewed from above.

[0106] In this way, the distance between the contact pad for the through electrode and the external connection terminal can also be pulled apart, and the capacitance of the capacitive coupling between the contact pad for the through electrode and the external connection terminal can also be reduced.

[0107] Further, in the present embodiment, it can also be that the second face is provided with a wiring that electrically connects the contact pad for the through electrode and the oscillation circuit, and the wiring is disposed closer to the first side than to the second side when viewed from above.

[0108] In this way, the distance between the wiring that electrically connects the contact pad for the through electrode and the oscillation circuit and the external connection terminal can be pulled apart, and the capacitance of the capacitive coupling between the wiring and the external connection terminal can be reduced.

[0109] Further, in the present embodiment, it can also be that the second face is provided with a contact pad for outputting a clock signal, and the contact pad for outputting a clock signal and the external connection terminal are electrically connected via an insulating layer.

[0110] In this way, instead of using the contact pad for outputting a clock signal formed on the second face of the semiconductor substrate, the external connection terminal provided via the insulating layer to this contact pad can be used to connect the vibration device to a terminal or wiring outside.

[0111] Further, in the present embodiment, it can also be that the area of the external connection terminal is larger than the area of the contact pad for outputting a clock signal.

[0112] By providing such a larger-area external connection terminal to the vibration device, the connection between the external connection terminal and a terminal or wiring outside when mounting the vibration device can be easily performed.

[0113] Further, in the present embodiment, it can also be that the contact pad for outputting a clock signal and the external connection terminal are disposed so as to overlap when viewed from above.

[0114] Thus, it is possible to output the clock signal from the output buffer circuit to the outside via the contact pad and the external connection terminal using the shortest path, and it is possible to output the clock signal with good signal characteristics to the outside.

[0115] Further, in the present embodiment, it can also be that, in plan view, the oscillation circuit is disposed at a position closer to the first side than to the second side.

[0116] Thus, by disposing the oscillation circuit at a position closer to the first side, it is possible to pull apart the distance between the external connection terminal disposed at a position closer to the second side and the oscillation circuit, and it is possible to reduce the capacitance of the capacitive coupling between the oscillation circuit and the external connection terminal.

[0117] Further, in the present embodiment, it can also be that, in plan view, the output buffer circuit is disposed at a position closer to the second side than to the first side.

[0118] Thus, by disposing the output buffer circuit at a position closer to the second side, it is possible to pull apart the distance between the through electrode disposed at a position closer to the first side, and it is possible to reduce the capacitance of the capacitive coupling between the output buffer circuit and the through electrode.

[0119] Further, in the present embodiment, it can also be that the vibration device includes an external connection terminal for a constant potential signal provided on the second face side across the insulating layer, and in plan view, the through electrode is disposed so as to overlap the external connection terminal for the constant potential signal.

[0120] Thus, it is possible to dispose the external connection terminal for clock signal output in the remaining region of the disposition region of the external connection terminal for the constant potential signal. Thereby, it is easy to dispose the through electrode and the external connection terminal for clock signal output so as not to overlap, and it is possible to suppress the generation of degradation of the oscillation characteristics and the like.

[0121] Further, in the present embodiment, it can also be that the vibration device includes a lid that is joined to the base in a manner that accommodates the vibration element.

[0122] Thus, it is possible to dispose the vibration element in the accommodation space formed by the base and the lid, and therefore, it is possible to properly protect the vibration element from impacts, dust, heat, humidity, and the like.

[0123] In addition, although the present embodiment has been explained in detail as described above, a person skilled in the art can easily understand various modifications that can be made without departing substantially from the new matters and effects of the present application. Therefore, such modifications are all included in the scope of the present application. For example, in the specification or the drawings, a term that is recorded at least once together with a different term that is more general or synonymous can be replaced with the different term in any place in the specification or the drawings. Furthermore, all combinations of the present embodiment and the modifications are also included in the scope of the present application. Furthermore, the structure, the operation, and the like of the vibration device are not limited to those explained in the present embodiment, and various modifications can be made.

Claims

1. A vibrating device, characterized by, It comprises: a base including a semiconductor substrate having a first surface and a second surface in an opposite relationship to the first surface, and a through electrode through between the first surface and the second surface; a vibration element disposed on the first surface side; and an external connection terminal for clock signal output and an external connection terminal for constant potential signal disposed on the second surface side through an insulating layer, on the second surface is disposed: an oscillation circuit electrically connected to the vibration element via the through electrode, oscillating the vibration element to generate an oscillation signal; and an output buffer circuit outputting a clock signal based on the oscillation signal, the clock signal from the output buffer circuit is output from the external connection terminal for clock signal output, in a plan view from a direction orthogonal to the first surface, the through electrode and the external connection terminal for clock signal output are disposed not to overlap, and the through electrode and the external connection terminal for constant potential signal are disposed to overlap.

2. The vibration device according to claim 1, wherein the base has a first side and a second side opposite to the first side, in the plan view, the through electrode is disposed closer to the first side than to the second side, in the plan view, the external connection terminal for clock signal output is disposed closer to the second side than to the first side.

3. The vibration device according to claim 2, wherein on the second surface is disposed a contact pad for through electrode electrically connected to the through electrode, in the plan view, the contact pad for through electrode is disposed closer to the first side than to the second side.

4. The vibration device according to claim 3, wherein on the second surface is disposed a wiring electrically connecting the contact pad for through electrode and the oscillation circuit, in the plan view, the wiring is disposed closer to the first side than to the second side.

5. The vibration device according to claim 1 or 2, wherein on the second surface is disposed a contact pad for clock signal output outputting the clock signal, the contact pad for clock signal output and the external connection terminal for clock signal output are electrically connected via the insulating layer.

6. The vibration device according to claim 5, wherein an area of the external connection terminal for clock signal output is larger than an area of the contact pad for clock signal output.

7. The vibration device according to claim 5, wherein the contact pad for clock signal output and the external connection terminal for clock signal output are disposed to overlap in the plan view.

8. The vibration device according to claim 2, wherein in the plan view, the oscillation circuit is disposed closer to the first side than to the second side.

9. The vibration device according to claim 2, wherein in the plan view, the output buffer circuit is disposed closer to the second side than to the first side.

10. The vibratory device of claim 1 or 2, wherein: the vibratory device comprises a cover engaged with the base in a manner that houses the vibratory element.

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