A temperature- and supply voltage-adaptive ring oscillator

Abstract

The present invention discloses a temperature- and power supply voltage-adaptive ring oscillator, comprising a power supply voltage-to-current converter, a CTAT current generator, and a current-controlled oscillator. The power supply voltage-to-current converter is used to offset the negative and positive temperature characteristics generated in the circuit, outputting a first current proportional to the power supply voltage. The CTAT current generator is used to increase the width-to-length ratio of a MOS transistor with a preset threshold voltage to be greater than that of a MOS transistor with a conventional threshold voltage, outputting a second current with a negative slope linearly related to temperature. The current-controlled oscillator is used to take the total current (the sum of the first and second currents) as input and output an oscillation frequency. Compared with existing technologies, this device has a simple circuit structure, achieves dual compensation for temperature and power supply voltage, and can be widely used in SoC systems, improving the device's applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of oscillators, and in particular to a ring oscillator capable of self-adapting to temperature and power supply voltage. Background Art

[0002] The open-loop on-chip ring oscillator is a key module in SoC chips. SoC chips require their system programs to operate at a stable clock frequency, ideally independent of environmental factors such as temperature and power supply voltage.

[0003] The common structure of an on-chip ring oscillator is a chain of odd-numbered single-ended or differential inverters biased by a current source. Its oscillation frequency is determined by the total delay of the loop. Assuming the structure of each stage in the inverter chain is identical, the total delay is determined by the delay of each stage. The delay of a single-stage inverter is determined by its size, bias current, threshold voltage, carrier mobility, and load capacitance. Assuming the size is fixed, the load capacitance is fixed, and the inverter delay primarily depends on the bias current, carrier mobility, and threshold voltage. For a current-source-biased inverter, the charge and discharge time of the load capacitance is less correlated with carrier mobility, so the effect of carrier mobility on the delay can be ignored. The threshold voltage directly affects the switching level and decreases linearly with temperature. Therefore, the resonant frequency of a constant-current-biased ring oscillator increases linearly with temperature, making constant-current-biased ring oscillators impractical for direct application in SoC designs.

[0004] To achieve a resonant frequency that is independent of temperature and power supply, the ring oscillator's bias current must exhibit a negatively sloped linear function with temperature. Furthermore, due to nonlinear effects such as the channel length modulation effect of the current source circuit, the bias current increases with increasing power supply voltage, necessitating a power supply voltage adaptive compensation circuit. Based on the above analysis, the resonant frequency of an open-loop ring oscillator increases with increasing temperature. Therefore, to achieve a constant resonant frequency over the entire temperature range, a specific current bias circuit must be designed that exhibits a negatively sloped linear function with temperature and compensates for the channel length modulation effect. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a ring oscillator that is adaptive to temperature and power supply voltage. The device has a simple circuit structure, realizes dual compensation of temperature and power supply voltage, can be widely used in SoC systems, and improves the applicability of the device.

[0006] In order to solve the above technical problems, the present invention provides a ring oscillator capable of self-adapting to temperature and power supply voltage, comprising: a power supply voltage-current converter, a CTAT current generator and a current controlled oscillator;

[0007] The power supply voltage-current converter is used to offset the negative temperature characteristics and positive temperature characteristics generated in the circuit and output a first current proportional to the power supply voltage;

[0008] The CTAT current generator is configured to output a second current having a negative slope linear relationship with temperature by setting a preset threshold voltage MOS transistor and a normal threshold voltage MOS transistor so that the width-to-length ratio of the preset threshold voltage MOS transistor is greater than the width-to-length ratio of the normal threshold voltage MOS transistor;

[0009] The current controlled oscillator is used to obtain the total current after subtracting the first current from the second current as the input of the current controlled oscillator, and output an oscillation frequency.

[0010] Furthermore, the power supply voltage-current converter includes:

[0011] A first power supply voltage, a second power supply voltage, a first ground, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a first resistor;

[0012] Wherein, the gate terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the second power supply voltage; the source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the first power supply voltage; the gate terminal of the first NMOS transistor and the gate terminal and the drain terminal of the second NMOS transistor are respectively connected to the drain terminal of the first PMOS transistor; the gate terminal of the third NMOS transistor and the gate terminal and the drain terminal of the fourth NMOS transistor are respectively connected to the drain terminal of the second PMOS transistor; the source terminal of the first NMOS transistor is connected to the first ground; the source terminals of the second NMOS transistor and the third NMOS transistor are respectively connected to the drain terminal of the first NMOS transistor; the gate terminal of the third NMOS transistor and the gate terminal and the drain terminal of the fourth NMOS transistor are respectively connected to the drain terminal of the second PMOS transistor; The drain end of the OS transistor is respectively connected to the source end of the fourth NMOS transistor and the first end of the first resistor; the gate-drain end of the third PMOS transistor and the gate end of the fourth PMOS transistor with gates and drains shorted are respectively connected to the second end of the first resistor; the source ends of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the first power supply voltage; the gate-drain end of the fifth NMOS transistor and the gate end of the sixth NMOS transistor with gates and drains shorted are respectively connected to the drain end of the fourth PMOS transistor; the source ends of the fifth NMOS transistor and the sixth NMOS transistor are respectively connected to the first ground, and the drain end of the sixth NMOS transistor serves as the current output end of the power supply voltage-current converter.

[0013] Furthermore, the CTAT current generator includes:

[0014] a third power supply voltage, a second ground, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a second resistor, and a first capacitor;

[0015] The source terminals of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are respectively connected to the third power supply voltage; the gate terminals of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected to each other; the gate-drain terminal of the seventh PMOS transistor with its gate and drain shorted is connected to the drain terminal of the eighth NMOS transistor; the drain terminal of the seventh NMOS transistor is respectively connected to the gate terminal of the seventh NMOS transistor and the first end of the second resistor; the second end of the second resistor is connected to the gate-drain terminal of the ninth NMOS transistor with its gate and drain shorted; the source terminals of the ninth NMOS transistor and the seventh NMOS transistor are respectively connected to the third power supply voltage; the drain terminal of the seventh NMOS transistor is respectively connected to the drain terminal of the sixth PMOS transistor, the first end of the first capacitor, and the gate terminal of the eighth NMOS transistor; the second end of the first capacitor is connected to the third power supply voltage; the source terminal of the eighth NMOS transistor is connected to the third power supply voltage; and the drain terminal of the eighth PMOS transistor serves as the current output terminal of the CTAT current generator.

[0016] Furthermore, it also includes: a CTAT current generator starting circuit;

[0017] The CTAT current generator startup circuit includes a ninth PMOS transistor, a tenth PMOS transistor, a tenth NMOS transistor, a fourth power supply voltage, and a third ground;

[0018] The gate bias voltage of the first PMOS transistor is connected to the gate terminals of the tenth NMOS transistor and the tenth PMOS transistor, respectively; the source terminal of the tenth NMOS transistor is connected to the third ground; the drain terminal of the tenth NMOS transistor is connected to the gate terminal of the ninth PMOS transistor and the drain terminal of the tenth PMOS transistor, respectively; the source terminals of the ninth PMOS transistor and the tenth PMOS transistor are connected to a fourth power supply voltage, respectively; and the drain terminal of the ninth PMOS transistor is connected to the gate terminal node of the eighth NMOS transistor.

[0019] Furthermore, the current controlled oscillator includes inverters, wherein the number of the inverters is an odd number, and each inverter is connected end to end.

[0020] Furthermore, the oscillation frequency output by the current-controlled oscillator is proportional to the total current.

[0021] Furthermore, the seventh NMOS transistor and the eighth NMOS transistor are the preset threshold voltage MOS transistors.

[0022] Furthermore, the first NMOS transistor and the second NMOS transistor are biased in a subthreshold region.

[0023] The embodiment of the present invention provides a temperature and power supply voltage adaptive ring oscillator, which has the following advantages compared with the prior art:

[0024] A temperature- and power supply voltage-adaptive ring oscillator is designed, including a power supply voltage-current converter, a CTAT current generator, and a current-controlled oscillator. The MOS transistor in the power supply voltage-current converter offsets the negative and positive temperature characteristics generated in the circuit, outputting a first current proportional to the power supply voltage to adjust the slope of the output current-to-power supply voltage characteristic curve of the power supply voltage-current converter, thereby fully compensating for the power supply characteristics of the current-controlled oscillator and the CTAT current generator. Furthermore, a preset threshold voltage MOS transistor and a regular threshold voltage MOS transistor are provided in the CTAT current generator, such that the preset threshold voltage MOS transistor has a larger width-to-length ratio than the regular threshold voltage MOS transistor. A second current with a negative slope linearly related to temperature is output, thereby adjusting the slope of the output current-temperature characteristic curve of the CTAT current generator, thereby fully compensating for the temperature characteristics of the current-controlled oscillator. The total current obtained by subtracting the first and second currents is used as the input of the current-controlled oscillator, which outputs an oscillation frequency. Compared with existing technologies, this device has a simple circuit structure, achieves dual compensation for temperature and power supply voltage, and can be widely used in SoC systems, improving the device's applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The figure is a schematic structural diagram of an embodiment of a temperature and power supply voltage adaptive ring oscillator provided by the present invention.

[0026] Figure 2 This is a schematic diagram of the structure of a power supply voltage-current converter of an embodiment of a temperature and power supply voltage adaptive ring oscillator provided by the present invention;

[0027] Figure 3 This is a schematic diagram of the circuit structure of a CTAT current generator of an embodiment of a temperature and power supply voltage adaptive ring oscillator provided by the present invention;

[0028] Figure 4 The figure is a circuit diagram of an embodiment of a temperature and power supply voltage adaptive ring oscillator provided by the present invention. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] Example 1

[0031] See also Figure 1 , Figure 1 FIG. 1 is a schematic structural diagram of an embodiment of a ring oscillator capable of self-adapting to temperature and power supply voltage provided by the present invention. Figure 1 As shown, the structure includes a power supply voltage-current converter 101, a CTAT current generator 102 and a current controlled oscillator 103, specifically as follows:

[0032] The power supply voltage-current converter 101 is used to offset the negative temperature characteristics and the positive temperature characteristics generated in the circuit and output a first current that is proportional to the power supply voltage.

[0033] In this embodiment, the power supply voltage-current converter includes a first power supply voltage V DD , the second power supply voltage V BP , first ground V SS , a first PMOS transistor M0, a second PMOS transistor M1, a third PMOS transistor M6, a fourth PMOS transistor M7, a first NMOS transistor M2, a second NMOS transistor M3, a third NMOS transistor M4, a fourth NMOS transistor M5, a fifth NMOS transistor M8, a sixth NMOS transistor M9 and a first resistor R0, wherein the first power supply voltage V DD and the second power supply voltage V BP Not supplied by the same power supply.

[0034] In this embodiment, the gate terminals of the first PMOS transistor M0 and the second PMOS transistor M1 are respectively connected to the second power supply voltage V BP The source terminals of the first PMOS tube M0 and the second PMOS tube M1 are connected to the first power supply voltage V DDThe gate terminal of the first NMOS transistor M2 and the gate terminal and the drain terminal of the second NMOS transistor M3 are respectively connected to the drain terminal of the first PMOS transistor M0; the gate terminal of the third NMOS transistor M4 and the gate terminal and the drain terminal of the fourth NMOS transistor M5 are respectively connected to the drain terminal of the second PMOS transistor M1; the source terminal of the first NMOS transistor M2 is connected to the first PMOS transistor M0; the source terminals of the second NMOS transistor M3 and the third NMOS transistor M4 are respectively connected to the drain terminal of the first NMOS transistor M2; the drain terminal of the third NMOS transistor M4 is respectively connected to the source terminal of the fourth NMOS transistor M5 and the first end of the first resistor R0; the gate and drain terminals of the third PMOS transistor M6 and the gate terminal of the fourth PMOS transistor M7 with gate and drain short-circuited are respectively connected to the second end of the first resistor R0; the source terminals of the third PMOS transistor M6 and the fourth PMOS transistor M7 are respectively connected to the first power supply voltage V DD The gate-drain short-circuited gate-drain terminal of the fifth NMOS tube M8 and the gate terminal of the sixth NMOS tube M9 are respectively connected to the drain terminal of the fourth PMOS tube M7; the source terminals of the fifth NMOS tube M8 and the sixth NMOS tube M9 are respectively connected to the first ground V SS The drain end of the sixth NMOS tube M9 is the current output end of the power supply voltage-current converter. The circuit structure of the power supply voltage-current converter is as shown in the attached figure. Figure 2 shown.

[0035] In this embodiment, the first NMOS transistor M2 and the second NMOS transistor M3 are biased in the subthreshold region, so that the drain-source voltage of the first NMOS transistor M2 satisfies the PTAT characteristic that is proportional to the absolute temperature. Since the drain terminal of the first NMOS transistor M2 is connected to the source terminal of the second NMOS transistor M3, the source voltage of the second NMOS transistor M3 is also PTAT. Similarly, the drain-source voltage of the third NMOS transistor M4 satisfies the PTAT characteristic that is proportional to the absolute temperature. Therefore, the source voltage of the fourth NMOS transistor M5 is the sum of the PTAT voltages of the second NMOS transistor M3 and the third NMOS transistor M4, which is recorded as V PTAT .

[0036] Specifically, to bias the MOS transistor in the subthreshold region, under a specific width-to-length ratio of the MOS transistor, applying a small bias current to the MOS transistor can cause it to enter the subthreshold region. Similarly, under a specific current, increasing the width-to-length ratio of the MOS transistor can also cause it to enter the subthreshold region.

[0037] As an example in this embodiment, as shown in the attached Figure 2 As shown in the circuit diagram, when the currents of the first PMOS tube M0 and the second PMOS tube M1 are equal and both are I BIf the first resistor R0 is large, the current flowing through the third NMOS transistor M4 and the first NMOS transistor M2 due to the first resistor R0 can be ignored. Therefore, the current flowing through the first NMOS transistor M2 is 2I B , the current flowing through the second NMOS tube M3 is I B , the current flowing through the third NMOS tube M4 and the fourth NMOS tube M5 is I B Assuming that the width-to-length ratios of the first NMOS transistor M2, the second NMOS transistor M3, the third NMOS transistor M4, and the fourth NMOS transistor M5 are all large, the first NMOS transistor M2 and the second NMOS transistor M3 can be biased in the subthreshold region, wherein the subthreshold region current formula is as follows:

[0038]

[0039] Where W / L represents the width-to-length ratio of the MOS tube, k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, and V T is the thermoelectric potential, V GS is the gate-source voltage, V TH is the threshold voltage.

[0040] As can be seen from the above, the current flowing through the first NMOS tube M2 is 2I B , the current flowing through the second NMOS tube M3 is I B , that is, the current of the first NMOS tube M2 is twice that of the second NMOS tube M3. Based on this, the source voltage of the second NMOS tube M3 is calculated. The calculation formula of the source voltage of the second NMOS tube M3 is as follows:

[0041]

[0042] Similarly, for the source voltage V PTAT The calculation formula is as follows:

[0043]

[0044] Wherein, k0 is the abbreviated temperature coefficient, and the temperature coefficient k0 is greater than zero; setting different width-to-length ratios W / L can modify the temperature coefficient k0. Based on the above formula, the source voltage V of the fourth NMOS transistor M5 can be obtained. PTAT Proportional to absolute temperature T.

[0045] In this embodiment, since the gate-source voltage of the MOS tube has a negative slope linear relationship with the temperature, the gate-source voltage V GS6 It can be expressed as:

[0046] V GS6 =V0-k1T;

[0047] Among them, -k1 is the temperature coefficient, k1 is greater than zero, and V0 is V at room temperature GS6 .

[0048] In this embodiment, if k0 is adjusted so that k0=k1, V can be guaranteed under reasonable circuit settings. GS6 Negative temperature characteristics and V PTAT The positive temperature characteristics of the transistors M6 and M7 cancel each other out. On this basis, the first current flowing through the third PMOS transistor M6, the fourth PMOS transistor M7, the fifth NMOS transistor M8 or the sixth NMOS transistor M9 can be expressed as:

[0049] V GS6 +V PTAT =V0-k1T+k0T=V0;

[0050]

[0051] Among them, I VDD The first current is proportional to the power supply voltage, that is, the output current of the current source increases as the power supply voltage increases, and the current needs to satisfy the requirement that it is only related to the power supply voltage but not to the temperature.

[0052] In this embodiment, the minimum operating voltage of the power supply voltage-current converter circuit structure is less than two MOS tubes V GS , so it can be applied to low power supply voltage.

[0053] In this embodiment, the power supply characteristics of the current controlled oscillator 103 and the CTAT current generator 102 are fully compensated by adjusting the slope of the power supply voltage-current generator output current-power supply voltage characteristic curve.

[0054] The CTAT current generator 102 is configured to output a second current having a negative slope linear relationship with temperature by setting a preset threshold voltage MOS transistor and a normal threshold voltage MOS transistor so that the width-to-length ratio of the preset threshold voltage MOS transistor is greater than the width-to-length ratio of the normal threshold voltage MOS transistor.

[0055] In this embodiment, the CTAT current generator 102 includes a third power supply voltage V DD , second ground V SS , the fifth PMOS tube M 10 , the sixth PMOS tube M 11 , the seventh PMOS tube M 14 , the eighth PMOS tube M 15 , the seventh NMOS tube M 12 , the eighth NMOS tube M 13 , the ninth NMOS tube M 16, a second resistor R1 and a first capacitor C1.

[0056] In this embodiment, the fifth PMOS transistor M 10 , the sixth PMOS tube M 11 The seventh PMOS tube M 14 and the eighth PMOS tube M 15 The source terminals are respectively connected to the third power supply voltage V DD The fifth PMOS tube M 10 , the sixth PMOS tube M 11 The seventh PMOS tube M 14 and the eighth PMOS tube M 15 The gate terminals are connected to each other; the seventh PMOSM with the gate and drain short-circuited 14 The gate-drain end of the tube and the eighth NMOS tube M 13 The drain end is connected to the seventh NMOS tube M 12 The drain end of each of the seventh NMOS tube M 12 The gate end of the second resistor R1 is connected to the first end of the second resistor R1; the second end of the second resistor R1 is connected to the ninth NMOS transistor M with the gate and drain short-circuited 16 The gate and drain terminals of the ninth NMOS tube M are connected; 16 and the seventh NMOS tube M 12 The source terminals are respectively connected to the third power supply voltage V DD The seventh NMOS tube M 12 The drain end of each of the sixth PMOS tube M 11 The drain end, the first end of the first capacitor C1 and the eighth NMOS tube M 13 The second end of the first capacitor C1 is connected to the gate end of the third power supply voltage V DD The eighth NMOS tube M 13 The source terminal is connected to the third power supply voltage V DD The eighth PMOS tube M 15 The drain end is the current output end of the CTAT current generator. The circuit structure of the CTAT current generator is as follows: Figure 3 shown.

[0057] In this embodiment, the seventh NMOS transistor M 12 With the eighth NMOS tube M 13 is a PMOS transistor with a preset threshold voltage, and the other MOS transistors are all MOS transistors with normal threshold voltages. The seventh NMOS transistor M 12 With the eighth NMOS tube M 13 The threshold voltage of the seventh NMOS tube M is higher than that of other NMOS tubes; 12, the eighth NMOS tube M 13 The threshold voltage of the MOSFET is higher than that of the conventional NMOS transistor, but the temperature coefficient of the threshold voltage is the same.

[0058] In this embodiment, since the seventh NMOS transistor M 12 The threshold voltage of the ninth NMOS tube M 16 The threshold voltage of the seventh NMOS tube M is high. 12 The gate-source voltage V GS12 Just like the ninth NMOS tube M 16 The gate-source voltage V GS16 High, the voltage difference is the voltage drop across the first resistor R1R1, so the target current can be generated, wherein the target current is the second current I CTAT .

[0059] As an example in this embodiment, if the preset threshold voltage MOS transistor is the seventh NMOS transistor M 12 The threshold voltage is V THH , the conventional threshold voltage MOS tube is the ninth NMOS tube M 16 The threshold voltage is V THL , and the current through each branch is the same, that is, the seventh NMOS tube M 12 The current of the ninth NMOS tube M 16 The current of the second resistor R1 is the same as the voltage drop across the second resistor R1, and the current I across the second resistor R1 is calculated based on the voltage drop across the second resistor R1. CTAT , and its calculation formula is as follows:

[0060]

[0061] Among them, (W / L)12 and (W / L)16 are the seventh NMOS transistor M 12 and the ninth NMOS tube M 16 The aspect ratio of N is set to be greater than 1, which can ensure that I CTAT It has a negative linear relationship with temperature.

[0062] In this embodiment, the second current I CTAT To generate a linear current that decreases with increasing temperature, but due to the inevitable channel length modulation effect of the field effect tube, a second current I CTAT The current increases as the supply voltage increases.

[0063] In this embodiment, the temperature characteristic of the ICO is fully compensated by adjusting the slope of the temperature characteristic curve of the output current of the CTAT current generator.

[0064] The current controlled oscillator 103 is configured to obtain a total current obtained by subtracting the first current from the second current as an input of the current controlled oscillator and output an oscillation frequency.

[0065] In this embodiment, the current controlled oscillator 103 includes inverters, wherein the number of the inverters is an odd number, and each inverter is connected end to end.

[0066] In this embodiment, the grounds of all inverters are combined, and the power terminals of all inverters are combined as the input terminal of the current controlled oscillator 103. When the input current increases, the resonant frequency of the current controlled oscillator 103 will also increase.

[0067] In this embodiment, the total current obtained by subtracting the output current of the power supply voltage-current converter from the output current of the CTAT current generator is used as the input bias current of the current controlled oscillator 103, thereby achieving dual compensation for temperature and power supply voltage. The input bias current meets two conditions: one is that it is independent of the power supply voltage, and the other is that the current decreases linearly with increasing temperature.

[0068] In this embodiment, the temperature and power supply voltage adaptive ring oscillator further includes a CTAT current generator startup circuit; the CTAT current generator startup circuit includes a ninth PMOS transistor M 18 , the tenth PMOS tube M 19 , the tenth NMOS tube M 17 , the fourth power supply voltage V DD and the third ground V SS , where the tenth NMOS tube M 17 It is an inverted ratio tube.

[0069] In this embodiment, the gate bias voltage of the first PMOS transistor M0 is respectively 17 and the tenth PMOS tube M 19 The gate end of the fifth PMOS tube M is connected, and the fifth PMOS tube M 10 , the sixth PMOS tube M 11 and the seventh PMOS tube M 14 The gate bias voltage of the tenth NMOS tube M is the same as the gate bias voltage of the first PMOS tube M0 and the second PMOS tube M1; 17 The source terminal and the third ground V SS The tenth NMOS tube M 17 The drain end of each of the ninth PMOS tube M 18 The gate end and the tenth PMOS tube M 19 The ninth PMOS tube M 18 and the tenth PMOS tube M 19The source terminals are respectively connected to the fourth power supply voltage V DD The ninth PMOS tube M 18 The drain end of the eighth NMOS tube M 13 The gate nodes are connected.

[0070] In this embodiment, the CTAT current generator startup circuit is used to help the current source circuit start up. Because a self-biased current source circuit may have multiple operating states, one of which is when all devices have no current flow and the circuit remains stable. This state is called When the circuit is in the locked state, the CTAT current generator startup circuit is used to inject current into any branch of the circuit, thereby helping the circuit jump into the normal state.

[0071] In this embodiment, the temperature and power supply voltage adaptive ring oscillator integrates a power supply voltage-current generator, a CTAT current generator and a current controlled oscillator. Based on the CTAT current generator startup circuit, the power supply voltage-current generator and the CTAT current generator are connected, as shown in FIG. Figure 4 After the circuit is integrated, the first power supply voltage, the third power supply voltage and the fourth power supply voltage are the same power supply voltage.

[0072] In summary, the present invention provides a temperature- and power supply voltage-adaptive ring oscillator, comprising: a power supply voltage-to-current converter, a CTAT current generator, and a current-controlled oscillator. The power supply voltage-to-current converter is used to offset the negative and positive temperature characteristics generated in the circuit, outputting a first current proportional to the power supply voltage. The CTAT current generator is used to output a second current with a negative slope linear relationship with temperature by setting a preset threshold voltage MOS transistor and a conventional threshold voltage MOS transistor so that the width-to-length ratio of the preset threshold voltage MOS transistor is greater than that of the conventional threshold voltage MOS transistor. The current-controlled oscillator is used to obtain the current obtained by subtracting the first and second currents as input to the current-controlled oscillator, and output an oscillation frequency. Compared with existing technologies, this device has a simple circuit structure, achieves dual compensation for temperature and power supply voltage, and can be widely used in SoC systems, improving the device's applicability.

[0073] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principles of the present invention. These improvements and substitutions should also be regarded as the scope of protection of the present invention.

Claims

1. A temperature and power supply voltage adaptive ring oscillator, characterized in that: include: Supply voltage-to-current converters, CTAT current generators, and current-controlled oscillators; The power supply voltage-current converter is used to offset the negative temperature characteristics and positive temperature characteristics generated in the circuit and output a first current proportional to the power supply voltage; The CTAT current generator is configured to output a second current having a negative slope linear relationship with temperature by setting a preset threshold voltage MOS transistor and a normal threshold voltage MOS transistor so that the width-to-length ratio of the preset threshold voltage MOS transistor is greater than the width-to-length ratio of the normal threshold voltage MOS transistor; The current controlled oscillator is configured to obtain a total current obtained by subtracting the first current from the second current as an input of the current controlled oscillator, and output an oscillation frequency; The power supply voltage-current converter includes: a first power supply voltage, a second power supply voltage, a first ground, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a first resistor; Wherein, the gate terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the second power supply voltage; the source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the first power supply voltage; the gate terminal of the first NMOS transistor and the gate terminal and the drain terminal of the second NMOS transistor are respectively connected to the drain terminal of the first PMOS transistor; the gate terminal of the third NMOS transistor and the gate terminal and the drain terminal of the fourth NMOS transistor are respectively connected to the drain terminal of the second PMOS transistor; the source terminal of the first NMOS transistor is connected to the first ground; the source terminals of the second NMOS transistor and the third NMOS transistor are respectively connected to the drain terminal of the first NMOS transistor; the gate terminal of the third NMOS transistor and the gate terminal and the drain terminal of the fourth NMOS transistor are respectively connected to the drain terminal of the second PMOS transistor; The drain end of the OS transistor is respectively connected to the source end of the fourth NMOS transistor and the first end of the first resistor; the gate-drain end of the third PMOS transistor and the gate end of the fourth PMOS transistor with gates and drains shorted are respectively connected to the second end of the first resistor; the source ends of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the first power supply voltage; the gate-drain end of the fifth NMOS transistor and the gate end of the sixth NMOS transistor with gates and drains shorted are respectively connected to the drain end of the fourth PMOS transistor; the source ends of the fifth NMOS transistor and the sixth NMOS transistor are respectively connected to the first ground, and the drain end of the sixth NMOS transistor serves as the current output end of the power supply voltage-current converter.

2. The temperature and power supply voltage adaptive ring oscillator according to claim 1, wherein: The CTAT current generator comprises: a third power supply voltage, a second ground, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a second resistor, and a first capacitor; The source terminals of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are respectively connected to the third power supply voltage; the gate terminals of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected to each other; the gate-drain terminal of the seventh PMOS transistor with its gate and drain shorted is connected to the drain terminal of the eighth NMOS transistor; the drain terminal of the seventh NMOS transistor is respectively connected to the gate terminal of the seventh NMOS transistor and the first end of the second resistor; the second end of the second resistor is connected to the gate-drain terminal of the ninth NMOS transistor with its gate and drain shorted; the source terminals of the ninth NMOS transistor and the seventh NMOS transistor are respectively connected to the third power supply voltage; the drain terminal of the seventh NMOS transistor is respectively connected to the drain terminal of the sixth PMOS transistor, the first end of the first capacitor, and the gate terminal of the eighth NMOS transistor; the second end of the first capacitor is connected to the third power supply voltage; the source terminal of the eighth NMOS transistor is connected to the third power supply voltage; and the drain terminal of the eighth PMOS transistor serves as the current output terminal of the CTAT current generator.

3. The temperature and power supply voltage adaptive ring oscillator according to claim 2, wherein: Also includes: CTAT current generator starting circuit; The CTAT current generator startup circuit includes a ninth PMOS transistor, a tenth PMOS transistor, a tenth NMOS transistor, a fourth power supply voltage, and a third ground; The gate bias voltage of the first PMOS transistor is connected to the gate terminals of the tenth NMOS transistor and the tenth PMOS transistor, respectively; the source terminal of the tenth NMOS transistor is connected to the third ground; the drain terminal of the tenth NMOS transistor is connected to the gate terminal of the ninth PMOS transistor and the drain terminal of the tenth PMOS transistor, respectively; the source terminals of the ninth PMOS transistor and the tenth PMOS transistor are connected to a fourth power supply voltage, respectively; and the drain terminal of the ninth PMOS transistor is connected to the gate terminal node of the eighth NMOS transistor.

4. The temperature and power supply voltage adaptive ring oscillator according to claim 2, wherein: The current controlled oscillator includes inverters, wherein the number of the inverters is an odd number, and each inverter is connected end to end.

5. The temperature and power supply voltage adaptive ring oscillator according to claim 1, wherein: The oscillation frequency output by the current-controlled oscillator is proportional to the total current.

6. The temperature and power supply voltage adaptive ring oscillator according to claim 2, wherein: The seventh NMOS transistor and the eighth NMOS transistor are the preset threshold voltage MOS transistors.

7. The temperature and power supply voltage adaptive ring oscillator according to claim 1, wherein: The first NMOS transistor and the second NMOS transistor are biased in a subthreshold region.

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