Signal receiver and signal transceiver

Abstract

The present application provides a signal receiver and a signal transceiver device capable of preventing leakage current. The signal receiver includes a terminal switch pair, a first resistor, a second resistor, and a pull-down circuit. The terminal switch pair receives an operating power. The terminal switch pair has a common control terminal. The first resistor is coupled between a first signal input terminal and the common control terminal. The second resistor is coupled between a second signal input terminal and the common control terminal. The pull-down circuit is coupled between the common control terminal and a reference voltage terminal. The pull-down circuit determines whether to pull down a first control voltage on the common control terminal to the reference voltage according to an enabled state or a power-off state of the signal receiver.

Description

TECHNICAL FIELD

[0001] The present invention relates to a signal receiver, and more particularly, to a signal receiver and a signal transceiver that can prevent unnecessary leakage current from occurring. BACKGROUND

[0002] In the prior art, when the power supply of a signal receiver is turned off and the signal transmitter is still in operation, an undesired conduction path can occur between the connection path of the signal receiver and the signal transmitter, resulting in leakage current. Notably, this leakage current phenomenon can cause unnecessary power consumption and can also damage the circuit components in the electronic device. SUMMARY

[0003] The present invention relates to a signal receiver and a signal transceiver that can prevent unnecessary leakage current from occurring.

[0004] According to an embodiment of the present invention, a signal receiver includes a terminal pair, a first resistor, a second resistor, and a pull-down circuit. The terminal pair receives an operating power supply. The terminal pair has a common control terminal. The first resistor is coupled between a first signal input terminal and the common control terminal. The second resistor is coupled between a second signal input terminal and the common control terminal. The pull-down circuit is coupled between the common control terminal and a reference voltage terminal. The pull-down circuit determines whether to pull down a first control voltage on the common control terminal to the reference voltage according to an enabled state or a power-off state of the signal receiver.

[0005] According to an embodiment of the present invention, a signal transceiver includes a signal transmitter and a signal receiver. The signal receiver includes a terminal pair, a first resistor, a second resistor, and a pull-down circuit. The terminal pair receives an operating power supply. The terminal pair has a common control terminal. The first resistor is coupled between a first signal input terminal and the common control terminal. The second resistor is coupled between a second signal input terminal and the common control terminal. The pull-down circuit is coupled between the common control terminal and a reference voltage terminal. The pull-down circuit determines whether to pull down a first control voltage on the common control terminal to the reference voltage according to an enabled state or a power-off state of the signal receiver. The signal receiver is coupled to the signal transmitter through the first signal input terminal and the second signal input terminal.

[0006] According to the above, the signal receiver of the present invention determines whether to pull down a first control voltage on the common control terminal to the reference voltage according to an enabled state or a power-off state of the signal receiver, thereby preventing unnecessary leakage current from occurring. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0008] Figure 1 schematic diagram of a signal receiver according to an embodiment of the present application;

[0009] Figure 2 schematic diagram of a signal receiver according to an embodiment of the present application;

[0010] Figure 3 schematic diagram of a signal transceiver according to an embodiment of the present application;

[0011] Figure 4 schematic diagram of a signal transceiver according to an embodiment of the present application;

[0012] BRIEF DESCRIPTION OF DRAWINGS

[0013] 100, 200, 302: signal receiver;

[0014] 110, 210, 310: terminal switch pair;

[0015] 120, 220, 320, 400: pull-down circuit;

[0016] 301: signal transmitter;

[0017] VDD, VDD1, VDD2: operating power supply;

[0018] VSS: reference voltage;

[0019] VA: first control voltage;

[0020] VB: second control voltage;

[0021] Q1: first transistor;

[0022] Q2: second transistor;

[0023] R1, R2, R3, R4, Rc, Rt1, Rt2: resistance;

[0024] IN1: first signal input terminal;

[0025] IN2: second signal input terminal;

[0026] SW: switch;

[0027] LG: logic circuit;

[0028] PDB: power supply on-off state signal. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0030] Reference will now be made in detail to exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts. Figure 1 , Figure 1 A schematic diagram of a signal receiver according to an embodiment of the present application is shown. The signal receiver 100 includes a terminal switch pair 110, a resistor R1, a resistor R2, and a pull-down circuit 120. The terminal switch pair 110 is coupled to an operating power source VDD, and the terminal switch pair has a common control terminal (a terminal that provides a first control voltage VA). The resistor R1 is coupled between a first signal input terminal IN1 and the common control terminal. The resistor R2 is coupled between a second signal input terminal IN2 and the common control terminal. The pull-down circuit 120 is coupled between the common control terminal and a reference voltage terminal (a terminal that provides a reference voltage VSS). Moreover, the pull-down circuit 120 determines whether to pull down the first control voltage VA on the common control terminal to the reference voltage VSS according to an enabled state or a disabled state of the signal receiver 100. For example, the reference voltage VSS can be a ground voltage, but is not limited thereto.

[0031] In the present embodiment, the terminal switch pair 110 includes a first transistor Q1 and a second transistor Q2, but is not limited thereto. The first transistor Q1 can have a first end receiving the operating power source VDD. A control terminal of the first transistor can be coupled to the common control terminal, and a second end of the first transistor Q1 can be coupled to the resistor R1. The second transistor Q2 can have a first end receiving the operating power source VDD. A control terminal of the second transistor Q2 can be coupled to the common control terminal, and a second end of the second transistor Q2 can be coupled to the resistor R2. For example, the first transistor Q1 or the second transistor Q2 can be a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), but is not limited thereto. In the present embodiment, the signal receiver 100 can be coupled to a signal transmitter (not shown) through the first signal input terminal IN1 and the second signal input terminal IN2.

[0032] It is noted that in the action details, assuming that the signal transmitter is in the enabled state, the signal receiver 100 is switched from the enabled state to the power-off state, the pull-down circuit 120 can be closed due to the power-off state of the signal receiver 100. At this time, the first control voltage VA is dominated by the voltage on the first signal input end IN1 and the second signal input end IN2. Based on the enabled state of the signal transmitter, one of the first signal input end IN1 and the second signal input end IN2 can have a relatively high level and can be provided to the common control end through the resistor R1 or the resistor R2 to pull up the first control voltage VA. Taking the first transistor Q1 and the second transistor Q2 as P-type metal oxide semiconductor field effect transistors as an example, the pulled-up first control voltage VA can make the first transistor Q1 and the second transistor Q2 be cut off. Therefore, the terminal switch pair 110 can be turned off according to the first control voltage VA on the common control end. From the above description, it can be seen that although the signal transmitter is in the enabled state, the signal receiver 100 will not generate a leakage path to cause a leakage current phenomenon, thereby avoiding unnecessary power consumption and damage to circuit components.

[0033] It is noted that when the signal receiver 100 is in the enabled state, the pull-down circuit 120 is enabled and can pull down the first control voltage VA on the common control end to the reference voltage VSS. Based on the first control voltage VA equal to the reference voltage VSS, the first transistor Q1 and the second transistor Q2 can be turned on. That is, the terminal switch pair 110 can be turned on according to the first control voltage VA on the common control end. Therefore, under the condition that the signal transmitter is in the enabled state, the signal receiver 100 can normally receive the signal transmitted by the signal transmitter through the first signal input end IN1 and the second signal input end IN2.

[0034] The following refers to Figure 2 , Figure 2 An embodiment of a signal receiver according to an embodiment of the present application is shown in a schematic diagram. The signal receiver 200 can include a terminal switch pair 210, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a pull-down circuit 220.

[0035] In this embodiment, the resistor R3 is coupled between the path in which the first transistor Q1 is coupled to the resistor R1. The resistor R4 is coupled between the path in which the second transistor Q2 is coupled to the resistor R2. For example, the resistor R3 and the resistor R4 can be 50 ohms to achieve the effect of impedance matching to avoid signal reflection, but are not limited thereto.

[0036] In the circuit design, the pull-down circuit 220 can include a switch SW and a logic circuit LG. The switch SW can be coupled between the common control terminal and the reference voltage terminal, and the switch SW is controlled by the second control voltage VB. For example, the switch SW can be an N-type metal oxide semiconductor field effect transistor, but is not limited thereto. Also, the logic circuit LG can be an AND gate, and the logic operation performed by the logic circuit LG is an AND logic operation, but is not limited thereto. In this way, the logic circuit LG receives the power on / off state signal PDB and the operating power VDD. The logic circuit LG performs a logic operation on the power on / off state signal PDB and the operating power VDD to generate the second control voltage VB.

[0037] Specifically, when the signal receiver 200 is in the power-off state, the power on / off state signal PDB and the operating power VDD are both low. At this time, the logic circuit LG can make the second control voltage VB low, and the switch SW is turned off by the second control voltage VB being low. That is, the pull-down circuit 120 is turned off because of the power-off state of the signal receiver 200. Also, the first signal input terminal IN1 and the second signal input terminal IN2 can be provided to the common control terminal through the resistor R1 or the resistor R2, respectively, to generate the first control voltage VA. It is worth noting that, since the signal transmitter is in the enabled state, the first signal input terminal IN1 and the second signal input terminal IN2 are high, so that the first control voltage VA can immediately obtain a high level. Then, the first transistor Q1 and the second transistor Q2 are turned off according to the first control voltage VA on the common control terminal, and the terminal switch pair 210 can be turned off. Therefore, although the signal transmitter is in the enabled state, no leakage path is generated to cause a leakage current phenomenon, thereby avoiding unnecessary power consumption and damage to circuit components.

[0038] In addition, when the signal receiver 200 is in the enabled state, the power on / off state signal PDB and the operating power VDD are both high. At this time, the logic circuit LG can make the second control voltage VB high, and the switch SW is turned on by the second control voltage VB being high. That is, the pull-down circuit 220 is enabled because of the enabled state of the signal receiver 200. Also, the pull-down circuit 220 can pull down the first control voltage VA on the common control terminal to the reference voltage VSS. Taking the first transistor Q1 and the second transistor Q2 as P-type metal oxide semiconductor field effect transistors as an example, the pulled-down first control voltage VA can make the first transistor Q1 and the second transistor Q2 turned on. Therefore, the terminal switch pair 210 can be turned on according to the first control voltage VA on the common control terminal. As can be seen from the above description, when the signal transmitter 200 is in the enabled state, the signal receiver 200 can normally receive the signal of the signal transmitter through the first signal input terminal IN1 and the second signal input terminal IN2.

[0039] Furthermore, the pull-down circuit 220 may further include a resistor Rc. The resistor Rc is coupled between the control terminal of the switch SW (the terminal providing the second control voltage VB) and the reference voltage terminal (the terminal providing the reference voltage VSS). The resistor Rc is used to prevent the control terminal of the switch SW from floating.

[0040] In this embodiment, to avoid affecting the output of the signal transmitter in normal mode (when both the signal receiver 200 and the signal transmitter are enabled), the resistance values ​​of resistors R1 and R2 can be relatively larger than the resistance values ​​of resistors R3 and R4. Taking a resistance value of 50 ohms for both resistors R3 and R4 as an example, the resistance values ​​of resistors R1 and R2 can be, for example, 120 kiloohms.

[0041] Please refer to the following: Figure 3 , Figure 3 This diagram illustrates a signal transceiver apparatus according to an embodiment of the present invention. The signal transceiver apparatus 300 may include a signal transmitter 301 and a signal receiver 302. For a description of the signal receiver 302, please refer to... Figure 1 as well as Figure 2 The explanation will not be elaborated upon here. Figure 3 and Figure 2 The difference lies in that the signal receiver 302 can be coupled to the signal transmitter 401 via either the first signal input terminal IN1 or the second signal input terminal IN2. It is worth noting that, for ease of explanation, the signal transmitter 401 is simplified to resistors Rt1 and Rt2. For example, in this embodiment, the first signal input terminal IN1 or the second signal input terminal IN2 can be coupled to the operating power supply VDD1 via resistors Rt1 and Rt2, respectively. Furthermore, in this embodiment, the terminal switch pair 410 of the signal receiver 402 can be coupled to the operating power supply VDD2, and the logic circuit LG can receive the power on / off status signal PDB and the operating power supply VDD2 to perform logical operations to generate a second control voltage VB.

[0042] In the present embodiment, in terms of action details, it is assumed that when the signal transmitter 401 is in the enabled state, the signal receiver 402 is switched from the enabled state to the power-off state, the pull-down circuit 420 can be turned off due to the power-off state of the signal receiver 402. At this time, the first control voltage VA is dominated by the voltage on the first signal input end IN1 and the second signal input end IN2. Based on the signal transmitter being in the enabled state, one of the first signal input end IN1 and the second signal input end IN2 can have a relatively high level and can be provided to the common control end through the resistor R1 or the resistor R2 to pull up the first control voltage VA. Taking the first transistor Q1 and the second transistor Q2 as P-type metal oxide semiconductor field effect transistors as an example, the pulled-up first control voltage VA can make the first transistor Q1 and the second transistor Q2 be cut off. Therefore, the terminal switch pair 410 can be turned off according to the first control voltage VA on the common control end. As can be seen from the above description, although the signal transmitter 401 is in the enabled state, no leakage path is generated to cause a leakage current phenomenon, thereby avoiding unnecessary power consumption and damage to circuit components.

[0043] The following refers to Figure 1 and Figure 4 , Figure 4 shows an embodiment of a pull-down circuit of an embodiment of the present application. The pull-down circuit 400 can include a switch SW and a logic circuit LG. The switch SW can be coupled between the common control end and the reference voltage end, and the switch SW is controlled by the second control voltage VB. In the present embodiment, the switch SW can be a P-type metal oxide semiconductor field effect transistor, but is not limited thereto. Moreover, the logic circuit LG can be a NAND gate, and the logic operation is a NAND logic operation, but is not limited thereto. In this way, the logic circuit LG receives the power-on / off state signal PDB and the operating power VDD. The logic circuit LG performs logic operation on the power-on / off state signal PDB and the operating power VDD to generate the second control voltage VB.

[0044] Specifically, when the signal receiver 100 is in the power-off state, the power-on / off state signal PDB and the operating power VDD are both low. At this time, the logic circuit LG can make the second control voltage VB be high, and the switch SW is turned off by the high second control voltage VB. Moreover, the first signal input end IN1 and the second signal input end IN2 can be provided to the common control end through the resistor R1 or the resistor R2 to generate the first control voltage VA. Then, the first transistor Q1 and the second transistor Q2 are cut off according to the first control voltage VA on the common control end, and the terminal switch pair 110 can be turned off. Therefore, although the signal transmitter is in the enabled state, no leakage path is generated to cause a leakage current phenomenon, thereby avoiding unnecessary power consumption and damage to circuit components.

[0045] In addition, when the signal receiver 100 is in the enabled state, the power on / off state signal PDB and the operating power VDD are both high. At this time, the logic circuit LG can make the second control voltage VB low, and the switch SW is turned on by the low second control voltage VB. That is, the pull-down circuit 400 is enabled due to the enabled state of the signal receiver 100. Moreover, the pull-down circuit 400 can pull down the first control voltage VA on the common control terminal to the reference voltage VSS. Taking the first transistor Ql and the second transistor Q2 as P-type metal oxide semiconductor field effect transistors as an example, the pulled-down first control voltage VA can turn on the first transistor Ql and the second transistor Q2. Therefore, the terminal switch pair 110 can be turned on according to the first control voltage VA on the common control terminal. As can be seen from the above description, when the signal transmitter 100 is in the enabled state, the signal receiver 100 can normally receive the signal of the signal transmitter through the first signal input terminal INl and the second signal input terminal IN2.

[0046] Furthermore, the pull-down circuit 400 can further include a resistor Rc. The resistor Rc is coupled between the control terminal of the switch SW (the terminal point providing the second control voltage VB) and the operating power terminal (the terminal point providing the operating power VDD) VDD. The resistor Rc can be used to avoid floating of the control terminal of the switch SW.

[0047] According to the above description, the signal receiver and the signal transceiver device of the present application can determine whether to pull down the first control voltage on the common control terminal to the reference voltage according to the enabled state or the power-off state of the signal receiver when the signal transmitter is in the enabled state. In this way, when the signal transmitter is in the enabled state, the signal receiver will not generate a leakage path to cause a leakage current phenomenon, thereby avoiding unnecessary power consumption and damage to circuit components.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacements to some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal receiver, comprising: a terminal switch pair receiving an operating power supply, the terminal switch pair having a common control terminal; a first resistor coupled between a first signal input terminal and the common control terminal; a second resistor coupled between a second signal input terminal and the common control terminal; and a pull-down circuit coupled between the common control terminal and a reference voltage terminal, determining whether to pull down a first control voltage on the common control terminal to the reference voltage according to an enabled state or a power-off state of the signal receiver, wherein when the signal receiver is in the power-off state, a voltage on the first signal input terminal or the second signal input terminal is provided to the common control terminal through the first resistor or the second resistor, and the terminal switch pair is turned off according to the first control voltage on the common control terminal.

2. The signal receiver of claim 1, wherein when the signal receiver is in the enabled state, the pull-down circuit pulls down the first control voltage on the common control terminal to the reference voltage.

3. The signal receiver of claim 1, wherein the terminal switch pair comprises: a first transistor having a first terminal receiving the operating power supply, a control terminal of the first transistor coupled to the common control terminal, and a second terminal of the first transistor coupled to the first resistor; and a second transistor having a first terminal receiving the operating power supply, a control terminal of the second transistor coupled to the common control terminal, and a second terminal of the second transistor coupled to the second resistor.

4. The signal receiver of claim 3, further comprising: a third resistor coupled between a path of the first transistor coupled to the first resistor; and a fourth resistor coupled between a path of the second transistor coupled to the second resistor.

5. The signal receiver of claim 1, wherein the pull-down circuit comprises: a switch coupled between the common control terminal and the reference voltage terminal, controlled by a second control voltage; and a logic circuit receiving a power-on / off state signal and the operating power supply, performing a logic operation on the power-on / off state signal and the operating power supply to generate the second control voltage.

6. The signal receiver of claim 5, wherein the pull-down circuit further comprises: a third resistor coupled between a control terminal of the switch and the reference voltage terminal.

7. The signal receiver of claim 5, wherein the logic operation is an AND logic operation.

8. The signal receiver of claim 1, wherein the reference voltage is a ground voltage.

9. A signal transceiver apparatus, comprising: a signal transmitter; and the signal receiver of claim 1, wherein the signal receiver is coupled to the signal transmitter through the first signal input terminal and the second signal input terminal. ​ ​ ​ ​ ​

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