Multiple device semiconductor chip with electrical access to devices on either side

Abstract

A semiconductor chip comprising: a semiconductor body having a main surface and a back surface opposite the main surface; a first bonding pad disposed on the main surface; a second bonding pad disposed on the back surface; a first switching device monolithically integrated in the semiconductor body and having a first input-output terminal electrically connected to the first bonding pad; and a second switching device monolithically integrated in the semiconductor body and having a first input-output terminal electrically connected to the second bonding pad.

Description

BACKGROUND

[0001] Bidirectional switches offer a number of advantageous electrical characteristics that make them useful in a wide array of applications. Of particular interest are bidirectional switches implemented in a single semiconductor device (package). However, current bidirectional switches implemented in that manner can not exhibit sufficient power density. Further, it can be desirable to reduce the package size and / or the effort to produce such bidirectional switches. SUMMARY

[0002] A semiconductor chip is disclosed. In embodiments, the semiconductor chip comprises: a semiconductor body comprising a main surface and a back surface opposite the main surface; a first bond pad disposed on the main surface; a second bond pad disposed on the back surface; a first switching device monolithically integrated in the semiconductor body and comprising a first input-output terminal electrically connected to the first bond pad; and a second switching device monolithically integrated in the semiconductor body and comprising a first input-output terminal electrically connected to the second bond pad.

[0003] Independently or in combination, the first and second switching devices form a bidirectional switch circuit connected in series between the first and second bond pads.

[0004] Independently or in combination, the first and second switching devices further each comprise a second input-output terminal, and the second input-output terminals of the first and second switching devices are electrically connected to each other by an electrical connection inside the semiconductor body.

[0005] Independently or in combination, the semiconductor chip further comprises a third bond pad disposed on the main surface and a fourth bond pad disposed on the back surface, the first switching device further comprises a control terminal electrically connected to the third bond pad, and the second switching device further comprises a control terminal electrically connected to the fourth bond pad.

[0006] Independently or in combination, the semiconductor chip further comprises a fifth bond pad disposed on a side surface of the semiconductor body extending between the main surface and the back surface, and the second input-output terminals of the first and second switching devices are electrically connected to the fifth bond pad.

[0007] Independently or in combination, the first and second switching devices are each configured as a power transistor.

[0008] Independently or in combination, the first and second switching devices are each configured as a silicon carbide-based MOSFET device or a silicon carbide-based IGBT.

[0009] Independently or in combination, a source region of the first switching device abuts a silicon-terminated surface of the semiconductor body and a source region of the second switching device abuts a carbon-terminated surface of the semiconductor body.

[0010] Independently or in combination, the source region of the first switching device abuts the silicon termination surface of the semiconductor body and the source region of the second switching device abuts the silicon termination surface of the semiconductor body.

[0011] Independently or in combination, the first input-output terminal of the first and second switching devices is a source terminal and the second input-output terminal of the first and second switching devices is a drain terminal.

[0012] A semiconductor package is disclosed. In embodiments, the semiconductor package comprises: a semiconductor body comprising a main surface and a back surface opposite the main surface; first and second switching devices each monolithically integrated in the semiconductor body; an electrically insulating encapsulation encapsulating the semiconductor chip; a first package contact electrically connected to the first switching device via a first bonding pad disposed on the main surface; and a second package contact electrically connected to the second switching device via a second bonding pad disposed on the back surface.

[0013] Independently or in combination, the first and second switching devices each comprise a first input-output terminal and a second input-output terminal, the first input-output terminal of the first switching device is electrically connected to the first bonding pad, the first input-output terminal of the second switching device is electrically connected to the second bonding pad, and the second input-output terminals of the first and second switching devices are electrically connected to each other via electrical connections inside the semiconductor body.

[0014] Independently or in combination, the first and second switching devices form a bidirectional switching circuit connected in series between the first and second bonding pads.

[0015] Independently or in combination, the encapsulation is a dielectric substrate comprising a first side and a second side opposite the first side, the semiconductor die is embedded within the dielectric substrate such that the main surface of the semiconductor body faces the first side of the dielectric substrate and such that the back surface of the semiconductor body faces the second side of the dielectric substrate, the first package contact comprises a structured portion of a first metallization layer disposed on the first side of the dielectric substrate, and the second package contact comprises a structured portion of a second metallization layer disposed on the second side of the dielectric substrate.

[0016] Independently or in combination, the dielectric substrate is a laminate substrate comprising a plurality of electrically insulating layers stacked on top of each other.

[0017] Independently or in combination, the first and second switching devices each include a control terminal, the control terminal of the first switching device is electrically connected to a third bonding pad provided on the main surface, the control terminal of the second switching device is electrically connected to a fourth bonding pad provided on the rear surface, and the semiconductor package also includes a third package contact portion, which is electrically connected to one or both of the third and fourth bonding pads.

[0018] Either alone or in combination, the semiconductor package further comprises a conductive leadframe, the leadframe comprising a die pad and a plurality of leads, and wherein the first, second, and third package contacts are provided by the leads.

[0019] Independently or in combination, the semiconductor chip is mounted on the die pad, the rear surface of the semiconductor body faces the die pad, and a portion of the rear surface of the semiconductor body including the fourth bonding pad laterally overhangs beyond the die pad, and the fourth bonding pad is electrically connected to one of the leads.

[0020] Independently or in combination, the second input-output terminals of the first and second switching devices are electrically inaccessible from outside the semiconductor package.

[0021] Independently or in combination, the semiconductor package further includes a fifth package contact electrically connected to the second input-output terminals of the first and second switching devices through a fifth bonding pad provided on a side surface of the semiconductor body extending between the main surface and the rear surface.

[0022] Independently or in combination, the first and second switching devices are each configured as a power transistor.

[0023] Independently or in combination, the first and second switching devices are each configured as a silicon carbide based MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals denote corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and described in detail in the subsequent description.

[0025] Figure 1A and 1B FIG. 4 shows a circuit diagram of a bidirectional switch according to an embodiment. Figure 1A shows a circuit diagram of a bidirectional switch with a common drain configuration, and Figure 1B A circuit schematic of a bidirectional switch with a common-source configuration is shown.

[0026] Figure 2 A cross-sectional view of a semiconductor chip including a plurality of switching devices monolithically integrated therein is shown in accordance with an embodiment.

[0027] Figure 3A 、 3B Fig. 3C and 3D show plan views of a main surface of a semiconductor chip according to an embodiment, the semiconductor chip comprising a plurality of switching devices monolithically integrated therein. Figure 3A Fig. 4 shows a plan view of a main surface of a semiconductor chip according to a first option, Figure 3B Fig. 5 shows a plan view of a back surface of a semiconductor chip according to the first option, Figure 3C Fig. 6 shows a plan view of a main surface of a semiconductor chip according to a second option, and Figure 3D Fig. 7 shows a plan view of a back surface of a semiconductor chip according to the second option.

[0028] Figure 4 Fig. 8 shows a cross-sectional view of an embedded semiconductor package with a semiconductor chip according to an embodiment, the semiconductor chip comprising a plurality of switching devices monolithically integrated therein.

[0029] Figure 5 Fig. 9 shows a process flow of a method of forming an embedded semiconductor package according to an embodiment.

[0030] Figure 6A 、 6B Figs. 6C, 6D, 6E, 6F and 6G show certain steps for producing a molded semiconductor package with a semiconductor chip comprising a plurality of switching devices monolithically integrated therein according to an embodiment. Figure 6A Fig. 6A shows providing a leadframe, Figure 6B Fig. 6B shows mounting a semiconductor die on the leadframe, Figure 6C Fig. 6C shows forming electrical interconnections between the semiconductor die and the package leads according to a first option, Figure 6D Fig. 6D shows forming electrical interconnections between the semiconductor die and the package leads according to a second option, Figure 6E and 6F Fig. 6E shows forming wire bond connections between bond pads of the semiconductor die and the package leads in two different isometric views, and Figure 6G Fig. 6F shows forming a molded encapsulation on the leadframe. DETAILED DESCRIPTION

[0031] Embodiments of a semiconductor chip are disclosed that include two switching devices monolithically integrated therein. The semiconductor chip is configured such that the two switching devices are electrically accessible on opposite facing sides of the semiconductor chip. To this end, the semiconductor chip includes first and second bond pads disposed on a front and back surface of the semiconductor chip, respectively. The first and second bond pads are connected to the first and second switching devices, respectively. In one particular embodiment, the first and second switching devices form a bidirectional switch circuit connected in series between the first and second bond pads. Compared to a multi-chip equivalent circuit, a multi-device semiconductor chip according to any of the embodiments described herein provides advantages including reduced material consumption, reduced and simplified processing steps, and improved heat dissipation. This approach requires relatively less resources and is therefore very environmentally friendly.

[0032] Figure 1A and 1B A bidirectional switch circuit 100 according to two different embodiments is shown. The bidirectional switch circuit 100 includes a first bidirectional terminal 102 and a second bidirectional terminal 104. In an off state of the bidirectional switch circuit 100, current flow between the first and second bidirectional terminals 102, 104 is inhibited. In an on state of the bidirectional switch circuit 100, current flow between the first and second bidirectional terminals 102, 104 in either direction, i.e. from the first bidirectional terminal 102 to the second bidirectional terminal 104 or from the second bidirectional terminal 104 to the first bidirectional terminal 102, is allowed.

[0033] The bidirectional switch circuit 100 includes first and second switching devices 106, 108 connected in series between the first and second bidirectional terminals 102, 104. The first and second switching devices 106, 108 each include a first input-output terminal 110, a second input-output terminal 112, and a control terminal 114. The first input-output terminal 110 of the first switching device 106 is electrically connected to the first bidirectional terminal 102, and the first input-output terminal 110 of the second switching device 108 is electrically connected to the second bidirectional terminal 104. The second input-output terminal 112 of the first switching device 106 is electrically connected to the second input-output terminal 112 of the second switching device 108 at a central node of the bidirectional switch circuit 100. The control terminals 114 of the first and second switching devices 106, 108 are each connected to a control terminal 116 of the bidirectional switch circuit 100.

[0034] In Figure 1AIn an embodiment, the first and second switching devices 106 and 108 are implemented as MOSFET transistors, wherein the first input-output terminals 110 of the first and second switching devices 106 and 108 each correspond to a source terminal, the second input-output terminals 112 of the first and second switching devices 106 and 108 each correspond to a drain terminal, and the control terminals 114 of the first and second switching devices 106 and 108 each correspond to a gate terminal. The bidirectional switch circuit 100 operates as follows. A positive bias can be applied between the first and second bidirectional terminals 102 and 104, for example, 100V or higher can be applied to the first bidirectional terminal 102 and 0V can be applied to the second bidirectional terminal 104. In the off-state of the bidirectional switch circuit 100, both the first and second switching devices 106 and 108 are in the off-state and no current flows between the first and second bidirectional terminals 102 and 104. In the on-state of the bidirectional switch circuit 100, the control terminal 116 of the bidirectional switch circuit 100 is biased to generate a positive gate-source voltage in the second switching device 108 that is higher than its threshold voltage. For example, if the second bidirectional terminal 104 is biased to 0V, the control terminal 116 of the bidirectional switch circuit 100 may be biased to 5V, so that V GS =5V. In this state, the second switching device 108 is turned on. In addition, current is allowed to flow through the intrinsic body diode 118 of the first switching device 106. Thus, a conductive connection is completed between the first and second bidirectional terminals 102, 104. Alternatively, a negative bias can be applied between the first and second bidirectional terminals 102, 104, for example, 100V or higher can be applied to the second bidirectional terminal 104, while 0V is applied to the first bidirectional terminal 102. In that case, applying the same bias to the control terminal 116 of the bidirectional switch circuit 100 generates a positive gate-source voltage V in the first switching device 108 that is higher than its threshold voltage. GS As a result, the first switching device 108 turns on and current is allowed to flow through the intrinsic body diode 118 of the second switching device 108 .

[0035] exist Figure 1B In the embodiment of FIG. 1 , the first and second switching devices 106 and 108 are also implemented as MOSFET transistors, but the polarities of these devices are opposite. Therefore, the first input-output terminals 110 of the first and second switching devices 106 and 108 each correspond to a drain terminal, and the second input-output terminals 112 of the first and second switching devices 106 and 108 each correspond to a source terminal. Figure 1B The working principle of the bidirectional switch circuit 100 is Figure 1AThe operation of the bidirectional switch circuit 100 is the same, except that the conduction state of each device is reversed. Thus, if a positive voltage is applied between the first and second bidirectional terminals 102, 104, the bidirectional switch circuit 100 enters a conducting state by turning on the first switch device 106 and causing current to flow through the intrinsic body diode 118 of the second switch device 108.

[0036] Although Figure 1A and 1B The first and second switch devices 106, 108 are shown implemented as N-type enhancement mode MOSFET transistors, but this represents only one potential type of switch device that can be used to form the bidirectional switch circuit 100. More generally, the bidirectional switch devices can comprise any type of active switch device configured to control the flow of current between two terminals in one or both directions. Examples of such switch devices include any type of MOSFET, e.g., n-channel, p-channel, enhancement mode, depletion mode, etc. In another example, the first and second switch devices 106, 108 can be implemented with insulated gate bipolar transistors (IGBTs), where the first and second input-output terminals 110, 112 correspond to the emitter and collector terminals, respectively (or vice versa). In that case, the first and second switch devices 106, 108 can be configured as so-called reverse conducting IGBTs, which are IGBTs having an integrated body diode in parallel with their emitter and collector terminals. The integrated body diode provides a reverse conducting path, thereby enabling bidirectional current flow between the first and second bidirectional terminals 102, 104 in a similar manner as described above.

[0037] The bidirectional switch circuit 100 can optionally include a fourth terminal 120. The fourth terminal 120 is connected to a center node of the bidirectional switch circuit 100 that connects the second input-output terminals 112 of the first and second switch devices 106, 108 together. The fourth terminal 120 can provide a sense terminal, e.g., to determine the voltage and / or current flowing through the first and second switch devices 106, 108 during operation. This information can be used to detect and / or prevent the first and second switch devices 106, 108 from operating under potentially damaging conditions, such as breakdown conditions.

[0038] The bidirectional switch circuit 100 can use different or additional Figure 1A and 1BThe combination of circuit elements shown can be implemented in a combination of circuit elements. For example, the bidirectional switch circuit 100 includes multiple sets of first and second switching devices 106, 108, with each set connected in parallel between the first and second bidirectional terminals 102, 104. Additionally or alternatively, the bidirectional switch circuit 100 can include independent diodes connected in parallel with the first and second input-output terminals 110, 112 and having the same polarity as the intrinsic body diode 118 shown in the figure. In the case of MOSFET configurations, these independent diodes can provide enhanced current carrying capability compared to the intrinsic body diode 118 of the devices. In the case of IGBTs, these independent diodes can provide reverse conduction capability.

[0039] With reference to Figure 2 The semiconductor chip 200 includes a semiconductor body 202, which in turn includes a main surface 204 and a back surface 206 opposite the main surface 204. The semiconductor body 202 can include any of a variety of semiconductor materials, including IV-type semiconductors such as silicon, silicon-germanium, silicon carbide, etc., and III-V-type semiconductors such as gallium nitride, gallium arsenide, etc. Moreover, the semiconductor body 202 can include any of these semiconductor materials throughout the semiconductor body 202 or can include any combination thereof.

[0040] The first and second switching devices 106, 108 are each monolithically integrated in the semiconductor body 202. This means that the active device regions (e.g., source, drain, body, etc.) of the first and second switching devices 106, 108 are formed in the semiconductor material of the semiconductor body 202.

[0041] The semiconductor chip 200 has a multi-sided bonding pad configuration such that at least one terminal of the first switching device 106 is electrically accessible via the main surface 204 and such that at least one terminal of the second switching device 108 is electrically accessible via the back surface 206. To this end, the semiconductor chip 200 includes first and third bonding pads 208, 212 disposed on the main surface 204 and second and fourth bonding pads 210, 214 disposed on the back surface 206. These bonding pads can be, for example, metallized structured regions of copper, aluminum, alloys thereof, etc., which provide the outermost contact surfaces of the semiconductor chip 200.

[0042] According to an embodiment, the first and second switching devices 106, 108 are arranged in the semiconductor body 202 and form a bidirectional switch circuit 100 connected in series between the first and second bond pads 208, 210. In this embodiment, the first input-output terminal 110 of the first switching device 106 is electrically connected to the first bond pad 208, and the first input-output terminal 110 of the second switching device 108 is electrically connected to the second bond pad 210. The control terminal 114 of the first switching device 106 can be electrically connected to the third bond pad 212, and the control terminal 114 of the second switching device 108 can be electrically connected to the fourth bond pad 214. In a different embodiment (not shown), the control terminals 114 of the first and second switching devices 106, 108 can be connected to bond pads disposed on the same side of the semiconductor body 202. In yet another embodiment (not shown), the control terminals 114 of the first and second switching devices 106, 108 can be connected to a single bond pad disposed on either side of the semiconductor body 202, e.g., in cases where independent control of the switching devices is not required.

[0043] The second input-output terminals 112 of the first and second switching devices 106, 108 can be electrically connected to each other by an electrical connection inside the semiconductor body 202. This means that the second input-output terminals 112 of the first and second switching devices 106, 108 are connected to each other by a semiconductor material that is an integral part of the semiconductor body 202 or by a conductive material formed within the semiconductor body 202. For example, such an electrical connection can be provided by a metal via structure or a doped polysilicon conductive structure disposed within a trench of the semiconductor body 202. Alternatively, such an electrical connection can be provided by forming the first and second switching devices 106, 108 to share a common doped active region (e.g., a drain region) that forms the second input-output terminal 112 of each device. In either example, this configuration frees up area on the front and back surfaces 204, 206 by reducing the number of bond pads. This allows the first and second bond pads 208, 210 to be enlarged, thereby reducing the contact resistance of these connections.

[0044] Optionally, the semiconductor chip 200 can include a fifth bond pad 216 disposed on a side surface of the semiconductor chip 200 extending between the front and back surfaces 204, 206. The fifth bond pad 216 can be configured as a terminal connection to the second input-output terminals 112 of the first and second switching devices 106, 108. Thus, the fifth bond pad 216 can provide the sense terminal 120 of the bidirectional switching circuit 100. The fifth bond pad 216 can be electrically connected to the second input-output terminals 112 of the first and second switching devices 106, 108, for example, by a metal or polysilicon line or by a direct connection to the highly doped semiconductor material. In another embodiment, the second input-output terminals 112 of the first and second switching devices 106, 108 are electrically not accessible such that there is no bond pad connection from the outer surface of the semiconductor chip 200 to these terminals.

[0045] In embodiments where the first and second switching devices 106, 108 are SiC-based switches, the source region of the first switching device 106 abuts the silicon termination surface of the chip 200, and the source region of the second switching device 108 abuts the carbon termination surface of the chip. Alternatively, depending on the manufacturing process, the source region of the first switching device 106 can abut the silicon termination surface of the chip 200, and the source region of the second switching device 108 can also abut the silicon termination surface of the chip 200. The silicon termination surface refers to a contact surface of the semiconductor body 202 that is predominantly silicon. Likewise, the carbon termination surface refers to a contact surface of the semiconductor body 202 that is predominantly carbon.

[0046] In embodiments, the first and second switching devices 106, 108 are configured as vertical devices. This means that the first and second switching devices 106, 108 are configured to conduct electrically in a direction orthogonal to the front surface 204 of the semiconductor body 202. In one particular example of a vertical device configuration, the doped active region (e.g., source region) corresponding to the first input-output terminals 110 of the first switching device 106 extends to the front surface 204, and the doped active region (e.g., source region) corresponding to the first input-output terminals 110 of the second switching device 108 extends to the back surface 206. In that case, the first and second bond pads 208, 210 can be in direct low-ohmic contact with the doped active regions of each device.

[0047] In embodiments, the first and second switching devices 106, 108 are configured as lateral devices. This means that the first and second switching devices 106, 108 are configured to conduct electrically in a direction parallel to the main surface 204 of the semiconductor body 202. In one particular example of a lateral device configuration, the doped active regions of the first switching device 106 (e.g., source, body, and drain in the case of a MOSFET) extend to the main surface 204, and each of the doped active regions of the second switching device 108 extend to the back surface 206 of the semiconductor body 202. In that case, the first and second bond pads 208, 210 can be in direct low-ohmic contact with the first input-output terminal 110 of the first and second switching devices 106, 108, respectively.

[0048] In embodiments, the first and second switching devices 106, 108 are each configured as a power transistor. A power transistor is a transistor with a rated control voltage of 100 V (volts) or more and / or a rated control current of 1 A (amperes) or more. More commonly, power transistors are configured to control voltages of about 500 V to 1700 V or even up to 3.3 kV and / or currents of about 10 A to 100 A or more. These high voltage ratings and / or current ratings are achieved by appropriate adjustment of the physical parameters of the device, such as the length and dopant concentration of the drift region, the thickness and material type of the base semiconductor material in which the active doped regions are formed, the thickness and material type of the dielectric material, etc. In one particular embodiment, the first and second switching devices 106, 108 are configured as silicon carbide-based power MOSFET devices. This means that the source, drain, and body regions of the first and second switching devices 106, 108 are formed in a silicon carbide material. Since SiC material has a higher breakdown field strength and thermal conductivity, SiC-based transistors can provide superior voltage blocking and better thermal performance compared to corresponding silicon-based transistors.

[0049] Reference is made to Figures 3A-3D depictions of two potential bond pad configurations for the semiconductor chip 200. Figure 3A The main surface 204 of the semiconductor chip 200 is depicted and Figure 3B The back surface 206 of the semiconductor chip 200 is depicted according to a first option. In this embodiment, the semiconductor chip 200 includes two of the first bond pads 208 on the main surface 204 and two of the second bond pads 210 on the back surface 206. The pair of bond pads on each surface can connect to a single device or can form independent connections to two devices in parallel to each other. Figure 3C The main surface 204 of the semiconductor chip 200 is depicted and Figure 3DThe back surface 206 of the semiconductor chip 200 according to the second option is depicted. In this embodiment, the semiconductor chip 200 includes one of the first bond pads 208 that occupies substantially most of the primary surface 204 and one of the second bond pads 210 that occupies substantially most of the back surface 206. This can be preferable to reduce, for example, the electrical resistance of the terminal connections. More generally, the geometry of the bond pads can be adjusted according to particular design requirements. Moreover, the geometry of the bond pads on each side of the semiconductor chip 200 need not be the same.

[0050] By configuring the semiconductor chip 200 to include the first and second switching devices 106, 108 monolithically integrated therein, the following advantages can be realized. The semiconductor chip 200 effectively uses semiconductor material compared to a multi-chip solution, which can be particularly beneficial in the case of expensive semiconductors such as silicon carbide. Moreover, the multi-device integration allows for sharing of at least some of the processing steps used to form each switching device. For example, an implantation post- anneal step can be used to activate dopants of the active doped regions of both the first and second switching devices 106, 108. Moreover, improvements in thermal capacity and thermal conductivity can be realized. For example, by incorporating two semiconductor devices into a high thermal conductivity material such as silicon carbide, thermal dissipation caused by interconnects (e.g., clips, solder, etc.) can be eliminated.

[0051] Figures 4-6G Embodiments of a semiconductor package 300 and a method of producing a semiconductor package 300 are disclosed. The semiconductor package 300 includes a semiconductor chip 200 as described herein. The semiconductor package 300 advantageously provides a multi-device circuit, such as the bidirectional switching circuit 100, in a single package. Thereby, carrier-level interconnects between terminals of the devices, such as conductive traces, clips, wire bonds, etc., can be eliminated from the circuit, thereby reducing parasitic effects. In addition to the depicted embodiments, the semiconductor package 300 can more generally have a wide variety of package types. Examples of these package types include through-hole packages, surface mount packages, flat packages, and embedded packages.

[0052] The semiconductor package 300 can include a first package contact 302, a second package contact 304, a third package contact 306, and a fourth package contact 308. Each of these package contacts 302, 304, 306, 308 is an externally accessible electrical contact to a respective terminal of the semiconductor chip 200. The first package contact 302 is electrically connected to the first switching device 106 through the first bond pad 208. The second package contact 304 is electrically connected to the second switching device 108 through the second bond pad 210. The third package contact 306 is electrically connected to the first switching device 106 through the third bond pad 212. The fourth package contact 308 is electrically connected to the second switching device 108 through the fourth bond pad 214. Thus, the first package contact 302 provides an externally accessible electrical contact to the first input-output terminal 110 of the first switching device 106, the second package contact 304 provides an externally accessible electrical contact to the first input-output terminal 110 of the second switching device 108, and so on. Optionally, the semiconductor package 300 can include a fifth package contact 310 electrically connected to the fifth bond pad 216, if present. This fifth package contact 310 can be disposed on any side of the semiconductor package 300.

[0053] Referring to Figure 4 , an embodiment of a semiconductor package 300 configured as a buried package is depicted. A buried package refers to a particular type of semiconductor package that does not use soldering techniques and wirebonds for package interconnections. In a buried package, the package interconnections are provided by plating techniques. In some cases, a buried package can not include a chip carrier (e.g., a leadframe) to which a semiconductor die is mounted. In the depicted embodiment, a dielectric substrate 312 serves as an encapsulant for the semiconductor package 300. The dielectric substrate 312 includes a first side 314 over the major surface 204 of the semiconductor body 202 and a second side 316 under the back surface 206 of the semiconductor body 202. The dielectric substrate 312 can include an epoxy material, a hybrid epoxy and fiberglass material (such as FR-4, FR-5, CEM-4, etc.), and a resin material (such as bismaleimide trazine (BT) resin). The dielectric substrate 312 of a buried package can be formed by lamination techniques, in which multiple layers of electrically insulating material are stacked on top of one another in sequence, examples of which will be described in greater detail below. Alternatively, the dielectric substrate 312 of a buried package can be formed by molding techniques such as compression molding.

[0054] In Figure 4In embodiments, the package contacts 302, 304, 306, and 308 are provided by structured areas of metallization provided on the first and second sides 314, 316 of the dielectric substrate 312. Specifically, the first package contact 302 includes a structured portion of a first metallization layer 318 provided on the first side 314 of the dielectric substrate 312, the second package contact 304 includes a structured portion of a second metallization layer 320 provided on the second side 316 of the dielectric substrate 312, and so on. The first and second metallization layers 318, 320 can be layers of deposited conductive metal, such as copper, aluminum, or the like. Trenches can be formed in the dielectric substrate 312 so that the structured portions of the first and second metallization layers 318, 210 can reach the bond pads of the semiconductor die 200. These trenches can be filled with conductive via structures, such as tungsten plugs. Alternatively, the package contacts 302, 304, 306, and 308 can be continuous metal structures that extend into trenches in the dielectric substrate 312 and reach the bond pads of the package.

[0055] Reference is made to Figure 5 A first process step 400 in a method of forming the embedded semiconductor package 300 includes providing a carrier structure. The carrier structure can include an electrically insulating substrate having a metal layer, such as a Cu or Al foil, provided thereon.

[0056] According to a second process step 402 of the method, the semiconductor die 200 is placed on the carrier structure with the back surface 206 of the semiconductor die 200 facing and being disposed on the metal foil. Optionally, a plurality of semiconductor dies 200 can be placed on a single carrier structure, and the subsequent process steps can be performed in parallel to form a plurality of semiconductor packages 300.

[0057] According to a third process step 404 of the method, the dielectric substrate 312 is partially formed on the carrier so that the major surface 204 of each semiconductor die 200 is covered by the dielectric material. In one example, this is accomplished by lamination techniques whereby layers of electrically insulating material are stacked on top of one another in sequence. Each constituent layer can generally include any dielectric material suitable for semiconductor encapsulation. Examples of such dielectric materials include epoxy materials, hybrid epoxy and fiberglass materials (such as FR-4, FR-5, CEM-4, etc.), and resin materials (such as bismaleimide triazine (BT) resin). According to another embodiment, the dielectric material is formed by molding techniques. According to this technique, the carrier and / or each semiconductor die is disposed within a mold cavity of a mold tool. A molding material, such as an epoxy material or a thermoset resin, is injected into the mold cavity and subsequently hardened.

[0058] According to a fourth process step 406 of the method, the dielectric material is hardened, separated from the carrier structure and inverted such that the back surface 206 of each semiconductor chip 200 faces away from the carrier structure.

[0059] According to a fifth process step 408 of the method, further dielectric material is formed such that the back surface 206 of each semiconductor chip 200 is covered by the dielectric material. This can be done using lamination techniques or molding techniques as described with reference to the third process step 404. As a result, a dielectric substrate 312 is created that covers both sides of the semiconductor chips 200.

[0060] According to a sixth process step 410 of the method, holes or trenches are formed in the dielectric substrate 312. These holes or trenches are formed to expose the bond pads of the semiconductor chips 200 as required, e.g. the first, second, third and fourth bond pads 208, 210, 212, 214. This can be done using drilling techniques such as laser drilling, for example. Alternatively, this can be done using etching techniques.

[0061] According to a seventh process step 412 of the method, first and second metallization layers 318, 320 are deposited on both sides of the dielectric substrate 312. These metallization layers 318, 320 can be formed by plating techniques, e.g. electroplating or electroless plating, in which the exposed portions of the bond pads act as seeds for the plating process. These metallization layers 318, 320 can comprise various conductive metals (e.g. Cu, Al, Ni, etc.), as well as alloys thereof. These metallization layers 318, 320 can be formed as continuous layers that cover both sides of the dielectric substrate 312 and fill each hole or trench formed in the dielectric substrate 312.

[0062] According to an eighth process step 414 of the method, the metallization layers disposed on either side of the dielectric substrate 312 can be structured to form metallized portions that are laterally isolated from one another. This can be done using masked etching techniques, for example.

[0063] Reference Figures 6A-6G, depicting selected steps for forming a semiconductor package 300 configured as a molded package. In this embodiment, the semiconductor package 300 includes a leadframe 500, which serves as a chip carrier. The leadframe 500 can include an electrically conductive metal, such as copper, aluminum, etc., and alloys thereof. The leadframe 500 includes a die pad 502 and a plurality of electrically conductive leads 504. In this embodiment, the leads 504 provide first, second, and third package contacts, which are electrically connected to the first, second, third, and fourth bond pads 208, 210, 212, 214 of the semiconductor chip 202, respectively (with the third and fourth bond pads 212, 214 connected to one of the leads 504). If desired, one of the leads 504 can provide an additional package contact, which is electrically connected to the fifth bond pad 216 (if present)

[0064] Referring to Figure 6A , a leadframe 500 is provided that includes a die pad 502 and a plurality of electrically conductive leads 504. As shown, the leadframe 500 can be part of a unit leadframe, in which the leads 504 and the die pad 502 are attached to a peripheral ring of a leadframe strip. The same basic structure is repeated in the leadframe strip so that multiple semiconductor packages 300 can be produced at one time.

[0065] Referring to Figure 6B , the semiconductor chip 200 is mounted on the die pad 502. The semiconductor chip 200 is mounted so that the second bond pad 210 faces and is electrically connected to the die pad 502. An electrically conductive adhesive, such as solder, sinter, conductive paste, etc., can be provided between the second bond pad 210 and the die pad 502 to effect such connection. One of the leads 504 can be merged with the die pad and thereby form a second package contact that is directly electrically connected to the second bond pad 210.

[0066] According to an embodiment, the semiconductor chip 200 is mounted on the die pad 502 so that a portion of the back surface 206, including the fourth bond pad 214, overhangs laterally beyond the die pad 502. That is, the semiconductor chip 200 is mounted in a partially overlapping arrangement so that a non-overlapping portion of the semiconductor chip 200, including the fourth bond pad 214, is accessible from under the semiconductor chip 200.

[0067] Referring to Figure 6C and 6D , two different techniques for electrically connecting the first bond pad 208 to one of the leads 504 are shown. In the option shown in Figure 6C , a metal interconnect stud 506 is connected to the first bond pad 208 and to a contact pad associated with one of the leads 504. An electrically conductive adhesive, such as solder, can be provided at one or both interfaces with the metal interconnect stud 506. In the option shown in Figure 6DAmong the options shown in FIG. 2, bond wires 508 are provided between the first bond pad 208 and the contact pads associated with one of the leads 504. These bond wires 508 can be attached using wire bonding techniques, for example. In either case, the connected lead 502 provides a first package contact electrically connected to the first bond pad 208. The bond wires 508 can comprise aluminum, copper, other metals, and alloys thereof.

[0068] Referring to FIG. 3, a package 100 is formed by wire bonding the first and second bond pads 208, 210 to the leads 504 of the leadframe 500. The first and second bond pads 208, 210 are electrically connected to the leads 504 by wire bonds 508. The wire bonds 508 can comprise aluminum, copper, other metals, and alloys thereof. Figure 6E and 6F The third and fourth bond pads 212, 214 are each electrically connected to one of the leads 504. A first bond wire 510 is provided between the third bond pad 212 and an upper side of a contact pad associated with one of the leads 504. A second bond wire 512 is provided between the fourth bond pad 214 and a lower side of a contact pad associated with one of the leads 504. In this case, a single lead provides a third package contact electrically connected to both the first and second bond pads 212, 214. Alternatively, if independent control of the first and second switching devices 106, 108 is desired, the first and second bond wires 510, 512 can be routed to independent leads 504.

[0069] Referring to FIG. 4, a package 100 is formed by wire bonding the first and second bond pads 208, 210 to the leads 504 of the leadframe 500. The first and second bond pads 208, 210 are electrically connected to the leads 504 by wire bonds 508. The wire bonds 508 can comprise aluminum, copper, other metals, and alloys thereof. Figure 6G After the necessary electrical interconnections are formed, an encapsulant 514 is formed over the leadframe 500. This can be accomplished using a molding process such as injection molding, compression molding, transfer molding, etc. The encapsulant 514 can comprise an electrically insulating molding compound material such as an epoxy, a thermoset plastic, etc. Subsequently, a lead trimming process can be performed to sever the dam bars between each of the leads 504 and separate the leadframe 500 from the peripheral ring of the leadframe strip.

[0070] As used herein, the terms "electrically connected," "directly electrically connected," and the like describe a permanent low impedance connection between electrically connected elements, such as direct contact between the relevant elements or a low impedance connection via a metal and / or a highly doped semiconductor.

[0071] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are to be interpreted in accordance with the change of

[0072] As used herein, the terms "have," "having," "contain," "containing," "include," "including," and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude the presence or addition of one or more other elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0073] With the above variations and applications in mind, it should be understood that the present application is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present application is limited only by the following claims, and their legal equivalents.

Claims

1. A semiconductor chip, comprising: a semiconductor body comprising a main surface and a back surface opposite to the main surface; a first bonding pad arranged on the main surface; a second bonding pad arranged on the back surface; a first switching device monolithically integrated in the semiconductor body and comprising a first input-output terminal electrically connected to the first bonding pad; and a second switching device monolithically integrated in the semiconductor body and comprising a first input-output terminal electrically connected to the second bonding pad, wherein the first switching device and the second switching device form a bidirectional switching circuit connected in series between the first bonding pad and the second bonding pad, wherein the first switching device and the second switching device are each configured as a power transistor, wherein the first switching device and the second switching device are each configured as a silicon carbide-based MOSFET device or a silicon carbide-based IGBT, and wherein a source region of the first switching device abuts a silicon termination surface of the semiconductor body, and wherein a source region of the second switching device abuts a carbon termination surface of the semiconductor body. The first switching device and the second switching device each further comprise a second input-output terminal, and wherein the second input-output terminals of the first switching device and the second switching device are electrically connected to each other by an electrical connection inside the semiconductor body.

2. The semiconductor chip of claim 1, wherein, The semiconductor chip further comprises a third bonding pad arranged on the main surface and a fourth bonding pad arranged on the back surface, wherein the first switching device further comprises a control terminal electrically connected to the third bonding pad, and wherein the second switching device further comprises a control terminal electrically connected to the fourth bonding pad.

3. The semiconductor chip of claim 1, wherein, The semiconductor chip further comprises a fifth bonding pad arranged on a side surface of the semiconductor body extending between the main surface and the back surface, and wherein the second input-output terminals of the first switching device and the second switching device are electrically connected to the fifth bonding pad.

4. The semiconductor chip of claim 2, wherein, A source region of the first switching device abuts a silicon termination surface of the semiconductor body, and wherein a source region of the second switching device abuts a silicon termination surface of the semiconductor body.

5. The semiconductor chip of claim 1, wherein, The first input-output terminals of the first switching device and the second switching device are source terminals, and wherein the second input-output terminals of the first switching device and the second switching device are drain terminals.

6. The semiconductor chip of claim 2, wherein, 7. A semiconductor package, comprising: a semiconductor chip comprising a semiconductor body comprising a main surface and a back surface opposite to the main surface; a first switching device and a second switching device each monolithically integrated in the semiconductor body; an electrically insulating encapsulation encapsulating the semiconductor chip; a first package contact electrically connected to the first switching device by a first bonding pad arranged on the main surface; and a second package contact electrically connected to the second switching device by a second bonding pad arranged on the back surface, ​ ​ wherein the first and second switching devices form a bidirectional switch circuit connected in series between the first and second bond pads, wherein the first and second switching devices are each configured as a power transistor, wherein the first and second switching devices are each configured as a silicon carbide-based MOSFET device or a silicon carbide-based IGBT, and wherein a source region of the first switching device abuts a silicon termination surface of the semiconductor body, and wherein a source region of the second switching device abuts a carbon termination surface of the semiconductor body.

8. The semiconductor package of claim 7, wherein, The first and second switching devices each comprise a first input-output terminal and a second input-output terminal, wherein the first input-output terminal of the first switching device is electrically connected to the first bond pad, wherein the first input-output terminal of the second switching device is electrically connected to the second bond pad, and wherein the second input-output terminals of the first and second switching devices are electrically connected to each other by an electrical connection inside the semiconductor body.

9. The semiconductor package of claim 8, wherein, The encapsulation is a dielectric substrate comprising a first side and a second side opposite the first side, wherein the semiconductor chip is embedded within the dielectric substrate such that the main surface of the semiconductor body faces the first side of the dielectric substrate and such that the back surface of the semiconductor body faces the second side of the dielectric substrate, wherein the first package contact comprises a structured portion of a first metallization layer disposed on the first side of the dielectric substrate, and wherein the second package contact comprises a structured portion of a second metallization layer disposed on the second side of the dielectric substrate.

10. The semiconductor package of claim 9, wherein, The dielectric substrate is a laminate substrate comprising a plurality of electrically insulating layers stacked on top of each other.

11. The semiconductor package of claim 8, wherein, The first and second switching devices each comprise a control terminal, wherein the control terminal of the first switching device is electrically connected to a third bond pad disposed on the main surface, wherein the control terminal of the second switching device is electrically connected to a fourth bond pad disposed on the back surface, and wherein the semiconductor package further comprises a third package contact electrically connected to one or both of the third and fourth bond pads.

12. The semiconductor package of claim 11, further comprising a conductive leadframe, the conductive leadframe comprising a die pad and a plurality of leads, and wherein, The first, second, and third package contacts are provided by the plurality of leads.

13. The semiconductor package of claim 12, wherein, The semiconductor chip is mounted on the die pad, the back surface of the semiconductor body faces the die pad and a portion of the back surface of the semiconductor body comprising the fourth bond pad laterally overhangs the die pad, and wherein the fourth bond pad is electrically connected to one of the plurality of leads.

14. The semiconductor package of claim 8, wherein, The second input-output terminals of the first and second switching devices are not electrically accessible from outside of the semiconductor package.

15. The semiconductor package of claim 8, wherein, The semiconductor package further includes a fifth package contact electrically connected to the second input-output terminal of the first and second switching devices through a fifth bond pad disposed on a side surface of the semiconductor body extending between the front surface and the back surface.

Images