Test device for a digital-to-analog conversion chip

Abstract

The present application relates to the technical field of circuit, and provides a testing device for digital-to-analog conversion chip, which utilizes standard test codes provided by a processing unit, carries out digital-to-analog conversion through a sampling amplification unit with a D / A chip to be tested to obtain a detection value which can represent the difference between the test voltages after conversion of any two adjacent standard test codes; and utilizes a reference amplification unit with a reference D / A chip to carry out digital-to-analog conversion on the standard test codes to obtain a reference value which can represent the difference between the reference voltages after conversion of the two adjacent standard test codes; then a comparison unit compares the detection value with the reference value to generate a detection signal, a processing unit calculates or obtains a group of static parameter vectors of the D / A chip to be tested according to the detection signal, and judges whether the digital-to-analog conversion function of the D / A chip to be tested is normal according to the comparison result between the variation of the group of static parameter vectors and a preset error range. Thus, the testing time of the digital-to-analog conversion chip can be effectively shortened.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of circuit, in particular to a testing device for digital-to-analog conversion chip. BACKGROUND

[0002] Digital-to-analog conversion chip (hereinafter referred to as D / A chip) is an integrated chip for converting digital signal into analog voltage signal. It is widely used in industrial control field, and also widely used in communication electronic field, such as voltage input of voltage-controlled crystal oscillator control voltage end, analog intermediate frequency signal conversion of digital baseband intermediate frequency signal in wireless communication base station, etc. For example, D / A chip SGM5204 / 5207 integrates 32 / 48 12-bit digital-to-analog converters (DACs). An ideal DAC should exhibit a linear relationship between its digital input and its analog output, but in actual DACs, this relationship is often nonlinear due to component mismatches, non-ideal layout, modeling limitations, and other sources of deviation from ideal or expected behavior.

[0003] Therefore, in industrial applications, it is necessary to calculate the static parameters of DAC. The existing D / A chip test can be divided into two aspects, one is the test of digital input interface, and the other is the function test of analog output interface (i.e. the test of digital-to-analog conversion function). The test method of digital input interface is relatively simple and easy to implement, and the register configuration and read-write test can be directly realized by using CPU bus interface. As for the analog output port, since the output voltage directly drives electrical equipment (such as motor and other voltage-controlled devices), these devices have no direct feedback channel connection with the D / A system, therefore, the test of digital-to-analog conversion function of analog output port cannot be directly realized by using the system itself.

[0004] The existing D / A chip adopts a multi-point sampling linear ladder histogram method or a column chart method to test the static parameters of the DAC, such as offset error, integral nonlinearity (INL), differential nonlinearity (DNL), gain error, absolute accuracy error, and aperture error. Since the analog voltage is a continuous signal and the digital code is a discrete value, for the DAC, the analog output voltage is determined based on the digital input code, thereby causing the ladder to increase from one digital code to the next digital code. The width of each ladder is a function of the resolution degree of the DAC and the component mismatch inside the DAC. The DNL error refers to the difference between the actual ladder width between the continuous digital codes and the ideal DAC ladder width. The ideal DAC ladder width can be referred to as '1 LSB', and the DNL error can be expressed in units of LSB. For example, +1 / 2 LSB DNL error means that the ladder width is 50% larger than the ideal DAC ladder width. One of the main parameter indicators of the DAC is conversion accuracy, which refers to the error between the output analog voltage value and the ideal output voltage value. The deviation should generally be less than ±1 / 2 LSB.

[0005] The linear ladder histogram or column chart method belongs to a statistical method, which has randomness and roughness, and the output voltage value from the DAC output cannot determine the input code of the input DAC. In the process of testing the DAC, only when the sampling points are sufficient or even all the input codes of the DAC are traversed, can a more accurate test result be obtained. As described above, the D / A chip SGM5204 / 5207 integrated with multiple DACs needs to traverse each input code of the DAC in the mass production test stage to obtain the voltage difference DNL of the adjacent two output codes. If the histogram test method is used, the total number of voltage values of all test points is 131072 / 196608, and the original scheme needs to scan and test the voltage values of all input codes, which will consume a long time for testing, thereby causing high test cost and long delivery cycle.

[0006] Therefore, how to design a test circuit capable of shortening the test time of the DAC becomes a technical problem to be solved at present. SUMMARY

[0007] To solve the above technical problem, the disclosure provides a test device for a digital-to-analog conversion chip, which can effectively shorten the test time of the analog output of the D / A chip.

[0008] The disclosure provides a test device for a digital-to-analog conversion chip, comprising:

[0009] a processing unit configured to provide a first standard test code and a second standard test code in a set of standard test codes;

[0010] a sampling amplification unit configured to receive the first standard test code, perform digital-to-analog conversion on the first standard test code, and output a detection value representing a difference between two test voltages converted from two adjacent first standard test codes;

[0011] a reference amplification unit configured to receive the second standard test code, perform digital-to-analog conversion on the second standard test code, and output a reference value representing a difference between two reference voltages converted from the two adjacent first standard test codes;

[0012] a comparison unit having input ends connected to the sampling amplification unit and the reference amplification unit, respectively, and configured to compare the detection value with the reference value and generate a detection signal,

[0013] wherein the processing unit is further connected to an output end of the comparison unit, and is configured to calculate or obtain a set of static parameter vectors of a digital-to-analog conversion chip under test according to the set of detection signals, and determine whether the digital-to-analog conversion function of the digital-to-analog conversion chip under test is normal according to a comparison result of a variation of the set of static parameter vectors and a preset error range.

[0014] Preferably, the sampling amplification unit comprises:

[0015] a digital-to-analog conversion chip under test configured to perform digital-to-analog conversion on the first standard test code and output a test voltage converted from the first standard test code, each test voltage corresponding to one first standard test code;

[0016] a sample-and-hold module configured to hold and output the test voltage corresponding to the current first standard test code;

[0017] a differential amplifier connected to the digital-to-analog conversion chip under test and the sample-and-hold module, respectively, and configured to obtain a difference between two test voltages converted from two adjacent first standard test codes, amplify the difference, and output the detection value.

[0018] Preferably, the sampling amplification unit further comprises:

[0019] a first switch module having a control end, a first selection end, and a second selection end, the control end being connected to an output end of the digital-to-analog conversion chip under test, the first switch module being controlled by a first control signal to select one of the first selection end and the second selection end to be connected.

[0020] Preferably, the sample-and-hold module comprises:

[0021] a first comparator, a non-inverting input of the first comparator being connected to the first selection terminal;

[0022] a second comparator, a non-inverting input of the second comparator being connected to ground through a second resistor and a first capacitor in series, and an inverting input of the second comparator being connected to an inverting input of the first comparator through a first resistor;

[0023] a second switch module, connected between an output of the first comparator and a non-inverting input of the second comparator, the second switch module being controlled by a second control signal to control the connection between the output of the first comparator and the non-inverting input of the second comparator;

[0024] a first diode and a second diode, a positive terminal of the first diode and a negative terminal of the second diode being commonly connected to an output of the first comparator, and a negative terminal of the first diode and a positive terminal of the second diode being commonly connected to an inverting input of the first comparator.

[0025] Preferably, the differential amplifier comprises:

[0026] a third comparator, a non-inverting input of the third comparator being connected to an output of the second comparator, and an output of the third comparator being connected to an output of the differential amplifier through a third resistor and a fourth resistor in series;

[0027] a fourth comparator, a non-inverting input of the fourth comparator being connected to the second selection terminal, an inverting input of the fourth comparator being connected to an inverting input of the third comparator through a ninth resistor, and an output of the fourth comparator being connected to ground through a fifth resistor and a sixth resistor in series;

[0028] a fifth comparator, a non-inverting input of the fifth comparator being connected to a connection node of the fifth resistor and the sixth resistor, an inverting input of the fifth comparator being connected to a connection node of the third resistor and the fourth resistor, and an output of the fifth comparator being an output of the differential amplifier for providing the detection value.

[0029] Preferably, the reference amplification unit comprises:

[0030] a reference digital-to-analog conversion chip, configured to perform digital-to-analog conversion processing according to the second standard test codes, and output converted reference voltages, each of the output reference voltages corresponding to one of the input second standard test codes;

[0031] an operational amplifier module, connected between the reference digital-to-analog conversion chip and the comparison unit, configured to obtain a difference between two reference voltages converted from two adjacent first standard test codes, and perform amplification processing to output the reference value.

[0032] Preferably, the aforementioned operational amplifier module comprises an operational amplifier and a circuit located outside the periphery of the operational amplifier chip, the non-inverting input of the operational amplifier is connected to the output of the aforementioned reference digital-to-analog conversion chip, the inverting input is connected to the ground through a seventh resistor, and the output is connected to the connection node of the inverting input of the aforementioned operational amplifier and the aforementioned seventh resistor through an eighth resistor and a second capacitor connected in parallel, and

[0033] The operational amplifier also has a positive power supply end connected to a positive power supply signal and a negative power supply end connected to a negative power supply signal, and the aforementioned positive power supply end is connected to the ground through a third capacitor and a fourth capacitor connected in parallel, and the aforementioned negative power supply end is connected to the ground through a fifth capacitor and a sixth capacitor connected in parallel.

[0034] Preferably, the aforementioned comparison unit comprises:

[0035] A sixth comparator, the non-inverting input of which is connected to the output of the aforementioned fifth comparator, the inverting input of which is connected to the output of the aforementioned operational amplifier, and the output of which provides the aforementioned detection signal.

[0036] Preferably, the aforementioned processing unit comprises:

[0037] A calculation module connected to the output of the aforementioned sixth comparator, for calculating or obtaining a static parameter vector of the aforementioned to-be-tested digital-to-analog conversion chip according to a group of the aforementioned detection signals;

[0038] A judgment module connected to the aforementioned calculation module, for reading and judging whether the digital-to-analog conversion function of the aforementioned to-be-tested digital-to-analog conversion chip is normal according to the comparison result of the variation of the static parameter vector and a preset error range.

[0039] Preferably, the aforementioned processing unit further comprises:

[0040] A correction module connected to the aforementioned judgment module, for obtaining a compensation code set according to the aforementioned detection signal when the variation of the aforementioned static parameter vector exceeds the preset error range, so that the aforementioned processing unit updates the aforementioned standard test code set according to the aforementioned compensation code set;

[0041] A storage module connected to the aforementioned correction module, for storing the aforementioned standard test code set and the aforementioned compensation code set, and the arrangement order of the difference between any two adjacent test voltages in the aforementioned compensation code set is consistent with the arrangement order of the corresponding two first standard test codes in the aforementioned standard test code set.

[0042] The beneficial effects of the present disclosure are: the test device for the D / A conversion chip provided by the present disclosure utilizes the processing unit to provide the first standard test code and the second standard test code in the standard test code set; the sampling amplification unit performs D / A conversion processing according to the first standard test code, and outputs the detection value obtained after conversion, which represents the difference between the two test voltages converted from any two adjacent first standard test codes; and the reference amplification unit performs D / A conversion processing according to the second standard test code, and outputs the reference value obtained after conversion, which represents the difference between the two reference voltages converted from the two adjacent first standard test codes; then the comparison unit compares the detection value with the reference value to generate a detection signal, and the processing unit calculates or obtains a group of static parameter vectors of the D / A conversion chip to be tested according to the group of detection signals, and judges whether the D / A conversion function of the D / A conversion chip to be tested is normal according to the comparison result of the variation of the group of static parameter vectors and the preset error range. Thus, the voltage value of each test code is collected in the prior art, and whether the D / A conversion function of the D / A conversion chip to be tested is normal is directly judged according to the variation of the group of static parameter vectors output by the sixth comparator, so that the test time of the analog output of the D / A chip is effectively shortened. BRIEF DESCRIPTION OF DRAWINGS

[0043] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings.

[0044] Figure 1 The structure block diagram of the test device for the D / A conversion chip provided by the present disclosure is shown;

[0045] Figure 2 The structure block diagram of the test device is shown Figure 1 The structure block diagram of the test device is shown

[0046] Figure 3 The circuit schematic diagram of the test device in an embodiment is shown Figure 2 The circuit schematic diagram of the test device in an embodiment is shown

[0047] Figure 4 The structure block diagram of the processing unit in the test device is shown Figure 1 The structure block diagram of the processing unit in the test device is shown DETAILED DESCRIPTION

[0048] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the related drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be realized in different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the present disclosure more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

[0050] The test of the digital-to-analog conversion function of the D / A chip can be divided into static parameter test and dynamic parameter test. The static parameter test function uses a single analog signal as an initial signal, converts the analog signal into a digital quantity, then outputs the digital quantity into a data acquisition card, converts the digital signal output by the data acquisition card into an analog signal, and compares it with the analog signal as the initial signal, thereby achieving the purpose of detecting a single point of the D / A chip. The dynamic parameter test function can use a sinusoidal analog signal as an initial signal, divide the sinusoidal into equal time interval points, convert the voltage amplitude of each point into a digital quantity, then output the digital quantity into a data acquisition card, convert the sampling points of the digital signal output by the data acquisition card into an analog signal, and compare them one by one with the points of the analog signal as the initial signal, thereby achieving the purpose of detecting dynamic points of the D / A chip.

[0051] Many DACs include an array of capacitors that can be dynamically configured by switches coupled to the capacitors to form a capacitor divider network. Each switch can couple its respective capacitor to one of several voltages, e.g., an analog input voltage, a positive reference voltage, or a negative reference voltage. Each bit of an input digital code is typically determined successively from most significant bit to least significant bit by an iterative successive approximation technique.

[0052] Some DACs include a MSB capacitor bank (also referred to as a “MSB capacitor array”) and a LSB capacitor bank (referred to as a “LSB capacitor array”). In some implementations, the capacitors in the MSB capacitor array are nominally all identical (i.e., have the same capacitance value), while the LSB capacitor bank can be binary weighted (e.g., 4C, 2C, 1C). Some DACs operate according to a thermometer encoding scheme, in which a binary intermediate digital code from a successive approximation register (SAR) is converted to a thermometer intermediate digital code that contains one bit for each capacitor in the MSB capacitor array. By controlling the switches of individual MSB capacitors, a particular proportion of a reference voltage can be generated and provided to a comparator for comparison with an output voltage in order to thereby determine each bit of the digital input code.

[0053] Hereinafter, the disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 A structure block diagram of a testing device for a digital-to-analog conversion chip provided by an embodiment of the disclosure is shown, Figure 2 A structure block diagram of a testing device for a digital-to-analog conversion chip provided by an embodiment of the disclosure is shown,Figure 1 The diagram shows a structural block diagram of a further embodiment of the test apparatus.

[0055] refer to Figure 1 and Figure 2 This disclosure provides a testing apparatus 100 for a digital-to-analog converter (D / A) chip, including but not limited to: a processing unit 110, a sampling amplification unit 120 integrating a D / A chip 121 under test, a reference amplification unit 130 integrating a reference D / A chip 131, and a comparison unit 140. The processing unit 110 provides standard test codes from a set of standard test codes. The sampling amplification unit 120 is connected to the processing unit 110 and receives a first standard test code, performs digital-to-analog conversion processing based on the first standard test code, and outputs a detection value obtained after conversion. This detection value represents the difference between two test voltages after conversion of any two adjacent first standard test codes. The reference amplification unit 130 is connected to the processing unit 110 and receives a first standard test code. The first standard test code is used to perform digital-to-analog conversion processing and output a reference value after conversion. This reference value represents the difference between the two reference voltages after conversion by the two adjacent first standard test codes. The input terminal of the comparison unit 140 is connected to the sampling amplification unit 120 and the reference amplification unit 130 respectively, and is used to compare the aforementioned detection value with the aforementioned reference value to generate a detection signal. The processing unit 110 is connected to the output terminal of the comparison unit 140. The processing unit 110 is also used to calculate or obtain a set of static parameter vectors of the D / A chip 121 under test based on a set of aforementioned detection signals, and to determine whether the digital-to-analog conversion function of the D / A chip 121 under test is normal based on the comparison result of the change of the set of static parameter vectors with the preset error range.

[0056] In a further embodiment of this disclosure, the sampling amplification unit 120 includes, but is not limited to, a D / A chip under test 121, a sample-and-hold module 122, and a differential amplifier 123.

[0057] The D / A chip under test 121 is connected to the processing unit 110 and is used to perform digital-to-analog conversion processing according to the aforementioned first standard test code, and output the converted test voltage. Each output test voltage corresponds to an input first standard test code. The input terminal of the sample-and-hold module 122 is connected to the D / A chip under test 121. The sample-and-hold module 122 is used to hold and output the test voltage corresponding to the current first standard test code. The input terminal of the differential amplifier 123 is connected to the D / A chip under test 121 and the sample-and-hold module 122 respectively. It is used to obtain the difference between the two test voltages converted from two adjacent first standard test codes, amplify the difference, and output the aforementioned detection value.

[0058] Figure 3 Show Figure 2Circuit diagram of the test device shown in one embodiment.

[0059] Reference Figure 2 And Figure 3 In further embodiments of the present disclosure, the sampling amplification unit 120 further comprises a first switch module SW1 having a control end, a first selection end and a second selection end (not shown), the control end being connected with the output end VOUT1 of the D / A chip 121 under test, the first switch module SW1 being controlled by a first control signal S1, one of the first selection end and the second selection end being selected to be connected.

[0060] Further, the sample and hold module 122 comprises: a first comparator 1221, a second comparator 1222, a second switch module SW2, a first diode D1 and a second diode D2, a first resistor R1, a second resistor R2 and a first capacitor C3.

[0061] The non-inverting input end of the first comparator 1221 is connected with the first selection end of the first switch module SW1, and the inverting input end is connected to the inverting input end of the second comparator 1222 through the first resistor R1; the non-inverting input end of the second comparator 1222 is connected to the analog ground AGND through the second resistor R2 and the first capacitor C3 in series, and the inverting input end is connected to the inverting input end of the first comparator 1221 through the first resistor R1; the second switch module SW2 is connected between the output end of the first comparator 1221 and the non-inverting input end of the second comparator 1222, and is controlled by a second control signal S2 to control the connection between the output end of the first comparator 1221 and the non-inverting input end of the second comparator 1222; the anode end of the first diode D1 and the cathode end of the second diode D2 are commonly connected to the output end of the first comparator 1221, and the cathode end of the first diode D1 and the anode end of the second diode D2 are commonly connected to the inverting input end of the first comparator 1221.

[0062] Further, the differential amplifier 123 at least comprises: a third comparator 1231, a fourth comparator 1232, a fifth comparator 1233, a second resistor R5, a third resistor R3 and a fourth resistor R8, a fifth resistor R6 and a sixth resistor R9.

[0063] The non-inverting input terminal of the third comparator 1231 is connected with the output terminal of the second comparator 1222, and the output terminal is connected with the output terminal of the differential amplifier 123 through the series connection of the third resistor R3 and the fourth resistor R8; the non-inverting input terminal of the fourth comparator 1232 is connected with the second selection terminal of the first switch module SW1, the inverting input terminal is connected with the inverting input terminal of the third comparator 1231 through the second resistor R5, and the output terminal is connected with the ground GND through the series connection of the fifth resistor R6 and the sixth resistor R9; the non-inverting input terminal of the fifth comparator 1233 is connected with the connection node of the fifth resistor R6 and the sixth resistor R9, the inverting input terminal is connected with the connection node of the third resistor R3 and the fourth resistor R8, and the output terminal is used as the output terminal of the differential amplifier 123 and used for providing the detection value. At the same time, the third comparator 1231 is connected with the negative power supply end of the negative power supply signal -VCC through the resistor R4, and the fourth comparator 1232 is connected with the negative power supply end of the negative power supply signal -VCC through the resistor R7.

[0064] Further, the reference amplification unit 130 comprises a reference D / A chip 131 and an operational amplifier module 132, and the operational amplifier module 132 comprises an operational amplifier 1321 and a peripheral circuit of the operational amplifier 1321, wherein the peripheral circuit comprises a seventh resistor R11, an eighth resistor R10, a second capacitor C10, a third capacitor C8, a fourth capacitor C9, a fifth capacitor C6 and a sixth capacitor C7.

[0065] The reference D / A chip 131 is used for digital-to-analog conversion processing according to the second standard test code, and outputs the converted reference voltage, and each output reference voltage corresponds to an input second standard test code; the operational amplifier 1321 is connected between the reference D / A chip 131 and the comparison unit 140, and is used for obtaining the difference between the two reference voltages converted by the two adjacent first standard test codes, and amplifying the difference to output the reference value.

[0066] Specifically, the non-inverting input terminal of the operational amplifier 1321 is connected with the output terminal of the reference D / A chip 131, the inverting input terminal is connected with the analog ground AGND through the seventh resistor R12, the output terminal is connected with the connection node of the inverting input terminal of the operational amplifier 1321 and the seventh resistor R12 through the parallel connection of the eighth resistor R10 and the second capacitor C10, and the operational amplifier 1321 further has a positive power supply end connected with the positive power supply signal VCC and a negative power supply end receiving the negative power supply signal -VCC, and the positive power supply end is connected with the analog ground AGND through the parallel connection of the third capacitor C8 and the fourth capacitor C9, and the negative power supply end is connected with the analog ground AGND through the parallel connection of the fifth capacitor C6 and the sixth capacitor C7.

[0067] Further, the comparison unit 140 comprises at least a sixth comparator 141, whose non-inverting input is connected to the output VOUT3 of the fifth comparator 1233, and whose inverting input is connected to the output VOUT4 of the operational amplifier 1321, and whose output VOUT5 provides the aforementioned detection signal.

[0068] Further, the operational amplifier 1321 and the differential amplifier 123 are amplifiers with the same amplification factor after calibration test.

[0069] In the embodiment, the D / A chip 121 to be tested is for example a 12-bit DAC, and the reference D / A chip 131 is for example a tested reference 16-bit D / A chip, which is used to output the expected reference reference, and the reference voltage VREF provided to the reference D / A chip 131 and the D / A chip 121 to be tested can be provided by a separate power supply module, or can also be extracted by a power supply part of the driving overall test device 100 through a circuit processing mode such as a voltage dividing circuit. The setting of the reference voltage is determined according to the D / A conversion index range of the actual D / A chip to be tested. The principle of selecting the reference voltage is that the reference voltage should be within the analog output voltage range of the D / A chip. If the analog voltage output range of the D / A chip is 0-a volts, the reference voltage should be selected between 0<reference voltage<a volts, for example a / 2 volts. In addition, multiple reference voltages can be set to test the same D / A chip, or different reference voltages can be used to test different D / A chips.

[0070] In the embodiment, the comparison unit 140 can be implemented using a voltage comparator chip, and the selection of the voltage comparator chip model is determined according to the D / A conversion index range of the actual D / A chip 121 to be tested. The principle of selecting the voltage comparator chip is that the input voltage range of its two inputs is greater than the analog voltage output range of the D / A chip 121 to be tested. Of course, the comparison unit 140 can also not use a voltage comparator chip, but use a voltage comparator circuit composed of operational amplifiers, which has the same effect.

[0071] The detection value output by the differential amplifier 123 is an amplified signal of the test voltage difference, and the reference value output by the operational amplifier 1321 is an amplified signal of the reference voltage difference, and the comparison result of the two is also a voltage signal.

[0072] The processing unit 110 is not only used to provide the test of the entire test environment, but also to control the input of the digital input end of the D / A chip 121 to be tested and the reference D / A chip 131, and to read the voltage comparison result output by the comparison unit 140.

[0073] Figure 4 It is shownFigure 1 The structural block diagram of a further embodiment of the processing unit in the test device.

[0074] Reference Figure 4 In a further embodiment of the present embodiment, the processing unit 110 can include a calculation module 111, a judgment module 112, a correction module 113 and a storage module 114.

[0075] The calculation module 111 is connected with the output end VOUT5 of the sixth comparator 141, and is configured to calculate or obtain the static parameter vector of the D / A chip 121 to be tested according to a set of the aforementioned detection signals; the judgment module 112 is connected with the calculation module 111, and is configured to read and judge whether the D / A conversion function of the D / A chip 121 to be tested is normal according to the comparison result between the variation of the static parameter vector and the preset error range; the correction module 113 is connected with the judgment module 112, and is configured to obtain a compensation code set according to the aforementioned detection signals when the variation of the static parameter vector exceeds the preset error range, so that the processing unit 110 updates the aforementioned standard test code set according to the aforementioned compensation code set; the storage module 114 is connected with the correction module 113, and is configured to store the aforementioned standard test code set and the aforementioned compensation code set, and the arrangement order of the difference between any two adjacent test voltages in the compensation code set is consistent with the arrangement order of the corresponding two first standard test codes in the aforementioned standard test code set.

[0076] In the test process of a single D / A chip 121 to be tested: assuming that we need to ensure that the DNL of each D / A chip 121 in the mass production test is within ±0.5 times the LSB range.

[0077] First, the digital interface of the processing unit 110 controls the reference D / A chip 131 to output a certain number of positioning corresponding to the expected 0.5 times DNL after conversion of the second standard test code; second, the processing unit 110 controls the D / A chip 121 under test to output the test voltage value corresponding to the conversion of the current first standard test code; then the processing unit 110 controls the sample and hold module 122 to latch the current output test voltage value; then the processing unit 110 controls the D / A chip 121 under test to output the test voltage value corresponding to the conversion of the next first standard test code of the current first standard test code; and the difference between the two adjacent test voltages is amplified by a certain multiple by the differential amplifier 123 and input to the sixth comparator 141 in the comparison unit 140, the differential amplifier 123 and the operational amplifier 1321 are amplifiers with the same amplification multiple after calibration test, the detection value and the reference value (0.5 times LSB) corresponding to the output of the two are compared as the positive and negative input signals of the sixth comparator 141, and the output result (detection signal) of the comparison is received and processed by the processing unit 110; repeating the above steps to traverse all gradients of the first standard test code, a set of static parameter vectors output by the comparator 141 can be obtained, and then the processing unit 110 judges whether the D / A chip 121 under test meets the expected DNL value according to the change amount of the set of static parameter vectors. For example, the change amount of the set of static parameter vectors of the analog output of the D / A chip 121 under test should be less than the expected DNL value range, and the output of the comparison unit 140 should be a low level (logic "0"); the processing unit 110 reads the detection signal output by the comparison unit 140, judges whether it is logic "0", if yes, it indicates that the digital-to-analog conversion function test of the D / A chip 121 under test is valid; if not, it indicates that the digital-to-analog conversion function test of the D / A chip is invalid.

[0078] Further, the sampling and amplification unit 120, the reference amplification unit 130 and the comparison unit 140 can be calibrated respectively before each test, and the calibration data is stored in the processing unit 110. According to the calibration data, compensation is carried out in the program to improve the accuracy of the test, and when the change amount of the static parameter vector exceeds the preset error range, the processing unit 110 acquires a compensation code set according to the aforementioned detection signal, so that the processing unit 110 updates the aforementioned first standard test code set according to the aforementioned compensation code set.

[0079] In summary, the test device 100 for D / A chip provided by the embodiment of the present disclosure utilizes the processing unit 110 to provide a standard test code in a standard test code set; the sampling amplification unit 120 performs digital-to-analog conversion processing according to the aforementioned first standard test code, and outputs a detection value obtained after conversion, which represents the difference between two test voltages converted from any two adjacent first standard test codes; and the reference amplification unit 130 performs digital-to-analog conversion processing according to the aforementioned second standard test code, and outputs a reference value obtained after conversion, which represents the difference between two reference voltages converted from the aforementioned two adjacent first standard test codes; then the comparison unit 140 compares the aforementioned detection value with the aforementioned reference value to generate a detection signal, and the processing unit 110 calculates or obtains a set of static parameter vectors of the D / A chip 121 to be tested according to the set of detection signals, and judges whether the digital-to-analog conversion function of the D / A chip 121 to be tested is normal according to the comparison result of the variation of the set of static parameter vectors and the preset error range. Thus, the voltage value of each test code is collected in the prior art, and whether the digital-to-analog conversion function of the D / A chip 121 to be tested is normal is directly judged according to the variation of the set of static parameter vectors output by the sixth comparator 141, so that the test time of the analog output of the D / A chip is effectively shortened.

[0080] It should be noted that in the description of the present disclosure, it is understood that the terms "upper", "lower", "inner", etc. indicate the orientation or positional relationship, which are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0081] In addition, in this document, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or equipment comprising the element.

[0082] Finally, it should be noted that: obviously, the above embodiments are only examples for clearly illustrating the present disclosure, and are not limitations on the embodiments. Based on the above description, other different forms of changes or variations can also be made by those of ordinary skill in the art. Here, it is not necessary or possible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present disclosure.

Claims

1. A testing device for a digital-to-analog conversion chip, comprising: a processing unit configured to provide a first standard test code and a second standard test code in a set of standard test codes; a sampling amplification unit configured to receive the first standard test code, perform a digital-to-analog conversion process according to the first standard test code, and output a detection value representing a difference between two test voltages converted from any two adjacent first standard test codes; a reference amplification unit configured to receive the second standard test code, perform a digital-to-analog conversion process according to the second standard test code, and output a reference value representing a difference between two reference voltages converted from the two adjacent first standard test codes; a comparison unit having input terminals connected to the sampling amplification unit and the reference amplification unit respectively, configured to compare the detection value with the reference value, and generate a detection signal, wherein the processing unit is connected to an output terminal of the comparison unit, and is further configured to calculate or obtain a set of static parameter vectors of a to-be-tested digital-to-analog conversion chip according to a set of the detection signals, and determine whether a digital-to-analog conversion function of the to-be-tested digital-to-analog conversion chip is normal according to a comparison result between a variation of the set of static parameter vectors and a preset error range, the sampling amplification unit comprises: a to-be-tested digital-to-analog conversion chip configured to perform a digital-to-analog conversion process according to the first standard test code, and output a test voltage converted from the first standard test code, each test voltage corresponding to one first standard test code; a sample-and-hold module configured to hold and output the test voltage corresponding to the current first standard test code; a differential amplifier connected to the to-be-tested digital-to-analog conversion chip and the sample-and-hold module respectively, configured to obtain a difference between two test voltages converted from two adjacent first standard test codes, and perform an amplification process, and output the detection value.

2. The test device of claim 1, wherein, the sampling amplification unit further comprises: a first switch module having a control terminal, a first selection terminal and a second selection terminal, the control terminal being connected to an output terminal of the to-be-tested digital-to-analog conversion chip, the first switch module being controlled by a first control signal to select one of the first selection terminal and the second selection terminal to be connected.

3. The test device of claim 2, wherein, the sample-and-hold module comprises: a first comparator having a non-inverting input terminal connected to the first selection terminal; a second comparator having a non-inverting input terminal connected to ground through a second resistor and a first capacitor in series, and having an inverting input terminal connected to an inverting input terminal of the first comparator through a first resistor; a second switch module connected between an output terminal of the first comparator and a non-inverting input terminal of the second comparator, the second switch module being controlled by a second control signal to control a connection between the output terminal of the first comparator and the non-inverting input terminal of the second comparator; a first diode and a second diode, a positive terminal of the first diode and a negative terminal of the second diode being commonly connected to the output terminal of the first comparator, and a negative terminal of the first diode and a positive terminal of the second diode being commonly connected to the inverting input terminal of the first comparator.

4. The test device of claim 3, wherein, the differential amplifier comprises: A third comparator, a non-inverting input terminal of the third comparator is connected with an output terminal of the second comparator, and an output terminal is connected with an output terminal of the differential amplifier through a third resistor and a fourth resistor in series connection; A fourth comparator, a non-inverting input terminal of the fourth comparator is connected with the second selection terminal, and an inverting input terminal is connected with an inverting input terminal of the third comparator through a ninth resistor, and an output terminal is connected with ground through a fifth resistor and a sixth resistor in series connection; A fifth comparator, a non-inverting input terminal of the fifth comparator is connected with a connection node of the fifth resistor and the sixth resistor, and an inverting input terminal is connected with a connection node of the third resistor and the fourth resistor, and an output terminal is used as an output terminal of the differential amplifier, for providing the detection value.

5. The test device of claim 4, wherein, The reference amplification unit comprises: A reference digital-to-analog conversion chip, for carrying out digital-to-analog conversion processing according to the second standard test code, and outputting a converted reference voltage, each reference voltage output corresponding to one second standard test code input; An operational amplifier module, comprising an operational amplifier and a circuit located in the periphery of the operational amplifier, a non-inverting input terminal of the operational amplifier is connected with an output terminal of the reference digital-to-analog conversion chip, an inverting input terminal is connected with ground through a seventh resistor, and an output terminal is connected with a connection node of the inverting input terminal of the operational amplifier and the seventh resistor through an eighth resistor and a second capacitor connected in parallel, and the output terminal also provides the reference value.

6. The test device of claim 5, wherein, The operational amplifier also has a positive power supply terminal connected with a positive power supply signal and a negative power supply terminal receiving a negative power supply signal, and the positive power supply terminal is connected with ground through a third capacitor and a fourth capacitor connected in parallel, and the negative power supply terminal is connected with ground through a fifth capacitor and a sixth capacitor connected in parallel.

7. The test device of claim 6, wherein, The comparison unit comprises: A sixth comparator, a non-inverting input terminal of the sixth comparator is connected with an output terminal of the fifth comparator, an inverting input terminal is connected with an output terminal of the operational amplifier, and an output terminal provides the detection signal.

8. The test device of claim 7, wherein, The processing unit comprises: A calculation module, connected with an output terminal of the sixth comparator, for calculating or obtaining a static parameter vector of the to-be-tested digital-to-analog conversion chip according to a group of detection signals; A judgment module, connected with the calculation module, for reading and judging whether the digital-to-analog conversion function of the to-be-tested digital-to-analog conversion chip is normal according to a comparison result of a variation of the static parameter vector and a preset error range.

9. The test device of claim 8, wherein, The processing unit further comprises: A correction module, connected with the judgment module, for acquiring a compensation code set according to the detection signal when the variation of the static parameter vector exceeds the preset error range, so that the processing unit updates the standard test code set according to the compensation code set; A storage module, connected with the correction module, for storing the standard test code set and the compensation code set, and an arrangement order of a difference value between any two adjacent test voltages in the compensation code set is consistent with an arrangement order of corresponding two first standard test codes in the standard test code set.

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