Control circuit of pipeline analog-to-digital converter

Abstract

A control circuit of a pipeline analog-to-digital converter. The pipeline analog-to-digital converter includes a multiplication digital-to-analog converter, and the multiplication digital-to-analog converter includes a capacitor. The control circuit includes first to sixth switches, and first and second buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output ends of the first and second buffer circuits are respectively coupled to the first and second switches. The input end of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input end of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives a control signal through the sixth switch. The first reference voltage is not equal to the second reference voltage, and the first switch and the second switch are not turned on at the same time.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital converter (ADC), and more particularly to a control circuit of a pipeline ADC or pipelined ADC. Background Art

[0002] Figure 1 The conventional pipeline analog-to-digital converter 100 includes a plurality of serially connected operation stages 110, a terminal analog-to-digital converter 120, and a digital correction circuit 130. The differential input signal V in After multiple stages of comparison, subtraction, and amplification operations, the digital correction circuit 130 finally corrects the output of each operation stage 110 and the output of the terminal analog-to-digital converter 120 to generate a digital code D, which is the differential input signal V in The operation principle of the pipeline analog-to-digital converter 100 is well known to those skilled in the art, so it will not be described in detail.

[0003] Figure 2 for Figure 1 The functional block diagram of any one of the operation stages 110 in FIG. The operation stage 110 includes a sub-analog-to-digital converter 112, a latch circuit 114 (also referred to as a storage circuit), an encoder 116, and a multiplying digital-to-analog converter (MDAC) 118. The sub-analog-to-digital converter 112 includes a plurality of comparators (or quantizers) that convert the differential input signal V in With multiple preset voltages (V R1 To V Rn The number of comparators (or quantizers) and the number of preset voltages (ie, the value of n) are related to the number of bits of the pipelined analog-to-digital converter 100.

[0004] Because the result of the comparator (or quantizer) cannot be maintained for a long time, the output end of the sub-ADC 112 is coupled to the latch circuit 114, which is used to temporarily store the result of the comparator (or quantizer) (i.e., the output value of the sub-ADC 112).

[0005] The encoder 116 is used to encode the result of the comparator (or quantizer) and generate a digital signal b. The multiplication digital-to-analog converter 118 selects a reference voltage V based on the digital signal b during the amplification stage. REF+ , reference voltage V REF- and / or voltage V CM_REF, voltage V CM_REF is the reference voltage V REF+ And reference voltage V REF- The multiplying digital-to-analog converter 118 converts the differential input signal V in The differential input signal V in Perform subtraction and multiplication operations to output a differential output signal V out . The differential output signal V out becomes the differential input signal of the next operation stage 110 or the terminal analog-to-digital converter 120. In some cases, the multiplying digital-to-analog converter 118 only needs a reference voltage V REF+ And reference voltage V REF- , without the need for voltage V CM_REF .

[0006] However, since there is at least a latch circuit 114 between the multiplication digital-to-analog converter 118 and the sub-analog-to-digital converter 112 (sometimes the encoder 116 may be omitted), the output value of the sub-analog-to-digital converter 112 must go through some gate delays before reaching the multiplication digital-to-analog converter 118. These gate delays prevent the multiplication digital-to-analog converter 118 from utilizing the complete amplification stage, resulting in an increase in the power consumption area of ​​the operational amplifier of the multiplication digital-to-analog converter 118. Summary of the invention

[0007] In view of the shortcomings of the prior art, one of the objectives of this case is to provide a control circuit of a pipeline analog-to-digital converter to improve the shortcomings of the prior art.

[0008] The present case discloses a control circuit of a pipeline analog-to-digital converter. The pipeline analog-to-digital converter includes a multiplication digital-to-analog converter, and the multiplication digital-to-analog converter includes a capacitor. The control circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first buffer circuit, and a second buffer circuit. The first switch is coupled between the first end of the capacitor and the first reference voltage. The second switch is coupled between the first end of the capacitor and the second reference voltage. The first buffer circuit has a first input terminal and a first output terminal, wherein the first output terminal is coupled to the first switch, and the first input terminal is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The second buffer circuit has a second input terminal and a second output terminal, wherein the second output terminal is coupled to the second switch, and the second input terminal is coupled to the fourth reference voltage through the fourth switch, or receives a control signal through the sixth switch. The first reference voltage is not equal to the second reference voltage, and the first switch and the second switch are not turned on at the same time.

[0009] The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a known pipeline analog-to-digital converter;

[0011] Figure 2 for Figure 1 A functional block diagram of any one of the computing stages 110;

[0012] Figure 3 is a functional block diagram of an embodiment of any operation stage in the pipelined analog-to-digital converter of the present invention;

[0013] Figure 4 It is a functional block diagram of another embodiment of any operation stage in the pipeline analog-to-digital converter of the present invention;

[0014] Figure 5 show Figure 3 or Figure 4 An embodiment of a multiplying digital-to-analog converter 518;

[0015] Figure 6 Showing two non-overlapping clock pulses Φ1 and Φ2;

[0016] Figure 7 A circuit diagram of an embodiment of a control circuit of a pipelined analog-to-digital converter of the present invention;

[0017] Figure 8 Three embodiments showing clock pulse Φ and pulse PLS;

[0018] Figure 9a and Figure 9b show Figure 7 Two embodiments of the control circuit;

[0019] Fig.10 A circuit diagram of another embodiment of the control circuit of the pipeline analog-to-digital converter of the present invention; and

[0020] Fig.11 FIG. 4 is a circuit diagram of another embodiment of the control circuit of the pipeline analog-to-digital converter of the present invention. DETAILED DESCRIPTION

[0021] The technical terms used in the following description refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.

[0022] The disclosure of this case includes a control circuit of a pipelined analog-to-digital converter. Since some components of the control circuit of the pipelined analog-to-digital converter of this case may be known components individually, the detailed description of the known components will be omitted below without affecting the full disclosure and feasibility of the device embodiment.

[0023] Figure 3 The operation stage 510 is an embodiment of any operation stage in the pipeline analog-to-digital converter of the present invention. The operation stage 510 includes a sub-analog-to-digital converter 512, a control circuit 515, and a multiplication digital-to-analog converter 518. The control circuit 515 is coupled between the sub-analog-to-digital converter 512 and the multiplication digital-to-analog converter 518. The operation principle of the sub-analog-to-digital converter 512 is similar to that of the Figure 2 The operation principle of the multiplication digital-to-analog converter 518 is similar to that of the multiplication digital-to-analog converter 118, except that the multiplication digital-to-analog converter 518 directly receives the reference voltage V R (Reference voltage V R Represents the reference voltage V REF+ , reference voltage V REF- and / or voltage V CM_REF ), rather than selecting the reference voltage V based on any signal REF+ , reference voltage V REF- and / or voltage V CM_REF .

[0024] Figure 4 The operation stage 610 is another embodiment of any operation stage in the pipeline analog-to-digital converter of the present invention. The operation stage 610 includes a sub-analog-to-digital converter 512, a control circuit 515, an encoder 516, and a multiplication digital-to-analog converter 518. The control circuit 515 is coupled between the encoder 516 and the multiplication digital-to-analog converter 518. The operation principle of the encoder 516 is similar to that of Figure 2 The encoder 116 is the same as that of FIG. 1 , so it will not be described in detail.

[0025] Figure 5 show Figure 3 or Figure 4 An embodiment of the multiplication digital-to-analog converter 518 can be applied to a 1.5-bit pipelined analog-to-digital converter. The multiplication digital-to-analog converter 518 is based on two non-overlapping clock pulses Φ1 and Φ2 (such as Figure 6 Assume that the circuit operates at the first level of the clock pulse (which can be a high level or a low level), then "non-overlapping" means that the two clock pulses are not at the first level at the same time. Figure 6The time interval between time point t1 and time point t2 and the time interval between time point t1' and time point t2' are non-overlapping intervals of the two clock pulses. "The circuit operates at the first level of the clock pulse" means that the circuit is active during the period when the clock pulse is at the first level, for example, operating in a certain stage (such as the sampling stage or the amplification stage discussed below).

[0026] See also Figure 5 . The multiplication digital-to-analog converter 518 mainly includes an operational amplifier 650 for amplifying the signal. The inverting input terminal (negative terminal) of the operational amplifier 650 is coupled to the capacitor C0a and the capacitor C1a through the switch S4a, and the non-inverting input terminal (positive terminal) of the operational amplifier 650 is coupled to the capacitor C0b and the capacitor C1b through the switch S4b. The multiplication digital-to-analog converter 518 operates alternately in the sampling stage and the amplification stage according to the clock pulses Φ1 and Φ2. The following is explained by taking the inverting input terminal of the operational amplifier 650 as an example. In the sampling stage (the clock pulse Φ1 is the first level (for example, a high level) and the clock pulse Φ2 is the second level (for example, a low level)), switches S0a, S1a, and S2a are turned on, and switches S3a, S4a, and S5a are turned off. In this stage, capacitors C0a and C1a respond to the signal Sampling. In the amplification stage (clock pulse Φ2 is at the first level, and clock pulse Φ1 is at the second level), switches S0a, S1a, S2a are turned off, and switches S3a, S4a, S5a are turned on. In this stage, capacitor C0a becomes a feedback capacitor, and the multiplication digital-to-analog converter 518 performs a feedback operation on the input signal V in Perform subtraction and multiplication operations and output differential output signal V out (including signal and signal ) is used as the input of the next operation stage. A person skilled in the art can understand the operation principle of the non-inverting input terminal of the operational amplifier 650 according to the above description, so it will not be described in detail. Figure 5 The voltage V cm is usually the common-mode voltage at the input of op amp 650, while voltage V R+ and V R- (Both together Figure 3 or Figure 4 The reference voltage V R indicates) can be selected from Figure 3 or Figure 4 The reference voltage V REF+ , reference voltage V REF- or voltage V CM_REF .

[0027] A person skilled in the art can understand the operating principle of a multiplication digital-to-analog converter applied to a pipelined analog-to-digital converter with more bits (more than 2.5 bits) based on the above description, so it will not be described in detail.

[0028] exist Figure 3 and Figure 4 In the embodiment of the present invention, the control circuit 515 operates according to the clock pulse Φ and the pulse PLS. The clock pulse Φ can be Figure 6 The control circuit 515 selects the reference voltage V based on the control value (or control signal) Ctrl. REF+ , reference voltage V REF- and / or voltage V CM_REF As the reference voltage V R (Right now, Figure 5 The voltage V R+ is the reference voltage V REF+ , reference voltage V REF- and voltage V CM_REF One, and the voltage V R- is the reference voltage V REF+ , reference voltage V REF- and voltage V CM_REF In other words, the control circuit 515 outputs the reference voltage V according to the control value Ctrl. REF+ , reference voltage V REF- and / or voltage V CM_REF to the multiplying digital-to-analog converter 518. In some embodiments, the multiplying digital-to-analog converter 518 does not require a voltage V CM_REF , that is, the reference voltage V R Can include reference voltage V REF+ and / or reference voltage V REF- , but does not include the voltage V CM_REF .

[0029] exist Figure 3 In the embodiment of , the control value Ctrl is the output value of the sub-analog-to-digital converter 512 (i.e., the result of the comparator (or quantizer)). Figure 4 In the embodiment, the control value Ctrl is the output of the encoder 516 (ie, the digital signal b).

[0030] Figure 7 FIG. 4 is a circuit diagram of an embodiment of a control circuit of a pipelined analog-to-digital converter of the present invention. Figure 3 and Figure 4 The control circuit 515 can be composed of Figure 7 The control circuit 700 is implemented as shown in FIG. Figure 5The embodiment of the present invention is a capacitor C1a or capacitor C1b), and includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, a switch SW6, a buffer circuit 710 and a buffer circuit 720. The output end of the buffer circuit 710 is coupled to the switch SW1, and the output end of the buffer circuit 720 is coupled to the switch SW2.

[0031] One end of the capacitor Cx (ie, the end not coupled to the operational amplifier 650) is coupled to the reference voltage V REF+ , and the reference voltage V is coupled via switch SW2 REF- The switch SW1 and the switch SW2 are controlled by the first switch control signal CS1 and the second switch control signal CS2, respectively, and the first switch control signal CS1 and the second switch control signal CS2 are outputs of the buffer circuit 710 and the buffer circuit 720, respectively. The buffer circuit 710 and the buffer circuit 720 are used to improve the driving capability of the first switch control signal CS1 and the second switch control signal CS2, respectively. In some embodiments, the buffer circuit 710 and the buffer circuit 720 each include at least one inverter.

[0032] The input terminal of the buffer circuit 710 is coupled to the first reference voltage through the switch SW3, and is coupled to the sub-analog-to-digital converter 512 or the encoder 516 through the switch SW5 (i.e., the control value Ctrl is received through the switch SW5). The input terminal of the buffer circuit 720 is coupled to the second reference voltage through the switch SW4, and is coupled to the sub-analog-to-digital converter 512 or the encoder 516 through the switch SW6 (i.e., the control value Ctrl is received through the switch SW6). The first reference voltage is equal to or not equal to the second reference voltage. The switches SW3 and SW4 are turned on or off according to the clock pulse Φ, and when the clock pulse Φ is a first level (e.g., a high level), the multiplication digital-to-analog converter 518 operates in a sampling phase. More specifically, when the clock pulse Φ is a first level (i.e., when the multiplication digital-to-analog converter 518 operates in a sampling phase), the switches SW3 and SW4 are turned on, so that the voltage at the input terminal of the buffer circuit 710 is equal to the first reference voltage, and the voltage at the input terminal of the buffer circuit 720 is equal to the second reference voltage. Because the buffer circuit 710 and the buffer circuit 720 are used to enhance the driving capability of the first switch control signal CS1 and the second switch control signal CS2, when the voltage at the input end of the buffer circuit 710 and the buffer circuit 720 is substantially constant (i.e., when the switch SW3 and the switch SW4 are turned on), the first switch control signal CS1 and the second switch control signal CS2 are maintained at substantially fixed levels. In some embodiments, when the switch SW3 is turned on, the switch SW1 is turned off, and when the switch SW4 is turned on, the switch SW2 is turned off.

[0033] The switches SW5 and SW6 are turned on or off at the same time under the control of the pulse PLS. In some embodiments, when the pulse PLS is at a first level (e.g., a high level), the switches SW5 and SW6 are turned on, so that the input end of the buffer circuit 710 and the input end of the buffer circuit 720 receive the control value Ctrl. When the buffer circuit 710 and the buffer circuit 720 receive the control value Ctrl and the switches SW3 and SW4 are turned off, the levels of the first switch control signal CS1 and the second switch control signal CS2 depend on the control value Ctrl. In some embodiments, when the switches SW3 and SW4 are turned off and the switches SW5 and SW6 are turned on, the switches SW1 and SW2 are not turned on at the same time (i.e., the capacitor Cx is not coupled to the reference voltage V at the same time). REF+ And reference voltage V REF- ).

[0034] Figure 8 Three embodiments of clock pulse Φ and pulse PLS (i.e., PLS_1, PLS_2, and PLS_3) are shown. When the clock pulse Φ is at a first level (e.g., a high level), switches SW3 and SW4 are turned on and switches SW1 and SW2 are turned off; when the clock pulse Φ is at a second level (e.g., a low level), switches SW3 and SW4 are turned off. For pulses PLS_1, PLS_2, and PLS_3, when the pulse PLS is at a first level (e.g., a high level), switches SW5 and SW6 are turned on; when the pulse PLS is at a second level (e.g., a low level), switches SW5 and SW6 are turned off. Figure 8 As shown, the time during which the switch SW5 and the switch SW6 are turned on in each cycle of the clock pulse Φ is Δt1, Δt2 or Δt3.

[0035] The falling edges of the pulses PLS_1, PLS_2, and PLS_3 are located during the second level of the clock pulse Φ. The pulses PLS_1, PLS_2, and PLS_3 are converted from the first level to the second level (i.e., the switches SW5 and SW6 are controlled to be turned off before the control value Ctrl becomes the preset value) before the comparator (or quantizer) of the sub-analog-to-digital converter 512 is reset (i.e., before the control value Ctrl becomes the preset value). In some embodiments, the falling edges of the pulses PLS_1, PLS_2, and PLS_3 are no later than the middle point of the second level of the clock pulse Φ (i.e., no later than Figure 8 time point T1).

[0036] The rising edge of pulse PLS_1 is substantially aligned with the falling edge of clock pulse Φ, the rising edge of pulse PLS_2 is slightly ahead of the falling edge of clock pulse Φ (i.e., switches SW3, SW4, SW5 and SW6 are turned on at the same time for a period of time), and the rising edge of pulse PLS_3 is slightly behind the falling edge of clock pulse Φ (i.e., switches SW5 and SW6 are turned on only after switches SW3 and SW4 are turned off).

[0037] In some embodiments, the comparator (or quantizer) of the sub-analog-to-digital converter 512 is started and reset according to a reference clock pulse (not shown), and the pulse PLS can be generated based on the reference clock pulse or the clock pulse Φ. For example, the reference clock pulse or the clock pulse Φ can be subjected to multiple gate delays to generate the rising edge and / or falling edge of the pulse PLS. The falling edge of the pulse PLS can also be obtained by subjecting the rising edge of the pulse PLS to multiple gate delays. Those skilled in the art are familiar with the design principles of using gate delay techniques to achieve the above-mentioned pulse PLS, so they will not be repeated.

[0038] In some embodiments (such as Figure 9a As shown, switch SW1 is implemented by a P-type metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, hereinafter referred to as PMOS) (M1), switch SW2 is implemented by an N-type metal-oxide-semiconductor field-effect transistor (hereinafter referred to as NMOS) (M2), switch SW3 is implemented by NMOS (M3), switch SW4 is implemented by PMOS (M4), switch SW5 is implemented by NMOS (M5), switch SW6 is implemented by NMOS (M6), the first reference voltage is the ground voltage, the second reference voltage is the power supply voltage VDD (the power supply voltage VDD is greater than the ground voltage), the buffer circuit 710 includes an odd number of inverters, and the buffer circuit 720 includes an odd number of inverters.

[0039] In other embodiments (such as Figure 9b As shown), the switch SW1 (M1) and the switch SW2 (M7) are switches of the same type (for example, the transistors M1 and M7 are both PMOS), the number of inverters included in the buffer circuit 710 and the number of inverters included in the buffer circuit 720 are both even numbers, and the first reference voltage and the second reference voltage are both the power supply voltage VDD.

[0040] Please note that the above embodiments are only for illustration and are not intended to limit the present invention. Figure 7The components, signals and / or parameters include but are not limited to: the types of switches SW1-SW6 (PMOS, NMOS or equivalent components), multiple voltages (a first reference voltage, a second reference voltage, a reference voltage V REF+ , reference voltage V REF- ), the level of the clock pulse Φ and the pulse PLS and / or the duty cycle, and the number of inverters included in the buffer circuits 710 and 720.

[0041] exist Figure 7 In the embodiment, after the switch SW5 (or SW6) changes from on to off, the voltage at the input end of the buffer circuit 710 (or 720) can be naturally maintained for a period of time (depending on the leakage current of the switch SW3 (or SW4)).

[0042] Fig.10 FIG. 8 is a circuit diagram of another embodiment of the control circuit of the pipelined analog-to-digital converter of the present invention. The control circuit 800 is similar to the control circuit 700, except that the control circuit 800 further includes a feedback path 810. The feedback path 810 is coupled between the output end of the buffer circuit 710 and the input end of the buffer circuit 710, and the feedback path 810 includes an inverter 815 and a switch SW7. The input end of the inverter 815 is coupled to the output end of the buffer circuit 710, and the output end of the inverter 815 is coupled to the input end of the buffer circuit 710 through the switch SW7. The switch SW7 is controlled by the inverted signal #PLS of the pulse PLS. More specifically, when the pulse PLS is at the first level (i.e., the switch SW5 and the switch SW6 are turned on), the switch SW7 is turned off (i.e., the feedback path 810 is disconnected), and when the pulse PLS is at the second level (i.e., the switch SW5 and the switch SW6 are turned off), the switch SW7 is turned on. As a result, after the switch SW5 changes from on to off, the inverter 815 on the feedback path 810 can help maintain the voltage at the input end of the buffer circuit 710 at a constant value.

[0043] Please note that Fig.10 In the embodiment of the present invention, the voltage at the input terminal of the buffer circuit 710 is in opposite phase to the voltage at the output terminal of the buffer circuit 710. More specifically, when the number of inverters in the buffer circuit 710 is an odd number, the number of inverters on the feedback path 810 is an odd number. However, in other embodiments, when the number of inverters in the buffer circuit 710 is an even number, the number of inverters on the feedback path 810 is an even number.

[0044] In other embodiments, another feedback circuit coupled between the output terminal of the buffer circuit 720 and the input terminal of the buffer circuit 720 may also be implemented.

[0045] Fig.11FIG. 1 is a circuit diagram of another embodiment of the control circuit of the pipeline analog-to-digital converter of the present invention. In some embodiments, Figure 3 and Figure 4 The control circuit 515 is implemented by a combination of the control circuit 900 and the control circuit 700, or by a combination of the control circuit 900 and the control circuit 800. The control circuit 900 is used to provide a voltage V CM_REF For the capacitor Cx, the control circuit 900 includes a buffer circuit 910, a buffer circuit 920, a transmission gate 930, a switch SW8, a switch SW9, a switch SW10, and a switch SW11.

[0046] When the clock pulse Φ is at the first level, the switches SW8 and SW9 are turned on. At this time, the voltage at the input end of the buffer circuit 910 and the voltage at the input end of the buffer circuit 920 are respectively the first reference voltage and the second reference voltage (the first reference voltage is equal to or not equal to the second reference voltage), so that the transmission gate 930 is turned off (that is, the capacitor Cx does not receive the voltage V CM_REF ). When the clock pulse Φ is at the second level and the pulse PLS is at the first level, the switches SW8 and SW9 are turned off, and the switches SW10 and SW11 are turned on. At this time, the input end of the buffer circuit 910 and the input end of the buffer circuit 920 receive the control value Ctrl. When the clock pulse Φ is at the second level and the pulse PLS is at the second level, the switches SW8, SW9, SW10 and SW11 are all turned off. At this time, the reference voltage VR is equal to or not equal to the voltage V CM_REF .

[0047] In some embodiments, the buffer circuit 910 and the buffer circuit 920 are implemented by inverters, the number of inverters in the buffer circuit 910 is an even number, and the number of inverters in the buffer circuit 920 is an odd number. In this way, when the control value Ctrl is 0 (i.e., low level), the voltage at the output end of the buffer circuit 910 and the voltage at the output end of the buffer circuit 920 are low level and high level respectively, so that the transmission gate 930 is turned on (i.e., the reference voltage VR is equal to the voltage V CM_REF ). When the control value Ctrl is 1 (ie, high level), the voltage at the output end of the buffer circuit 910 and the voltage at the output end of the buffer circuit 920 are high level and low level respectively, so that the transmission gate 930 is turned off.

[0048] In summary, because the control circuit of the present invention reduces the gate delay on the signal path, the control value Ctrl (i.e., the output of the sub-ADC 512 or the output of the encoder 516) can be quickly provided to the multiplication DAC 518. Therefore, the pipeline ADC has a faster response and the power consumption area of ​​the operational amplifier is reduced.

[0049] Please note that the shapes, sizes and proportions of the components in the above disclosed figures are for illustration only and are only for the purpose of helping a person having ordinary knowledge in the technical field to understand the present invention, and are not intended to limit the present invention.

[0050] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. A person with ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be subject to the scope of the patent application defined in this specification.

[0051] Description of reference numerals:

[0052] 100: Pipeline analog-to-digital converter

[0053] 110, 510, 610: computing level

[0054] 120: Terminal analog-to-digital converter

[0055] 130: Digital correction circuit

[0056] 112, 512: Sub-Analog-to-Digital Converter

[0057] 114: Latch circuit

[0058] 116, 516: Encoder

[0059] 118, 518: Multiplying Digital-to-Analog Converter

[0060] 515, 700, 800, 900: Control circuit

[0061] 650: Operational Amplifier

[0062] S0a, S1a, S2a, S3a, S4a, S5a, S0b, S1b, S2b, S3b, S4b, S5b, SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11: Switch

[0063] C0a, C1a, C0b, C1b, Cx: capacitors

[0064] Φ1, Φ2, Φ: clock pulse

[0065] PLS, PLS_1, PLS_2, PLS_3: Pulse

[0066] Ctrl: Control value (control signal)

[0067] V REF+ 、V REF-, Vref1, Vref2, V R : Reference voltage

[0068] V CM_REF :Voltage

[0069] 710, 720, 910, 920: Buffer circuit

[0070] CS1: First switch control signal

[0071] CS2: Second switch control signal

[0072] M1, M2, M3, M4, M5, M6, M7: transistors

[0073] 810: Feedback Path

[0074] 815: Inverter

[0075] 930: Transmission Gate

Claims

1. A control circuit of a pipeline analog-to-digital converter, the pipeline analog-to-digital converter comprising a multiplication digital-to-analog converter, the multiplication digital-to-analog converter comprising a capacitor, the control circuit comprising: A first switch coupled between the first terminal of the capacitor and a first reference voltage; A second switch coupled between the first terminal of the capacitor and a second reference voltage; The third switch; Fourth switch; Fifth switch; The sixth switch; A first buffer circuit having a first input terminal and a first output terminal, wherein the first output terminal is coupled to the first switch, and the first input terminal is coupled to a third reference voltage through the third switch, or receives a control signal through the fifth switch; as well as A second buffer circuit having a second input terminal and a second output terminal, wherein the second output terminal is coupled to the second switch, and the second input terminal is coupled to a fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch; The first reference voltage is not equal to the second reference voltage, and the first switch and the second switch are not turned on at the same time. The pipeline analog-to-digital converter further includes a sub-analog-to-digital converter or an encoder, and the control signal is the output value of the sub-analog-to-digital converter or the output of the encoder.

2. The control circuit according to claim 1, wherein the multiplying digital-to-analog converter performs a sampling operation at a first level of a clock pulse, the third switch and the fourth switch are turned on at the first level of the clock pulse, and the first switch and the second switch are turned off at the first level of the clock pulse. 3 . The control circuit according to claim 1 , wherein the multiplying digital-to-analog converter performs a sampling operation at a first level of a clock pulse, and the fifth switch and the sixth switch are turned on before the clock pulse is converted from the first level to a second level. 4 . The control circuit as claimed in claim 1 , wherein the multiplying digital-to-analog converter performs a sampling operation at a first level of a clock pulse, and the fifth switch and the sixth switch are turned on after the clock pulse is converted from the first level to a second level. 5 . The control circuit according to claim 3 , wherein the fifth switch and the sixth switch are changed from an on state to an off state before the control signal changes level.

6. The control circuit according to claim 1, further comprising: a transmission gate coupled to the first end of the capacitor and receiving a fifth reference voltage; The seventh switch; The eighth switch; The ninth switch; 10th switch; A third buffer circuit having a third input terminal and a third output terminal, wherein the third output terminal is coupled to the transmission gate, and the third input terminal is coupled to the third reference voltage through the seventh switch, or receives the control signal through the ninth switch; as well as The fourth buffer circuit has a fourth input terminal and a fourth output terminal, wherein the fourth output terminal is coupled to the transmission gate, and the fourth input terminal is coupled to the fourth reference voltage through the eighth switch, or receives the control signal through the tenth switch.

7. The control circuit according to claim 1 or 6, further comprising: feedback path, including inverter; The inverter has an input terminal and an output terminal, the input terminal is coupled to the first output terminal of the first buffer circuit, and the output terminal is coupled to the first input terminal of the first buffer circuit. 8 . The control circuit as claimed in claim 7 , wherein when the fifth switch or the sixth switch is turned on, the feedback path is disconnected.

9. The control circuit according to claim 1 or 6, wherein the first switch is a P-type metal oxide semiconductor field effect transistor, the second switch is an N-type metal oxide semiconductor field effect transistor, the first buffer circuit includes at least one inverter, the second buffer circuit includes at least one inverter, and the fourth reference voltage is greater than the third reference voltage.

10. The control circuit according to claim 1 or 6, wherein the first switch and the second switch are metal oxide semiconductor field effect transistors of the same type, the first buffer circuit includes at least one inverter, the second buffer circuit includes at least one inverter, and the fourth reference voltage is equal to the third reference voltage.

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