Stimulus used to organize processing paths for testing methods, layouts, and computer program products of microcircuits.

Abstract

The activation of processing paths in a microelectronic circuit is achieved by providing one or more input messages (101, 102, 103) to decision software (104) and executing the decision software (104) to determine whether one or more of the processing paths of the microelectronic circuit will be activated with a test signal (112). The decision to activate the processing path with the test signal results in continued activation of one or more of the processing paths with the test signal, and the monitoring of whether a timing event occurs on the one or more activated processing paths. A timing event is a change in the digital value at the input of the corresponding register circuit on the activated processing path, occurring after an allowable time limit defined by the trigger signal of the corresponding register circuit.

Description

Field of the Invention

[0001] This invention generally relates to techniques for testing the correct operation of processing paths in microelectronic circuits. Specifically, this invention relates to timing such tests so that sufficiently recent test results are available when needed without unnecessarily interfering with the other functions of the microelectronic circuit. Background of the Invention

[0003] In microelectronic circuits, the processing path includes a chain of register circuits following logic units. Register circuits must store the output value of the previous logic unit on the rising and / or falling edge of the trigger signal (if the register circuit is a flip-flop) or at a high or low level of the trigger signal (if the register circuit is a latch). Excessively high clock frequencies and / or excessively low operating voltages can cause timing events where the output value of the previous logic unit changes too late to be correctly stored.

[0004] Adaptive microelectronic circuits can dynamically change their operating voltage and / or clock frequency to control their power consumption in relation to desired performance: if a temporary degradation in maximum performance is acceptable, power consumption can be reduced by decreasing the operating voltage and / or clock frequency. To provide the microelectronic circuit with knowledge of whether the combination of currently used operating voltage and clock frequency poses a risk of timing events, at least some of its processing paths must be equipped for timing event detection. For example, circuit solutions enabling timing event detection are discussed in patent applications PCT / FI2017 / 050290, PCT / FI2017 / 050475, PCT / FI2017 / 050853, PCT / FI2017 / 050852, and PCT / FI2018 / 050882. Testing the operation of a microelectronic circuit against the possibility of timing events can be referred to as stimulating certain processing paths. The most critical processing paths to stimulate are the so-called critical paths, on which the longest processing delays can be expected based on delay distribution analysis. Stimuli involve intentionally changing the generated digital values ​​and allowing them to propagate through selected processing paths while searching for anomalies in things temporarily stored in the register circuitry of those processing paths. This does not occur when these processing paths are in normal operation. Stimuli for testing purposes are not permitted to alter the state of microelectronic circuits, including register and memory values, unless the bit being changed is a bit unrelated to the overall state of the microelectronic circuit. Therefore, the problem to be solved is how to manage the timing of processing path stimuli for testing purposes.

[0005] Overview

[0006] The object of this invention is to provide a method, arrangement, and computer program product for organizing the stimulation of processing paths in a microelectronic circuit so that they can be used to test the operation of the microelectronic circuit without interfering with its normal operation. Another objective is to organize testing to match the varying processing capabilities required by different processes to be executed. These and further advantageous objectives are achieved by the features listed in the appended independent claims. Advantageous embodiments of the invention are described in the dependent claims.

[0007] According to a first aspect of the invention, a method for organizing the excitation of processing paths in a microelectronic circuit is provided. The method includes providing one or more input messages to decision software; executing the decision software to determine, based on at least the one or more input messages, whether one or more of the processing paths of the microelectronic circuit will be excited with a test signal; and, as a result of the determination that one or more of the processing paths of the microelectronic circuit will be excited with the test signal, continuing to excite one or more of the processing paths with the test signal, and monitoring whether a timing event occurs on these one or more excited processing paths. The timing event is a change in a digital value at an input of a corresponding register circuit on the excited processing path, the change occurring after an allowable time limit defined by a trigger signal of the corresponding register circuit. According to one embodiment, the method includes executing a scheduler as part of a real-time operating system running in the microelectronic circuit; scheduling the execution of the tasks according to a priority defined by a plurality of tasks associated with the microelectronic circuit, by the execution of the scheduler; and repeatedly setting the microelectronic circuit to an idle state during idle periods between consecutive running segments of the tasks, by the execution of the scheduler. The advantage of this is that controlled stimuli for processing paths can be logically and flexibly added to the execution of a real-time operating system, and have a predictable and controllable impact on its operation.

[0008] According to one embodiment, the method includes setting up a microelectronic circuit to enter an idle state by scheduling the execution of an idle task with a lower priority associated with the other tasks, and stimulating the execution of the one or more processing paths by running a stimulus task with a priority higher than that of the idle task but lower than that of the other tasks. The advantage of this is that the code for stimulating the processing paths and the code for running the idle tasks can be separated from each other during creation, editing, and maintenance.

[0009] According to one embodiment, the activation of the one or more processing paths occurs after an interrupt disable instruction is issued and before an interrupt enable instruction is issued. The advantage of this is that interrupt handling can be ensured to not interfere with the activation of the processing path, and vice versa.

[0010] According to one embodiment, the occurrence of a specific instruction (such as a NOP (No Operation) instruction) or a specific instruction set is used as one of the one or more input messages to activate the one or more processing paths during the execution of the specific instruction or the specific instruction set. The advantage of this is that the activation of the one or more processing paths can be controllably overlapped with the execution of other instructions without interfering with other data processing.

[0011] According to one embodiment, the occurrence of a write operation involving writing one or more digital values ​​to a predefined register is used as one of the one or more input messages, so that the activation of the one or more processing paths is executed in response to the occurrence of such a write operation. The advantage of this is that the one or more values ​​written to the predefined register can be used to control the manner in which the activation is completed.

[0012] According to one embodiment, the occurrence of compiled machine-executable instructions automatically added by the compiler to the real-time operating system is used as one of the one or more input messages to trigger the execution of the one or more processing paths in response to the occurrence of the machine-executable instructions. The advantage of this is that the one or more instructions used to execute the trigger have a standard form, without requiring too much additional work from those writing the operating system code.

[0013] According to one embodiment, the method includes using the idle state to perform housekeeping operations on the microelectronic circuit, such as defrauding or erasing one or more flash memory blocks of the released system memory. The advantage of this is that the idle period can be at least partially used for a useful purpose.

[0014] According to one embodiment, the method includes using the idle state to perform non-core operations of the microelectronic circuitry, such as on-chip or off-chip interconnect latency; other I / O latency; power control logic latency, such as sleep mode latency; cache miss latency; integrated memory controller latency; or other memory latency. The advantage of this is that the idle period can be at least partially used for a useful purpose.

[0015] According to one embodiment, the method includes issuing a wait-interrupt instruction after the housekeeping operation has been performed, the wait-interrupt instruction suspending further execution of any task in the microelectronic circuit until a subsequent interrupt is received; and executing the stimulus of the one or more processing paths after the housekeeping operation is performed but before the wait-interrupt instruction is issued. The advantage of this is that the order of operations performed in idle mode is well-defined, and therefore the effect of such operations is deterministic in all cases.

[0016] According to one embodiment, the method includes—as a result of determining that one or more processing paths of a microelectronic circuit will be excited with the test signal—checking whether those one or more processing paths to be excited already have data processing activity; and in response to finding that those one or more processing paths to be excited already have data processing activity, canceling the determined excitement of those one or more processing paths with the test signal, and using the data processing activity to monitor whether a timing event has occurred on those one or more processing paths. The advantage of this is that naturally occurring activity on the processing paths can be used twice to detect possible timing events, and redundant excitement of the processing paths can be avoided.

[0017] According to one embodiment, before proceeding to stimulate one or more processes in the processing path with the test signal, it is checked whether sufficient time will exist within a maximum permissible delay as part of other operations of the microelectronic circuitry to perform the stimulation. In response to the check indicating that sufficient time will exist within the maximum permissible delay as part of other operations of the microelectronic circuitry to perform the stimulation, the method includes waiting for the sufficient time before proceeding to stimulate one or more processes in the processing path. In response to the check indicating that sufficient time will not exist within the maximum permissible delay as part of other operations of the microelectronic circuitry to perform the stimulation, the method includes forcibly changing the other operations of the microelectronic circuitry to provide the sufficient time, and then proceeding to stimulate one or more processes in the processing path. The advantage of this is that the stimulation of the processing path can be performed in a timely manner while avoiding interference with other running processes. According to one embodiment, the method includes selecting at least one of a selected operating voltage level and a selected clock frequency based on an upcoming moment for executing at least one of the plurality of tasks; and performing the stimulation on the one or more processing paths at the selected operating voltage level and / or clock frequency, such that the stimulation indicates the ability of the microelectronic circuit to successfully execute the upcoming task. The advantage of this is that, depending on the task in question, sufficient performance of the microelectronic circuit for the upcoming task can be ensured in a flexible manner. According to a second aspect, a microelectronic circuit is provided, comprising a processing unit including processing paths and configured to provide one or more input messages to decision software; execute the decision software to determine, based on at least the one or more input messages, whether one or more of the processing paths of the microelectronic circuit will be stimulated with a test signal; and—as a result of determining that the one or more processing paths of the microelectronic circuit will be stimulated with the test signal—continue to stimulate the one or more processing paths with the test signal and monitor whether a timing event occurs on the one or more stimulated processing paths. A timing event is a change in the digital value at the input of the corresponding register circuit on the stimulated processing path, which occurs after an allowable time limit defined by the trigger signal of the corresponding register circuit.

[0018] According to one embodiment, the microelectronic circuit is configured to execute a scheduler as part of a real-time operating system within the microelectronic circuit; through the execution of the scheduler, the execution of the tasks is scheduled according to a priority definition associated with multiple tasks in the microelectronic circuit; through the execution of the scheduler, the microelectronic circuit is repeatedly set to an idle state during idle periods between consecutive periods of task execution; and the setting of entering the idle state is used as one of the one or more input messages to stimulate one or more of the processing paths with the test signal during one or more of the idle periods. The advantage of this is that controlled stimulation of processing paths can be logically and flexibly added to the execution of the real-time operating system, and has a predictable and controllable impact on its operation.

[0019] According to one embodiment, the processing unit is configured to execute the settings for the microelectronic circuit to enter the idle state by scheduling the execution of idle tasks, the priority associated with the idle tasks being lower than the priority associated with the other tasks; and to execute the activation of the one or more processing paths by running activation tasks with a priority higher than the priority of the idle tasks but lower than the priority associated with the other tasks. The advantage of this is that the code for activating the processing paths and the code for running the idle tasks can be separated from each other during creation, editing, and maintenance.

[0020] According to one embodiment, the processing unit is configured to issue an interrupt disable instruction before the stimulus of the one or more processing paths and an interrupt enable instruction after the stimulus of the one or more processing paths. The advantage of this is that it can be ensured that interrupt handling will not interfere with the stimulus of the processing path, and vice versa.

[0021] According to one embodiment, the processing unit is configured to use the occurrence of a specific instruction (such as a NOP (No Operation) instruction) or a specific instruction set as one of the one or more input messages to execute the stimulus of the one or more processing paths during the execution of the specific instruction or the specific instruction set. The advantage of this is that the stimulus of the one or more processing paths can be controllably overlapped with the execution of other instructions without interfering with other data processing.

[0022] According to one embodiment, the processing unit is configured to use the occurrence of a write operation involving writing one or more digital values ​​to a predefined register as one of the one or more input messages, so as to execute the stimulus of the one or more processing paths in response to the occurrence of such a write operation. The advantage of this is that the one or more values ​​written to the predefined register can be used to control the manner in which the stimulus is completed.

[0023] According to one embodiment, the processing unit is configured to use the occurrence of compiled machine-executable instructions automatically added by the compiler to the real-time operating system as one of the one or more input messages, so as to execute the stimulus of the one or more processing paths in response to the occurrence of the machine-executable instructions. The advantage of this is that the one or more instructions that can be used to execute the stimulus have a standard form, without requiring too much additional work from those writing the operating system code.

[0024] According to one embodiment, the processing unit is configured to use the idle state to perform housekeeping operations of the microelectronic circuit, such as defrauding or erasing one or more flash memory blocks of the released system memory. The advantage of this is that the idle period can be at least partially used for a useful purpose.

[0025] According to one embodiment, the processing unit is configured to use the idle state to run non-core operations of the microelectronic circuitry, such as on-chip or off-chip interconnect latency; other I / O latency; power control logic latency, such as sleep mode latency; cache misses; integrated memory controller latency; or other memory latency. The advantage of this is that the idle period can be at least partially used for a useful purpose.

[0026] According to one embodiment, the processing unit is configured to issue a wait-interrupt instruction after the housekeeping or non-core operation has been performed. This wait-interrupt instruction suspends further execution of any task in the microelectronic circuit until a subsequent interrupt is received. Furthermore, the stimulus is executed on the one or more processing paths after the housekeeping or non-core operation has been performed but before the wait-interrupt instruction has been issued. The advantage of this is that the order of operations performed in idle mode is well-defined, and therefore the effect of such operations is deterministic in all cases.

[0027] According to one embodiment, the processing unit is configured to: check whether the one or more processing paths to be excited have already engaged in data processing activity, as a result of determining that one or more processing paths of a microelectronic circuit will be excited by the test signal; and in response to finding that the one or more processing paths to be excited have already engaged in data processing activity, cancel the determined excitation of those one or more processing paths with the test signal, and use the data processing activity to monitor whether timing events have occurred on those one or more processing paths. The advantage of this is that naturally occurring activity on the processing paths can be used twice to detect possible timing events, and redundant excitation of the processing paths can be avoided.

[0028] According to one embodiment, the processing unit is configured to: before stimulating one or more of the processes in the processing path with the test signal, check whether sufficient time will exist within a maximum permissible delay as part of other operations of the microelectronic circuit to perform the stimulus; in response to the check indicating that sufficient time will exist within the maximum permissible delay as part of other operations of the microelectronic circuit to perform the stimulus, wait for the sufficient time before proceeding to stimulate one or more of the processes in the processing path; and in response to the check indicating that sufficient time will not exist within the maximum permissible delay as part of other operations of the microelectronic circuit to perform the stimulus, force a change in the other operations of the microelectronic circuit to provide the sufficient time, and then proceed to stimulate one or more of the processes in the processing path. The advantage of this is that the stimulus of the processing path can be performed in a timely manner while avoiding interference with other running processes.

[0029] According to one embodiment, the processing unit is configured to select at least one of a selected operating voltage level and a selected clock frequency based on the imminent time of execution of at least one of the plurality of tasks; and to perform the stimulus on the one or more processing paths at the selected operating voltage level and / or clock frequency, such that the stimulus indicates the ability of the microelectronic circuitry to successfully execute the upcoming task. The advantage of this is that, depending on the task in question, sufficient performance of the microelectronic circuitry for the upcoming task can be ensured in a flexible manner.

[0030] According to a third aspect of the invention, a computer program product is provided comprising one or more sets of one or more machine-executable instructions stored on a computer-readable medium, the instructions being configured to, when executed on one or more processors, cause to implement the methods described above or later herein.

[0031] Brief description of the attached figures

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of the specification, illustrate embodiments of the invention and, together with the specification, help to explain the principles of the invention. In the drawings:

[0033] Figure 1 A method was explained.

[0034] Figure 2 It explains a real-time operating system with a scheduler and multiple tasks.

[0035] Figure 3 The explanation focused on using a scheduler to allocate task execution and idle periods.

[0036] Figure 4 One method was explained using state diagrams.

[0037] Figure 5 The implementation of method replacement has been explained.

[0038] Figure 6 The explanation covers the implementation aspects of method replacement, and...

[0039] Figure 7 The various parts of the microelectronic circuit were explained.

[0040] Detailed description

[0041] Figure 1 This paper describes a method for stimulating processing paths in microelectronic circuits. As an alternative or supplement, Figure 1 It can be viewed as one or more sets of machine-readable instructions that, when executed on one or more processors, cause the execution of this method.

[0042] As shown by reference numerals 101, 102, and 103 in the accompanying drawings, one or more input messages can be provided to the decision-making software. Various types of input messages are possible. As a first example, the occurrence of a specific instruction (such as a NOP (No Operation) instruction) or a specific set of instructions can be used as one of the one or more input messages. In this case, if the decision-making software decides to do so, it can activate one or more processing paths during the execution of the specific instruction or set of instructions, as will be described in more detail later.

[0043] As a second example, the occurrence of a write operation involving writing one or more digital values ​​to a predefined register can be used as one of one or more input messages. In this case, if the decision software decides to do so, it can execute one or more processing paths in response to the occurrence of such a write operation, as will be described in more detail later.

[0044] As a third example, the occurrence of compiled machine-executable instructions automatically added to the real-time operating system by the compiler can be used as one of the aforementioned input messages. In this case, if the decision software decides to do so, it can execute one or more processing paths in response to the occurrence of such machine-executable instructions, as will be described in more detail later.

[0045] Figure 1Step 104 involves executing decision-making software to determine, based on at least the provided input information, whether one or more of the processing paths of the microelectronic circuit will be stimulated with a test signal. A positive result, namely the decision that one or more processing paths of the microelectronic circuit will be stimulated with the test signal, ultimately leads to step 112, which involves continuing to stimulate one or more of the processing paths with the test signal. It also involves monitoring whether a timing event occurs on one or more of such stimulated processing paths. In this document, a timing event refers to a change in the digital value at the input of the corresponding register circuit on the stimulated processing path, which occurs after an allowable time limit defined by the trigger signal of the corresponding register circuit.

[0046] However, after making a preliminary positive decision in step 104, the method may involve checking whether the one or more processing paths to be stimulated already have data processing activity, as shown in step 105. Reference numeral 106 indicates that the one or more processing paths to be stimulated have already had data processing activity. This results in the cancellation of the determined stimulation of one or more processing paths with a test signal, and the data processing activity is used to monitor whether timing events occur on those one or more processing paths. The decision algorithm may return to its waiting state, as... Figure 1 As shown by reference numeral 107 in the attached figure.

[0047] An example of following this sequence of steps 104-105-106-107 could be as follows: the input information that initially triggers the execution of the decision algorithm involves information about detected temperature changes, while a significant amount of processing is underway. Generally, due to the physical effects of temperature on signal propagation along the processing path, reaching or exceeding a certain threshold temperature for a microelectronic circuit can mean that timing events become more likely. Particularly problematic is when the temperature far exceeds the threshold during periods of low processing activity, making the probability of timing events unacceptably high due to the combined effect of operating voltage, clock frequency, and temperature: multiple timing events could occur and cause problems once more payload data is processed. However, if a significant amount of processing is already underway when the threshold temperature is reached, normal processing of the payload data will have already generated timing events (if any). Therefore, the system will receive an early warning that the temperature is about to cause problems and can react by, for example, increasing the operating voltage and / or decreasing the clock frequency to counteract the effects of the temperature.

[0048] Reference numeral 108 indicates that insufficient “native” or “payload” processing activity is in progress, so the system may drift toward a higher probability of timing events without proper warning. The result would then be a decision to intentionally feed “test” or “dumb” signals into at least some selected delay-critical processing paths and see if their propagation through such paths leads to a timing event. Figure 1 In this embodiment, an additional check is required: to check whether sufficient time exists within the maximum permissible delay for executing the stimulus as part of other operations of the microelectronic circuit. This check is as follows: Figure 1 Step 109 is shown in the figure, and its two possible results are explained by reference numerals 110 and 113.

[0049] The method checks whether sufficient time will exist within the maximum permissible delay as part of other operations of the microelectronic circuitry to execute the stimulus. For example, this check might indicate that the scheduler of the microelectronic circuitry's real-time operating system currently knows only a small number of tasks are waiting to execute, after which an idle period may occur. As a result, the method continues at step 111 to wait for the sufficient time before proceeding at step 112 to stimulate the one or more processing paths in question. Alternatively, if the check indicates that sufficient time for executing the stimulus is unlikely within the maximum permissible delay as part of other operations of the microelectronic circuitry, as in step 113, the method continues at step 114 to force a change in the other operations of the microelectronic circuitry to provide the sufficient time, and then continues at step 112 to stimulate the one or more processing paths.

[0050] Figure 2 The execution of scheduler 201, which is part of a real-time operating system 202 running in a microelectronic circuit, is described. The purpose of scheduler 201 is to schedule the execution of multiple tasks 203, 204, 205, 206, and 207 in the microelectronic circuit. Scheduling involves deciding which task will run at what time. The execution of the scheduler may be triggered by various events, such as, for example, operating system calls, external interrupts, or the so-called system clock expiration. The system clock is an internal hardware interrupt of the microelectronic circuit, and the length of its expiration time defines the shortest possible delay after a task may request to be woken up.

[0051] Each task is associated with a corresponding priority and is scheduled to run in the order defined by its associated priority. Figure 2 This aligns with the common practice of representing higher priority with larger quantities, therefore in Figure 2Of the five tasks illustrated as an example, task D has the highest priority, followed by task B, then tasks A and C with the same priority, and finally the idle task 207 with the lowest priority. For each of tasks A through D, there exists an associated, task-specific stack 208, 209, 210, or 211 containing stored information, which the microelectronic circuitry can manipulate while executing instructions of the running task. During periods when a task is not running, the latest state is stored in the stack, and this state can be retrieved from the stack when the task next starts running.

[0052] Real-time operating systems typically do not spend all or even most of their time running actual tasks. Instead, microelectronic circuits are repeatedly set to an idle state by executing scheduler 201. Therefore, idle periods lie between consecutive periods of running tasks. Setting microelectronic circuits to an idle state can be described as running an idle task 207, which has a lower priority than any actual task. While idle periods represent activity lower than tasks, they may involve more than just waiting. The idle state can be used to run such housekeeping operations by implementing the idle task 207 as code that causes the execution of housekeeping operations on the microelectronic circuits, such as defrauding freed system memory, erasing one or more flash memory blocks, etc.

[0053] The intervals between consecutive periods of running tasks may involve varying degrees of activity reduction, with the concepts of idle mode and hibernation mode being referenced here. Figure 3 An example is given. In Figure 3 In the middle, and above Figure 2 Very similarly, assuming a scheduler executes as part of a real-time operating system. By executing this scheduler, multiple tasks are scheduled to run in an order defined by priorities associated with the tasks. Figure 3 In the diagram, the moments when the scheduler or at least a portion thereof is running are interpreted as vertical shading.

[0054] Next to the name of each task A, B, C, or D, its state is shown as a line graph: the task in question may be running, ready, or blocked. In the microelectronic circuit under consideration, only one task can run at a time. When a task is not running, it may be ready or blocked. A ready task has made a request to run, but is currently "preempted" by a higher-priority task that is running. The term "blocked" is a common name for a task that is neither running nor requesting to run; this term must be widely understood so that it does not require some external obstacle to prevent the task from running. For example, a task might be blocked, so after completing its current round of execution, it enters an inactive state and sets a wake-up timer, at which point it needs to run again. Another common representation of a blocked state is that the task in question has made a request for an unavailable resource. To some extent, a wake-up timer can be considered such a resource because the resource it represents (the wake-up time) is unavailable until the wake-up timer expires. Figure 3 In the lower half of the diagram, the tasks in the white rectangles above the horizontal dividing line are running, while the tasks in the shaded rectangles below the line are waiting in a relative order defined by their priorities. First, task A is running. Running the scheduler at point 301 does not reveal any higher-priority tasks, and task A continues running. Running the scheduler at point 302 results in a request to run task B. Assume the tasks have similar priorities. Figure 2 In this process, task B has a higher priority than task A, so it is scheduled to run while task A is in the ready state. Running the scheduler at point 303 results in a request to run the highest priority task D, which also causes task B to be placed in the ready state, and so on.

[0055] The scheduler is activated at point 304 when task A finishes what it's doing and is blocked (e.g., to start its own wake-up timer). Since no other task besides the idle task requests to run, the microcircuit is set to an idle state. At point 305, the same operation repeats, and the idle state continues. At point 306, the code executing the idle task causes a WFI (Wait for Interrupt) instruction to be issued, possibly after any housekeeping operations belonging to the idle task have been performed. The WFI instruction suspends further execution of any task in the microcircuit until a subsequent interrupt is received. This interrupt can be an external interrupt or an internal interrupt (such as the system clock). A deeper inactivity state than idle mode can be called hibernation mode, and it continues until a subsequent interrupt causes the scheduler to run at point 307. Figure 3 This leads to the discovery of a request to run task C.

[0056] Figure 4An example of executing the above-described type of method is illustrated in the form of a state diagram. States 401 and 402 together correspond to the running scheduler; here, it is assumed that the scheduler can run in compressed mode, represented by state 401, where only the occurrence of a request is checked, or in expanded mode, represented by state 402, where the highest priority task that issued the request is selected to run. For clarity, in Figure 4 In this context, idle tasks are not considered tasks in the proper sense, so the transition from state 402 to state 403 only occurs when the scheduler finds a run request from any "real" task in state 402.

[0057] A return from state 403 to state 402 can occur for a variety of reasons. Figure 4 Some examples are given below. A running task may be ready, for example, by signaling the appropriate wake-up timer. Additionally, external or internal interrupts may cause a transition.

[0058] If no request from a "true" task is found in state 402, a transition to idle state 404 occurs. Housekeeping operations can be performed, but will not cause any state transition. An external or internal interrupt (such as the system clock) may cause a transition to state 401, but if no request is found, a transition back to idle state 404 occurs. Waiting for instructions (WFI) may cause a transition from idle state 404 to hibernation state 405. An external or internal interrupt (such as the system clock) may cause a transition to state 401.

[0059] exist Figure 4 During one or more idle periods, represented by the time spent in idle state 404, the method may include activating one or more processing paths in a microelectronic circuit and monitoring whether a timing event occurs on such activated processing paths. A timing event is a change in a digital value at the input of a corresponding register circuit on the activated processing path, occurring after an allowable time limit defined by a trigger signal of the corresponding register circuit. Using idle periods for timing event detection has several advantages. First, by definition, since an idle period is a period in which no real task is running, activating a processing path for the purpose of detecting a timing event does not steal time from any such real task or otherwise interfere with its execution. Second, since manipulation of the task stack is only permitted while the task itself is running, the “redundant” data values ​​used to detect timing events are not mixed with the actual data being processed by the task.

[0060] In cases where the idle state involves running idle tasks that perform housekeeping functions, such housekeeping functions must be time-ordered and processing paths may be incentivized for timed event detection so that they do not interfere with each other. An embodiment can also be presented where one or more processing paths are incentivized for timed event detection as their own task. This can be achieved by running an incentivized task with a priority higher than the idle task but lower than other tasks. This is in... Figure 5 The diagram schematically illustrates that the transition from any previous state 501 to the idle state 404 passes through a timed event detection state 502. Another possibility is to combine states 502 and 404 to implement the activation of the processing path for the code used in timed event detection. Figure 5 State 502 in the code is written as part of the code that implements other functions that will be executed as part of the idle task (State 404).

[0061] Figure 6 Another possible embodiment is shown. This embodiment is particularly suitable if it is known that not all tasks require the same level of maximum performance from the microelectronic circuitry. The operating voltage level and / or clock frequency can be selected based on the imminent moment when at least one task will be executed, and the performance requirements, varying from task to task, can be known. As an example, running the scheduler at state 402 may indicate that there is only one task requesting execution, and for that task, a relatively low clock frequency is sufficient. The microelectronic circuitry or some of its control entities can select a combination of lower operating voltage and lower clock frequency deemed suitable for that particular task. Subsequently, in Figure 6 At state 502, one or more processing paths can be stimulated using a selected operating voltage level and / or clock frequency to enable the stimulation to indicate the microelectronic circuit's ability to successfully execute an upcoming task.

[0062] One possibility for timing one or more processing paths for the purpose of performing timed event detection is to make it occur during a specific instruction (such as a NOP (No Operation) instruction) or a particular set of instructions or instructions. A NOP is a "nothing" instruction during which no actual data processing occurs. To some extent, the time spent executing a NOP instruction is wasted, but using NOP instructions is justifiable, for example, to achieve a specific timing purpose, to force memory alignment, to prevent danger, to occupy a branch delay slot, to invalidate an existing instruction, or as a placeholder for an active instruction that may be added later. Overlapping the activation of a processing path for TEO purposes with the execution of a NOP or its corresponding "nothing" instruction is a way to better utilize what would otherwise be considered "wasted" time.

[0063] One possibility for timing one or more processing paths to perform timed event detection is to make it occur during hardware-related latency, such as on-chip or off-chip interconnect latency, other I / O latency, power control logic latency (such as sleep mode latency), cache misses, integrated memory controller latency, or other memory latency. More generally, hardware-related latency is any time interval during which the processor must wait for data due to hardware constraints. Common examples include waiting for I / O and memory (especially in the case of cache misses). In some cases, control of I / O and / or memory is offloaded to a separate controller, freeing the processor to execute other instructions (if those instructions are available). In other cases, the processor will poll I / O and / or memory at cyclic intervals. In both cases, if data is not readily available, free execution time can be obtained for, for example, stimulating one or more processing paths to perform timed event detection.

[0064] The processor may also include a power management controller that monitors key parameters to ensure the processor remains within specifications, such as maximum power (or energy), current, and temperature. The controller may attempt to minimize any of these variables or react when any parameter approaches its limits. Furthermore, this control may reside within the operating system, for example, with predefined power and / or performance states. Control of variables such as those described above is achieved by changing the processor's operating frequency and / or voltage. Due to limitations in the physical implementation of the processor's voltage and / or frequency generation, changes cannot occur arbitrarily rapidly. Additionally, any changes approaching limits or within the predefined range of the monitored variables may require checking whether the processor can still reach the upcoming operating point.

[0065] One approach to stimulating a processing path for TEO purposes is to trigger the stimulating of one or more processing paths using a write operation that involves writing one or more digital values ​​to a predefined register. If the register has multiple bits, the one or more values ​​written to the predefined register can be used to control the manner of stimulating the path.

[0066] One possibility for generating machine-executable instructions is using a so-called compiler program, which causes one or more processing paths to be stimulated for TEO purposes. Many compilers involve the possibility that, during compilation, the compiler automatically adds certain machine-executable instructions to the compiled program, such as in a real-time operating system. In other words, the person writing the operating system code doesn't need to manually add the complete code for the TEO stimulus mechanism; they only need to add a single line of code to instruct the compiler to add the standard form of the instruction set at compile time.

[0067] Figure 7A microelectronic circuit comprising multiple processing paths 701 and a control unit 702 is schematically illustrated. One or more of the processing paths 701 may be assumed to be delay-critical or otherwise made advantageous for activation, and are therefore equipped with register circuitry capable of time borrowing and timing event detection, and also with one or more controllable data event injection points for on-demand activation of said processing paths(s). The control unit 702 can activate any desired processing path 701 by giving appropriate control commands. Advantageously, the control unit 702 is also responsible for executing the aforementioned scheduler. One or more signal collection circuits 703 are provided for collecting indicator signals, such as TEO (Timing Event Observation) signals, and for providing information about them to the control unit 702.

[0068] Figure 7 At least a portion of the microelectronic circuit consists of adaptive circuit elements, the performance of which can be configured by assuming individual operating parameter values ​​for one or more of the microelectronic circuit's operating parameters. Examples of such operating parameters include operating voltage, trigger signal frequency, and the length of the timing event detection window. The selection of operating parameter values ​​is... Figure 7 The diagram is illustrated using working parameter blocks, with block 704 being an example.

[0069] For example, a register circuit can be made adaptive by ensuring its performance is configurable by allowing one or more operating parameters of the register circuit to assume their own operating parameter values. Therefore, the circuit elements do not need to be adaptive to be included in an adaptive system or microelectronic circuit. Examples could be adaptive systems or microelectronic circuits where the supply voltage and / or power consumption level and / or other parameters can be set externally while the internal circuitry remains unchanged and cannot be further configured: for example, the monitoring window length can be fixed and cannot be changed.

[0070] The control unit 702 of the adaptive microelectronic circuit is configured to select the values ​​of operating parameters based on performance measurements obtained from portions of the microelectronic circuit. The results of such performance measurements may, for example, indicate the number of timing events detected per unit time collected by one or more signal collection circuits 703.

[0071] Control unit 702 can be configured to reduce the operating voltage value in response to the above result, which indicates the level of detected timing events below a first threshold. To avoid a situation where a low number of detected timing events are due to low activity or no activity on the processing path, control unit 702 can be configured to activate one or more such processing paths.

[0072] Figure 7The DFT (Design for Testability) capability of the microelectronic circuit is considered to provide test input arrangement 705 and test output arrangement 706. Test input arrangement 705 enables the selective feeding of test signals to the circuit elements of processing path 701, while test output arrangement 706 enables the selective collection of test output signals from the circuit elements of processing path 701. Examples of test input and test output signals are provided, along with associated control commands that control unit 702 can use to selectively set the circuit elements in processing path 701 to test mode.

[0073] It will be apparent to those skilled in the art that the basic idea of ​​this invention can be implemented in various ways as technology advances. Therefore, this invention and its embodiments are not limited to the examples described above, but can be varied within the scope of the claims.

Claims

1. A method for stimulating processing paths in a microelectronic circuit, comprising: - Provide one or more input pieces of information to the decision-making software. - The decision-making software is executed to determine, based on at least one or more of the input information, whether one or more processing paths of the microelectronic circuit will be excited with a test signal, and - As a result of determining that one or more processing paths of the microelectronic circuit will be excited with the test signal, the process continues to excite one or more processing paths in the processing path with the test signal and monitor whether a timing event occurs on the excited one or more processing paths. The timing event is a change in the digital value at the input of the corresponding register circuit on the activated processing path, the change occurring after an allowed time limit defined by the trigger signal of the corresponding register circuit. Its features are: The method includes, as a result of determining that one or more processing paths of the microelectronic circuit will be excited with the test signal, checking whether those one or more processing paths to be excited already have data processing activity, and - The method includes, in response to discovering that one or more processing paths to be stimulated already have data processing activity, canceling the determined stimulation of those one or more processing paths with a test signal, and using the data processing activity to monitor whether a timing event occurs on those one or more processing paths.

2. The method as described in claim 1, characterized in that, include: - Executes the scheduler, which is part of the real-time operating system running in the microelectronic circuit. - Through the execution of the scheduler, the tasks are scheduled to run in an order defined by priorities associated with multiple tasks in the microelectronic circuit. - Through the execution of the scheduler, during idle periods between consecutive periods of running the task, the microelectronic circuit is repeatedly set to an idle state, and - Use the setting to enter an idle state as one of the one or more input messages so that during one or more of the idle periods, one or more processing paths in the processing paths are stimulated with the test signal.

3. The method as described in claim 2, characterized in that, include: - The setting for the microelectronic circuit to enter the idle state is executed by scheduling the execution of idle tasks, wherein the priority associated with the idle tasks is lower than the priority associated with other tasks, and - The incentives for the one or more processing paths are executed by running an incentive task with a priority higher than that of the idle task but lower than that of the other tasks.

4. The method as described in claim 2 or 3, characterized in that, The activation of the one or more processing paths occurs after the interrupt disable instruction is issued and before the interrupt enable instruction is issued.

5. The method as described in claim 1, characterized in that, The occurrence of a specific instruction or a specific set of instructions is used as one of the one or more input messages to trigger the execution of the one or more processing paths during the execution of the specific instruction or the specific set of instructions.

6. The method as described in claim 5, characterized in that, The specific instructions include the NOP (No Operation) instruction.

7. The method as described in claim 1, characterized in that, The occurrence of a write operation involving writing one or more digital values ​​to a predefined register is used as one of the one or more input messages to trigger the execution of the one or more processing paths in response to the occurrence of such a write operation.

8. The method as described in claim 2, characterized in that, The occurrence of machine-executable instructions in compiled form, which are automatically added by the compiler to the real-time operating system, is used as one of the one or more input messages to stimulate the execution of the one or more processing paths in response to the occurrence of the machine-executable instructions.

9. The method as described in claim 2, characterized in that, This includes using the idle state to run the internal processing operations of the microelectronic circuit.

10. The method as described in claim 9, characterized in that, The internal processing operations of the microelectronic circuit include defrauding or erasing one or more flash memory blocks of the released system memory.

11. The method as described in claim 9 or 10, characterized in that, include: - After the housekeeping operation has been performed, a wait-for-interrupt instruction is issued, which suspends further execution of any task in the microelectronic circuit until a subsequent interrupt is received. - The stimulus of the one or more processing paths is executed after the housekeeping operation is performed but before the wait interruption instruction is issued.

12. The method as described in claim 2, characterized in that, This includes using the idle state to run non-core operations of the microelectronic circuit.

13. The method as described in claim 12, characterized in that, The non-core operations of the microelectronic circuit include: - On-chip or off-chip interconnect delay, - Other I / O delays, - Power control logic delay, - Cache miss. - Integrated memory controller latency, or - Other memory latency.

14. The method as described in claim 13, characterized in that, The power control logic delay includes a sleep mode.

15. The method according to any one of claims 12-14, characterized in that, include: - After the non-core operation has been executed, a wait-for-interrupt instruction is issued. This wait-for-interrupt instruction suspends further execution of any task in the microelectronic circuit until a subsequent interrupt is received. - The stimulus of one or more processing paths is executed after the non-core operation is performed but before the wait interrupt instruction is issued.

16. The method as described in claim 1, characterized in that, Before proceeding to excite one or more processing paths in the processing path with the test signal, it is checked whether sufficient time will exist within the maximum permissible delay as part of other operations of the microelectronic circuit to perform the excitation, so that... - In response to the check indicating that sufficient time will exist within the maximum permissible delay as part of other operations of the microelectronic circuit for executing the stimulus, the system waits for the sufficient time before proceeding to stimulate one or more processing paths in the processing path. - In response to the check indicating that there is no sufficient time to perform the stimulus as part of other operations of the microelectronic circuit within the maximum permissible delay, the other operations of the microelectronic circuit are forcibly changed to provide the sufficient time, and then proceed to stimulate the one or more processing paths in the processing path.

17. The method as described in claim 2, characterized in that, include: - Based on the imminent moment of executing at least one of the plurality of tasks, select at least one of the selected operating voltage level and the selected clock frequency, and - Execute the stimulus on one or more processing paths at a selected operating voltage level and / or clock frequency so that the stimulus indicates the microelectronic circuit's ability to successfully perform an upcoming task.

18. A microelectronic circuit including a processing unit, the processing unit including a processing path and configured to: - Provide one or more input pieces of information to the decision-making software. - The decision-making software is executed to determine, based on at least one or more of the input information, whether one or more processing paths of the microelectronic circuit will be stimulated with a test signal, and - As a result of determining that one or more processing paths of the microelectronic circuit will be excited by the test signal, the process continues to excite one or more processing paths in the processing path with the test signal and monitor whether a timing event occurs on the excited one or more processing paths. The timing event is a change in the digital value at the input of the corresponding register circuit on the activated processing path, the change occurring after an allowed time limit defined by the trigger signal of the corresponding register circuit. Its features are, The processing unit is configured to: As a result of determining that one or more processing paths of the microelectronic circuit will be excited with the test signal, it is checked whether those one or more processing paths to be excited already have data processing activity, and - In response to the discovery that one or more processing paths to be stimulated already have data processing activity, cancel the determined stimulation of those one or more processing paths with test signals, and use the data processing activity to monitor whether timing events occur on those one or more processing paths.

19. The microelectronic circuit as described in claim 18, characterized in that, The processing unit is configured to: - Executes the scheduler, which is part of the real-time operating system running in the microelectronic circuit. - Through the execution of the scheduler, the tasks are scheduled to run in an order defined by priorities associated with multiple tasks in the microelectronic circuit. - Through the execution of the scheduler, during idle periods between consecutive periods of running the task, the microelectronic circuit is repeatedly set to an idle state, and - Use the setting to enter an idle state as one of the one or more input messages so that during one or more of the idle periods, one or more processing paths in the processing paths are stimulated with the test signal.

20. The microelectronic circuit as claimed in claim 19, characterized in that, The processing unit is configured to: - The setting for the microelectronic circuit to enter the idle state is executed by scheduling the execution of idle tasks, wherein the priority associated with the idle tasks is lower than the priority associated with other tasks, and - The incentives for the one or more processing paths are executed by running an incentive task with a priority higher than that of the idle task but lower than that of the other tasks.

21. The microelectronic circuit as described in claim 19 or 20, characterized in that, The processing unit is configured to issue an interrupt disable instruction before the stimulus of the one or more processing paths and to issue an interrupt enable instruction after the stimulus of the one or more processing paths.

22. The microelectronic circuit as described in claim 18, characterized in that, The processing unit is configured to use the occurrence of a specific instruction or a specific instruction set as one of the one or more input messages, so as to execute the stimulus of the one or more processing paths during the execution of the specific instruction or the specific instruction set.

23. The microelectronic circuit as described in claim 22, characterized in that, The specific instructions include the NOP (No Operation) instruction.

24. The microelectronic circuit as described in claim 18, characterized in that, The processing unit is configured to use the occurrence of a write operation involving writing one or more digital values ​​to a predefined register as one of the one or more input messages, so as to execute the stimulus of the one or more processing paths in response to the occurrence of such a write operation.

25. The microelectronic circuit as described in claim 19, characterized in that, The processing unit is configured to use the occurrence of compiled machine-executable instructions automatically added by the compiler to the real-time operating system as one of the one or more input messages, so as to execute the stimulus of the one or more processing paths in response to the occurrence of the machine-executable instructions.

26. The microelectronic circuit as described in claim 19, characterized in that, The processing unit is configured to use the idle state to run the internal processing operations of the microelectronic circuit.

27. The microelectronic circuit as described in claim 26, characterized in that, The internal processing operations of the microelectronic circuit include defrauding or erasing one or more flash memory blocks of the released system memory.

28. The microelectronic circuit as described in claim 26 or 27, characterized in that, The processing unit is configured to: - After the housekeeping operation has been performed, a wait-for-interrupt instruction is issued, which suspends further execution of any task in the microelectronic circuit until a subsequent interrupt is received. - The stimulus of the one or more processing paths is executed after the housekeeping operation is performed but before the wait interruption instruction is issued.

29. The microelectronic circuit as described in claim 19, characterized in that, This includes using the idle state to run non-core operations of the microelectronic circuit.

30. The microelectronic circuit as described in claim 29, characterized in that, The non-core operations of the microelectronic circuit include: - On-chip or off-chip interconnect delay, - Other I / O delays, - Power control logic delay, - Cache miss. - Integrated memory controller latency, or - Other memory latency.

31. The microelectronic circuit as described in claim 30, characterized in that, The power control logic delay includes a sleep mode.

32. The microelectronic circuit according to any one of claims 29-31, characterized in that, The processing unit is configured to: - After the non-core operation has been executed, a wait-for-interrupt instruction is issued. This wait-for-interrupt instruction suspends further execution of any task in the microelectronic circuit until a subsequent interrupt is received. - The stimulus of one or more processing paths is executed after the non-core operation is performed but before the wait interrupt instruction is issued.

33. The microelectronic circuit as described in claim 18, characterized in that, The processing unit is configured to: - Before stimulating one or more processing paths in the processing path with the test signal, check whether there will be sufficient time to perform the stimulation as part of other operations of the microelectronic circuit within the maximum permissible delay; - In response to the check indicating that sufficient time will exist within the maximum permissible delay as part of other operations of the microelectronic circuit for executing the stimulus, the system waits for the sufficient time before proceeding to stimulate one or more processing paths in the processing path. - In response to the check indicating that there will not be sufficient time to perform the stimulus as part of other operations of the microelectronic circuit within the maximum permissible delay, the other operations of the microelectronic circuit are forcibly changed to provide the sufficient time, and then proceed to stimulate the one or more processing paths in the processing path.

34. The microelectronic circuit as described in claim 19, characterized in that, The processing unit is configured to: - Select at least one of the selected operating voltage level and the selected clock frequency based on the upcoming moment of executing at least one of the plurality of tasks, and - The one or more processing paths are stimulated at a selected operating voltage level and / or clock frequency so that the stimulation indicates the ability of the microelectronic circuit to successfully perform an upcoming task.

35. A computer program product comprising one or more sets of one or more machine-executable instructions stored on a computer-readable medium, the instructions being configured to, when executed on one or more processors, cause to perform the method as claimed in any one of claims 1 to 17.

Images