Fingerprint recovery management for memory systems

Abstract

This application is directed to imprint recovery management for memory systems. In some cases, memory cells can become imprinted, which can refer to various conditions in which a cell becomes biased to store one logical state rather than another, is not susceptible to being written to a different logical state, or both. Imprinted memory cells can be recovered using a recovery or repair process, which can be initiated according to various conditions, detections, or inferences. In some examples, a system can be configured to perform imprint recovery operations that are adjusted or selected according to the characterized severity of the imprint, operating mode, environmental conditions, and other factors. Imprint management techniques can improve the robustness, accuracy, or efficiency with which a memory system or component thereof can operate in the presence of conditions associated with memory cell imprinting.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT application No. PCT / US2020 / 049178, filed September 3, 2020, entitled “IMPRINT RECOVERY MANAGEMENT FOR MEMORY SYSTEMS”, filed by Basuta et al., which claims priority to U.S. Patent Application No. 16 / 581,045, filed September 24, 2019, entitled “IMPRINT RECOVERY MANAGEMENT FOR MEMORY SYSTEMS”, both of which are assigned to the assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] This technical field relates to imprint recovery management for memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, frequently represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM, on the other hand, may lose its stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memory but can be non-volatile because it uses ferroelectric capacitors as storage devices.

[0006] Some memory types are susceptible to imprinting, which can refer to various conditions where one memory cell tends to store one logical state rather than another, is not easily written to with a different logical state (e.g., a logical state different from the one stored before a write operation), or both. In some cases, the likelihood of imprinting can increase over time (e.g., a longer duration in which a memory cell stores a logical state may be associated with an increased likelihood of the memory cell being imprinted by that logical state). Alternatively, the likelihood of imprinting may increase with temperature (e.g., a higher temperature of a memory cell storing a logical state may be associated with an increased likelihood of the memory cell being imprinted by that logical state). Imprinted memory cells can be associated with read errors, write errors, or other behaviors or vulnerabilities that may damage the operation of the memory device or the system containing the memory device. Summary of the Invention

[0007] A method is described. The method may include: determining that a set of memory cells contained in a memory device are imprinted in a corresponding first logical state; instructing a host device coupled to the memory device that the set of memory cells are imprinted in the corresponding first logical state; receiving from the host device approval to perform an imprint restoration procedure on the set of memory cells, the imprint restoration procedure improving the ability of the set of memory cells to switch between storing the corresponding first logical state and storing a corresponding second logical state; and performing the imprint restoration procedure on the set of memory cells, at least in part based on receiving the approval from the host device.

[0008] Another method is described. The method may include: determining that a set of memory cells contained in a memory device are imprinted in a corresponding first logic state; reading the corresponding first logic state from the set of memory cells; storing the corresponding first logic state in a second location outside the set of memory cells; and performing an imprint recovery procedure on the set of memory cells after storing the corresponding first logic state outside the set of memory cells, the imprint recovery procedure being configured to improve the ability of the set of memory cells to switch between storing the corresponding first logic state and storing a corresponding second logic state.

[0009] Another method is described. The method may include: receiving, at a memory device, a read command from a host device coupled to the memory device for data in a memory array within the memory device; identifying a data error in the data; determining that the data error exceeds the correction capability of an error correction procedure supported by the memory device; switching the memory array to a safe mode, at least in part based on the determination that the data error exceeds the correction capability of the error correction procedure; and performing a trace recovery procedure on the memory array, at least in part based on the determination that the data error exceeds the correction capability of the error correction procedure and while operating the memory array in safe mode, the trace recovery procedure improving the ability of memory cells in the memory array to switch between storing different logical states.

[0010] Another method is described. The method may include: issuing a read command for data in the memory device from a host device to a memory device coupled to the host device; receiving, at the host device, an indication of a data error in the read command from the memory device; and executing a data recovery procedure for the data at the host device, at least in part based on the received indication of the data error. Attached Figure Description

[0011] Figure 1 This document describes examples of systems that support imprint management based on the examples disclosed herein.

[0012] Figure 2 This document describes instances of memory dies that support trace management for memory systems, based on the examples disclosed herein.

[0013] Figure 3A and 3B Examples illustrating the nonlinear electrical properties of ferroelectric memory cells with hysteresis curves based on the various examples disclosed herein.

[0014] Figure 4A and 4B Examples illustrating the nonlinear electrical properties of imprinted ferroelectric memory cells with hysteresis curves, based on the various examples disclosed herein.

[0015] Figure 5 This document describes instances of systems that support imprint management for memory systems, based on the examples disclosed herein.

[0016] Figure 6 This document describes an instance of a process flow that supports imprint management for memory systems, based on the examples disclosed herein.

[0017] Figure 7This document describes curves illustrating imprint detection conditions that support imprint management for memory systems, based on the examples disclosed herein.

[0018] Figure 8A and 8B This document describes an example of a footprint evaluation process for footprint management in a memory system, based on the examples disclosed herein.

[0019] Figure 9 This document describes an example of cell biasing for trace management in a memory system, based on the examples disclosed herein.

[0020] Figure 10 This document describes instances of signaling support for imprint management in memory systems, based on the examples disclosed herein.

[0021] Figure 11 This document describes instances of state diagrams supporting imprint management for memory systems, based on the examples disclosed herein.

[0022] Figures 12 to 16 This document describes an instance of a process flow that supports imprint management for memory systems, based on the examples disclosed herein.

[0023] Figure 17 A block diagram is shown that supports imprint management for a memory system according to various aspects of this disclosure.

[0024] Figure 18 A block diagram of a host device supporting imprint management for a memory system is shown, according to aspects of this disclosure.

[0025] Figures 19 to 22 The flowchart illustrates one or more methods for trace management of memory systems, based on the examples disclosed herein. Detailed Implementation

[0026] Memory devices, when used as part of electronic devices such as mobile devices, personal computers, wireless communication devices, servers, Internet of Things (IoT) devices, vehicles, or vehicle components, may experience various conditions. In some cases, one or more memory cells of a memory device may be imprinted. Imprinting can refer to various conditions in which memory cells of the memory device tend to store one logical state rather than another, are not easily written to with different logical states (e.g., logical states different from those stored before a write operation), or both. The likelihood of a memory cell being imprinted with a logical state can be related to the length of uninterrupted (e.g., continuous) storage of the logical state, the temperature of the memory cell during storage of the logical state, or other factors.

[0027] In one instance, a memory device may undergo imprinting due to prolonged exposure to high temperatures, such as being in a hot vehicle, exposed to direct sunlight, or in other environments. This condition can be termed static baking (e.g., when one or more memory cells remain in a specific logical state while exposed to high temperatures). In some cases, static baking can imprint (e.g., thermally imprint) the individual memory cells of the memory device, causing the memory cells to be biased towards or trapped in a first state (e.g., a state corresponding to logic 0) and unable to enter another state (e.g., a state corresponding to logic 1). In another instance, the memory cells of the memory device may store logical states, or a charge state or material state that may or may not be associated with data, under manufacturing conditions. A certain number of imprints may be performed on the memory device before it is installed in a system or before it operates within the system, such as imprinting over time while idle or without power in a warehouse, which may lead to performance degradation or failure during initial operation. In another instance, imprinting may be unintentionally or maliciously caused by operating parameters or access patterns.

[0028] When compared to unimprinted memory cells, imprinted memory cells can be associated with adverse performance characteristics. For example, imprinted memory cells may prevent charge flow during access operations (e.g., read or write operations), may prevent polarization changes during access operations, may prevent changes in material properties such as changes in atomic distribution or arrangement, resistance changes, or threshold voltage changes, or may be associated with other behaviors different from those of unimprinted memory cells (e.g., asymmetric behavior relative to different logic states). In one instance, when a write operation is performed on an imprinted memory cell to write a target logic state, the memory cell may not store the target logic state, or the memory device may be unable to read the memory cell while storing the target state, which can cause access errors (e.g., write errors, read errors) or data corruption.

[0029] In some cases, recovery or repair processes can be used to recover imprinted memory cells (e.g., de-imprinting, detachment, repair, normalization, equalization). For example, memory cells in an array can be recovered (e.g., from recoverable imprints) by applying various biasing techniques, such as applying one or more voltages or voltage pulses to the memory cells, or by performing multiple access operations (e.g., multiple read operations, multiple write operations, multiple read and write operations) on the memory cells of the memory array. In various instances, such biasing can be performed in maintenance or recovery modes that may or may not be associated with specific data access (e.g., as requested or commanded by a host device, on a scheduled basis, based on detection or prediction of imprinting), or in imprint maintenance or recovery modes that modify the parameters of access operations (e.g., read operations, write operations, refresh operations) while supporting data transfer in the imprint maintenance or recovery mode. In some cases, parameters can be permanently or indefinitely modified to support imprint recovery or prevention (e.g., the duration or magnitude of the access voltage can be modified). Such techniques can mitigate the effects of imprinting, for example, by returning memory cells to a generally normalized, leveled, or otherwise symmetrical behavior with respect to different logical states.

[0030] Recovery operations related to memory cell imprints, according to the described techniques, can be initiated based on various conditions or detections. For example, an electronic device or memory device can detect conditions associated with imprinting (e.g., conditions associated with high temperature, conditions associated with maintaining a logical state for a relatively long period, indication of the memory device being powered on for the first time, unintentional or malicious access patterns that could generate imprints), and initiate a recovery operation based at least in part on the detected conditions. In other words, in some instances, the likelihood of imprinting can be inferred based on operating conditions, or the presence of imprinting can be predicted in other ways. In some instances, such detection can be based on signaling transmitted between the electronic device (e.g., a host device, a host controller) and the memory device, or various tracking, monitoring, sensing, or computational operations performed by one or both of the memory device or the electronic device containing the memory device.

[0031] In some cases, electronic or memory devices may not have imprinting indications or may lack information relating to determining or predicting whether imprinting has occurred or may occur. For example, a memory device may be powered off or deactivated during use of the electronic device, such as when the electronic device is powered off or loses power (e.g., when the battery is depleted, when the power supply is disconnected), or when the electronic device is in standby mode or other modes in which the memory device is powered off or otherwise does not monitor operating or environmental conditions. During power-off, deactivation, or hibernation, electronic and memory devices may be exposed to one or more operating or environmental conditions that can affect the operation of the memory device, but the device may not detect conditions that would be associated with imprinting. For example, if the device is not powered on, it may not monitor thermal history or conditions. Therefore, in some instances, the memory device may perform an imprint detection procedure (e.g., detecting the presence of an imprint in the memory device) to determine whether an imprint recovery operation should be performed on the memory array. A memory device or a system containing a memory device may initiate or execute such detection procedures after activation (e.g., as part of an initialization, power-on, or startup process) in response to a request from a host device, or on any other scheduled (e.g., periodic) or event-driven (e.g., triggered) basis, including the various scenarios described herein.

[0032] The techniques disclosed herein can improve the robustness, accuracy, or efficiency of a memory device or its host device, or a system comprising a memory device and a host device, in the presence of conditions associated with memory cell imprinting. For example, according to the described techniques, the memory device, host device, or both can perform various operations to detect the presence of memory cell imprints or infer the likelihood of such imprints. The memory device can be configured accordingly to perform various operations in response to such detection or inference, which can be more efficient than performing such operations continuously or preemptively. In some instances, the system can be configured to characterize the severity or directionality of the imprint and perform imprint recovery operations scaled or selected according to the characterized severity or directionality. Alternatively or concurrently, the imprint recovery operation can be customized by the system for specific operating conditions of the memory device or host device, such as operating modes or environmental conditions, which in some instances may be at least partially based on signaling or operational negotiation between the memory device and the host device. In some cases, the described techniques also take into account various aspects of data retention or operational integrity, including various signaling, data transfer, or operational management between the memory device and the host device.

[0033] First, as referenced Figure 1 The features of this disclosure are described in the context of the memory system and memory die described up to 4. Figures 5 to 16The features of this disclosure are further described in the context of imprint detection and restoration techniques. (See references...) Figure 17 The device diagrams and flowcharts for memory trace management described up to 32 further illustrate and describe these and other features of this disclosure.

[0034] Figure 1 This document describes an example of a system 100 supporting imprint management based on the examples disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and multiple channels 115 coupling the external memory controller 105 to the memory device 110. System 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0035] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. In some instances, system 100 may be an example of a portable electronic device. For example, system 100 may describe aspects of computers, laptops, tablets, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a system component configured to store data for one or more other components of system 100.

[0036] At least some parts of system 100 may be instances of host devices. Such host devices may be instances of devices that use memory to execute processes, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, computers, laptops, tablets, smartphones, cellular phones, wearable devices, internet-connected devices, and some other fixed or portable electronic devices, etc. In some cases, host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device.

[0037] In some cases, memory device 110 may be a separate device or component configured to communicate with other components of system 100 and provide physical memory addresses or spaces that can be used or referenced by system 100. In some instances, memory device 110 may be configured to cooperate with one or more different types of system 100. Signaling between components of system 100 and memory device 110 may be used to support modulation schemes for modulated signals, various pin designs for transmitting signals, various physical package dimensions of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions and / or other factors.

[0038] Memory device 110 may be configured to store data for components of system 100. In some cases, memory device 110 may act as a slave device to system 100 (e.g., responding to and executing commands provided by system 100 via external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (e.g., memory chips) supporting a desired or specified capacity for data storage. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0039] System 100 may further include processor 120, basic input / output system (BIOS) component 125, one or more peripheral components 130, and input / output (I / O) controller 135. The components of system 100 may be electrically connected to each other via bus 140.

[0040] Processor 120 may be configured to provide at least a portion of the control or other functionality for system 100. Processor 120 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations of these types of components. In this case, processor 120 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), or system-on-a-chip (SoC), and other instances.

[0041] BIOS component 125 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100. BIOS component 125 may also manage data flow between processor 120 and various components of system 100 (e.g., peripheral components 130, I / O controller 135). BIOS component 125 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0042] Peripheral component 130 can be any input or output device, or an interface to such a device, which can be integrated into or integrated with system 100. Examples may include a disk controller, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, serial or parallel port, or peripheral card slot, such as peripheral component interconnect (PCI) or dedicated graphics port. Peripheral component 130 can be any other component that a person skilled in the art would understand as a peripheral device.

[0043] I / O controller 135 manages data communication between processor 120 and peripheral components 130, input devices 145, or output devices 150. I / O controller 135 can manage peripheral devices that are not integrated into system 100 or are not integrated with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0044] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or it may be managed by I / O controller 135.

[0045] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, audio speaker, printing device, or another processor on a printed circuit board. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0046] The components of system 100 may consist of general-purpose or special-purpose circuitry designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive components.

[0047] Memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a series of memory cells (e.g., one or more grids, one or more segments), wherein each memory cell is configured to store at least one bit of digital data. In some cases, memory array 170 may include ferroelectric RAM (FeRAM) memory cells. Reference Figure 2 The characteristics of memory array 170 and / or memory cells are described in more detail.

[0048] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or an example of a 3D memory cell array. For example, a 2D memory device may contain a single memory die 160. A 3D memory device may contain two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked one on top of the other (e.g., relative to a substrate) or adjacent to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, hierarchy, layer, or die. A 3D memory device may contain any number of stacked memory dies 160-N (e.g., two high stacked memory dies, three high stacked memory dies, four high stacked memory dies, five high stacked memory dies, six high stacked memory dies, seven high stacked memory dies, eight high stacked memory dies). This increases the number of memory cells that can be positioned on the substrate compared to a single 2D memory device, which in turn can reduce manufacturing costs or increase the performance of the memory array, or both. In some 3D memory devices, different stacks may share at least one common access line, such that some stacks may share at least one of word lines, digital lines, and / or board lines.

[0049] The device memory controller 155 may include circuitry or components configured to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, instructions, or other configurations enabling the memory device 110 to perform various operations and may be configured to receive, transmit, or execute commands, data, or control information relating to components of the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or a processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command or a read command, the write command instructing the memory device 110 to store certain data representing components of system 100 (e.g., processor 120), and the read command instructing the memory device 110 to provide certain data stored in memory die 160 to components of system 100 (e.g., processor 120). In some cases, the device memory controller 155 may be combined with the local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein. Examples of components that may be included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for receiving signals (e.g., from an external memory controller 105), a transmitter for transmitting signals (e.g., to an external memory controller 105), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers configured to support the operation of the described device memory controller 155 or local memory controller 165.

[0050] A local memory controller 165 (e.g., local to memory die 160) may be configured to control the operation of memory die 160. In some instances, the local memory controller 165 may be configured to communicate with device memory controller 155 (e.g., to receive or transmit data and / or commands). The local memory controller 165 may support device memory controller 155 in controlling the operation of memory device 110 as described herein. In some cases, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Therefore, the local memory controller 165 may be configured to communicate with device memory controller 155, communicate with other local memory controllers 165, or communicate directly with external memory controller 105 or processor 120.

[0051] External memory controller 105 may be configured to facilitate the transfer of information, data, and / or commands between components of system 100 (e.g., processor 120) and memory device 110. External memory controller 105 may act as a communication link between components of system 100 and memory device 110, allowing components of system 100 to operate without needing to know the operational details of the memory device. Components of system 100 may present requests (e.g., read or write commands) to external memory controller 105 that it can fulfill. External memory controller 105 may translate or interpret communications exchanged between components of system 100 and memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0052] In some cases, the external memory controller 105 or other components of system 100, or the functions described herein, may be implemented by processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by processor 120 or other components of system 100. Although the external memory controller 105 is depicted as being external to memory device 110, in some cases, the external memory controller 105, or the functions described herein, may be implemented by memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across processor 120 and memory device 110, such that portions of the external memory controller 105 are implemented by processor 120, and other portions are implemented by device memory controller 155 or local memory controller 165. Similarly, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may be performed by the external memory controller 105 (separate from or included in the processor 120).

[0053] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some instances, channels 115 may be configured to support communication between external memory controller 105 and memory device 110. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between or associated with terminals of components of system 100. For example, channel 115 may include a first terminal comprising one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. Pins may be instances of conductive input or output points of devices of system 100, and pins may be configured to act as part of a channel. In some cases, the pins or pads of the terminal may be part of the signal path of channel 115. Additional signal paths may be coupled to the terminals of the channel for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., within memory device 110 or its components, such as within memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0054] Channel 115 (and associated signal paths and terminals) can be dedicated to transmitting a specific type of information. In some cases, channel 115 can be an aggregated channel and therefore can contain multiple individual channels. For example, data channel 190 can be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), and so on. Signals transmitted via the channel can use a dual data rate (DDR) timing scheme. For example, some symbols of the signal can be recorded on the rising edge of the clock signal, and other symbols of the signal can be recorded on the falling edge of the clock signal. Signals transmitted via the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be recorded for each clock cycle.

[0055] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, CA channel 186 may contain a read command for the address of desired data. In some cases, CA channel 186 may be registered on the rising and / or falling clock edges. In some cases, CA channel 186 may contain any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0056] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between high and low states and coordinate the operation of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK_t and CK_c signals) and the signal paths of CK channels 188 may be configured accordingly. In some cases, the clock signals may be single-ended. CK channels 188 may contain any number of signal paths. In some cases, clock signals CK (e.g., CK_t and CK_c signals) may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Clock signals CK may therefore be referred to differently as control clock signals CK, command clock signals CK, or system clock signals CK. The system clock signal CK can be generated by the system clock, which may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0057] In some cases, channel 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channel 190 may transmit (e.g., bidirectionally) information to be written to or read from memory device 110.

[0058] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may contain any number of signal paths.

[0059] In some cases, other channels 192 may include one or more write clock (WCK) channels. While the 'W' in WCK nominally stands for "write," the write clock signals WCK (e.g., WCK_t and WCK_c signals) provide a timing reference generally used for access operations of memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t and WCK_c signals), and the signal paths of the WCK channel may be configured accordingly. The WCK channel may contain any number of signal paths. The data clock signal WCK can be generated by a data clock, which may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0060] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels can be configured to convey error detection signals, such as checksums, to improve system reliability. EDC channels can contain any number of signal paths.

[0061] Channel 115 can use a variety of different architectures to couple external memory controller 105 to memory device 110. Examples of various architectures may include buses, point-to-point connections, cross switches, high-density in-cell modules such as silicon in-cell modules, or channels formed in an organic substrate, or combinations thereof. For example, in some cases, the signal path may at least partially contain high-density in-cell modules, such as silicon in-cell modules or glass in-cell modules.

[0062] Various modulation schemes can be used to modulate the signal transmitted on channel 115. In some cases, binary symbol (or binary hierarchy) modulation schemes can be used to modulate the signal transmitted between external memory controller 105 and memory device 110. A binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals two. Each symbol in a binary symbol modulation scheme can be configured to represent one bit of digital data (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and so on.

[0063] In some cases, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. The multi-symbol modulation scheme can be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme can be configured to represent more than one bit of digital data (e.g., the symbol can represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8 and other PAM configurations, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and so on. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) can be a signal modulated using a modulation scheme that includes at least three levels for encoding information of more than one bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, multi-level, or higher-order modulation schemes and symbols.

[0064] In some cases, one or more memory cells of memory array 170 may be imprinted. Imprinting can refer to various conditions in which a memory cell tends to store one logical state rather than another, is not easily written to with a different logical state (e.g., a logical state different from the logical state stored before the write operation), or both. The likelihood of a memory cell being imprinted with a logical state can be related to the length of time the logical state is stored (e.g., continuous duration, uninterrupted duration), the temperature of the memory cell while the logical state is stored, unintentional or malicious access patterns, or other factors. According to the described techniques, components of system 100 can be configured to selectively perform various operations to mitigate or recover from such imprinting, which can improve the robustness, accuracy, or efficiency of the memory device 110, the host device, or the entire system 100 in the presence of conditions associated with memory cell imprinting.

[0065] For example, according to the described techniques, memory device 110, host device (e.g., external memory controller 105), or both, can perform various operations to detect the presence of memory cell imprints or infer the likelihood of memory cell imprints. Memory device 110 can be configured accordingly to perform various operations in response to such detection or inference, which can be more efficient than performing such operations continuously or preemptively. In some instances, one or more components of system 100 can be configured to characterize the severity or directionality of the imprint and perform imprint recovery operations that are scaled or selected according to the characterized severity or directionality. Alternatively or additionally, the imprint recovery operation can be customized by system 100 for specific operating conditions of memory device 110, host device (e.g., external memory controller 105), or the entire system 100, such as operating modes or environmental conditions, which in some instances may be at least partially based on signaling or operational negotiation between memory device 110 and host device (e.g., external memory controller 105).

[0066] Figure 2 This document describes an example of a memory die 200 supporting trace management for a memory system, based on the examples disclosed herein. The memory die 200 may be a reference. Figure 1 An example of the described memory die 160. In some cases, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each programmable to store different logical states (e.g., programmed to one of a set of two or more possible states). For example, memory cell 205 may be configured to store one bit of digital logic at a time (e.g., logic 0 and logic 1). In some cases, memory cell 205 (e.g., multi-level memory cell 205) may be configured to store more than one bit of digital logic at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0067] In some instances, memory cell 205 may store charges representing programmable logic states (e.g., storing charges in capacitors, capacitive memory elements, or other capacitive storage devices). In one instance, charged and uncharged capacitors may each represent two logic states. In another instance, positively charged (e.g., first polarity, positive polarity) and negatively charged (e.g., second polarity, negative polarity) capacitors may each represent two logic states. DRAM or FeRAM architectures may use such designs, and the capacitors employed may contain dielectric materials with linear or parapolar polarization properties as insulators. In some instances, different amounts of charge on the capacitors may represent different logic states, and in some instances, more than two logic states may be supported in a given memory cell 205. In some instances, such as FeRAM architectures, memory cell 205 may contain ferroelectric capacitors with insulating (e.g., non-conductive) layers between the terminals of the capacitors, using ferroelectric material as the capacitor. Different degrees or polarities of polarization of the ferroelectric capacitors may represent different logic states (e.g., supporting two or more logic states in a given memory cell 205). Ferroelectric materials exhibit nonlinear polarization properties, including reference polarization. Figure 3A and 3B Those properties are discussed in more detail.

[0068] In some instances, memory cell 205 may use a configurable material to store logical states, which may be referred to as a memory element, memory storage element, material element, material memory element, material portion, material portion with write polarity, etc. The configurable material of memory cell 205 may have one or more variable and configurable characteristics or properties (e.g., material states) that represent (e.g., correspond to) different logical states. For example, the configurable material may take different forms, different atomic configurations, different degrees of crystallinity, different atomic distributions, or otherwise maintain different properties. In some instances, such characteristics may be associated with different resistances, different threshold voltages, or other properties that can be detected or distinguished during read operations to identify the logical states stored by the configurable material. In some instances, the configurable material may refer to a chalcogenide-based memory component. For example, a chalcogenide memory element may be used in a phase-change memory (PCM) cell or a self-selecting memory cell. A chalcogenide memory element may be an example of a resistive memory or a limit memory.

[0069] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210, digital line 215, and / or board line 220. In some cases, digital line 215 may also be referred to as a bit line. References to access line, word line, digital line, board line, bit line, or the like are interchangeable and do not affect understanding or operation. Activating or selecting word line 210, digital line 215, or board line 220 may involve applying a voltage to the corresponding access line (e.g., "biasing" the corresponding access line).

[0070] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, board lines 220) arranged in a grid pattern. Memory cells 205 may be located at the intersections of word lines 210, digital lines 215, and / or board lines 220. A single memory cell 205 can be accessed at its intersection by applying a bias to the word lines 210, digital lines 215, and board lines 220 (e.g., applying a voltage to the word lines 210, digital lines 215, or board lines 220).

[0071] Access to memory cell 205 can be controlled via row decoder 225, column decoder 230, and board driver 235. For example, row decoder 225 may receive a row address from local memory controller 265 and activate word lines 210 based on the received row address. Column decoder 230 may receive a column address from local memory controller 265 and activate digital lines 215 based on the received column address. Board driver 235 may receive a board address from local memory controller 265 and activate board lines 220 based on the received board address, or may activate a common board or board node shared by the segment of the memory cell 205 being accessed. For example, memory die 200 may include multiple word lines 210 labeled WL_1 to WL_M, multiple digital lines 215 labeled DL_1 to DL_N, and multiple board lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Memory cell 205 at its intersection can be accessed by activating word line 210, digital line 215, and board line 220, such as WL_1, DL_3, and PL_1. The intersection of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205. In some cases, the intersection of word line 210, digital line 215, and board line 220 can be referred to as the address of memory cell 205.

[0072] Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. In some instances, capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 (e.g., cell bottom, bottom node) may be coupled to switching component 245, and a second node of capacitor 240 (e.g., cell board, board node) may be coupled to board line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0073] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 245. A capacitor 240 (e.g., at the bottom of the cell) can be electronically communicated with digital line 215 using switch assembly 245. For example, when switch assembly 245 is deactivated, capacitor 240 may be isolated from digital line 215, and when switch assembly 245 is activated, capacitor 240 may be coupled to digital line 215. In some cases, switch assembly 245 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source may be greater than or less than the transistor's threshold voltage. In various instances, switch assembly 245 may be a p-type transistor or an n-type transistor. Word line 210 can be electronically communicated with the gate of switch assembly 245, and switch assembly 245 can be activated / deactivated based on the voltage applied to word line 210.

[0074] Sensing component 250 can be configured to detect the state (e.g., polarization state, charge state) stored in capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers to amplify or otherwise convert signals generated by accessing memory cell 205. For example, during a read operation, capacitor 240 of memory cell 205 may output a signal (e.g., discharge charge) to its corresponding digital line 215, which may cause a change in the voltage of digital line 215. The sensing amplifier can detect small changes in charge or voltage of digital line 215 during the read operation and can generate a signal corresponding to logic 0 or logic 1 based on the detected charge.

[0075] In some instances, sensing component 250 may be configured to compare a signal received from memory cell 205 (e.g., via digital line 215) with a reference line 255 (e.g., a reference voltage). Sensing component 250 may determine the stored state of memory cell 205 based on this comparison. In one instance, in binary signaling, if digital line 215 has a higher voltage than the reference signal 255, then sensing component 250 may determine that the stored state of memory cell 205 is logic 1, and if digital line 215 has a lower voltage than the reference line 255, then sensing component 250 may determine that the stored state of memory cell 205 is logic 0. Sensing component 250 may include various transistors, amplifiers, or other circuitry systems for detecting and amplifying differences in signals. The detected logic state of memory cell 205 can be provided as an output of sensing component 250 (e.g., provided to input / output component 260) and can indicate the detected logic state to another component of memory device 110 including memory die 200, such as device memory controller 155 (e.g., directly or using local memory controller 265). In some cases, sensing component 250 can communicate electronically with row decoder 225, column decoder 230 and / or board driver 235.

[0076] In some cases, sensing component 250 or reference line 255 may (e.g., via local memory controller 265) be configured to control or adjust a reference voltage for determining (reading) the logic state stored in memory cell 205 (e.g., according to various operating modes or other adjustments). For example, during access modes (e.g., where application data can be written to or read from memory cell 205), sensing component 250 and reference line 255 may be configured to use a default reference voltage to determine (e.g., read) the state stored in memory cell 205. The default reference voltage may be configured or set to a voltage level that reduces or minimizes errors during sensing operation or otherwise maximizes the read window (e.g., a reference voltage that is equalized or centralized with respect to the detection of different logic states). For example, a default voltage can be configured (e.g., as a static configuration, or as a configuration adjusted during operation) to a voltage level between the voltage of digital line 215 when reading memory cell 205 of storage logic 1 and the voltage of digital line 215 when reading memory cell 205 of storage logic 0 (e.g., the distance to the digital line 215 voltage associated with logic 1 is equal to the distance to the digital line 215 voltage associated with logic 0). This facilitates accurate determination of the stored memory state.

[0077] The local memory controller 265 can control access to the memory cell 205 through various components (such as row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 can be a reference. Figure 1 An example of the described local memory controller 165. In some cases, one or more of the row decoder 225, column decoder 230, board driver 235, and sensing components 250 may be located in the same position as the local memory controller 265. The local memory controller 265 may be configured to receive data from a reference... Figure 1 The described external memory controller 105 or device memory controller 155 receives one or more commands and / or data, translates the commands and / or data into information usable by the memory die 200, performs one or more operations on the memory die 200, or transmits data from the memory die 200 to the external memory controller 105 or device memory controller 155 in response to performing one or more operations. The local memory controller 265 can generate row, column, and / or board line address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may differ for the various operations discussed during operation of the memory system 200.

[0078] In some cases, the local memory controller 265 may be configured to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify the target memory cell 205 on which a write operation will be performed. The local memory controller 265 may identify the target word line 210, target digital line 215, and / or target board line 220 that are in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, target digital line 215, and / or target board line 220 (e.g., by applying voltage to the word line 210, digital line 215, or board line 220) to access the target memory cell 205. The local memory controller 265 may apply a specific signal (e.g., voltage) to digital line 215 and a specific signal (e.g., voltage) to board line 220 during a write operation to store a specific state in capacitor 240 of memory cell 205, the specific state indicating the desired logic state.

[0079] In some cases, the local memory controller 265 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify the target memory cell 205 on which the read operation will be performed. The local memory controller 265 may identify the target word line 210, target digital line 215, and / or target board line 220 that are in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, target digital line 215, and / or target board line 220 (e.g., by applying voltage to the word line 210, digital line 215, or board line 220) to access the target memory cell 205. Target memory cell 205 can transmit a signal to sensing component 250 in response to applying a bias voltage to the access line. Sensing component 250 can amplify the signal. Local memory controller 265 can activate sensing component 250 (e.g., latching sensing component) and thereby compare the signal received from memory cell 205 with reference line 255. Based on the comparison, sensing component 250 can determine the logic state stored in memory cell 205. As part of a read operation, local memory controller 265 can transmit the logic state stored in memory cell 205 to external memory controller 105 (or device memory controller).

[0080] In some memory architectures, accessing memory cell 205 can degrade or corrupt the logic state stored in memory cell 205, and a rewrite or refresh operation can be performed to return the original logic state to memory cell 205. In DRAM or FeRAM, for example, the capacitor of memory cell 205 can partially or completely discharge during a sensing operation, thereby corrupting the logic state stored in memory cell 205. Therefore, in some instances, the logic state stored in memory cell 205 can be rewritten after an access operation that returns the memory cell to its original logic state (e.g., in a rewrite operation). Local memory controller 265 can rewrite the logic state to the target memory cell after a read operation, and in some cases, a rewrite operation can be considered part of a read operation. In some cases, activating a single access line (e.g., word line 210, digital line 215, board line 220) can cause all memory cells 205 coupled to the activated access line to discharge. Therefore, some or all of the memory cells 205 coupled to the access lines associated with the access operation can be rewritten after the access operation (e.g., all cells of the accessed row, all cells of the accessed column).

[0081] In some instances, reading memory cell 205 can be non-destructive. That is, after reading memory cell 205, the logic state of memory cell 205 may not need to be rewritten. However, in some instances, refreshing the logic state of memory cell 205 may or may not be necessary in the absence of other access operations. For example, the stored logic state can be maintained by periodically refreshing the memory cell 205 by applying appropriate write, rewrite, refresh, or equalization pulses or bias voltages. Refreshing memory cell 205 can reduce or eliminate read interference errors or logic state corruption caused by charge leakage or changes in the atomic configuration of memory elements over time.

[0082] In some cases, environmental conditions such as static baking can shift or alter the programmable characteristics of memory cell 205. For example, in FeRAM applications, static baking can shift or change other aspects of the polarization capacity, coercivity, or charge mobility of memory cell 205, which can cause memory cell 205 to be biased to a specific logic state (e.g., biased towards being written to or read as a logic 1 state or biased towards being written to or read as a logic 0 state). In memory applications using configurable materials (e.g., material memory elements), these or other conditions can cause variable and configurable characteristics or properties to be less likely to change in response to write operations, such as being less likely to be programmed with different atomic configurations, less likely to be programmed with different crystallinity, less likely to be programmed with different atomic distributions, or less likely to be programmed with some other properties associated with different logic states. Such changes to programmable characteristics can be referred to as imprinting and can cause read or write behavior different from when imprinting does not occur (e.g., asymmetry with respect to logic states). For example, when a write operation is performed on an imprinted memory cell that is in an initial state to change the logic state of the memory cell, the memory cell 205 may remain or return to its initial (e.g., imprinted) state, or may otherwise be read as having stored its initial state. For example, if the memory cell 205 is imprinted in a logic 0 state, then after an attempt is made to write to the memory cell 205 in a logic 1 state (e.g., after performing a write operation corresponding to a logic 1 state), the memory cell 205 may continue to remain in the logic 0 state, or continue to be read as having stored a logic 0 state.

[0083] In some cases, the memory die 200 or the memory device 110 or system 100 containing the memory die 200 may be configured to execute an imprint detection procedure to determine whether an imprint recovery operation should be performed. In some cases, the imprint detection procedure may assess or determine the number of memory cells 205 that have been imprinted or trapped in a certain logic state, or otherwise determine or infer the presence, severity, or direction of the imprint.

[0084] In one instance, the imprint detection procedure may include writing or attempting to write at least a first set of logical states to a set of memory cells 205. The memory die 200 may be configured or configured to read the set of memory cells 205 and perform an analysis procedure that compares the written logical states with the logical states read from the set of memory cells 205 to determine whether a recovery operation should be performed. As used herein, a written logical state may refer to a logical state that is attempted to be written or intended to be written, and a written logical state may refer to an attempted logical state, but in some cases, the write logical state may not be successful (e.g., due to imprints on the target memory cell 205).

[0085] In some cases, for one or more write operations, and using one or more read reference voltages, a footprint detection program can determine how many logic states read from the set of memory cells 205 do not match the corresponding logic states that have been written. For example, memory die 200 (e.g., local memory controller 265) or a memory device or host device that otherwise operates memory die 200 can determine that a mismatch or error has occurred when a logic state read from memory cell 205 differs from a logic state written to memory cell 205. The footprint detection program can count the number of mismatches or errors to determine whether a recovery operation should be performed, which may include performing one or more comparisons or other calculations based on the number of mismatches or errors.

[0086] In some cases, to support imprint detection or evaluation procedures, sensing component 250 or reference line 255 may be configured to adjust a reference voltage from a default reference voltage to a reference voltage greater than or less than the default reference voltage (e.g., an offset reference voltage). It is anticipated that using an offset reference voltage when reading a set of memory cells 205 will introduce or otherwise be associated with a number of mismatches or errors (e.g., the expected difference between the stored logic state and the detected logic state), regardless of the imprint. For example, a first offset reference voltage may be closer to the digital line voltage associated with logic 1 than the default reference voltage, which may reduce or eliminate the read margin associated with reading a memory cell storing logic 1. This may increase read mismatches or errors associated with sensing operations. That is, even without an imprint, a sensing operation modified to use an offset reference voltage is expected to produce a certain number of erroneous reads, such as detecting logic 0 when actually reading a memory cell 205 storing logic 1. In some instances, aspects of the expected and measured mismatches or errors can be utilized in imprint evaluation, as described herein.

[0087] In some cases, the imprint detection or evaluation procedure may be configured to adjust the reference voltage from a default reference voltage to multiple different reference voltages (e.g., multiple offset reference voltages) that are greater than or less than the default reference voltage, wherein each of the offset reference voltages may be associated with a corresponding expected number of mismatches or errors (e.g., according to a random or probabilistic distribution). In some cases, it may be possible to determine whether to perform an imprint recovery procedure by comparing the determined number of mismatches observed when reading memory unit 205 using the operating reference voltage or offset reference voltage with the corresponding expected number of mismatches, and by using correlation analysis as described herein.

[0088] In some cases, various imprint recovery or repair processes can be used to recover the imprinted memory cell 205 (e.g., imprint removal, detachment, repair, normalization, equalization). For example, various biasing techniques can be applied, such as applying one or more voltages or voltage pulses to the memory cell 205 (e.g., recovering the memory cell 205 based on voltage pulses or biases applied via digital line 215, board line 220, or both). In various instances, such voltage pulses or biases may comprise one or more pulses, wherein pulses can be applied according to different pulse, step size, ramp, or other characteristic shapes that have different durations, amplitudes, polarities, and combinations thereof. In some instances, such voltage pulses may be applied based on the severity or directionality of the detected or inferred imprint, based on the operating conditions of the memory cell 205 at the time of imprint recovery, based on the operating mode of the memory die 200 or the memory device or host device associated with the memory die 200, or various combinations thereof.

[0089] Alternatively or concurrently, memory cell 205 can be restored by performing access operations (e.g., multiple read operations, multiple write operations, multiple read and write operations) on memory cell 205, said operations being customizable (e.g., modified) or specifically performed for imprint restoration (e.g., according to imprint restoration or maintenance modes). For example, an imprint repair operation may involve cycling the logical states on memory cell 205 by writing multiple opposite logical states to memory cell 205 (e.g., including the application of repetitive or alternating write bias). In some cases, memory cell 205 may be cycled a defined number of times during repair or maintenance operations, or may be repeatedly cycled over a defined amount of time. In some cases, the repair operation may involve performing multiple read operations on memory cell 205 (e.g., including the application of repetitive or alternating read bias), and read operations may be included as part of a loop (e.g., with or without corresponding write or rewrite operations). Alternatively or additionally, the refresh operation may be modified for specific purposes of trace recovery (e.g., by extending the refresh duration, by increasing the refresh bias amplitude), and in various instances, the refresh operation may or may not be performed during operating modes that support data exchange with the host device. In some instances, the read operation may be used to determine when the trace in memory cell 205 has diminished, or more generally, to characterize the severity of the trace. For example, the read operation may be used to compare the read logic state of memory cell 205 with a logic state that means a write has been made to memory cell 205 to determine whether they match, or whether the read signal associated with the read logic state is closer to a reference voltage than expected or desired.

[0090] In various instances, such biasing can be performed in maintenance or recovery modes of the memory die 200 that may or may not be associated with specific data access (e.g., requested or commanded by the host device). This can involve various signaling or data exchanges between the host device and the memory device containing the memory die 200, as well as other auxiliary memory devices that may support various data retention, redundancy, or integrity techniques. Such techniques can mitigate the effects of imprinting, for example, by returning memory cells 205 to behavior that is substantially normalized, leveled, or otherwise symmetrical relative to different logical states, and improve robustness against vulnerabilities that may be associated with imprinting.

[0091] Figure 3A and 3B Examples illustrating the nonlinear electrical properties of ferroelectric memory cells with hysteresis curves 300-a and 300-b, based on various examples disclosed herein. Hysteresis curves 300-a and 300-b can be further explained as shown in the references. Figure 2Examples of write and read processes for a memory cell 205 employing a ferroelectric capacitor 240 are described below. Hysteresis curves 300-a and 300-b depict the charge Q stored on the ferroelectric capacitor 240 as a function of the voltage difference V between the terminals of the ferroelectric capacitor 240. cap And change (for example, when based on voltage difference V) cap When charge is permitted to flow into or out of a ferroelectric capacitor. For example, a voltage difference V cap This can represent the voltage difference between the plate line side and the digital line side of capacitor 240 (e.g., the difference between the voltage at the plate node and the voltage at the bottom node, which can be referred to as V). plate -V bottom ,like Figure 2 (as explained in the text).

[0092] Ferroelectric materials are characterized by polarization, wherein the material can maintain a non-zero charge in the absence of an electric field. Examples of ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitor 240 described herein may comprise these or other ferroelectric materials. The polarization within the ferroelectric capacitor 240 results in a net charge on the surface of the ferroelectric material and attracts opposite charges through the terminals of the ferroelectric capacitor 240. Thus, charge can be stored at the interface between the ferroelectric material and the capacitor terminals. Because the polarization can be maintained for a relatively long time, or even indefinitely, in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to capacitors, for example, those without ferroelectric properties (e.g., capacitors used in some DRAM arrays). The use of ferroelectric materials reduces the need to perform refresh operations for some memory architectures, making the maintenance of the logic state of a FeRAM architecture associated with significantly lower power consumption compared to maintaining the logic state of a DRAM architecture.

[0093] Hysteresis curves 300-a and 300-b can be understood from the perspective of a single terminal of the ferroelectric capacitor 240. By way of example, if the ferroelectric material is negatively polarized, then positive charge accumulates at the relevant terminal of the ferroelectric capacitor 240. Similarly, if the ferroelectric material is positively polarized, then negative charge accumulates at the relevant terminal of the ferroelectric capacitor 240. Furthermore, it should be understood that the voltages in hysteresis curves 300-a and 300-b represent the voltage difference across the capacitor (e.g., the potential between the terminals of the ferroelectric capacitor 240) and are directional. For example, a positive voltage can be achieved by applying a positive voltage to the transparent terminal (e.g., the cell plate) and keeping the reference terminal (e.g., the cell bottom) grounded or virtually grounded (or approximately zero volts (0V)). In some instances, a negative voltage can be applied by keeping the transparent terminal (e.g., the cell plate) grounded and applying a positive voltage to the reference terminal (e.g., the cell bottom). In other words, a positive voltage can be applied to generate a negative voltage difference V across the ferroelectric capacitor 240. cap This causes the terminal in question to be negatively polarized. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to produce the voltage difference V shown in hysteresis curves 300-a and 300-b. cap .

[0094] As depicted in hysteresis curve 300-a, the ferroelectric material used in ferroelectric capacitor 240 can maintain positive or negative polarization when there is no net voltage difference between the terminals of ferroelectric capacitor 240. For example, hysteresis curve 300-a illustrates two possible polarization states: charge state 305-a and charge state 310-a, which can represent a negative saturation polarization state and a positive saturation polarization state, respectively. Charge states 305-a and 310-a can be in physical conditions describing the residual polarization (Pr) value, which can refer to the polarization or charge retained after the removal of an external bias (e.g., voltage). According to the example of hysteresis curve 300-a, charge state 305-a can represent logic 0 when no voltage difference is applied across ferroelectric capacitor 240, and charge state 310-a can represent logic 1 when no voltage difference is applied across ferroelectric capacitor 240. In some instances, the logic values ​​of the corresponding charge states or polarization states can be reversed or interpreted in the opposite manner to adapt to other schemes for operating memory cell 205.

[0095] By applying a net voltage difference across the ferroelectric capacitor 240, logic 0 or 1 can be written into a memory cell by controlling the polarization of the ferroelectric material and thus the charge on the capacitor terminals. For example, voltage 315 can be equal to or greater than the positive saturation voltage, and applying voltage 315 across the ferroelectric capacitor 240 causes charge accumulation until charge state 305-b is reached (e.g., writing logic 0). After removing voltage 315 from the ferroelectric capacitor 240 (e.g., applying zero net voltage across the terminals of the ferroelectric capacitor 240), the charge state of the ferroelectric capacitor 240 can follow path 320 as shown between charge state 305-b and charge state 305-a at zero voltage across the capacitor. In other words, charge state 305-a can represent a logic 0 state at the equilibrium voltage across the positively saturated ferroelectric capacitor 240.

[0096] Similarly, voltage 325 can be equal to or less than the negative saturation voltage, and applying voltage 325 across ferroelectric capacitor 240 can cause charge accumulation until charge state 310-b is reached (e.g., a logic 1 is written). After removing voltage 325 from ferroelectric capacitor 240 (e.g., applying zero net voltage to the terminals of ferroelectric capacitor 240), the charge state of ferroelectric capacitor 240 can follow path 330 as shown between charge state 310-b and charge state 310-a at zero voltage across the capacitor. In other words, charge state 310-a can represent a logic 1 state at the equilibrium voltage across the negatively saturated ferroelectric capacitor 240. In some instances, voltages 315 and 325, representing the saturation voltage, can have the same magnitude across ferroelectric capacitor 240 but opposite polarities.

[0097] To read or sense the stored state of the ferroelectric capacitor 240, a voltage can also be applied across the ferroelectric capacitor 240. In response to the applied voltage, the subsequent charge Q stored in the ferroelectric capacitor changes, and the extent of this change can depend on the initial polarization state, the applied voltage, the intrinsic or other capacitance on the access line, and other factors. In other words, the charge state or access line voltage resulting from the read operation can depend on whether the initially stored charge state 305-a, charge state 310-a, or some other charge state, and other factors.

[0098] Hysteresis curve 300-b illustrates an example of the access operation for reading stored charge states 305-a and 310-a. See reference... Figure 2 The described board line 220 and digital line 215 are subjected to a read voltage 335, for example, as a voltage difference. Hysteresis curve 300-b illustrates that the read voltage 335 is a positive voltage difference V. cap (For example, where V) plate -V bottomA positive read operation is performed across the ferroelectric capacitor 240. This positive read voltage can be referred to as a "plate-high" read operation, where plate line 220 is initially at a high voltage and digital line 215 is initially at a low voltage (e.g., ground). While read voltage 335 is shown as a negative voltage across the ferroelectric capacitor 240, in alternative operations, the read voltage can be a positive voltage across the ferroelectric capacitor 240, which can be referred to as a "plate-low" read operation.

[0099] When selecting memory cell 205 (e.g., via reference as shown in the reference), Figure 2 When the switch assembly 245 is activated via word line 210, a read voltage 335 can be applied across the ferroelectric capacitor 240. After the read voltage 335 is applied to the ferroelectric capacitor 240, charge can flow into or out of the ferroelectric capacitor 240 via the associated digital line 215 and board line 220, and in some instances, different charge states or access line voltages may be generated depending on whether the ferroelectric capacitor 240 is in charge state 305-a (e.g., logic 0), charge state 310-a (e.g., logic 1), or some other charge state.

[0100] When a read operation is performed on ferroelectric capacitor 240 in charge state 305-a (e.g., logic 0), additional positive charge can accumulate on ferroelectric capacitor 240, and the charge state can follow path 340 until the charge and voltage of charge state 305-c are reached. The amount of charge flowing through capacitor 240 can be associated with the intrinsic capacitance of digital line 215 or another access line (e.g., a signal line from digital line 215 opposite to an amplifier such as a charge transfer sensing amplifier) ​​or another capacitance (e.g., the intrinsic capacitance of digital line 215, the capacitance of a capacitor or capacitive element coupled to digital line 215, or a combination thereof). In a “board-height” read configuration, read operations associated with charge states 305-a and 305-c, or more generally with a logic 0 state, can be associated with a relatively small amount of charge transfer (e.g., compared to read operations associated with charge states 310-a and 310-c, or more generally, compared to reading a logic 1 state).

[0101] As shown by the transition between charge states 305-a and 305-c, the voltage change at capacitor 240 is relatively large for a given change in charge, so the resulting voltage 350 across ferroelectric capacitor 240 can be a relatively large positive value. Therefore, after reading logic 0 in the "board height" read operation, it equals the board line voltage V under charge state 310-c. PL and V cap (For example, V) plate -V bottomThe difference in digital line voltage can be a relatively low voltage. Such a read operation may not change the residual polarization of the ferroelectric capacitor 240 storing charge state 305-a; therefore, after performing the read operation, if the read voltage 335 is removed (e.g., by applying zero net voltage across the ferroelectric capacitor 240, by equalizing the voltage across the ferroelectric capacitor 240), the ferroelectric capacitor 240 can return to charge state 305-a via path 340. Therefore, performing a read operation with a positive read voltage across the ferroelectric capacitor 240 in charge state 305-a can be considered a non-destructive read process. In some cases, a rewrite operation may not be necessary or can be omitted in such situations.

[0102] When a read operation is performed on the ferroelectric capacitor 240 in charge state 310-a (e.g., logic 1), the stored charge may or may not be reversed in polarity because a net positive charge accumulates on the ferroelectric capacitor 240, and the charge state may follow path 360 until the charge and voltage of charge state 310-c are reached. The amount of charge flowing through the ferroelectric capacitor 240 may also be associated with the intrinsic capacitance of the digital line 215 or another capacitance. In a “board-height” read configuration, read operations associated with charge states 310-a and 310-c, or more generally, read operations associated with a logic 1 state, may be associated with a relatively large amount of charge transfer or a relatively small capacitor voltage V. cap Associated (e.g., compared to read operations associated with charge states 305-a and 305-c, or more generally, compared to read operations associated with a logic 1 state).

[0103] As illustrated by the transition between charge states 310-a and 310-c, in some cases, due to the relatively small voltage change at capacitor 240 for a given change in charge, the resulting voltage 355 can be a relatively small positive value. Therefore, after reading logic 1 in the "board height" read operation, the voltage 355 in charge state 310-c is equal to the board line voltage V. PL and V cap (For example, V) plate -V bottom The difference in digital line voltage can be a relatively high voltage.

[0104] The transition from charge state 310-a to charge state 310-d can be described as a sensing operation associated with the polarization or local reduction or reversal of charge in the ferroelectric capacitor 240 of the memory cell 205 (e.g., the magnitude of charge Q decreases from charge state 310-a to charge state 310-d). In other words, depending on the properties of the ferroelectric material, after a read operation, if the read voltage 335 is removed (e.g., by applying zero net voltage across the ferroelectric capacitor 240, by equalizing the voltage across the ferroelectric capacitor 240), the ferroelectric capacitor 240 may not return to charge state 310-a. Conversely, when zero net voltage is applied to the ferroelectric capacitor 240 after a read operation using charge state 310-a with read voltage 335, the charge state can follow path 365 from charge state 310-c to charge state 310-d, indicating a net reduction in polarization (e.g., a charge state with smaller positive polarization compared to the initial charge state 310-a, as described by the charge difference between charge state 310-a and charge state 310-d). Therefore, performing a read operation with charge state 310-a while having a positive read voltage on the ferroelectric capacitor 240 can be described as a destructive read process.

[0105] In some cases, a rewrite operation (e.g., applying voltage 325) can be performed after such a read operation, which can transition the memory cell from charge state 310-d to charge state 310-a (e.g., indirectly, such as via charge state 310-b). In various instances, such a rewrite operation can be performed after any read operation, or selectively based on certain conditions (e.g., when the read voltage and the write voltage associated with the detected logic state are opposite). However, in some sensing schemes, reduced residual polarization can still be read as the same stored logic state as a saturated residual polarization state (e.g., supporting the detection of logic 1 based on both charge state 310-a and charge state 310-d), thereby providing a degree of non-volatility to memory cell 205 relative to the read operation.

[0106] In other instances (e.g., when the ferroelectric material is able to maintain polarization in the presence of at least a certain level of depolarization field, or when the ferroelectric material has sufficient coercivity, not shown), after a read operation, the ferroelectric capacitor 240 can return to charge state 310-a with the read voltage removed, and performing such a read operation in charge state 310-a with a positive read voltage on the ferroelectric capacitor 240 can be described as a non-destructive read process. In these cases, a rewrite operation may not be necessary after such a read operation.

[0107] After a read operation is initiated, the positions of charge states 305-c and 310-c can depend on several factors, including the specific sensing scheme and circuitry. In some cases, the final charge can depend on the net capacitance of the digital line 215 coupled to memory cell 205, which may include intrinsic capacitance, integrating capacitors, etc. For example, if ferroelectric capacitor 240 is electrically coupled to digital line 215 at 0V and applies read voltage 335 to board line 220, then when memory cell 205 is selected, the voltage on digital line 215 can be attributed to the charge flowing from ferroelectric capacitor 240 to the net capacitance of digital line 215. Therefore, in some instances, the voltage measured at sensing component 250 may not be equal to read voltage 335, or the resulting voltage 350 or 355, but may instead depend on the voltage on digital line 215 after the charge sharing period.

[0108] After a read operation is initiated, the positions of charge states 305-c and 310-c on the hysteresis curve 300-b may depend on the net capacitance of digital line 215 and can be determined through load line analysis. In other words, charge states 305-c and 310-c may be defined relative to the net capacitance of digital line 215 or another access line (e.g., a signal line from digital line 215 opposite to the charge transfer sensing amplifier). Therefore, the voltage of ferroelectric capacitor 240 after a read operation (e.g., voltage 350 when reading ferroelectric capacitor 240 storing charge state 305-a, and voltage 355 when reading ferroelectric capacitor 240 storing charge state 310-a) may be different and may depend on the initial state of ferroelectric capacitor 240. In some instances, the amount of polarization change of ferroelectric capacitor 240 of memory cell 205 caused by a sensing operation may be selected according to a specific sensing scheme. In some instances, sensing operations with a larger polarization change of the ferroelectric capacitor 240 of memory cell 205 when detecting the logic state of memory cell 205 can be associated with relatively greater robustness (e.g., a wider sensing margin).

[0109] The voltage of the digital line 215 or signal line (where applicable) generated by the read operation can be compared with a reference voltage (e.g., via a reference). Figure 2The initial state (e.g., charge state, logic state) of the ferroelectric capacitor 240 is determined by comparing the reference line 255 described. In some instances, the digital line voltage may be the difference between the read voltage 335 and the final voltage across the capacitor 240 (e.g., (read voltage 335 - voltage 350) when reading the ferroelectric capacitor 240 with stored charge state 305-a, or (read voltage 335 - voltage 355) when reading the ferroelectric capacitor 240 with stored charge state 310-a). In some instances, the digital line voltage may be the sum of the plate line voltage and the final voltage across the ferroelectric capacitor 240 (e.g., voltage 350 when reading the ferroelectric capacitor 240 with stored charge state 305-a, or voltage 355 when reading the ferroelectric capacitor 240 with stored charge state 310-a).

[0110] In some instances, a read operation of memory cell 205 may be associated with a fixed voltage of digital line 215, wherein the charge state of ferroelectric capacitor 240 may be the same after the read operation is initiated, regardless of its initial charge state. For example, in a read operation in which digital line 215 and board line 220 are held at a fixed relative voltage supporting read voltage 335, ferroelectric capacitor 240 may transition to charge state 370 for both cases where the ferroelectric capacitor initially stores charge state 305-a and cases where the ferroelectric capacitor initially stores charge state 310-a. Therefore, instead of using the voltage difference of digital line 215 to detect the initial charge state or logic state, in some instances, the initial charge state or logic state of ferroelectric capacitor 240 may be determined at least in part based on the charge difference associated with the read operation. For example, as illustrated by hysteresis curve 300-b, logic 1 can be detected based on the difference in charge Q between charge state 305-a and charge state 370 (e.g., a relatively large amount of charge transfer), and logic 0 can be detected based on the difference in charge Q between charge state 310-a and charge state 370 (e.g., a relatively small amount of charge transfer).

[0111] In some instances, such detection may be supported by a charge-transfer sensing amplifier, a cascode (e.g., a transistor configured in a cascode arrangement), or another signal generation circuitry between digital line 215 and a signal line coupled to the sensing amplifier, wherein the voltage of the signal line may be based at least in part on the amount of charge transferred to capacitor 240 after a read operation is initiated (e.g., where the described charge transfer may correspond to the amount of charge transferred through the charge-transfer sensing amplifier, cascode, or another signal generation circuitry). In such instances, the voltage of the signal line may be compared to a reference voltage (e.g., at sensing component 250) to determine the initial logic state stored in ferroelectric capacitor 240, even if digital line 215 remains at a fixed voltage level.

[0112] In some instances where digital line 215 remains at a fixed read voltage 335, capacitor 240 may be positively saturated after a read operation, regardless of whether capacitor 240 was initially in charge state 305-a (e.g., logic 0) or initially in charge state 310-a (e.g., logic 1). Accordingly, after such a read operation, capacitor 240 may be charged at least temporarily according to the logic 0 state, regardless of its initial or predetermined logic state. Therefore, a rewrite operation may be required at least when capacitor 240 is intended to store the logic 1 state, where such a rewrite operation may involve applying a write voltage 325 to store the logic 1 state, as described with reference to hysteresis curve 300-a. Such a rewrite operation may be configured or otherwise described as a selective rewrite operation, since a rewrite voltage may not be required when capacitor 240 is intended to store the logic 0 state. In some instances, this type of access scheme may be referred to as a "2Pr" scheme, where the charge difference used to distinguish logic 0 from logic 1 may be equal to twice the residual polarization of memory cell 205 (e.g., the charge difference between charge state 305-a (positive saturated charge state) and charge state 310-a (negative saturated charge state)).

[0113] In some sensing schemes, a reference voltage can be generated such that it falls between possible voltages (e.g., those of digital line 215, signal lines) that can be generated by reading different logic states. For example, when reading logic 1, the reference voltage can be selected to be lower than the voltage obtained on digital line 215 or the signal line, and when reading logic 0, the reference voltage can be selected to be higher than the voltage obtained on digital line 215 or the signal line, and vice versa, depending on the general usage. In other instances, comparisons can be made at portions of sensing component 250 or associated sensing amplifier that are different from the portions coupled to digital line 215 or the signal line, and thus when reading logic 1, the reference voltage can be selected to be lower than the voltage obtained at the comparison portion of sensing component 250 or associated sensing amplifier, and when reading logic 0, the reference voltage can be selected to be higher than the voltage obtained at the comparison portion of sensing component 250 or sensing amplifier. During the comparison at sensing component 250 or sensing amplifier, the sensed voltage can be determined to be higher or lower than the reference voltage, and thus the stored logic state (e.g., logic 0, logic 1) of memory cell 205 can be determined.

[0114] During sensing operations, the signals generated from reading each memory cell 205 can vary with manufacturing, operational, or other changes between the memory cells 205. For example, the capacitors 240 of each memory cell 205 may have different levels of capacitance, saturation, polarization, or coercivity, such that logic 0 can be associated with different charge levels of different memory cells 205, and logic 1 can be associated with different charge levels of different memory cells 205. Furthermore, intrinsic or other capacitance may be different for different digital lines 215 or for different signal lines in the memory device 110, and may also vary within the digital line 215 from the perspective of different memory cells 205 on the same digital line 215. Therefore, for these and other reasons, reading logic 0 can be associated with different voltage levels of the digital line 215 or signal line of different memory cells 205 (e.g., the resulting voltage 350 may be different for different memory cells 205), and reading logic 1 can be associated with different voltage levels of different memory cells 205 (e.g., the resulting voltage 355 may be different for different memory cells 205).

[0115] In some instances, a default reference voltage may be provided between the statistically averaged voltage associated with read logic 0 and the statistically averaged voltage associated with read logic 1, but the reference voltage may be relatively closer to the voltage generated by reading one of the logic states of any given memory cell 205. The minimum difference between the voltage generated by reading a particular logic state (e.g., a statistical value for reading multiple memory cells 205 of the memory device) and the associated default reference voltage level may be referred to as the “minimum read voltage difference” or “read margin”, and having a lower minimum read voltage difference or read margin may be associated with the difficulty or sensitivity of reliably sensing the logic state of the memory cells 205 in a given memory device 110 or memory die 200.

[0116] Examples of hysteresis curves 300-a and 300-b illustrate the equalization or normalization behavior of a memory cell 205 containing ferroelectric capacitor 240 when subjected to write or read pulses. However, based on various operating or environmental conditions, the ferroelectric capacitor 240 can be imprinted with specific logic states. Imprinting can refer to various conditions in which the ferroelectric capacitor 240 tends to store one logic state rather than another, is not easily written to different logic states (e.g., a logic state different from the logic state stored before the write operation), or both. For example, compared to hysteresis curves 300-a and 300-b, an imprinted ferroelectric capacitor 240 can be associated with higher coercivity (e.g., relative to a changed or reversed polarization state), reduced saturation polarization, shallower polarization slope, or other characteristics that may be asymmetrical relative to different logic states. Memory arrays with imprinted ferroelectric capacitors 240 can be associated with read errors, write errors, or other behaviors that could damage the memory device or the system containing the memory device. Based on the examples disclosed herein, the imprinted ferroelectric capacitor 240 can be restored using various imprint restoration or repair processes (e.g., imprint removal, detachment, repair, normalization, equalization).

[0117] Figure 4A and 4B Examples of nonlinear electrical characteristics of imprinted ferroelectric memory cells with hysteresis curves 400-a and 400-b, according to various examples disclosed herein, are described. Hysteresis curves 400-a and 400-b illustrate examples of characteristics of ferroelectric capacitor 240 that can be shifted due to imprinting of a logic state or charge state (e.g., imprinting of logic 1, imprinting of charge state 310-a), which may be related to a change in the configuration of the electrostatic domain in ferroelectric memory cell 205. For example, the shift characteristics of hysteresis curves 400-a and 400-b illustrated by imprinted hysteresis curve 440 may be due to the ferroelectric capacitor 240 having maintained a certain charge state for a relatively long time or under relatively high temperature conditions or both (e.g., under static baking conditions).

[0118] Figure 4A Examples illustrating the shift from the imprinted hysteresis curve 430-a to the imprinted hysteresis curve 440-a can correspond to the coercive magnetic shift of the ferroelectric capacitor 240. In some instances, the coercive magnetic shift to the imprinted hysteresis curve 440-a can be associated with increased resistance to changes in polarization during write operations, such as increased resistance to changes in the polarization state of a domain (e.g., where a domain is capable of reversing its polarization, but where such reversals generally require a relatively high voltage bias).

[0119] For example, according to hysteresis curve 400-a, when a voltage 315 is applied to the imprinted ferroelectric capacitor 240 in charge storage state 310-a (e.g., the write bias associated with writing logic 0, as referenced...), Figure 3A As described, charge can accumulate until charge state 405-a is reached. However, compared to charge state 305-b, which corresponds to the saturation condition of an equalized or normalized ferroelectric capacitor 240 in which the polarization of the ferroelectric capacitor is completely reversed, charge state 405-a may not correspond to a saturation condition, but may instead illustrate an instance of local polarization reversal in response to a write voltage 315. After removing voltage 315 from ferroelectric capacitor 240 (e.g., applying zero net voltage to the terminals of ferroelectric capacitor 240), the charge state of ferroelectric capacitor 240 may follow path 420-a shown between charge state 405-a and charge state 405-b at zero voltage across the capacitor.

[0120] In various instances, charge state 405-b may have a lower charge than charge state 305-a (e.g., the charge state of the de-marked memory cell 205 corresponds to logic 0). While the illustrative example of hysteresis curve 400-a illustrates charge state 405-b as having a net charge Q that is positive under various conditions (e.g., various marks severity, various coercive magnetic shifts, various polarization reversals in a set of domains of memory cell 205 or ferroelectric capacitor 240), the net charge of charge state 405-b may have a positive or negative value. Thus, in various cases, such charge states may indicate the storage of logic 0 or logic 1, or they may indicate a charge state that can be read by the memory device as storing logic 0 or logic 1. In other words, due to the shift from the imprinted hysteresis curve 430-a to the imprinted hysteresis curve 440-a, applying voltage 315 to the imprinted memory cell may or may not successfully write the ferroelectric capacitor imprinted with logic 1 to logic 0, or may not support the ferroelectric capacitor being successfully read as logic 0.

[0121] Figure 4BExamples illustrating the shift from the imprinted hysteresis curve 430-b to the imprinted hysteresis curve 440-b can illustrate a shift or drop in the saturation polarization or polarization capacitance of the ferroelectric capacitor 240. In some instances, the shift or drop to the imprinted hysteresis curve 440-a may be associated with some domains in the ferroelectric capacitor being unable to reverse their polarization during a write operation (e.g., some domains are frozen or trapped in a certain polarization state). In some instances, the coercivity of the domains capable of reversing their polarization may be substantially the same or similar to that of the domains in the imprinted state, but the capacitance for polarization reversal (e.g., under saturation voltage or applied bias) may be reduced. In other instances, such imprinting may also be accompanied by aspects of the shift in the coercivity of those domains capable of reversing their polarization (e.g., as referenced). Figure 4A (As described).

[0122] For example, according to hysteresis curve 400-b, when a voltage 315 is applied to a stored charge state 310-a of the imprinted ferroelectric capacitor 240 (e.g., a write bias associated with writing logic 0, as described with reference to FIG3), charge can accumulate until charge state 405-c is reached. However, compared to charge state 305-b, which may correspond to the saturation condition of the de-imprinted (e.g., equalized or normalized) ferroelectric capacitor 240 in which the polarization of the ferroelectric capacitor is completely reversed, charge state 405-c may correspond to an effective saturation condition of the ferroelectric capacitor with reduced capacitance for polarization reversal or unable to support polarization reversal in response to write voltage 315. After removing voltage 315 from the ferroelectric capacitor 240 (e.g., applying zero net voltage to the terminals of the ferroelectric capacitor 240), the charge state of the ferroelectric capacitor 240 may follow the path 420-b shown between charge state 405-c and charge state 405-d at zero voltage across the capacitor.

[0123] In various instances, charge state 405-d may have a lower charge than charge state 305-a (e.g., the charge state of the de-imprinted memory cell 205 corresponds to logic 0). While the illustrative example of hysteresis curve 400-b illustrates charge state 405-b as having a negative net charge Q under various conditions (e.g., various imprinting severity, various polarization immobility degrees in a set of domains of memory cell 205 or ferroelectric capacitor 240), the net charge of charge state 405-d may have a positive or negative value. Thus, in various cases, such charge states may indicate the storage of logic 0 or logic 1, or they may indicate a charge state that can be read by the memory device as storing logic 0 or logic 1. In other words, due to the shift from the de-imprinted hysteresis curve 430-b to the imprinted hysteresis curve 440-b, applying voltage 315 to the imprinted memory cell may or may not successfully write the ferroelectric capacitor imprinted with logic 1 to logic 0, or may not support the successful reading of the ferroelectric capacitor as logic 0.

[0124] While hysteresis curves 400-a and 400-b illustrate simplified examples of mechanisms that can be associated with imprinting in the ferroelectric capacitor 240, other mechanisms or conditions, or combinations thereof, can be associated with memory cell imprinting. For example, a memory cell imprinted with logic 1 can be associated with a reference... Figure 3A , 3B The charge state 310-a described in 4A and 4B may or may not be associated with it, and may have different charge states after imprinting (e.g., due to charge degradation during imprinting, due to a sudden drop in saturation polarization of the logic state or charge state during imprinting itself, due to charge leakage, due to changes or reductions in saturation polarization of charge state 310-a that may be altered when rewritten with a logic 1 state). In another instance, the imprint may alter (e.g., broaden) the distribution of polarization reversal voltage over a set of domains in the ferroelectric capacitor 240, which may be associated with (e.g., a shallower slope of Q between different polarization states compared to V) in the polarization reversal region. cap This may or may not be accompanied by coercive magnetic shift or polarization reversal capacity changes (e.g., as referenced). Figure 4A and 4B (As described). In some instances, the imprinting in the ferroelectric capacitor 240 may be associated with other phenomena or various combinations of these and other phenomena.

[0125] In some cases, the imprint of the ferroelectric memory cell 205 (e.g., as by...) Figure 4A or Figure 4B(Or otherwise illustrated) Local electrostatic interactions in memory cell 205, which is in a write state, can be driven by a blocking domain (e.g., a charge domain). For example, when an appropriate write bias is applied, imprinted memory cell 205 can change its charge state or polarization state. However, when the write bias is removed, memory cell 205 can return to the imprinted charge state or polarization state, which may be referred to as inversion switching, de-switching, or bounce-back. Therefore, it may be necessary to perform imprint recovery operations (e.g., in repair mode, in maintenance mode, in recovery mode) to normalize or equalize the memory cells in the memory device, thereby addressing or mitigating these effects (e.g., returning the charge mobility of memory cell 205 to a normalized or equalized state, returning to the hysteresis curve 430 after imprint removal, restoring residual polarization capacity, normalizing or equalizing coercivity).

[0126] In some instances, imprint recovery can be supported by placing the memory cell 205 in an opposite state (e.g., opposite to the imprinted state) for a duration long enough to alter the local electrostatic configuration that restores the memory cell to the imprinted state. For example, applying bias time and charge state switching (e.g., bias switching, charge switching, polarization switching) can aid recovery.

[0127] Regarding bias time, moving charged defects can alter the configuration within memory cell 205 in accordance with the applied bias, which can also be aligned with the desired polarization state. In some instances, this process may be scaled with the total cumulative bias time. However, bias time is only beneficial when the internal electric field aligns with the applied electric field. For example, a large accumulation of localized charge within memory cell 205 may shield the applied field and prevent localized reconfiguration of defects in some portions of memory cell 205. While unipolar (e.g., non-switching, non-cyclic) bias can be used to support imprint recovery and has certain advantages, cyclic methods may be more efficient in some instances.

[0128] Regarding charge state switching, in some instances, the bias applied by repeated switching can provide repeated opportunities for domains within memory cell 205 to experience random switching events. For example, for domains that may or may not experience polarization switching events at a given voltage or bias, based on a probability distribution, repeated charge switching can provide these domains with more opportunities to switch polarization, thereby increasing the probability that such a switch will actually occur. In some instances, state or bias switching can also increase the internal temperature of memory cell 205, which can further enhance defect or domain mobility. Therefore, both the increase in temperature and the repeated opportunities for repolarization can help with the imprint recovery of memory cell 205.

[0129] Such a mechanism can facilitate a phenomenon known as “wake-up” or “recovery” from the processed (time zero, initial, start) imprinted state of memory cell 205. This mechanism also facilitates recovery from fatigue, which may be related to charge domains that are symmetrically uninvolved in the polarization switching process (e.g., uninvolved whether switching from logic 0 to logic 1 or vice versa). In some instances, fatigue recovery can be driven by “wake-up” of domains within cells that were previously uninvolved in polarization switching. Because fatigue can be defined as the loss of polarization signal due to repeated switching of polarization states, recovery from fatigue can depend on variations in the applied bias voltage (e.g., higher bias voltage or longer pulses compared to typical or initial operating conditions).

[0130] While some aspects of memory cell imprinting are described with reference to ferroelectric memory applications, imprinting management according to this disclosure can also be applied to other memory technologies that experience drift or other shifts in characteristics that may be asymmetrical with respect to different logic states. For example, material memory elements, such as phase-change, resistive, or limit memories, may experience material separation or fixation due to memory cell imprinting (e.g., due to storing a logic state for a duration, or due to storing a logic state at a high temperature), where such effects may be associated with storing or reading a particular logic state rather than another (e.g., asymmetrically associated with it, or drifting toward it). In some instances, in such applications, the imprinted memory cell 205 may be associated with increased resistance to changes from one configurable material property or characteristic to another, which may correspond to phenomena such as relatively large resistance to changes from one threshold voltage to another, relatively large resistance to changes from one resistance to another, and other characteristics.

[0131] In various instances, imprint recovery operations, which may include cycles of signal or pulse loops, bias times, or access operations, can normalize or equalize the characteristics of material memory elements, such as normalizing or equalizing material distribution, moving defects to one end or the other, distributing defects more uniformly within a cell, or moving material memory elements for atomic reconfiguration. For example, in some phase-change memory applications, imprint recovery may selectively apply aspects of the seasoning step according to various techniques used for imprint management described herein.

[0132] Figure 5 This document describes an example of a system 500 that supports imprint management for memory systems, based on the examples disclosed herein. System 500 may include references... Figure 1The system 500 may include one or more components as described in section 4. For example, system 500 may include host device 510 and memory device 540. In some instances, system 500 may also include one or more auxiliary memory devices 590, which in various instances may include memory devices having the same or similar functionality as memory device 540, or may be memory devices with different configurations or characteristics. For example, auxiliary memory device 590 may include memory devices configured to provide additional storage capacity to host device 510, redundant memory devices for redundant or backup information storage, memory devices with different access speeds or non-volatility, memory devices with different storage architectures, memory devices arranged or configured for different roles in the memory hierarchy, and so on.

[0133] In some cases, one or more memory cells of the memory array 555 (e.g., reference) Figure 2 The described memory cell 205 may be imprinted, or may be susceptible to imprinting. Imprinting can refer to various conditions where one memory cell tends to store one logical state rather than another, is not easily written to with a different logical state (e.g., a logical state different from the logical state stored before the write operation), or both. In some instances, imprinting itself may degrade or destroy the logical state stored at the memory cell, but such effects may not directly cause problems with the operation of system 500. For example, imprinting may occur when system 500 is powered off or inactive, but system 500 may not be configured to rely on memory device 540 for non-volatile data storage. However, after power is supplied or system 500 is started, for example, host device 510 may attempt to write data to memory device 540 (e.g., transfer data from a non-volatile storage device, such as non-volatile secondary storage device 590, such as a hard disk drive or flash memory device, as part of a boot operation, as part of a BIOS-level operation, as part of loading the operating system, or before loading the operating system), and such write operations may fail due to the imprinted state of memory array 555. In other words, in some instances or configurations, the basic operations (e.g., writing and reading) that are taking place in the imprinted memory cell may be more problematic than the loss of information associated with the imprint itself.

[0134] According to various examples of the described techniques, components of system 500 can be configured to perform various operations to detect, infer, mitigate, disable, or recover from such imprints, which can improve the robustness, accuracy, or efficiency of the memory device 540, host device 510, or the entire system 500 in the presence of conditions associated with memory cell imprints. For example, memory device 540, host device 510, or both can perform various operations to detect the presence of imprints in memory array 555 or infer the likelihood of such imprints, and memory device 540 can be configured accordingly to perform various operations on memory array 555 in response to such detection or inference. Imprint recovery procedures, such as those described herein, can include various memory cell biasing or access techniques specifically initiated or modified to accelerate the equalization or normalization of imprinted memory cells that may exhibit asymmetric characteristics relative to different logic states. In some cases, the described techniques may also take into account various aspects of data retention or operational integrity, including various signaling, data transfer, or operational management between the host device 510, the memory device 540, and any auxiliary memory device 590.

[0135] The described imprint management techniques may employ various distributions for detection, computation, evaluation, and operation between memory device 540 and host device. In some instances, memory device 540 may include chip-level or transistor-level circuitry configured to support various imprint management techniques (e.g., local memory controller 265, device memory controller 155, local memory controller 165). Alternatively or additionally, memory device 540 may include an onboard processor or integrated processor (e.g., a processor with integrated RAM, a processor with an integrated RAM controller) coupled to an associated memory die and configured or programmed to support various imprint management techniques. Alternatively or additionally, host device 510 may include a processor, controller, or another circuitry configured or programmed to support various imprint management techniques, which may contain various signaling to or from memory device 540 or any auxiliary memory device 590.

[0136] In some instances, one or more components of system 500 may be configured to characterize imprint severity (e.g., magnitude, degree) or directionality (e.g., whether the imprint is more correlated with one logical state than with another, or whether it is more sensitive to one logical state than another, or whether the imprint is asymmetrical) and perform imprint recovery operations adjusted or selected based on the characterized severity or direction. Alternatively, the imprint recovery operation may be customized by system 500 for specific operating conditions of memory device 540, host device 510, or the entire system 500, such as operating modes or environmental conditions, which in some instances may be at least partially based on signaling or operational negotiation between memory device 540 and host device 510. Alternatively, the imprint recovery operation may be based on various operating modes, permissions, approvals, or prohibitions, which may be at least partially based on signaling or operational negotiation between memory device 540 and host device 510.

[0137] The host device 510 can be a host device or a reference device. Figure 1 Examples of the described external memory controller 105, or any combination thereof. The host device may include a host device interface 515, a host device controller 520, and an imprint manager 525. Although the host device interface 515, host device controller 520, and imprint manager 525 are described as independent components, one or more of the described components, or portions thereof, may be collectively or generally described as components, controllers, processors, or circuit systems configured to perform the various techniques described herein.

[0138] Host device interface 515 can be used as a reference. Figure 1 The instances of one or more channels 115 described may also be associated with them in other ways. For example, host device interface 515 may include a transceiver that supports bidirectional signaling or communication (e.g., commands, status indications, data, and other information) with memory device 540 (e.g., with memory interface 545). In some instances, host device interface 515 may also power memory device 540 (e.g., from a battery of host device 510, from a power supply of host device 510, or from a power supply connected to host device 510).

[0139] The host device controller 520 may be a processing element in the host device 510 that exchanges information (e.g., application data, user data) with the memory device 540. For example, the host device controller 520 may issue a read command and receive data from the memory device 540 in response to the read command, or the host device controller 520 may issue a write command to the memory device 540 accompanied by write data provided to the memory device 540 or otherwise associated with said write data. The host device controller 520 may also control various other aspects of the operation of the host device 510. For example, the host device controller 520 may manage various operating modes or configurations of the host device 510, control various information or signaling between the host device 510 and the memory device 540, or control various operations of the host device 510 in response to signaling from the memory device 540.

[0140] The imprint manager 525 can be configured to perform various operations related to imprint detection or imprint recovery as described herein, or to control or modify other operations of the host device 510 that are otherwise related to imprint management of the memory device 540. In some instances, this approach can support task offloading of imprint management from the memory device 540 to the host device 510, which can support relatively streamlined memory architectures (e.g., with relatively limited onboard processing power or performance), enabling the support of relatively complex technologies by enhancing the capabilities of the host device 510, and other benefits.

[0141] In some instances, the imprint manager 525 may detect various conditions that may be associated with the potential imprinting of the memory array 555 (e.g., temperature, time, host device 510 malfunction, access patterns that may unintentionally or maliciously generate imprints, blue screen events). In response to such detection, the imprint manager 525 may issue a command to the memory device 540 to execute an imprint detection procedure (e.g., to allow the memory device 540 to directly assess whether the memory array 555 has been imprinted), or issue a command to the memory device 540 to execute an imprint recovery procedure (e.g., regardless of whether the memory device 540 has detected an imprint). In some instances, such commands may be accompanied by information for triggering such commands, an indication of the severity of the detected conditions, indications that the memory device 540 may use to identify or select conditions for an imprint recovery procedure, or indications of how imprint recovery should be actively performed. In some instances, the imprint manager 525 may support the selection of an imprint recovery method based on system status, user requirements, or other parameters, and may instruct the memory device 540 to make such a selection, or may provide information to the memory device 540 so that the memory device 540 can make such a selection.

[0142] In some instances, the imprint manager 525 may authorize or approve the memory device 540 to enter a recovery mode, during which ongoing data operations (e.g., read operations, write operations, data exchange between the host device 510 and the memory device 540) may or may not be supported. In some instances, the imprint manager 525 may receive an indication that the memory device 540 is performing a recovery operation and may suspend access to the memory device 540 or perform access to the memory device 540 in a slower rate or otherwise degraded or less performant mode. In some instances, the imprint manager 525 may refuse a request from the memory device 540 to perform an imprint detection or recovery operation, or may block or disallow such operations (e.g., when the host device 510 is operating in a mode requiring certain performance from the memory device 540, or when the memory device 540 could perform such operations by default but the host device 510 believes such operations can be disabled).

[0143] In some instances, imprint manager 525 may receive an indication from memory device 540 that memory array 555 is imprinted or may be imprinted, and imprint manager 525 may issue or initiate (e.g., via host device controller 520) a mode specifically configured to mitigate the imprinting of memory array 555. For example, in response to such an indication of detected or inferred imprinting of the memory array, imprint manager 525 may issue read, write, or refresh commands associated with a pattern of logical state, such as a cyclic or alternating write operation between a solid pattern of logical states or other patterns of logical states (e.g., according to alternating logical states, according to alternating checkerboard patterns, according to a reversed write-back operation).

[0144] The system may also include a memory device 540, which may be a reference. Figure 1 and 2 Examples of memory device 110, memory die 160, or memory die 200 described herein. Memory device 540 may include memory interface 545, memory controller 550, one or more memory arrays 555 (e.g., memory array 555-a and memory array 555-b), imprint detection component 560, imprint recovery component 565, and error correction code (ECC) component 570. Although memory interface 545, memory controller, imprint detection component 560, imprint recovery component 565, and ECC component 570 are described as independent components, one or more of the described components or portions thereof may be collectively or generally described as components, controllers, processors, or circuit systems configured to perform the various techniques described herein.

[0145] Memory interface 545 may be a reference Figure 1Examples of one or more channels 115 described or otherwise associated therewith. For example, memory interface 545 may include a transceiver that supports bidirectional signaling or communication (e.g., commands, status indications, data, and other information) with host device 510 (e.g., host device interface 515). In some instances, memory interface 545 may also receive power from host device 510.

[0146] The memory controller 550 may be a processing element within the memory device 540 that exchanges information (e.g., application data, user data) with the host device 510. For example, the memory controller 550 may receive a read command and, in response to the read command, transmit responsive data to the host device 510; or the memory controller 550 may receive a write command from the host device 510 accompanied by write data provided from or otherwise associated with the host device 510. The memory controller 550 may also control various other aspects of the operation of the memory device 540. For example, the memory controller 550 may manage various operating modes or configurations of the memory device 540, control various information or signaling between the memory device 540 and the host device 510, or control various operations of the memory device 540 in response to signaling from the host device 510.

[0147] In some instances, memory controller 550 may receive, process, and execute commands from memory interface 545 (e.g., through interaction with memory array 555 or other aspects of memory device 540). Memory controller 550 may be configured in various ways and may be an example of or otherwise include or refer to the functionality of device memory controller 155, local memory controller 165, local memory controller 265, or combinations thereof. In some instances, memory controller 550 may include hardware or circuitry (e.g., transistor-level circuitry) configured for combinational logic using various techniques, or may be a separate processing component or chip within memory device 540 that interfaces with memory array 555.

[0148] Memory array 555 can be a reference Figure 1 and 2 An example of the described memory array 170. In some instances, the memory array 555 may include an array 205 of memory cells comprising ferroelectric capacitors as corresponding memory storage elements. However, the described imprint management technique can be implemented using other types of memory arrays 555, such as memory arrays with material memory elements that store logic states based on variable and configurable material properties.

[0149] The imprint detection component 560 can be configured to perform various operations to detect or predict the presence of memory cell imprints in the memory array 555. In some instances, the imprint detection component 560 can operate independently of or in the absence of the imprint manager 525 to support various imprint detection techniques within the memory device 540. For example, the imprint detection component 560 can operate autonomously without coordinating imprint detection techniques with the host device 510 (e.g., using on-die or other integrated circuit systems or the processing capabilities of the memory device 540). In some instances, this approach can benefit imprint detection techniques that benefit from a deeper understanding of chip-level conditions or other relatively direct understanding of operating conditions (e.g., without needing to express such understanding to the host device), and can support the memory device 540 being agnostic to different host devices of different types or capabilities. In other instances, the imprint detection component 560 can operate based on signaling exchanged with the imprint manager 525 in a coordinated imprint management system, which can support imprint management coordination between the host device 510 and the memory device. In some instances, this approach can support the offloading of tasks from memory device 540 to host device 510 in the management of imprints, which can support relatively streamlined memory architectures (e.g., with relatively limited onboard processing power or performance), enabling the support of relatively complex technologies by enhancing the capabilities of host device 510, as well as other benefits.

[0150] The imprint detection component 560 can support various detections that enable the selective or tailored application of imprint recovery techniques. For example, while certain aspects of imprint recovery may generally benefit the memory device, performing the recovery procedure may require a certain amount of time or other system resources, which could affect the performance or operation of the memory device 540 or the host device 510. In some instances, imprint recovery techniques can have detrimental effects, such as accelerated fatigue or other wear mechanisms, which need to be balanced with the presence or sensitivity of the imprint. Therefore, for these and other reasons, the recovery procedure can be selectively performed based on the preferred presence of a detected or inferred imprint, or the recovery procedure can be selectively blocked based on the absence of a detected or inferred imprint. Thus, the imprint detection component 560 can be configured to support determining when to perform the recovery procedure, which can provide efficiency and reliability benefits, as well as other benefits that can be understood by those skilled in the art.

[0151] In some instances, the imprint detection component 560 may execute or manage (e.g., cause the memory device 540 to execute, cause the imprint detection component 560 to execute) one or more imprint detection procedures to determine whether the memory array 555 and / or the memory cells of the memory array 555 are operating within one or more specifications (e.g., whether a recovery operation is being performed). In some cases, the imprint detection component 560 may determine that the memory array 555 is operating within one or more specifications and send an indication to another component of the memory device 540 or to the host device 510 that the memory device 540 is operating appropriately. In other cases, the imprint detection component 560 may determine that the memory array 555 is not or may not be operating within one or more specifications (e.g., an imprint has occurred, an imprint has been detected, an imprint has been predicted), and may initiate a recovery procedure. The imprint detection component 560 may execute the imprint detection procedure (e.g., autonomously, or in response to a command from the host device 510) on a scheduled (e.g., periodic) or event-driven basis (e.g., in response to the detection of one or more triggering events).

[0152] In some instances, the imprint detection component 560 may detect various conditions that may be associated with the imprinting of the memory array 555 (e.g., temperature, time, memory device 540 malfunction, access patterns that may unintentionally or maliciously generate imprints). In response to such detection, the imprint detection component 560 may issue a command to the imprint recovery component 565 to initiate a recovery operation, or may trigger other (e.g., more specific, more complex) aspects of the imprint detection performed by the imprint detection component. In some instances, such a command or trigger may be accompanied by information for initiating or adjusting the operation, an indication of the severity of the conditions detected, an indication of the conditions available to the imprint recovery component 565 for selecting an imprint recovery procedure, or an indication of how aggressively imprint recovery should be performed. In some instances, the imprint detection component 560 may (e.g., to the imprint recovery component 565, to the memory controller 550) instruct one or more segments of the memory array 555 to perform an imprint detection procedure.

[0153] In some instances, the imprint detection component 560 may enable the imprint recovery component 565 to select an imprint recovery method based on system status, user needs, or other parameters. For example, it may provide information to the imprint recovery component 565, allowing it to make such a selection. In some instances, the imprint detection component 560 may provide such information to the imprint manager 525, enabling the imprint manager 525 to make such a selection.

[0154] In some instances, the imprint detection component 560 may signal the presence or prediction of an imprint in the memory array 555 to the host device 510, which may indicate or otherwise be interpreted as a request for the host device 510 to initiate a recovery operation, a request for the host device 510 to approve a recovery operation (e.g., signaling to approve the imprint recovery component 565 to continue imprint recovery), an indication that the memory device 540 will perform or is performing a recovery operation, an indication that the memory device 540 may or will be temporarily unavailable for access operations or may have reduced speed or performance for access operations, and other interpretations.

[0155] In some cases, the imprint detection component 560 may autonomously (e.g., unilaterally, without explicit commands from the host device 510) determine to execute an imprint detection procedure, which may be associated with the memory device 540 proactively or preemptively performing detection or recovery operations (e.g., in a set of operations transparent to the host device 510). In some instances, the imprint detection component 560 may determine to execute an imprint detection procedure in response to a command received from the host device 510 (e.g., from the imprint manager 525). In some cases, the command may be received by the memory device 540 as part of an activation procedure (e.g., as part of startup or initialization signaling).

[0156] In some instances, the imprint detection component 560 may perform detection operations as part of a startup process (e.g., as part of a power-on self-test (POST)), initialization of the memory device 540 (e.g., the first power-on of the memory device 540), or other operating conditions. In some instances, the imprint detection component 560 may perform such operations before data is loaded into the memory array 555 (e.g., before the operating system is loaded), which may include disabling or caching access commands from the host device 510. In some instances, the imprint detection component 560 may perform detection operations while data is stored in the memory array 555, and the imprint detection component 560 may support various coordinations with the host device 510 or other components of the memory device 540 to support the various data retention, redundancy, or integrity techniques described herein.

[0157] The imprint detection component 560 can support various techniques for determining the presence or likelihood of imprints in the memory array 555. For example, the imprint detection component 560 can know that the memory array 555 is storing logic states that may be imprinted, and detect or monitor the temperature or duration that may indicate static baking. In another instance, the imprint detection component can monitor access operations (e.g., performed by the memory controller 550) and can be configured to detect unintentional or malicious access conditions that can produce imprints, such as unfavorable access patterns, unfavorable bias, or other conditions that may be associated with asymmetrically altering memory cells in the memory array 555 relative to different logic states. Therefore, the imprint detection component 560 can be configured to support initiating or triggering various operations in the system 500 based on predictions of imprints or other unfavorable conditions, without having to directly detect the imprints themselves.

[0158] Alternatively or concurrently, the imprint detection component 560 may perform various operations intended to directly detect the presence or extent of an imprint in the memory array 555. In one instance, an imprint detection procedure that may be performed or managed by the imprint detection component 560 may include writing a first set of logical states to a subset of memory cells in the memory array 555. In some cases, prior to writing the first set of logical states, the memory device 540 may write a specific (e.g., known, configured, enforced) pattern of the logical states to the subset of memory cells, and the pattern may be configured to support subsequent operations of the imprint detection procedure. In other cases, the logical states stored in the subset of memory cells may not be a priori enforced, and therefore may be random (e.g., unknown, not specifically configured to support the imprint detection procedure) from the perspective of the imprint detection procedure.

[0159] Memory device 540 may be configured (e.g., via operation of an imprint detection component) to read a subset of memory cells to obtain a second set of logic states and determine a first number of mismatches or errors associated with the second set of logic states. In some cases, the memory device may compare the logic states read from each memory cell (e.g., logic states read from or detected from the second set of logic states) with the logic states written to each corresponding memory cell (e.g., the target logic state of a previous write operation written from the first set of logic states). A mismatch or error count may be made for each case where the read or detected logic state differs from the target logic state of the previous write operation. In one instance, an imprinted memory cell may remain in a first state (e.g., corresponding to a detected logic 1) even after an attempt is made to write the memory cell to a different state (e.g., corresponding to a target logic 0). Based on such discrepancies, the memory device 540 (e.g., imprint detection component 560) may determine or infer that an imprint has occurred or may have occurred on the memory cell. When the presence, quantity, or ratio of mismatch or error meets a threshold, the memory device 540 may continue to perform a recovery operation based on the mismatch or error between the second set of logic states and the first set of logic states (e.g., a recovery operation of the imprint recovery component 565 triggered or initiated by the imprint detection component 560).

[0160] Imprint detection component 560 can employ various techniques to determine and evaluate the number of mismatches or errors in such operations. For example, memory device 540 (e.g., sensing components of memory device 540) may be configured with a default or operating reference voltage for determining the logic state of memory cells under normal operating conditions, such as when reading application data from memory array 555. As an example, memory device 540 (e.g., imprint detection component 560) can obtain a second set of logic states by reading memory cells using the default reference voltage and comparing the resulting number of mismatches or errors with a threshold.

[0161] Alternatively, memory device 540 (e.g., imprint detection component 560) can obtain a second set of logic states by reading memory cells using a reference voltage lower or higher than a default reference voltage, which may be referred to as an offset reference voltage. In some cases, the offset reference voltage may be associated with the expected number of mismatches or errors (e.g., the expected number of errors that would occur due to reading with a reference voltage lower or higher than the default reference voltage, even without an imprint). Memory device 540 (e.g., imprint detection component 560) can compare the measured number of errors observed when reading a subset of memory cells using the offset reference voltage with the expected number of errors associated with the offset reference voltage. In some cases, imprint detection component 560 may determine whether to perform a recovery procedure based on this comparison. In some cases, two offset reference voltages may be used to obtain two sets of logic states. For example, a first offset reference voltage may be lower than the default reference voltage, and a second offset reference voltage may be higher than the default reference voltage.

[0162] Alternatively, memory device 540 (e.g., imprint detection component 560) can use the difference between the number of mismatches or errors observed when reading using two different reference voltages to determine whether a recovery procedure should be performed. For example, a second set of logic states and a third set of logic states can be obtained by reading memory cells using two corresponding offset reference voltages, both higher than or both lower than a default reference voltage. The measured difference (e.g., subtraction), slope, or other type of gradient (e.g., linear gradient, nonlinear gradient such as nonlinear regression) can be determined based on a first number of mismatches or errors associated with reading the subset of memory cells at a first offset reference voltage and a second number of errors associated with reading the subset of memory cells at a second offset reference voltage. The expected difference, slope, or other corresponding type of gradient can be defined based on a first expected number of errors resulting from reading using the first offset reference voltage and a second expected number of errors resulting from reading using the second offset reference voltage. The measured difference, slope, or other type of gradient can be compared to the expected counterpart to determine whether an imprint has occurred or whether a recovery procedure should be performed.

[0163] These examples are for illustrative purposes, and the imprint detection component 560 may perform one or more additional analyses based on the number of mismatches or errors (e.g., comparing the number of mismatches or errors with a threshold, comparing it relative to another number of mismatches or errors determined using another reference voltage, or otherwise analyzing the number of mismatches or errors) to determine whether to perform a recovery operation.

[0164] The memory device 540 may also include an ECC component 570 configured to support one or more ECC operations at the memory device 540. In various instances, the ECC component 570 may be configured to correct single-bit errors per word or per page, double-bit errors per word or page, or other configurations. In some instances, a trace detection component 560 may be coupled to the ECC component 570, and the trace detection component 560 may use information from the ECC component 570 to determine whether to perform a recovery procedure. For example, the trace detection component 560 may determine to perform a trace detection procedure when the number of mismatches or errors between the written and read logical states fails to meet a threshold, and in some cases, the threshold may be based on the number of errors that can be corrected by the ECC component 570, or the ratio of errors that can be corrected by the ECC component 570. In this regard, the trace detection component 560 may set the threshold for initiating a recovery operation to be at or above the number of errors that the ECC component 570 can correct (e.g., indicating a relatively severe condition). In some cases, the threshold for initiating a recovery operation may be zero errors (e.g., a recovery operation can be initiated as soon as a mismatch is detected).

[0165] In some instances, the imprint detection component 560 may be configured to set a threshold for initiating a recovery operation below the number of errors that can be corrected by the ECC component 570, indicating a less severe or moderately severe condition. For example, it may be assumed that the ECC component 570 handles some faults based on the capabilities of the adopted ECC scheme, but if the number of errors or the rate at which the ECC component 570 processes errors reaches a threshold level within this capability, then the imprint detection component 560 may be configured to preemptively initiate a recovery operation (e.g., before the ECC component catches up with the errors), which may involve triggering a relatively low-level or moderate recovery operation.

[0166] In some instances, multiple error thresholds or error ratio thresholds at ECC component 570 may be used as part of the recovery decision. For ECC correction ratios below a minimum threshold, no recovery operation may be initiated. For ECC correction ratios above a low threshold, “low severity” recovery operations may exist, such as recovery during operation (e.g., background recovery, maintenance recovery). For ECC correction ratios above a high threshold, or for functional failures exceeding ECC correction capabilities, “high severity” recovery operations may exist, such as discrete recovery events. In some instances, such techniques may be supported by a state machine approach (e.g., of memory controller 550, imprint detection component 560), where various transitions can be initiated if a counter exceeds a threshold. In some instances, such techniques may include real-time ratio determination during operation based on combinational logic techniques (e.g., chip-level or array-level techniques applied at memory device 540).

[0167] In one instance, considering the capability or error at the ECC component, the ECC ratio can be defined as the number of correctable ECC errors divided by the access count (e.g., time derivative, count derivative). In some instances, the ECC ratio can be calculated as an absolute value or otherwise considered, such as directly dividing the determined number of ECC errors by the access count. In some instances, the ECC ratio can be calculated or otherwise treated as an approximate derivative (e.g., a right shift of the counter after an overflow) to be incorporated into combinational logic. In some instances, memory device 540 may not be configured to execute an interrupt and terminate the system. Therefore, the techniques described in relation to the ECC ratio can use actual (e.g., determined) ECC counts or ratios, and actual ECC counts or ratios can be added to background counts or ratios that the ECC component 570 can detect (e.g., nominal ECC counts or ratios, threshold ECC counts or ratios, or normalized ECC counts or ratios). When such an addition causes a counter overflow, the corresponding rollback of the counter can be used as an indication of the difference relative to expected characteristics (e.g., detection or prediction of memory cell footprints).

[0168] In an illustrative example, over a certain number of access operations (e.g., one million activations, one billion activations, ten billion activations), the expected or threshold number of faults could be a corrected 10 words. If ECC component 570 corrects 35 words over the same number of access operations, the error is within the capabilities of the ECC component, but an unexpected drift or increase can be mitigated (e.g., by imprint detection component 560) by taking preventative measures (e.g., initiating a recovery operation) to reduce the correction load on ECC component 570.

[0169] In various instances, the number or rate of errors at ECC component 570 may include the total amount or rate of corrections, the number or rate of corrections independently considered in relation to a logical state (e.g., an error in logic 0, an error in logic 1), or the number or rate of corrections associated with a logical state (e.g., an error in logic 0, an error in logic 1) considered in isolation. In other words, ECC component 570 may support information related to the directionality of the number or rate of errors (e.g., relative to different logical states). Therefore, according to various instances of the described technology, imprint detection component 560, imprint recovery component 565, imprint manager 525, or various combinations thereof may consider error or mismatch directionality to determine one or more parameters related to imprint management.

[0170] The imprint recovery component 565 can be configured to perform various operations to equalize or normalize the memory cells of the memory array 555 (e.g., recover from actual or possible memory cell imprints, reduce the impact of conditions associated with memory cell imprints). For example, when one or more of the memory arrays 555 employ a ferroelectric memory architecture, the imprint recovery component 565 can perform or control operations configured to shift memory cells from an imprinted hysteresis curve 440 to or toward a de-imprinted hysteresis curve 430. In some instances, the imprint recovery component 565 can operate independently of or in the absence of the imprint manager 525 to support various imprint recovery techniques within the memory device 540. For example, the imprint recovery component 565 can operate autonomously (e.g., using the on-die or integrated circuitry processing capabilities of the memory device 540) without coordinating imprint recovery techniques with the host device 510. In some instances, such methods can benefit imprint recovery techniques that benefit from a deeper understanding of chip-level conditions or other relatively direct understanding of operating conditions (e.g., without needing to communicate such understanding to the host device), and can support memory device 540's agnosticness to different types or capabilities of different host devices. In other instances, imprint recovery component 565 can operate based on signaling exchanged with imprint manager 525 in a coordinated imprint management system, which can support imprint management coordination between host device 510 and memory device. In some instances, such methods can support offloading aspects of imprint management from memory device 540 to host device 510, which can support relatively streamlined memory architectures (e.g., with relatively limited onboard processing power or performance), allowing relatively complex techniques to be supported by the enhanced capabilities of host device 510, and other benefits.

[0171] In some instances (e.g., in response to a trigger or other information from the imprint detection component 560 or the imprint manager 525, intended to recover memory cells of the memory array 555), the imprint recovery component 565 may be configured to apply or otherwise control various biasing techniques, such as applying one or more voltages or voltage pulses to the memory cells, or performing multiple access operations (e.g., multiple read operations, multiple write operations, multiple read and write operations) on the memory cells of the memory array 555. In various instances, such biasing may be performed in maintenance or recovery modes that are either related to or independent of specific data access (e.g., requested or commanded by the host device 510, on a scheduling basis, based on the detection or prediction that an imprint has occurred), or in an imprint maintenance or recovery mode that modifies the parameters of the access operations (e.g., read operations, write operations, refresh operations) while supporting data transfer in the imprint maintenance or recovery mode. In some cases, the parameters may be modified permanently or indefinitely to support imprint recovery or prevention (e.g., the duration or magnitude of the access voltage may be modified).

[0172] The operation of the imprint recovery component 565 can be initiated, triggered, adjusted, or otherwise controlled or modified by various signaling (e.g., from the imprint detection component 560, from the imprint manager 525). For example, the imprint recovery component 565 may initiate a recovery operation based on initialization, permission, or authorization signaling generated within the memory device 540 or the host device 510. In some instances, various imprint management components (e.g., of the memory device 540, the host device 510) may detect various conditions associated with the recovery operation, and the imprint recovery component 565 may adjust or modify the recovery operation for different environmental (e.g., system or product) conditions or constraints, different unit technology sensitivities, and other factors. Alternatively or additionally, the imprint recovery component 565 may perform imprint recovery operations that are adjusted or selected based on the severity or direction represented by the imprint, specific operating conditions of the memory device 540, the host device 510, or the entire system 500, or based on various operating modes, permissions, approvals, or prohibitions.

[0173] In some instances, the imprint recovery component 565 may initiate operation based on the power-on or initialization of the memory device 540 in response to a boot operation of the host device 510. In some instances, the operation of the imprint recovery component itself may be part of a boot loop, and if the recovery operation is unsuccessful, the memory device 540 may send a signal to the host device 510 to try another memory device (e.g., an auxiliary memory device 590) to support the ongoing operation. Alternatively, the memory device 540 may provide signaling to the host device indicating that the memory device 540 needs to be replaced (e.g., a fault signal, a fault indicator).

[0174] In some instances, the imprint recovery component 565 may send one or more indications related to the imprint recovery procedure to the host device 510 (e.g., indications of the start or end of the imprint recovery operation). In some instances, the imprint recovery component 565 may otherwise provide signaling that the memory device 540 or one or more memory arrays 555 of the memory device 540 are unavailable for access operations.

[0175] In some instances, system 500 (e.g., host device interface 515, memory interface 545) can be configured for signaling between host device 510 and memory device 540 to support various operations or operating modes. In some instances, such system or controller signals can be set external to memory device 540 or external to memory array 555 and can control certain aspects of the recovery process. For example, a "recovery required" signal can be configured (e.g., via host device 510, via memory device 540) to signal, request, or otherwise trigger various imprint recovery operations described herein. In some instances, the "recovery required" signal can be enabled as a default or initial configuration or pre-configuration, causing imprint recovery operations to be performed preemptively at system 500 initial startup or before delivery to a consumer (e.g., early lifetime recovery or "wake-up" operations). In another instance, when imprint detection is performed by host device 510, a "controller-specified recovery" signal can be configured via host device 510 to schedule imprint recovery operations to be performed by memory device 540.

[0176] Alternatively or concurrently, other signaling may be provided to refine various aspects of imprint management in system 500. In some instances, a "disable recovery" signal may be configured (e.g., via host device 510, via memory device 540) to override (e.g., of memory device 540, memory array 555) internal recovery monitoring and prevent recovery operations, for example, when memory device 540 requires specific performance. In some instances, a "force recovery" signal may be configured (e.g., via host device 510, via memory device 540) to override or otherwise override internal recovery monitoring to initiate a recovery operation. In some instances, a "pause recovery" signal may be configured (e.g., via host device 510, via memory device 540) to temporarily override internal recovery operations, for example, to support temporary high-bandwidth data transfer scenarios, to temporarily reduce power consumption (e.g., low battery power), or under other conditions. In some instances, a “recovery time” signal can be configured (e.g., via host device 510, via memory device 540) to specify the time available for recovery operations (e.g., for discrete recovery events on memory array 555 or a subset thereof).

[0177] System 500 can be configured to support a variety of imprint recovery techniques, which can be broadly characterized as discrete recovery events across the entire memory array 555, recovery operations during operation, or other operations on the memory array 555 modified for the purpose of imprint recovery. While certain instances may be described in the context of one of these characteristics, such descriptions are provided as non-limiting examples for illustrative purposes, and various other instances or combinations may be used depending on the techniques described.

[0178] In the first set of examples, imprint management may include various techniques for performing discrete imprint recovery across the entire memory array 555. For example, some aspects of imprint management may be included in monitoring that operates when system 500 or host device 510 is started or powered on. In some instances, flags may be set before or when memory device 540 is powered off as an indication that an imprint may have occurred or should trigger the imprint management techniques described herein. Thus, system 500 may be configured to proactively attempt to recover from or mitigate the effects of an imprint.

[0179] In some instances, techniques for performing discrete imprint recovery may operate on the entire memory array 555 or a defined subset of the memory array 555 (e.g., in response to a trigger). Some techniques may impede the normal operation of system 500 and may include signaling or other operational understandings between host device 510 and memory device 540 (e.g., "pause" signaling, operation prohibition signaling, pause start operation). Therefore, in some instances, performing discrete imprint recovery may be performed before system 500 regains normal functionality, but including such operations (e.g., in a preventative manner) may prevent system 500 from failing solely due to the effects of the imprint.

[0180] In some instances, discrete imprint management techniques may include a monitoring step to assess whether memory array 555 or a subset of memory array 555 has passed or failed, such as a retest operation following imprint recovery biasing or access. The retest operation may include a scheme of signaling initiating additional imprint recovery biasing or access, a status update from memory device 540 to host device 510 (e.g., to imprint manager 525), or both, or associated with such a scheme.

[0181] In one instance, a full array recovery may be triggered or initiated by a boot sequence imprint monitoring failure or other functional failure (e.g., boot failure, blue screen event, high severity imprint monitoring failure). In another instance, a full array recovery may be triggered or initiated by the inability to use ECC correction for non-volatile data during recovery. In this case, memory device 540 or host device 510 (e.g., imprint manager 525) may signal to system 500 that data in memory array 555 needs to be replaced from storage device (e.g., secondary storage device 590) and initiate a clean reboot.

[0182] When system 500 is configured to select from various options of imprint recovery methods, in some cases, the selection of performing discrete recovery events across the entire memory array 555 may be preferred or advantageous. For example, discrete recovery events may be configured to provide relatively strong recovery over a relatively short time period. However, such techniques may be associated with relatively high power consumption, may pause certain aspects of memory operation during recovery, may be associated with causing fatigue or accelerating other degradation, or may involve other trade-offs. Therefore, in some cases, certain aspects of discrete recovery across the entire memory array 555 may be reserved for imprints of moderate or high severity (e.g., discrete recovery events across the entire memory array 555 may be disabled when low-severity imprints are detected or inferred).

[0183] In some cases, when the operating temperature of memory device 540 or host device 510 is determined to be relatively low (e.g., at or below a temperature threshold), discrete recovery events across the entire memory array 555 can be applied because less active trace recovery may be ineffective under these conditions where charge mobility or other responses to trace recovery are impaired. In other words, less active trace recovery techniques can appropriately and effectively normalize or equalize memory cells when the operating temperature of host device 510 or memory device 540 is high. The selection of such recovery techniques can also take into account power supply or power availability, since discrete recovery operations across the entire memory array 555 can only be selected, can be used for selection, or can be enabled under certain power conditions (e.g., battery charge is at or above a threshold, power consumption of system 500 is at or below a threshold, or host device 510 or system 500 is inserted).

[0184] In some instances, the described techniques for discrete imprint recovery across the entire memory array 555 may be supported by various signaling between the host device 510 and the memory device 540. For example, supported by such signaling, components of system 500 may understand that operation should be suspended or prohibited during imprint recovery. In some instances, the signaling may include or be accompanied by negotiation of available time (e.g., requested by memory device 540, approved by host device 510, or otherwise signaled). In some instances, such recovery techniques may include or be triggered by relatively complex imprint detection techniques, such as detection using multiple reference voltages at memory array 555, performing slope or gradient calculations or analyses, or other techniques that provide greater observability of imprint conditions at memory array 555.

[0185] In the second set of examples, smear management may include various techniques for performing smear recovery during operation of memory device 540 or memory array 555 (e.g., in maintenance mode). Memory array 555 may continue to operate during such techniques, but aspects of cell characteristics may be detected (e.g., the presence of detected or inferred smears, detection of unintentional or malicious access operations that could cause smears or other cell-level degradation or failure), allowing recovery operations to be performed during operation to mitigate, reduce, or prevent smears. In some instances, performing smear recovery during operation may degrade performance (e.g., increased power consumption, reduced bandwidth, increased latency), but such degradation may be within permissible specifications. Therefore, smear recovery during operation of memory device 540 may be used to provide recovery when a low to moderate amount of recovery is required but normal device operation is required and the reduced performance of memory device 540 or host device 510 is acceptable.

[0186] In some instances, trace recovery during operation can be associated with a monitoring scheme having multiple thresholds, thereby supporting recovery techniques that are relatively less proactive in some cases (e.g., relatively less proactive compared to discrete recovery events across the entire memory array 555). For example, if a low-severity trace is detected or inferred, low-level trace recovery can be performed without halting certain operations of system 500 (e.g., trace recovery can be performed while allowing a certain data exchange between memory device 540 and host device 510). In some cases, trace recovery during operation can be viewed as leveling or normalizing the maintenance mode or operation of memory array 555 before the trace causes such an access error, compared to other recovery techniques that can be performed based on the detection of a fault that may be associated with an access error (e.g., full fuse recovery of the faulty memory array 555).

[0187] In some instances, the threshold associated with imprint recovery during operation may be based on a detection scheme utilizing different reference voltages when reading the memory array 555 (e.g., reference voltage). Figure 7 (As described in Figure 8). For example, conditions associated with each of a set of reference voltages or a combination thereof can be used to individually indicate the severity of imprint detection or prediction. When imprint detection is performed at multiple reference voltages, if the conditions at memory array 555 fail a threshold at one or more reference voltages but pass a threshold at one or more other reference voltages, then system 500 can proceed with maintenance-type imprint recovery. If the conditions at memory array 555 fail a threshold at all reference voltages, then system 500 can proceed with full recovery mode (e.g., discrete recovery events across the entire memory array 555). In some instances, such techniques may be supported by chip-level analog thresholds at the memory array, where different thresholds are configured for each of the set of applied reference voltages.

[0188] Imprint recovery during operation can be triggered or adjusted based on various operating conditions in system 500. For example, such techniques can be triggered or adjusted based on the data load between host device 510 and memory device 540 or based on the processor load of host device 510, where a higher load may correspond to performing less destructive imprint recovery maintenance. In other instances, system 500 may be configured to detect non-functional or reduced-functionality modes (e.g., when system 500 or host device 510 is plugged in overnight), and techniques for imprint recovery during operation can be initiated based on such detection to support maintenance mode. In some instances, imprint recovery during operation may take into account handshakes or other signaling between host device 510 and memory device 540, and various aspects can be initiated or adjusted based on various requirements, operating modes, or other considerations.

[0189] In one instance, trace recovery during operation may utilize a self-refresh configuration at memory device 540. For example, a refresh may (e.g., uniformly) apply to the entire memory array 555, and refresh operations may be triggered more frequently at memory device 540 based on trace detection (e.g., increasing the rate or frequency of self-refresh operations). The increased rate or frequency of refresh operations may provide a bias voltage to the memory cells, thereby mitigating the effects of traces. In various instances, modified refresh operations may include one or more temporary modifications such as extensions, voltage changes, or state swaps / reversals, which may or may not affect normal operation. While such techniques may slow down the operation of memory device 540 or increase power consumption, they may otherwise be transparent to the operation of interfacing components (e.g., host device 510) and may not require signaling or negotiation between memory device 540 and the host device. In other instances, such extensions may be associated with commands or signaling between the host device 510 and the host device, such as signaling indicating or approving (e.g., authorizing execution) a relatively low-performance operating mode.

[0190] In some instances, trace recovery during operation may be based on, included in, or otherwise associated with ECC or wear leveling operations at memory device 540, where the associated operations may be modified based on triggers of relatively low severity. For example, a relatively small amount of recovery (e.g., a bias or access with a relatively low amplitude or relatively short duration) may be applied to each refreshed page based on ECC cleanup or wear leveling. In other words, the operations or algorithms associated with ECC or wear leveling may be modified for trace recovery purposes (e.g., at least in part based on the detection or inference of memory cell traces). Over time, such techniques may be applied to the entire memory array 555 while still supporting access operations to the memory array 555.

[0191] In one instance, the ECC correction count at ECC component 570 can be monitored (e.g., by state, by transition), and if the monitored count exceeds or otherwise meets a threshold, imprint maintenance can be triggered or initiated. In another instance, aspects of wear leveling may include shifting physical to logical pointers associated with data shifting to a new page. Recovery processing can be applied to unused physical pages before or after such shifts. In various instances, a number of (e.g., 1,000) fast cycles or a number of (e.g., 10) extended pulses can be used to bias the pages in transition.

[0192] Such techniques can be applied to other memory management methods that involve rotational data or any other refreshes. For example, smudge recovery during operation may include adding recovery cycles or biases to refreshed pages, increasing the number of self-refreshes, reducing the number of system refreshes that are skipped (e.g., in cases where memory device 540 is configured to skip system refreshes), and so on. In some instances, reducing the number of skipped system refreshes may not require any system knowledge (assuming partial refresh skipping) and, accordingly, may be supported without specific signaling between host device 510 and memory device 540. Higher voltages may be used when performing fast recovery (e.g., based on discrete recovery events), while lower voltages may be used for slow recovery of less severe smudges.

[0193] Depending on the specific instances, the described techniques may correspond to permanent or unidirectional changes during operation, or to changes that can be reset to normal operation after a set time, after a set number of times the entire array has been configured, or in response to conditions such as being in idle mode and being subjected to inserted operating conditions (e.g., a battery charging overnight). In some instances, imprint recovery during operation may be performed on a subset of the memory array 555 to recover the operating window of a specific subset.

[0194] When system 500 is configured to select from various options of imprint recovery methods, in some cases, performing recovery during operation may be preferred or advantageous. For example, recovery during operation can be performed to provide recovery by spreading recovery cycles across multiple operations when power consumption is a concern. In some instances, such techniques can be triggered or adjusted at relatively high operating temperatures of memory device 540 or the host device, as such techniques may be more effective at high temperatures than at low temperatures. Alternatively, such techniques can be triggered or adjusted at relatively early operating lifetimes (e.g., early or mid-life of the memory device), as such techniques can be relatively milder on memory device 540 (e.g., compared to discrete recovery events), and accordingly, may be less likely to accelerate fatigue or other degradation of memory array 555. Alternatively, such techniques can be triggered or adjusted based on the available time for recovery operations.

[0195] In the third set of examples, imprint management may include various techniques for imprint recovery by modifying the operation of memory device 540 or memory array 555. Imprint recovery by modifying operation can refer to various changes made to the normal operation of memory device 540 or memory array 555 in a manner intended to facilitate recovery, and may be associated with performance degradation within permissible specifications (e.g., increased power consumption, reduced bandwidth, increased latency). In some instances, the described techniques for imprint recovery by modifying operation may differ from imprint recovery during operation, since there may subsequently be no additional operations or procedures to be executed on a subset of memory array 555. Instead, imprint recovery by modifying operation can refer to various techniques that alter how standard operation works. Therefore, the application of the described recovery to the entire memory array 555 can be implied by the normal use of memory array 555 rather than explicit cycling of memory array 555. In some instances, such techniques may be intended for a relatively permanent change to the operation of memory device 540 or memory array 555, or at least a unidirectional change (e.g., a series of changes to parameters in the same direction, not a return to a previous state or configuration of operation).

[0196] In some instances, imprint recovery by modifying operations can leverage the flexibility of pulse width or amplitude at memory device 540. For example, normal operation of the memory device can begin with relatively short pulses (e.g., read pulses, write pulses, refresh pulses), such as shorter bias durations or pulses with relatively low amplitudes, which can benefit early-life operation (e.g., lower power consumption, lower fatigue, or other degradation). Based on detected or inferred imprint conditions, pulse width, pulse amplitude, or both (e.g., later in the lifetime) can be increased to improve imprint recovery or robustness. In some instances, such techniques can be applied near the end of the lifetime of (e.g., memory device 540, host device 510), where the improved resistance to imprinting may justify higher power consumption or corresponding accelerated memory array degradation.

[0197] One example of such a technique may include selective modification of the read pulse (e.g., cell bias applied during a read operation, cell bias after an activation or ACT command is issued), such as increasing the read pulse duration, increasing the read pulse amplitude, or both. In some instances, such modification may support restoring the normalization or equalization performance of the memory array 555, or otherwise compensate for changes in memory cell characteristics that may be caused by smudging. Another example of such a technique may include selective modification of the write pulse (e.g., cell bias applied during a write or write-back operation, cell bias after a precharge or PRE command is issued) (e.g., in response to smudging detection or prediction), such as increasing the write pulse duration, increasing the write pulse amplitude, or both.

[0198] In another instance, the “open page” time can be modified, which can refer to various techniques for modifying the voltage or duration of the applied bias during the time between the active page and the precharged page, the time of which can be alternatively referred to as the time between the open page and the closed page. In some instances, such techniques may involve modifying the duration of the period between the active page and the precharged page, which may correspond to an increase in the row activity time (tRAS) or other timing parameters. In some instances, the open page time may not be part of a read operation, nor part of a write or rewrite operation. Rather, from the perspective of at least some memory cells of memory array 555, the open time may refer to a wait state, and modifications during this state may not affect other timing specifications. Accordingly, the applied bias during the open page time can be adjusted for various considerations without necessarily affecting timing performance. Applying bias during this period may help mitigate smudging, but may cause problems for other reasons (e.g., degradation, fatigue, power consumption). Therefore, changes to the open page time for smudging management may be enabled relatively late during the operational lifetime of host device 510 or memory device 540, or during specific operating modes or conditions.

[0199] Another example may include various modifications to the cycle at refresh memory device 540. For instance, while a typical refresh pulse may have a relatively short duration (e.g., 15-25 nanoseconds), modifications in response to the detection or inference of a motif may include extending the refresh to a longer duration (e.g., 200 nanoseconds). In one example, the refresh operation may include cycles of various multiples (e.g., performing two refresh cycles for each triggered refresh), which can effectively multiply the bias time during the refresh operation. Thus, some modifications to the operation used for motif recovery may include extending the per-page refresh time to include recovery processing of the page being refreshed.

[0200] In another instance, for a memory device 540 that has ECC cleanup features enabled (e.g., passing ECC codes through the ECC engine to correct errors and then writing the corrected data back to the array), the cleanup frequency can be selectively increased in response to a low severity imprint monitoring warning.

[0201] The techniques for imprint recovery via modification operations can be selected or adjusted based on various criteria. For example, various techniques can be selected or adjusted based on the operating temperature of the memory device 540 or the host device 510. In one instance, imprint recovery techniques via modification operations are turned off or disabled at higher operating temperatures because other operations or biasing modes can effectively mitigate imprinting at higher temperatures. In another instance, various techniques can be selected or adjusted based on the age of components. For example, imprint recovery techniques via modification operations can be deactivated or disabled when the detected age or wear of the host device 510 or memory device 540 is below or otherwise meets a threshold for reducing wear or fatigue acceleration that may be associated with such techniques, or enabled when the detected age or wear of the host device 510 or memory device 540 exceeds or otherwise meets a threshold, because such wear or fatigue acceleration can be masked by the benefits of imprint management.

[0202] When system 500 is configured to select from various options of imprint recovery methods, in some cases, the choice to perform imprint recovery by modifying the operation of one or more of the memory devices 540 or memory array 555 may be preferred or advantageous. In some instances, imprint recovery by modifying operations can be used to provide relatively mild, relatively slow, or relatively weak recovery, for example, when relatively little recovery is required, when normal operation and near-optimal performance are required, or when power availability is relatively low or limited. In some instances, imprint recovery by modifying operations may preferably be applied at low severity or during the early lifespan of host device 510 or memory device 540, but such techniques may be beneficial later in lifespan. In some instances, imprint recovery by modifying operations may preferably be applied when power is limited or when the time available for recovery is relatively limited. In some instances, such techniques may not require signaling between memory device 540 and host device; in this case, such techniques may be preferably applied in embedded applications.

[0203] In other instances, recovery operations can be suppressed in certain situations. For example, if a trace is detected or predicted, but the corresponding severity is determined to be low, then system 500 can be configured to disable or otherwise not perform recovery operations, which can reduce unnecessary fatigue on the cells. In other instances, it may be preferable to avoid or disable recovery operations depending on the age of the device, which can prevent or reduce premature end-of-life failures that may be caused or exacerbated by the recovery method. For example, if memory device 540 or one or more memory arrays 555 are relatively old or late in their operating life, it may be advantageous to disable recovery operations until absolutely necessary (e.g., with a relatively high threshold for performing recovery operations), thereby reducing fatigue- and stress-induced current leakage on the memory cells of memory array 555. In another instance, if system 500 is unable to recover a portion of memory array 555 after multiple recovery attempts (e.g., indicating that a portion of memory array 555 is at or near the end of its operating life), then recovery on said portion of memory array 555 can be disabled to allow operation on the still functional portion of memory array 555. In some instances, recovery operations can be avoided or suppressed based on power supply or power availability. For example, if available power or power reserves are relatively low (e.g., unplugged mode, battery-only mode, low battery conditions), recovery operations can be suppressed or scaled down to reduce power consumption. In some instances, the power state of system 500 can change (e.g., host device 510 can be plugged into a wired power source), and host device 510 can respond by indicating the availability of maintenance operations so that memory device 540 can continue imprint recovery operations.

[0204] In some instances, system 500 may be configured to consider the severity of detected imprints as part of the described imprint recovery operation. For example, various imprint monitoring techniques may be configured to detect or predict imprint severity and may initiate or configure responses based on different severity thresholds. In one instance, if severity monitoring exceeds a relatively low threshold, where the memory array 555 is still operational, a "low severity" recovery response may be triggered, such as recovery during operation or recovery via modification. In some instances, this may include or refer to using recovery as a maintenance mode before functional failure becomes widespread. In another instance, if severity monitoring exceeds a relatively high threshold, where the memory array 555 is not operational, or errors exceed ECC correction, a "high severity" recovery response may be triggered, such as discrete recovery events across the entire memory array 555. In some instances, this may include or refer to the restoration of the functional capabilities of the memory array 555.

[0205] In some instances, system 500 may be configured as part of the described imprint recovery operation, taking into account the directionality of the detected imprint. For example, some imprint detection techniques are able to distinguish whether the presence or severity of an imprint is related to a failure in one logical state or a failure in another. Alternatively or additionally, the tendency of an imprint to move in one direction or another can be known or predicted in other ways (e.g., based on known or predicted imprint phenomena associated with one or another logical state). The advantage of an imprint associated with a particular logical state can therefore be used to select a recovery method or to bias the recovery method toward counteracting an imprint in said logical state.

[0206] In some instances, system 500 may be configured to take temperature (e.g., the operating temperature of host device 510, the operating temperature of memory device 540, and the operating temperature of memory array 555) into account, as part of the described imprint recovery operation. For example, parameters such as bias voltage, bias time, or number of cycles may vary depending on the current temperature of the device, regardless of the recovery method used. In some instances, recovery may be faster or easier at higher temperatures, making it possible to support a given recovery with lower bias voltage or fewer cycles. Correspondingly, recovery may be slower or more difficult at lower temperatures, making it possible to support a given recovery with higher bias voltage or more cycles. In some instances, recovery may be temperature-constrained, making it possible to select a specific recovery technique when host device 510 or memory device 540 operates at relatively low temperatures.

[0207] In some instances, system 500 may be configured to take into account power conditions (e.g., the power supply or power availability of host device 510 or memory device 540) as part of the described imprint recovery operation. For example, the selection of the imprint recovery method may depend on available power, such as whether host device 510 or memory device 540 is operating in a low-power state, on battery, or plugged in (e.g., to mains power). In another instance, the degree of parallelism (e.g., the number of rows or pages recovered simultaneously) may be based on power conditions, such as increased parallelism of imprint recovery when plugged in. In various instances, such techniques may correspond to or otherwise take into account the performance mode of host device 510, the power state of host device 510, or other detected or inferred input power conditions.

[0208] In some instances, system 500 can be configured as part of the described imprint recovery operation, taking into account the age of memory device 540, memory array 555, or host device 510. For example, the device can be broadly considered to have experienced three age ranges, referred to as early life, mid-life, and late life, which may correspond to a bathtub curve. In various instances, such descriptions or characterizations or other monitoring of device life can be tracked through memory device 540, host device 510, or both, to select or adjust various imprint recovery techniques.

[0209] During early life conditions (e.g., of memory device 540, host device 510, system 500), recovery methods can be used to induce a "wake-up" in memory array 555. For example, early life recovery can be a system-triggered maintenance response to defined thermal stresses or encapsulation processes of the assembly (e.g., manufacturing operations during mounting, mounting, soldering on board, curing of stacked encapsulation molding compounds, brazing), or a system-triggered maintenance response by tracking the state of a counter. In some instances, early life recovery techniques may selectively tend towards a relatively small number of cycles with symmetrical, low-bias-extended pulse widths to gently wake up memory array 555.

[0210] During mid-life conditions (e.g., of memory device 540, host device 510, system 500), recovery methods can be used to recover from more significant or unexpected thermal stress events. For example, during mid-life conditions (e.g., of memory device 540, host device 510, system 500), the device may experience multiple failure mechanisms, such as imprinting, fatigue, leakage, etc. Without the benefit of using counters or system triggering, these events may be difficult to distinguish from mid-life failures. Mid-life recovery techniques may be triggered by memory device 540 or host device 510 and may include pre-configured techniques or selections among discrete recovery events across the entire memory array 555, recovery during operation, or recovery by modifying operations. In some instances, mid-life may be defined as “non-early life” (e.g., as a binary marker) or defined by using counters (e.g., access operation counters, odometers), both of which can be applied to the selection or adjustment of the recovery method.

[0211] During late-life conditions (e.g., of memory device 540, host device 510, system 500), recovery methods may tend to be more extreme and may emphasize modifications to standard operation, such as increasing write or read bias. In some instances, late-life recovery can be characterized as an "all or nothing" response, where host device 510 or memory device 540 may have little remaining lifetime, and the benefit of imprint recovery may outweigh any corresponding degradation in lifetime. In some instances, late-life may be defined by a "late-life" flag (e.g., as a binary flag) or limited by the use of a counter (e.g., an access operation counter, odometer), both of which can be applied to the selection or adjustment of the recovery method.

[0212] The assessment of newness or wear and tear can be supported by various technologies within system 500. For example, memory device 540 may include a die-on counter that can (e.g., at memory device 540, or at host device 510) be compared to a set of predefined lifetime usage thresholds to identify whether memory device 540 meets early-life, mid-life, or late-life conditions. In another instance, host device 510 or memory device 540 may include a controller that sets a flag or other indication corresponding to early-life, mid-life, or late-life conditions. For example, an early-life flag may be set after final system assembly or board soldering, or after initial startup and system testing, and toggled after a certain duration or another threshold of operation.

[0213] In some instances, imprint management techniques may also take into account various aspects of data retention in memory array 555, which may include various instances of static configuration or selective operation relative to whether to attempt to retain the data stored in the memory cells for which imprint recovery is applied.

[0214] In one instance, a trace recovery method may attempt to preserve data stored in memory array 555 by copying data from a subset of memory array 555 that will receive recovery processing to an alternative location (e.g., another memory address of the same memory array 555, a different memory array 555, or an auxiliary memory device 590). For example, the trace recovery process may involve copying data to a different subset of memory array 555 and remapping logic to physical address scrambling, wherein the recovery processing may be performed immediately after entering an idle state or while entering an idle state. In another instance, data may be preserved locally by performing a certain number of repeated cyclic reverse write-back operations, thereby substantially flipping the data state of a subset of the array for a given number of cycles. In some instances, such data preservation may be enabled if a trace detection or evaluation operation has delivered a low severity warning, and data can still be read from and written to the array without unrecoverable errors. In other words, if memory array 555 has not experienced unrecoverable errors, system 500 may be configured to attempt data preservation.

[0215] In another instance, in bypass mode, data can be read into (e.g., of sensing component 250) a sensing amplifier or latch and held at the sensing amplifier or latch, wherein the bias or cycle of memory array 555 does not overwrite the sensing amplifier or latch. In various instances, after a recovery operation, data from the recovered memory cell can be returned from the sensing amplifier or latched to the same location, or data from the recovered memory cell can be moved from the sensing amplifier or latched to a different location, making the recovered memory cell available for other data.

[0216] In some instances, the recovery method may not attempt to retain data. For example, if a trace failure is known, system 500 may be configured to avoid spending time on data retention (e.g., data retention may be disabled), which could expedite certain aspects of trace recovery. Such operations can be selectively performed or disabled in response to a high-severity trace monitoring failure when data cannot be read from or written to memory array 555 without errors, or when data retention is not expected by the user (e.g., during startup operation when memory device 540 or memory array 555 is configured in volatile mode or otherwise not intended to store required information).

[0217] In some instances, particularly in applications where a certain degree of non-volatility is expected for memory device 540 (e.g., when memory device 540 is configured to operate as non-volatile RAM), aspects of data retention during imprint recovery can be considered. For example, system 500 may be configured with data-tiered or other-tiered storage, where the purpose of memory device 540 may be to provide relatively high-speed storage. In one instance, memory device 540 may be configured to provide faster virtual memory functionality compared to other secondary memory devices 590. In some instances, this may include operating memory array 555 of memory device 540 in a non-volatile mode for rapid initialization (e.g., waking from a sleep mode in which memory device 540 is powered down). In such cases, system 500 may be configured to flush (e.g., copy) data from the virtual memory to secondary memory device 590 before entering a low-power mode, where the secondary memory device may support or be expected to support a greater degree of non-volatility or imprint resistance compared to memory device 540. In other words, memory device 540 may be configured to support fast boot (e.g., utilizing the possibility that stored information still exists), but may not explicitly or solely rely on the presence of such data at memory device 540. For example, system 500 may be configured to attempt initialization using information from memory device 540, and in the event of a failure (e.g., boot failure), imprinting techniques (e.g., detection operations, recovery operations) may be performed on memory device 540 before, during, or after attempting initialization using information copied to secondary memory device 590.

[0218] Evaporation, copying, or other redundancy techniques may additionally or alternatively include evaporation via address space identifiers (ASIDs), evaporation of program and operating system data, evaporation by user, evaporation based on program versus data, or evaporation or copying initiated by other configurations, and various operation management schemes may be configured accordingly. For example, when an error during access to memory device 540 cannot be recovered by normal ECC operation, data can be pulled back during error recovery using page tables or mappings (e.g., virtual memory mapping, data redundancy mapping), which may include data stored at a different memory array 555 or secondary memory device 590 (e.g., flash memory, hard disk, or another storage device). In other words, according to these and other techniques, system 500 may be configured to determine whether to pull data from memory array 555 or pull a copy from another memory (e.g., another memory array 555 or secondary memory device 590), which may have different (e.g., higher) degrees of non-volatility or other differences regarding the degree of imprinting. Such techniques for determining the location for accessing data copies can be combined with various imprinting management techniques described herein.

[0219] In another instance of applying the described techniques within a memory hierarchy, system 500 may be configured to copy information from memory device 540 to secondary memory device 590 during imprint detection or imprint recovery. For example, system 500 may be configured to apply such techniques as an attempt to back up or restore information (e.g., backing up data to secondary memory device 590) that would otherwise be lost when the information is written back to the imprinted memory cells of memory device 540. Such techniques may preferably be applied with secondary memory device 590 configured for relatively fast operation, such as secondary memory device 590 employing a DRAM or FeRAM architecture.

[0220] In some instances, system 500 can be configured to selectively enable or configure various aspects of data retention based on a variety of considerations. For example, if ECC correction at memory device 540 fails, system 500 can be configured to understand that the data in memory device 540 may be corrupted, making it unnecessary to retain the data in memory device 540 or a specific memory array 555 during imprint recovery (e.g., instead relying on data stored in another location). In another instance, system 500 can be configured to perform various operations based on system or product constraints, such as the volatile or non-volatile configuration of memory device 540. For example, if system 500 is configured to use memory device 540 in non-volatile mode, or if memory device 540 is otherwise not configured for non-volatile operation, system 500 (e.g., host device 510, memory device 540) can set a flag or mode register to recognize memory device 540 or its operation as non-volatile and perform imprint management techniques accordingly. In some instances, if imprint recovery is being performed after power-on or otherwise during operation of memory device 540, data retention may be required unless system 500 provides an indication that data retention is not required for a given subset of memory array 555. In another instance, various imprint recovery techniques described herein can be selectively enabled or configured based on detection of whether a backup location is available in another memory array 555 or auxiliary memory device 590. For example, imprint detection limits or thresholds can be set based on the presence or absence of such detections, or various recovery types can be selected based on the presence or absence of such detections.

[0221] In some instances, one or more of the aforementioned techniques may be utilized to mitigate or resolve aspects of security vulnerabilities, malicious attacks, or unintentional adverse access patterns. For example, when non-volatile memory in a memory device is moved closer to the processor (e.g., according to the memory hierarchy), the configuration of the system architecture may need to consider the possibility of data retention failures in the memory device and the mechanisms that could lead to such failures (e.g., whether due to imprinting or some other phenomenon). In some instances, imprinting in memory device 540 may be associated with certain vulnerabilities; therefore, host device 510, memory device 540, or the entire system 500 may be configured to address such vulnerabilities or improve resilience or robustness against them.

[0222] In one instance, the memory device may have security or operational vulnerabilities related to access patterns, such as row hammering, where row hammering can be used to gain access to different portions of the memory device. In some cases, it may be possible to attack memory cells that have been imprinted or otherwise degraded. For example, if the host device 510 (e.g., the CPU of the host device 510) performs speculative events in response to an error in the memory device 540, then imprints or other faults or phenomena in the memory device 540 could be the source of triggering such events. To improve robustness and security, the system 500 may be configured to mitigate such vulnerabilities by establishing a certain level of handover between the memory device 540 (e.g., imprint detection component 560, imprint recovery component 565, memory controller 550) and the host device 510 (e.g., imprint manager 525, host device controller 520). In some instances, imprint detection techniques, such as those described herein, can be configured in a way that prevents such attacks from occurring.

[0223] In one instance, an unrecoverable data error (e.g., one or more faulty bits) may be identified during a startup event or maintenance or recovery event (e.g., a footprint detection event, a footprint recovery procedure). In various instances, unrecoverable ECC errors can be the result of intentional engineered, unintentional adverse access patterns, or random failures. For example, regarding intentional exploitation, an adverse actor may intentionally imprint bits in critical locations of memory array 555, or identify memory cells in the array with other relative weaknesses in the direction of imprint bias or in relation to data retention, and engineer errors that will occur on these memory cells (e.g., writing critical data to known stored data locations in memory array 555 that are capable of imprinting or other degradation). Alternatively or additionally, random exploitation may result from actions such as intentionally de-energizing memory device 540, host device 510, or system 500 in an attempt to engineer retention failures, or radiating impacts to memory device 540 configured for non-volatile operation. In some instances, host device 510 may branch unpredictably when it receives corrupted data or code. Under benign conditions, such a branch may only cause host device 510 or system 500 to crash. It is advantageous to avoid such crashes (e.g., to avoid inconvenience), but such crashes may not be associated with other downstream processes. However, under adverse conditions, a branch can indicate a security problem.

[0224] According to various aspects of this disclosure, when system 500 (e.g., memory device 540, host device 510) identifies an error (e.g., an uncorrectable ECC error), regardless of whether it is related to a signature or some other cause, system 500 can be configured to continue various operations and signaling to mitigate or resolve security vulnerabilities.

[0225] According to various examples, memory device 540 may detect data errors (e.g., uncorrectable errors) or access patterns (e.g., one or more read commands, one or more write commands) that can adversely affect the storage characteristics of memory device 540, such as access patterns that can impair the ability of memory cells in memory array 555 to be written to or otherwise stored with data. For example, such detection may be performed during startup operation or during normal operation of system 500 (e.g., of memory device 540). In some examples, memory device 540 may detect access patterns that could cause host device 510 to initiate or otherwise execute speculative branches. In some examples, memory device 540 may identify imprinting attacks or forced imprinting, which may be associated with conditions that could lead to imprinting of ferroelectric capacitors (e.g., in FeRAM applications), imprinting of another type of capacitor (e.g., in DRAM applications), imprinting of material memory elements, or other types of imprinting. In some examples, memory device 540 may determine that data errors exceed the corrective capabilities at memory device 540 (e.g., of ECC procedures).

[0226] In response to such detection, memory device 540 may determine to cease normal operation (e.g., at least temporarily), which may be related to a violation of the assumption or configuration of non-volatility. In some instances, this may involve memory device 540 entering a safe mode, a maintenance mode, or a recovery mode, or a combination thereof. In some instances, memory device 540 may initiate a recovery operation on memory array 555, such as a trace recovery operation, and in some instances, recover data from another part of system 500 (e.g., from a different memory array 555, from auxiliary memory device 590). In some instances, memory device 540 may determine to completely cease operation, or at least remain suspended until a subsequent initialization or startup operation (e.g., initiated by host device 510).

[0227] Alternatively or concurrently, memory device 540 may be configured to indicate an error to host device 510 via implicit signaling or its absence, or via explicit signaling. In some instances, memory device 540 may lock or deactivate (e.g., memory controller 550) the address decoder of memory device 540, or lock (e.g., one or more memory arrays 555) certain addresses of memory device 540. In some instances, memory device 540 may be configured to return random data (e.g., instead of the requested data), which host device 510 may interpret as an error indication. In some instances, memory device 540 may be configured to block or disable responses to host device 510 (e.g., ignore commands from host device 510), such that memory device 540 may be considered at least temporarily fully locked (e.g., from the perspective of host device 510). In some instances, memory device 540 may be configured to send an exception message to host device 510, delegating the responsibility of response to host device 510. In some instances, the response of memory device 540 may be configured to intentionally cause a failure at host device 510, such as a deliberately designed blue screen event (e.g., instead of attempting to recover from the error, which could open a security vulnerability or allow malicious access).

[0228] In some instances, memory device 540 may be configured to transfer or authorize operational control to (e.g., switch to) maintenance mode, thereby circumventing or preventing access or other operations from generating malicious imprints. In some instances, such transfer may be accompanied by memory device 540 sending a message or other signaling to host device 510, which may generate an anomaly at host device 510. In some instances, such signaling may be accompanied by memory device 540 indicating an address with an ECC error to host device 510.

[0229] In some instances, host device 510 may be configured to identify errors in memory device 540 and attempt to recover data from another location, such as another memory array 555 or auxiliary memory device 590. In other words, host device 510 may attempt to perform an access operation with memory device 540, and based on the detection of an unrecoverable error in memory device 540 (e.g., implicitly, based on the characteristics of the response or the absence of a response from memory device 540, or explicitly, based on specifically configured signaling from memory device 540, based on detection or prediction or imprinting or other degradation at memory device 540), host device 510 may attempt to recover data (e.g., backup data, redundant data) at least partially based on auxiliary memory device 590. In one instance, such data recovery may be facilitated by signaling memory device 540 to such erroneous addresses or by returning an ECC error when accessing addresses with errors. In some instances, such signaling may include signaling memory device 540 to the faulty data requested by the read operation instead of the data requested by the read operation. Therefore, the host device 510 may attempt to pull the originally requested data from the backup location.

[0230] System 500 can be configured to recover from such conditions according to various procedures. For example, host device 510 can perform recovery using address tables, such as translation buffers (TLBs), cache tables, or any other logical or virtual mapping of addresses. Using such tables or another lookup resource, host device can attempt to retrieve data from alternative storage devices to replace potentially corrupted data. In some instances, such methods can prevent other failures at the host device, such as preventing blue screen events. In some instances, this method enables host device 510 to recover from ECC errors at memory device 540. In some instances, the exception can be passed to the processor (e.g., CPU) at the host device, which can initiate a new boot operation, where host device 510 can be configured to retry using memory device 540 (e.g., for a pre-configured number of retries) or use secondary storage device 590.

[0231] In one instance of such recovery, system 500 may be configured such that parity bits are stored elsewhere in system 500 (e.g., separately from memory device 540). In other words, when data is written to memory device 540, the parity bits associated with said data may be written to auxiliary memory device 590. In such an instance, system 500 may be configured such that host device 510 may attempt to correct data errors at memory device 540 using multiple memory devices (e.g., at least one auxiliary memory device 590). This may involve implementing a more complex error correction scheme (e.g., coordinated at host device 510) than the scheme performed or supported at memory device 540 (e.g., chip-level or on-die ECC scheme).

[0232] In some instances, such schemes may be supported or enhanced by a bit flipper in memory device 540, which can improve the robustness of memory device 540 against certain types of malicious attacks. For example, bit flipper functionality that includes write-back inversion can inherently improve robustness against malicious imprints because write-back inversion itself can disable or restore certain aspects of the imprint. However, the described techniques may prevent other malicious attacks, or attacks in which write-back inversion is insufficient to disable or prevent imprinting attacks. Furthermore, the described techniques are beneficial to system 500 or memory device 540 that is not configured with certain write-back techniques or has other inherent resistance to potentially attacked imprints or other memory degradation.

[0233] Figure 6 This document describes an example of a process flow 600 supporting imprint management for memory systems, based on the examples disclosed herein. Features of process flow 600 can be found in the references. Figures 1 to 5 The described memory device (e.g., reference) Figures 1 to 5 The described memory device 110, memory die 160, memory die 200, or memory device 540, or one or more components of the memory device (e.g., device memory controller 155, local memory controller 165, local memory controller 265, memory controller 550, or imprint detection component 560) are implemented or performed. In some instances, one or more of the described techniques may be offloaded to a host device (e.g., by reference). Figure 5 The described host device 510 or imprint manager 525 performs or is otherwise controlled by it.

[0234] In some cases, when an imprinting procedure is executed on a memory cell of a memory array, the logical state stored in the memory cell may be random from the perspective of the imprinting procedure. For example, the logical state stored in the memory cell may be unknown or otherwise not specifically configured to support the imprinting procedure. In other words, in some cases, the memory device may execute the imprinting procedure at point 615 on a memory cell where previously stored data is unrelated to the imprinting procedure (e.g., unaffected by it, not specific to the imprinting procedure). For example, the memory cell of the memory array where the imprinting procedure is executed above may have been used to store application data before the imprinting procedure (e.g., before conditions associated with imprinting). In these cases, the memory device may use any data stored in the memory cell as potential imprinted data or potential imprinted logical state before the start of the imprinting procedure at point 615. In these cases, the memory device may rely on or not rely on the randomness of the stored data to support a mixture of logical states of the evaluated memory cells or portions thereof throughout the memory array for the imprinting procedure at point 615.

[0235] In other cases, prior to executing the imprint detection procedure at 615, at 605, the memory device may write forced (e.g., known, pre-configured) data to the memory cells to be evaluated (e.g., a subset of the array), such that in the event of a subsequent imprint detection procedure, the memory device can execute the imprint detection procedure on these memory cells and treat the forced data as a potential imprinted logic state. Before determining to initiate an imprint detection procedure (e.g., before the shutdown and subsequent reactivation at 610), the memory device may proactively write forced data according to various techniques. Writing forced data may include the memory device writing all memory cells (e.g., a subset of cells used for imprint evaluation) to the same logic state (e.g., writing “solid” forced data), mixing desired logic states (e.g., writing “mixed” forced data, writing different logic states in known or pre-configured proportions), or a known logic state pattern (e.g., alternating logic states, a “chessboard” pattern).

[0236] As an example, a memory device may use one or more replica word lines or pages (e.g., memory cells, memory pages, or memory segments available through wear leveling or another procedure) as a subset of memory cells for which mandatory data will be written at 605. In some instances, based on a wear leveling procedure or algorithm, the memory controller may transfer data between one or more memory cells in the memory array, or with auxiliary memory devices. Wear leveling may involve, for example, transferring application data from one physical location within or across memory arrays or between memory arrays to another physical location, which prevents one memory cell or subset of the memory array from being written to or read more (e.g., much more) than another memory cell or subset. Excessive access can shorten the lifespan of overused memory cells compared to less frequently accessed memory cells; therefore, wear leveling protects individual memory cells of the memory device from being overused, thus preventing premature memory cell failure.

[0237] In some cases, the memory array may include additional (e.g., spare) memory cells, rows, or pages that can support the transfer or otherwise shifting of application data within the memory array. In some instances, such shifting of such space or application data within the memory array may be part of wear leveling functionality. In some instances, such spare memory cells may be referred to as gap memory cells and may be associated with one or more blank word lines or blank pages. Therefore, due to these and other aspects of operation or configuration, at any given time, some memory cells in the memory array may not be actively storing application data, or such data may be insignificant to the memory device or host device.

[0238] In some cases, spare memory cells may be available and can be used to store known or forced data that can be used for subsequent imprinting procedures. When the physical location of application data shifts according to a wear leveling procedure, the known or forced data used for subsequent imprinting procedures may also be shifted (e.g., shifted to the most recently available row or page that is not actively used for application data). In some cases, wear leveling operations can be performed on a word-line basis, and word lines coupled to memory cells not currently used for application data may be referred to as replica word lines or shift word lines. Thus, a first set of logical states (e.g., in known or forced mode) can be written to memory cells coupled to one or more replica word lines available through the wear leveling operation. Upon activation of the memory device or another trigger of the memory device, the memory controller can perform the imprinting procedure using the known or forced mode of the logical states written to memory cells in the memory array available through the wear leveling procedure (e.g., memory cells coupled to replica word lines).

[0239] In some cases, known or forced data may be continuously updated (e.g., refreshed) at the memory array. In these cases, known or forced data may exist at the memory array if a sudden or unexpected deactivation event occurs (e.g., power outage, crash) or other standby events in which the host device or memory device may not actively monitor or otherwise operate. In some cases, the memory controller may enforce a set of logical states at the memory array as part of one or more deactivation procedures, which may be included when initiating a shutdown or standby mode. For example, when a device such as a host device initiates a deactivation procedure, the host device controller 520, the imprint manager 525, the memory controller 550, or the imprint detection component 560 may identify one or more portions of the memory array 555 used to enforce data conditions, and the memory device may write forced data to the identified portion of the memory array.

[0240] In some instances, the memory device (e.g., imprint detection component 560) may record or otherwise track forced logic states such that subsequent access operations (e.g., read operations, write operations) to the same subset of memory cells can be compared to or otherwise based on the forced logic states (e.g., when evaluation data conditions are determined based on imprinted data conditions). In some instances, imprint detection component 560 or memory controller 550 may write data patterns as forced logic states. For example, forced data may include an alternating pattern of logic 0s and 1s, which may be called a checkerboard pattern, a solid pattern of all logic 0s or all logic 1s, or various other combinations or distributions of logic 0s and 1s. In some instances, enforcing known data conditions may involve reading and recording a set of logic states that have been written to a subset of memory cells. In this regard, a record of the written or stored data can be used as a forced or known logic state.

[0241] In some cases, the memory device or host device may perform an imprint detection procedure in response to the deactivation and reactivation of the memory device. For example, at 610, the memory device may be deactivated (e.g., as part of a power-down procedure for a device associated with the memory device, as part of entering a standby mode). During deactivation, the memory device may be exposed to various environmental conditions (e.g., increased temperature), which may be related to whether the memory cells of the memory device have been imprinted. Whether due to adverse environmental conditions or other reasons, imprints may appear in some cases when the memory device is deactivated or in a standby state. In a deactivated or standby state, the memory device may not track or sense the environmental conditions exposed therein or the duration of deactivation. The memory device may then be activated at 610 (e.g., before 615).

[0242] After activation, the memory device or host device may not have data or information available to determine whether to perform an imprint recovery procedure (e.g., related to the probability of imprinting when the memory device is deactivated). In some cases, after activation, the host device may initiate or the memory device may otherwise perform (e.g., autonomously) one or more evaluations. For example, as part of the power-on self-test (POST) procedure, the host device may instruct the memory device to perform, or the memory device may otherwise initiate or perform, one or more tests to determine whether the memory device is operating within one or more specifications (e.g., specifications related to memory cell equalization or normalization), which may include an imprint detection procedure.

[0243] At 615, the memory device or host device may execute an imprint detection procedure. In some cases, the memory device may execute the imprint detection procedure based on deactivation and activation at 610 or on another basis as described herein. In various instances, the operation of 615 may be triggered by activation of the memory device (e.g., by it) or based on imprint evaluation performed during other operations of the memory device or host device. In some instances, the operation of 615 may continue until the presence of an imprint is detected, or may be initiated based on some other indication of the imprint (e.g., static baking conditions, identification of an imprint, or unintentional or malicious access patterns). In some instances, the imprint detection procedure may include identifying a subset of memory cells of memory array 555 for performing one or more steps of the imprint detection process.

[0244] In some cases, the subset of memory cells used for the imprint detection procedure may be based on the location of memory already written to a forced logical state. For example, the subset of cells may be based on or correspond to a portion of memory array 555 written at step 605. In cases where the memory device has not previously enforced data, the memory device may select a subset of memory cells at 615 to perform the imprint detection procedure. The subset of memory cells may be predefined, randomly selected, or selected based on one or more other configuration or activation procedures. In some instances, selecting the subset of memory cells used for the imprint detection procedure may comprise one or more different segments of memory array 555 or memory device.

[0245] As part of the imprint detection procedure, at 615, the memory device may write a first set of logic states to a subset of memory cells. In some instances, the first set of logic states may contain known (e.g., pre-configured, pre-qualified, forced) patterns. For example, the memory device may write solid data consisting entirely of logic 0s or logic 1s to the subset of memory cells. In some instances, the memory device may write the opposite logic state to each memory cell in the subset, for example, by reading the current data state of the memory cell (e.g., using a default reference voltage) and then writing the opposite state to the corresponding memory cell; this may be referred to as a read-reverse write-back procedure. In some instances, the memory device may write a mixture of logic states as the first set of logic states. This may involve writing a pattern, such as an alternating pattern of logic 1s and logic 0s, a set of random logic states, or any other combination of logic states.

[0246] If forced data has been written to the memory array before the suspected imprinting event (e.g., before the memory device is deactivated, before the memory device enters a standby state), the first set of logical states can be based on the forced data. For example, if a set of solid logical states (e.g., all logic 0s) is forced before deactivation, the memory device can write a set of opposite solid logical states (e.g., all logic 1s), the same logical states (e.g., all logic 0s), or another logical pattern as described herein. In some cases, the memory device can write a data pattern to a subset of memory cells before deactivation.

[0247] As another part of the imprint detection procedure, the memory device may perform one or more read operations on one or more portions of the subset of memory cells (e.g., the memory cells). Read operations on the subset of memory cells may produce another set of logical states (e.g., a second set of logical states), which the memory device may compare with the first set of logical states (e.g., a write at 615). In some cases, as part of the imprint detection analysis, the memory device may perform additional read or write operations on the subset of memory cells to obtain additional sets of logical states.

[0248] In some cases, a memory device or host device may obtain a second set of logic states or other additional sets of logic states by reading evaluated memory cells using one or more different reference voltages. For example, a memory device may be configured with a default or operating reference voltage for use when reading the logic states of the memory array (e.g., under normal operation). The default or operating reference voltage may be set to reduce or minimize the number of read errors that occur during read operations or during normal operation (e.g., when the memory array 555 is in access mode or normal operation mode). In some cases, a memory device or host device may obtain a second set of logic states by reading evaluated memory cells using a default reference voltage. In some instances, a memory device or host device may obtain a second set of logic states by reading evaluated memory cells using one or more offset reference voltages. In these cases, the offset reference voltage may be associated with the expected number of errors or mismatches, as discussed herein (e.g., based on a probabilistic distribution of memory cell behavior).

[0249] The memory device can determine one or more error counts based on mismatches or differences between written logical states (e.g., a first set of logical states, one or more target logical states from a previous write operation) and read logical states (e.g., a second set of logical states). In some cases, the memory device or host device can compare a logical state read from each memory cell with a known, recorded, or forced value of a logical state previously written to said memory cell. If the logical states differ, the memory device or host device can determine an error or mismatch; if the logical states are the same, the memory device or host device can determine that no error or mismatch has occurred. The memory device or host device can count the number of errors in one or more portions of a subset of memory cells to determine the error count.

[0250] At 620, the memory device or host device may determine whether a recovery operation should be performed (e.g., based at least in part on the imprint detection procedure performed at 615). In some instances (e.g., when the imprint detection procedure at 615 includes identifying the number of errors or mismatches), such a determination of whether a recovery operation should be performed may be based on the number of identified errors or mismatches, for example, comparing the number of identified errors or mismatches with a threshold. For example, if a second set of logic states is obtained by reading a memory cell using a default reference voltage, then the threshold may be relatively low (e.g., zero errors or near-zero errors, based on ECC operation or the capability of ECC component 570). In some cases, if a second set of logic states is obtained by reading a memory cell using an offset reference voltage (e.g., a reference voltage higher or lower than the default reference voltage), then the threshold may be relatively high (e.g., based on the number of expected or probabilistic errors that may occur when reading at the offset voltage, as described herein, for example, regarding...). Figure 7 (As described).

[0251] In some cases, the memory device or host device may determine a first number of errors (e.g., due to reading using a first threshold voltage) and a second number of errors (e.g., due to reading using a second threshold voltage), and determine whether a recovery operation should be performed based on the first and second error numbers. This may include determining a gradient parameter (e.g., difference, linear slope, nonlinear regression) between the first and second error numbers, as described herein (e.g., regarding...). Figure 7 Further examples of the gradient parameters are described below. In some cases, the memory device or host device may determine to perform a recovery operation, for example, based on determining that a threshold has been met. For example, the threshold may be related to the number of errors, the gradient parameters, or other parameters.

[0252] In some instances, the memory device may indicate to the host device that a recovery operation is required, and the memory device may wait to receive instructions from the host device (e.g., a command to perform a recovery operation or enter access, or another operating mode, or approval to continue the recovery procedure). Therefore, in some cases, the host device may determine whether or when the memory device should perform a repair procedure in response to signaling from the memory device. If the memory device determines that a repair operation is not required (e.g., a threshold is not met), the memory device may indicate to the host device that it is ready to complete an activation procedure or otherwise enter access or another operating mode (e.g., indicated by memory device 540, at least in part based on the determination that memory array 555 is not imprinted or the imprinting level is not higher than a threshold, and that memory device 540 is available for access operation).

[0253] At 625, the memory device or host device may perform a recovery operation, which may include cycling through the memory cells of the memory array one or more times (e.g., according to a bias mode, according to an access operation mode). For example, the memory device may perform multiple access operations (e.g., read and write operations) on one or more memory arrays of the memory device. In some cases, a write operation may include a reverse write-back operation, wherein the corresponding memory cell is read (e.g., using a default reference voltage) and a complementary or opposite logic state of the determined (e.g., read) logic state is written back to the corresponding memory cell. In some instances, the recovery operation at 620 may include performing multiple write operations on all or substantially all memory cells in a subset of memory cells of the memory array based on analysis of data from subsets of memory cells from the same or different memory arrays.

[0254] In some instances, the memory device may determine that the recovery operation has been completed and send one or more relevant indications to the host device. In some cases, the memory device may perform a loop operation and then send an indication to the host device that the memory device can be started and used by the host device, or an indication that the memory device can enter access or another operating mode. In some cases, after the recovery operation is completed, the memory device may perform a subsequent or second imprint detection procedure to determine or otherwise evaluate whether the recovery operation was successful (e.g., confirming the success of the recovery operation before indicating availability to the host device or transitioning to a normal operating mode).

[0255] At 630, after determining at 620 that no recovery operation will be performed, or after the recovery operation at 625 is completed, the host device's memory device may enter an operating mode (e.g., normal operating mode, access mode). In various instances, this may include restoring access mode or normal operating mode, or completing the boot process.

[0256] While the example of process flow 600 illustrates imprint detection using the written and read logic states of the memory array (e.g., based on direct detection or evaluation of the presence of imprints), other examples of process flow 600 may utilize other imprint detection techniques, or may make decisions about recovery operations based on predictions or inferences about memory cell imprints (e.g., at 620), such as detecting or identifying conditions that may be related to or otherwise accompany memory cell imprints or failures (e.g., high temperature, inactivity duration, detection of unintentional or malicious access operations or patterns that may cause imprints or other skewnesses, asymmetries, or other adverse memory cell characteristics).

[0257] Figure 7 Curve 700 illustrates the imprint detection conditions for imprint management in a memory system, according to the examples disclosed herein. Curve 700 illustrates the amount of mismatch between a target logic state (e.g., a written logic state, an attempted write logic state, an expected logic state) and a detected logic state (e.g., a read logic state) as a function of a reference voltage used to detect the stored logic state (e.g., via sensing component 250, via reference line 255). As part of the imprint detection procedure, one or more of the shown imprint detection conditions may be determined by a memory device (e.g., a reference voltage). Figures 1 to 5 The memory device 110, memory die 160, memory die 200, or memory device 540 described herein, or one or more components of the memory device (e.g., referenced in the following text) Figures 1 to 5 The described device (memory controller 155, local memory controller 165, local memory controller 265, memory controller 550, or imprint detection component 560) is implemented or executed.

[0258] In the example of curve 700, the unimprinted feature 740 illustrates the expected number of mismatches when reading a group of representative memory cells 205 at different reference voltages without imprinting (e.g., when this group of representative memory cells 205 is equalized or normalized). For example, the expected number of mismatches can be related to a random or probabilistic relationship between the read voltage generated by the read operation and the corresponding reference voltage. According to the example shown by curve 700, a read signal (e.g., for digital line 215) above a reference voltage (e.g., for reference line 255) can indicate logic 1, and a read signal below a reference voltage can indicate logic 0. In intermediate voltage regions (e.g., near the default reference voltage), the expected number of mismatches for a given reference voltage can be zero. In some instances, the expected number of mismatches can be zero across the entire reference voltage range corresponding to the read window. As the reference voltage increases or decreases beyond such intermediate regions, the expected mismatch or error can increase along a slope according to a probabilistic or random relationship.

[0259] In the example of curve 700, imprinted feature 750 illustrates the number of mismatches when reading the same group of representative memory cells 205 under different reference voltages, where this group of representative memory cells has been imprinted by one or more logic states. Compared to unimprinted feature 740, imprinted feature 750 may have a kink slope associated with the imprints of multiple or mixed logic states. For example, on either side of the central region (e.g., around the default reference voltage 702), one side of the kink may be associated with the characteristics of memory cells imprinted in one logic state, and the other side of the kink may be associated with the characteristics of memory cells imprinted in another different logic state. In some instances, such kink characteristics may be utilized as part of an imprint detection operation.

[0260] In other instances, a representative group of memory cells may be imprinted with a single logic state (not shown), and the imprinted feature 750 may have the same or similar slope as the unimprinted feature 740, but the imprinted feature 750 may be shifted along the reference voltage axis. In such instances, as part of the imprint detection operation, the shift of characteristics may be utilized (e.g., based on detecting or identifying asymmetry relative to the default reference voltage 702, based on the detected mismatch being higher than expected on one side of the default reference voltage 702 but not higher than on the other side).

[0261] In some instances, the imprint detection procedure may include reading a subset of memory cells under one or more reference voltages (e.g., a default reference voltage 702, one or more offset reference voltages 705) and determining the number of mismatches (e.g., errors, differences) between logic states read using the respective reference voltages and previously written logic states or target logic states, as described herein. Curve 700 illustrates the instance relationship between the different reference voltages 702 and 705 used to read logic states, the expected number of mismatches 715 (e.g., expected faults, errors, or differences for normalized or leveled memory array 555, based on probabilistic or random relationships) when reading under the respective reference voltages 702 or 705, and the measured number of mismatches 720 (e.g., faults, errors, or differences) of instances of the imprinted memory array 555 when reading under the respective reference voltages 702 or 705.

[0262] The default reference voltage 702 can be the default or operating reference voltage of the memory device. Read operations using the default reference voltage 702 are expected to produce zero errors (e.g., where the expected number of mismatches 715-a is zero), statistically minor errors, or fewer errors than the number that can be corrected by ECC operation when the memory cells of the memory array are properly operated (e.g., in the absence of imprinting, in a leveling or normalizing memory array 555). In some cases, the default reference voltage 702 can be the reference voltage used by the memory device during normal operation procedures when performing access operations, such as data access associated with application data. While in some instances the default reference voltage 702 may be fixed at the memory device, in other instances, for reasons unrelated to imprinting, the default reference voltage 702 (e.g., for normal operation, for default operation) may be adjusted at the memory device during operation (e.g., adjusted to an adaptive reference voltage, adjusted to a configurable reference voltage to compensate for changes in memory device or memory cell characteristics applicable to normalizing or leveling operations).

[0263] As part of the imprint detection procedure, the memory device may use one or more offset reference voltages 705 to read memory cells, said offset reference voltages being less than the default reference voltage 702 (e.g., offset reference voltage 705-b or 705-c) or greater than the default reference voltage 702 (e.g., offset reference voltage 705-d or 705-e). In some cases, as part of the imprint detection procedure, the measured number of mismatches 720 detected at different offset reference voltages 705 may deviate from the expected number of mismatches 715, which may be associated with memory cells being imprinted in different logic states.

[0264] In some cases, the memory device may use an offset reference voltage 705, which is higher or lower than the default reference voltage 702, to determine the logic state stored at the memory cell to be evaluated for imprinting. As part of the imprint evaluation, the measured number of mismatches 720 at the offset reference voltage 705 may be compared with the expected number of mismatches 715 at the offset reference voltage. For example, the offset reference voltage 705-b may be associated with the expected number of mismatches 715-b when reading a normally operating memory cell (e.g., unimprinted, undegraded, leveled, normalized).

[0265] In some cases, as part of the imprint detection procedure, the memory device may use an offset reference voltage 705-b to read a subset of memory cells. The memory device may determine the measured number of mismatches 720-b resulting from reading the subset of memory cells using the offset reference voltage 705-b, and if at least a portion of the memory cells are imprinted, then the measured number of mismatches 720-b may be greater than or equal to the expected number of mismatches 715-b. In some cases, reading the subset of memory cells using the offset reference voltage 705-b may indicate or determine whether cells already written to a logic 0 state (e.g., a target logic state) are imprinted in a logic 1 state. For example, if the imprint detection procedure determines that a memory cell was intended to store a logic 0 state but is imprinted in a logic 1 state, then the measured number of mismatches 720-b may be greater than the expected number of mismatches 715-b.

[0266] In some cases, as part of the imprint detection procedure, the memory device may use an offset reference voltage 705-c to read a subset of memory cells. The memory device may determine the measured number of mismatches 720-c resulting from reading the subset of memory cells using the offset reference voltage 705-c. If at least a portion of the memory cells are imprinted, the measured number of mismatches 720-c may be less than or equal to the expected number of mismatches 715-c. In some cases, reading the subset of memory cells using the offset reference voltage 705-c may indicate or determine whether cells already written to a logic 0 state (e.g., a target logic state) are also imprinted in a logic 0 state. For example, if the imprint detection procedure determines that a memory cell intended to store a logic 0 state is also imprinted in a logic 0 state, the measured number of mismatches 720-c may be less than the expected number of mismatches 715-c.

[0267] In some cases, the memory device can use an offset reference voltage 705-d to read a subset of memory cells. The memory device can determine the measured number of mismatches 720-d resulting from reading the subset of memory cells using the offset reference voltage 705-d. If at least a portion of the memory cells are imprinted, the measured number of mismatches 720-d can be greater than or equal to the expected number of mismatches 715-d. In some cases, reading a subset of memory cells using the offset reference voltage 705-d can indicate or determine whether cells already written to a logic 1 state (e.g., a target logic state) are imprinted in a logic 0 state. For example, if an imprint detection program determines that a memory cell was intended to store a logic 1 state but is imprinted in a logic 0 state, the measured number of mismatches 720-d can be greater than the expected number of mismatches 715-d.

[0268] In some cases, as part of the imprint detection procedure, the memory device may use an offset reference voltage 705-e to read a subset of memory cells. The memory device may determine the measured number of mismatches 720-e resulting from reading the subset of memory cells using the offset reference voltage 705-e. If at least a portion of the memory cells are imprinted, then the measured number of mismatches 720-e may be less than or equal to the expected number of mismatches 715-e. In some cases, reading the subset of memory cells using the offset reference voltage 705-e may indicate or determine whether cells already written to a logic 1 state (e.g., a target logic state) are also imprinted in a logic 1 state. For example, if the imprint detection procedure determines that a memory cell intended to store a logic 1 state is also imprinted in a logic 1 state, then the measured number of mismatches 720-e may be less than the expected number of mismatches 715-e.

[0269] In some cases, the ability to detect imprints in a memory array based on memory cells intended to store logical states that can be imprinted in the same or different logical states may depend on the initial distribution of the imprinted memory cells (e.g., the number or proportion of memory cells imprinted in logic 0 state and the number or proportion of memory cells imprinted in logic 1 state), a set of logical states written to a subset of memory cells (e.g., a set of imprinted logical states, a first set of logical states), the number of imprinted memory cells, or combinations thereof. Therefore, to support various instances of imprint evaluation, the memory device may be configured to read memory cells based on a default reference voltage 702, one or more offset reference voltages 705, or various combinations thereof, wherein such conditions may be pre-configured, selected, or indicated by the memory device or the host device.

[0270] Figure 8A This document describes an example of an imprint evaluation process 800-a for imprint management in memory systems, based on the examples disclosed herein. The operation of the imprint evaluation process 800-a can be found in the reference... Figures 1 to 5 The described memory device (e.g., reference) Figures 1 to 5 The described memory device 110, memory die 160, memory die 200, or memory device 540, or one or more components of the memory device (e.g., device memory controller 155, local memory controller 165, local memory controller 265, memory controller 550, or imprint detection component 560) are implemented or performed. In some instances, one or more of the described techniques may be offloaded to a host device (e.g., by reference). Figure 5The described host device 510 or imprint manager 525 performs or is otherwise controlled by it. In other words, the system (e.g., system 500) can be configured to perform imprint evaluation process 800-a according to various distributions of operations between the memory device and the host device. The operation of imprint evaluation process 800-a may include references Figures 1 to 7 One or more techniques are described. In some instances, the imprint evaluation process 800-a may be configured to evaluate whether one or more memory cells of a memory array have shifted from the imprinted hysteresis curve 430 to the imprinted hysteresis curve 440, or any other change in hysteresis or charge mobility properties that may be caused by the imprinting of memory cells.

[0271] The imprint evaluation process 800-a illustrates instances where different combinations can be used to support the operation of multiple possible implementations of an imprint detection procedure, wherein the logical state of the memory cells used to execute the procedure is unknown at the start of the procedure (e.g., not enforced before the procedure begins). For example, prior to an imprint detection procedure or evaluation mode triggered by a deactivation event, a standby event, or otherwise, the imprint detection circuitry (e.g., imprint detection component 560, imprint manager 525) or controller (e.g., memory controller 550, host device controller 520) may not have written to or read data from the memory array for subsequent use in the imprint detection procedure. In some instances, the imprint detection procedure can be executed as part of the startup sequence, and the memory device may not have yet stored records of which logical states are stored at the respective memory cells. In some instances, the memory device may not have performed a read operation to determine the logical state of the memory cells after deactivation. The imprint detection procedure can be triggered or initiated based on various criteria, such as powering on the memory device or host device, initializing the memory device or host device, waking the memory device or host device from a hibernation or standby state, based on operational criteria, such as the number or ratio of errors (e.g., corrected by ECC components or algorithms) exceeding or otherwise meeting a threshold, or entering a diagnostic or maintenance mode, and other criteria.

[0272] At 805, the memory device or host device may identify one or more subsets of memory cells for executing an imprint detection procedure. These subsets may store non-mandatory logical states (e.g., unknown logical states, logical states that may not be specific to the imprint detection operation, or a set of logical states that may or may not have been imprinted). The subset of memory cells may comprise a portion of memory cells, such as a portion of memory array 555, may span more than one array, may be distributed across different portions of one or more memory arrays 555, or a combination thereof. The subset of memory cells may be determined by the memory device or host device after the imprint detection procedure is initiated, or may be specifically used (e.g., pre-configured for) executing the imprint detection procedure.

[0273] At 810, the memory device or host device may write a set of logical states (e.g., a first set of logical states) to a subset of memory cells in the memory array. The logical states written to the subset of memory cells may be referred to as a set of imprint evaluation logical states, written evaluation logical states, or more generally, imprint evaluation data. Imprint evaluation process 800-a illustrates three instances of writing a set of logical states to support imprint detection evaluation, one or more of which may be selected or performed by the memory device or host device based on various criteria (e.g., the configuration of the memory device or host device, the pre-configuration of the memory device or host device, the host device's selection and commands to the memory device, the operating conditions of the host device or memory device, the data type, the distribution of logical states that may be imprinted, etc.).

[0274] As a first example, at 810-a, the memory device or host device may write a set of solid (e.g., same, equal, equivalent) logic states to all memory cells in a subset of memory cells. In some cases, this may involve writing each cell to represent logic 0. In other cases, the memory device or host device may write each cell to represent logic 1. In various instances, the memory device or host device may write a set of solid logic states without reading or determining the current (e.g., imprinted, potentially imprinted) logic state written to each cell.

[0275] As a second example, at 810-b, the memory device or host device may write a set of opposite logic states to a subset of memory cells. In some instances, writing a set of opposite logic states may involve performing a read-invert write-back procedure for each cell. For example, for each of the subsets of memory cells, the memory device or host device may read the current logic state of the corresponding memory cell (e.g., using a default reference voltage 702), invert the logic state (e.g., determine the opposite or complementary logic state of the read logic state), and write the inverted or opposite logic state back to the corresponding memory cell. In some instances, such techniques may assume or rely on the presence of a certain amount of charge or other characteristic stored in the corresponding memory cell at 810-b, which would indicate a potential imprinted logic state.

[0276] As a third example, at 810-c, the memory device or host device may write a set of mixed data to a subset of memory cells. In some cases, writing the set of mixed data may include writing a pattern (e.g., a checkerboard pattern, alternating logic states) to a subset of the memory array, writing random data, writing multiple logic states of a certain distribution or proportion, reading and writing back the same logic state (e.g., read logic state, unreversed logic state, reading a subset of memory cells based on the default reference voltage 702), or other logic states.

[0277] In some instances, the memory device or host device may record or track which logic states are written to the corresponding memory cells. The memory device or host device may record or track a first set of logic states for comparison at a later time in the imprint detection procedure (e.g., during an evaluation operation).

[0278] In some cases, different portions of one or more memory arrays can be used to perform different parts (e.g., sub-operations) of the imprint evaluation process 800-a. For example, a memory device or host device may write a first portion of a first set of logical states to a first portion of a subset of memory cells, and write a second (e.g., remaining) portion of the first set of logical states to a second portion of the subset of memory cells. In some instances, a memory device or host device may write the same pattern or the same set of logical states to multiple portions of a subset of memory cells. For example, a subset of memory cells may contain multiple sets of repeating logical states. In this regard, the memory device or host device may use different sets of logical states written to different portions of the array to perform different parts of subsequent read operations (e.g., at 815).

[0279] At 815, the memory device or host device may read a subset of memory cells, which may include reading the logic states that were written to or attempted to be written to at step 810 (e.g., test data, evaluation data) to obtain a second set of logic states. In some cases, the memory device or host device may write an entire set of test data at 810 and then perform a read operation on the subset of memory cells at 815. In some cases, the memory device or host device may wait for a defined or predetermined duration or delay between writing and reading the test data (e.g., between the write at 810 and the read at 815).

[0280] The memory device or host device may use one or more reference voltages (e.g., default reference voltage 702 or one or more offset reference voltages 705) to read test data (e.g., read a subset of memory cells) one or more times. In some cases, the reference voltage used to read test data written to a subset of memory cells may depend on the analysis method used to assess whether an imprint has occurred or whether the memory device should perform a recovery procedure (e.g., selected or determined based at least in part on this analysis method).

[0281] At 820, the memory device or host device may perform an imprint evaluation method (e.g., to determine whether to perform imprint recovery) based at least in part on the test data read or determined at 815. Imprint evaluation process 800-a illustrates three instances for performing imprint detection evaluation, one or more of which may be selected and performed based on various criteria (e.g., configuration of the memory device or host device, pre-configuration of the memory device or host device, selection and commands of the host device to the memory device, operating conditions of the host device or memory device, data type, distribution of logical states that may be imprinted, etc.).

[0282] At 820-a, the memory device or host device may perform a first analysis method (e.g., method 1), which may include reading a subset of memory cells at two offset reference voltages. For example, the memory device or host device may evaluate or compare data obtained using a first offset reference voltage 705 (e.g., the measured quantity of mismatch 720 or error) with data obtained using a second offset reference voltage 705 (e.g., the measured quantity of mismatch 720 or error). In some cases, both the first and second offset reference voltages 705 may be lower than or both higher than a default reference voltage 702. For example, the memory device or host device may obtain a second set of logic states by reading a subset of memory cells using a first offset reference voltage 705 lower than the default reference voltage 702 (e.g., offset reference voltage 705-b). The memory device or host device may obtain a third set of logic states by reading a subset of memory cells using a second offset reference voltage 705, also lower than the default reference voltage (e.g., offset reference voltage 705-c).

[0283] In some cases, both the first and second offset reference voltages 705 may be less than the default reference voltage 702, and the second offset reference voltage 705 (e.g., offset reference voltage 705-c) may be less than the first offset reference voltage 705 (e.g., offset reference voltage 705-b, an offset reference voltage 705 further away from the default reference voltage 702 than the first offset reference voltage 705). The memory device or host device may obtain the second set of logic states by reading the first offset reference voltage 705 before obtaining the third set of logic states by reading the second offset reference voltage 705. In these cases, the memory device or host device may not need to rewrite the first set of logic states to a subset of memory cells because the expected mismatch amount 715 caused by a read under the second offset reference voltage 705 may be greater than the expected mismatch amount 715 caused by a read under the first offset reference voltage 705, or because the application of the first offset reference voltage 705 may be associated with a smaller change in charge state or polarization state compared to the application of the second offset reference voltage 705 (e.g., the first offset reference voltage is associated with a non-destructive read operation, or with a read operation that may not adversely affect the result of a read operation using the second offset reference voltage). In such instances, the memory device may or may not perform a rewrite operation between reads under the first offset reference voltage 705 and reads under the second offset reference voltage 705.

[0284] In some cases, a memory device or host device can be read at a first offset reference voltage 705 and subsequently at a second offset reference voltage 705 (e.g., an offset reference voltage 705 that has a greater difference from the first offset reference voltage and the default reference voltage 702). In these cases, the memory device may or may not rewrite the first set of logic states to a subset of memory cells after a read using the second offset reference voltage 705 and before a read using the first offset reference voltage 705 (e.g., depending on whether the logic states stored in the subset of memory cells may have been interfered with by a read under the second offset reference voltage 705). For example, if a read using the second offset reference voltage 705 introduces a larger number of mismatches or errors compared to a read at an offset reference voltage 705 further from the default reference voltage 702, or if a read using the second offset reference voltage 705 is associated with a change in the charge state or polarization state of the memory cell (e.g., when a read at the second offset reference voltage 705 is associated with a reduction in polarization of one or more memory cells, or when a read at the second offset reference voltage can affect the result of a read at the first offset reference voltage), then the memory device may rewrite the first set of logic states. In some instances, different subsets of memory cells can be used for reads at different offset reference voltages 705 (e.g., a first subset of memory cells is used for reads at the first offset reference voltage 705, and a second subset of memory cells is used for reads at the second offset reference voltage 705, wherein the first and second subsets are different or do not overlap), which overcomes any problems associated with reading the same memory cell at different reference voltages.

[0285] In some cases, both the first and second offset reference voltages 705 can be greater than the default reference voltage 702, and the second offset reference voltage 705 (e.g., offset reference voltage 705-e) can be greater than the first offset reference voltage 705 (e.g., offset reference voltage 705-d, an offset reference voltage 705 further away from the default reference voltage 702 than the first offset reference voltage 705). The memory device or host device can obtain the second set of logic states by reading the first offset reference voltage 705 before obtaining the third set of logic states by reading the second offset reference voltage 705. In these cases, the memory device or host device may not need to rewrite the first set of logic states to a subset of memory cells because the expected mismatch amount 715 caused by a read under the second offset reference voltage 705 may be greater than the expected mismatch amount 715 caused by a read under the first offset reference voltage 705, or because the application of the first offset reference voltage 705 may be associated with a smaller change in charge state or polarization state compared to the application of the second offset reference voltage 705 (e.g., the first offset reference voltage is associated with a non-destructive read operation, or with a read operation that may not adversely affect the result of a read operation using the second offset reference voltage). In such instances, the memory device may or may not perform a rewrite operation between reads under the first offset reference voltage 705 and reads under the second offset reference voltage 705.

[0286] In some cases, a memory device or host device can be read at a first offset reference voltage 705 and subsequently at a second offset reference voltage 705 (e.g., an offset reference voltage 705 that has a greater difference from the first offset reference voltage and the default reference voltage 702). In these cases, the memory device may or may not rewrite the first set of logic states to a subset of memory cells after a read using the second offset reference voltage 705 and before a read using the first offset reference voltage 705 (e.g., depending on whether the logic states stored in the subset of memory cells may have been interfered with by a read under the second offset reference voltage 705). For example, if a read using the second offset reference voltage 705 introduces a larger number of mismatches or errors compared to a read at an offset reference voltage 705 further from the default reference voltage 702, or if a read using the second offset reference voltage 705 is associated with a change in the charge state or polarization state of the memory cell (e.g., when a read at the second offset reference voltage 705 is associated with a reduction in polarization of one or more memory cells, or when a read at the second offset reference voltage can affect the result of a read at the first offset reference voltage), then the memory device may rewrite the first set of logic states. In some instances, different subsets of memory cells can be used for reads at different offset reference voltages 705 (e.g., a first subset of memory cells is used for reads at the first offset reference voltage 705, and a second subset of memory cells is used for reads at the second offset reference voltage 705, wherein the first and second subsets are different or do not overlap), which overcomes any problems associated with reading the same memory cell at different reference voltages.

[0287] A memory device or host device can determine a first number of mismatches or errors (e.g., a first measured number of mismatches 720) by comparing a second set of logic states with a first set of logic states. For example, a mismatch or error can be counted when a logic state read from a memory cell at 815 does not match a logic state written to the memory cell at 810 (e.g., the expected written logic state, the target logic state). Such a mismatch may indicate that the memory cell has been imprinted (e.g., subjected to a change from an imprinted hysteresis curve 430 to an imprinted hysteresis curve before the write operation at 810) and, in response to the write operation at 810, failed to become a written logic state, or reverted or flipped back to an imprinted logic state. Similarly, a memory device or host device can determine a second number of mismatches or errors (e.g., a second measured number of mismatches 720) by comparing a third set of logic states with the first set of logic states (e.g., written at 810 or rewritten after determining the second set of logic states).

[0288] In some cases, the memory device or host device may determine a first number of mismatches or errors and a difference between a second set of mismatches or errors (e.g., the difference between a first measured number of mismatches 720 and a second expected number of mismatches 720), and compare this determined or measured difference with expected differences between mismatches or errors associated with reads under the first and second offset reference voltages 705 (e.g., the difference between a corresponding first expected number of mismatches 715 and a corresponding second expected number of mismatches 715). For example, the memory device or host device may store or otherwise identify a first expected number of mismatches or errors associated with reads under the first offset reference voltage 705 (e.g., the expected number of mismatches 715-b or 715-d) and a second expected number of mismatches or errors associated with reads under the second offset reference voltage 705 (e.g., the expected number of mismatches 715-c or 715-e). Therefore, the memory device or host device can determine the expected difference (e.g., the difference between the expected number of mismatches or errors and the expected number of mismatches or errors 715-c and 715-b, and the difference between the expected number of mismatches 715-e and 715-d) based on a comparison of a first expected number of mismatches or errors and a second expected number of mismatches or errors.

[0289] The memory device or host device may determine to perform a recovery operation based on comparing the difference between the measured conditions of the two offset reference voltages 705 and the difference between the expected conditions of the two offset reference voltages 705. If the measured difference deviates from (e.g., higher or lower than) the expected difference by a predetermined amount or otherwise meets a threshold, then a trace recovery operation is initiated or performed. In one example, if the difference between the measured number of mismatches 720-c and the measured number of mismatches 720-b is less than the difference between the expected number of mismatches 715-c and the expected number of mismatches 715-b, or is less than a certain threshold amount, then a trace recovery operation is performed.

[0290] In some cases, the memory device or host device may determine a measured gradient (e.g., slope or another gradient, whether linear or nonlinear, such as nonlinear regression) based on a first number of mismatches or errors and a second set of mismatches or errors (e.g., the slope between the first measured number of mismatches 720 and the second measured number of mismatches 720), and compare this determined or measured gradient with an expected gradient between mismatches or errors associated with reads under the first and second offset reference voltages 705 (e.g., the slope between the corresponding first expected number of mismatches 715 and the corresponding second expected number of mismatches 715).

[0291] For example, a memory device or host device may store or otherwise identify the expected gradient between mismatches or errors at two offset reference voltages 705 (e.g., the slope between the expected numbers of mismatches 715-c and 715-b, respectively, at offset reference voltages 705-c and 705-b), and the memory device or host device may determine whether to perform a recovery operation based on comparing the measured gradient between mismatches or errors at the two offset reference voltages 705 (e.g., the slope between the measured numbers of mismatches 720-c and 720-b, respectively, at offset reference voltages 705-c and 705-b) with the expected gradient. In one instance, if the slope between the measured numbers of mismatches 720-c and 720-b is lower than the slope between the expected numbers of mismatches 715-c and 715-b, or lower than the slope between the expected numbers of mismatches 715-c and 715-b by a certain threshold number, then an imprint recovery operation will be performed. In some instances, such techniques can be beneficial during startup sequence because the slope or gradient can provide good observability of possible imprint features, and memory devices may be particularly sensitive to imprints when power is lost or otherwise maintained in a logical or charge state within the memory array.

[0292] In another example, the expected number of mismatches 715 can be calculated or otherwise determined (e.g., dynamically) based on the measured number of mismatches 720 and the expected slope. Such techniques can illustrate extrapolating from a set of measured mismatches to identify the expected number of mismatches based on a known difference between a known slope and an evaluated reference voltage, where another measured number of mismatches can be compared to the calculated expected value. If the second measured number of mismatches 720 differs from the extrapolated expected number of mismatches 715 by a certain threshold number (e.g., 16x), then a recovery operation can be initiated. Such techniques can be less computationally intensive than direct slope calculation or comparison and can be advantageous when the slope is easily understood or characterized, which can support hard decoding or other configuration of aspects of imprint detection.

[0293] At 820-b, the memory device or host device may perform a second analysis method (e.g., method 2), which may include reading a subset of memory cells using a default or operating reference voltage (e.g., default reference voltage 702). The memory device or host device may compare the data obtained from the read under the default reference voltage (e.g., the measured number of mismatches 720-a) with a threshold, wherein the threshold may be correlated with the expected number of errors (e.g., the expected number of mismatches 715-a). In some cases, it may be expected that reading a subset of memory cells using the default reference voltage will not produce any mismatch errors, or it may be expected that it will produce substantially zero errors.

[0294] In these instances, the memory device or host device may set a threshold for a mismatch or error of zero or substantially zero, and if this threshold is met (e.g., met or exceeded), it can be determined that a trace has occurred or a recovery operation will be performed. In some instances, the memory device or host device may set the threshold based on the tolerance of performing a read operation using the default reference voltage 702. For example, if the tolerance associated with the default reference voltage 702 specifies the allowable or expected number of read errors that occur when reading a defined number of cells, then the threshold may be set based on this tolerance (e.g., higher, lower, equal, etc.). In this regard, when the number of errors generated by reading using the default reference voltage exceeds the tolerance, the memory device or host device can determine that a trace has occurred.

[0295] In some cases, the relevant threshold (e.g., related to the difference between the expected number of mismatches 715 and the measured number of mismatches 720) may be based on ECC operations performed by the memory device. In this regard, the threshold may be at or above the number of errors that can be corrected by ECC operations for a subset of memory cells. For example, if the ECC operation uses a single error correction (SEC) codeword, then the threshold may be set to one error. In other instances, the threshold may be set below the number of errors that can be corrected by ECC operations for a subset of memory cells.

[0296] At 820-c, the memory device or host device may perform a third analysis method (e.g., method 3), which may include reading a subset of memory cells using one or more offset reference voltages 705. The memory device or host device may compare data obtained using one or more offset reference voltages 705 (e.g., the measured number of mismatches 720) with the expected number of mismatches 715 associated with reading using the same one or more offset reference voltages 705. In some cases, the memory device or host device may obtain a second set of logic states by reading using a first reference voltage (e.g., one of the offset reference voltages 705) and determine the number of errors or mismatches between the second set of logic states and the first set of logic states (e.g., the measured number of mismatches 720). The memory device or host device may compare the measured number of mismatches 720 with the expected number of mismatches 715 (e.g., for the corresponding offset reference voltage 705) and determine, based on the comparison, whether a trace has occurred or whether a recovery operation should be performed. For example, if for one or more of the evaluated offset reference voltages 705, the measured number of mismatches 720 is greater than or less than the corresponding expected number of mismatches 715 by a limited multiple or threshold amount, then the memory device can determine that a trace has occurred or determine to execute a recovery procedure.

[0297] In some cases, the memory device or host device may determine only the measured number of mismatches 720 at a single offset reference voltage 705. For example, when a subset of memory cells already contains a random or mixed distribution of logic states before initiating an imprint detection procedure (e.g., before 810), and when writing the first set of logic states (e.g., at 810) involves writing a random or mixed data distribution to the subset of memory cells, the error at a single offset reference voltage 705 may be determined (e.g., selected by the memory device or host device).

[0298] In some cases (e.g., when performing imprint evaluation under multiple offset reference voltages 705), the memory device or host device may use the second offset reference voltage 705 to determine a second measured number of mismatches 720. This determination may use a subset of memory cells different from the subset of memory cells used to determine the first measured number of mismatches 720, or the same subset of memory cells (e.g., when performing a rewrite operation, such as an imprint evaluation rewrite, between evaluations under different offset reference voltages 705). For example, the memory device or host device may write a third set of logic states to a second subset of memory cells in the memory array and obtain a fourth set of logic states by reading the third set of logic states using the second offset reference voltage 705. This may involve using an offset reference voltage 705 that is less than the default reference voltage 702 and an offset reference voltage 705 that is greater than the default reference voltage 702. For example, the first offset reference voltage 705 may be less than the default reference voltage 702 (e.g., offset reference voltage 705-b or offset reference voltage 705-c) and the second offset reference voltage 705 may be greater than the default reference voltage 702 (e.g., offset reference voltage 705-d or offset reference voltage 705-e). Therefore, a first measured number of mismatches 720 can be obtained by reading a first subset of memory cells using the first offset reference voltage 705, and a second measured number of mismatches 720 can be obtained by reading a second subset of memory cells using the second offset reference voltage 705.

[0299] The memory device or host device may determine whether a stain has occurred, or whether a recovery operation should be performed, based on comparing a first measured number of mismatch 720 with a first expected number of mismatch 715, comparing a second measured number of mismatch 720 with a second expected number of mismatch 715, or a combination thereof. For example, if the first or second measured number of mismatch 720 is greater than or less than the corresponding expected number of mismatch 715 by a predetermined multiple, then the memory device or host device may determine that a stain has occurred, or execute or trigger a recovery procedure.

[0300] Figure 8BThis document describes an example of an imprint evaluation process 800-b for imprint management in memory systems, based on the examples disclosed herein. The imprint evaluation process 800-b can be implemented or performed as described in the reference. Figure 8A The imprint evaluation process 800-a describes one or more features. The features in the imprint evaluation process 800-b can be derived from a reference. Figures 1 to 5 The described memory device (e.g., reference) Figures 1 to 5 The described memory device 110, memory die 160, memory die 200, or memory device 540, or one or more components of the memory device (e.g., device memory controller 155, local memory controller 165, local memory controller 265, memory controller 550, or imprint detection component 560) are implemented or performed. In some instances, one or more of the described techniques may be offloaded to a host device (e.g., by reference). Figure 5 The described host device 510 or imprint manager 525 performs or is otherwise controlled by it. In other words, the system (e.g., system 500) can be configured to perform imprint evaluation process 800-b according to various distributions of operations between the memory device and the host device. The operation of imprint evaluation process 800-b may include references Figures 1 to 8A One or more techniques are described. In some instances, the imprint evaluation process 800-b may be configured to evaluate whether one or more memory cells of a memory array have shifted from the imprinted hysteresis curve 430 to the imprinted hysteresis curve 440, or any other change in hysteresis or charge mobility properties that may be caused by the imprinting of memory cells.

[0301] The imprint evaluation process 800-b illustrates examples of operations that can be combined in different ways to support multiple possible implementations of an imprint detection procedure, wherein the logical state of the memory cells used to execute the procedure is known at the start of the procedure (e.g., enforced or otherwise configured before the procedure begins). For example, prior to an imprint detection procedure or evaluation mode triggered by an activation event, standby event, or otherwise, imprint detection circuitry (e.g., imprint detection component 560, imprint manager 525) or controller (e.g., memory controller 550, host device controller 520) may have specifically written or enforced data on the memory array for subsequent use in the imprint detection procedure, as described herein. The imprint detection procedure can be triggered or initiated based on various criteria, such as powering on the memory device or host device, initializing the memory device or host device, waking the memory device or host device from a hibernation or standby state, based on operational criteria, such as the number or rate of errors (e.g., corrected by an ECC component or algorithm) exceeding or otherwise satisfying a threshold, or entering a diagnostic or maintenance mode, and other criteria.

[0302] At 850, the memory device or host device may identify one or more subsets of memory cells for executing an imprinting procedure, said subset of memory cells may be storing mandatory or otherwise known logical states (e.g., a set of logical states that may have been imprinted or may not have been imprinted). The subset of memory cells may comprise a portion of memory cells, such as a portion of an array, may span more than one array, may be distributed across different portions of one or more arrays, or a combination thereof. The subset of memory cells may have already stored logical states that are mandated by the memory device before initiating the imprinting procedure. For example, to support the imprinting procedure, the memory device or host device may have written a re-decoded or tracked set of logical states to the subset of memory cells (e.g., before deactivation, or otherwise before initiating the imprinting procedure), as described herein. Thus, in the example of 800-b, the memory device may have a known data background that may or may not have been imprinted, which may facilitate certain aspects of imprinting, including those described herein.

[0303] In one instance, wear leveling can be continuously operated on the memory device, which can be used to implement a known data pattern. For example, in each open or available blank row or page, the wear leveling operation may include or otherwise enable writing a chessboard logic pattern to the blank row or page. The memory device can track which rows or pages have been written with the chessboard pattern, and therefore, blank rows or pages can be selected for imprint evaluation based on an understanding that they have been written with the chessboard pattern. In other instances, available rows or pages can be written with a solid data pattern or other patterns or proportions of data states. In other instances, a known data pattern can be enforced in a dedicated section of the memory array, which can be rewritten or reversed over time to prevent unrepresentative imprints or other conditions from existing in the dedicated section of the memory array.

[0304] At 855, the memory device or host device may write a set of logical states (e.g., a first set of logical states) to a subset of memory cells in the memory array. The logical states written to the subset of memory cells may be referred to as a set of imprint evaluation logical states, written evaluation logical states, or more generally, imprint evaluation data. Imprint evaluation process 800-b describes three instances of writing a set of logical states to support imprint detection evaluation, one or more of which may be selected or performed by the memory device or host device based on various criteria (e.g., the configuration of the memory device or host device, the pre-configuration of the memory device or host device, the host device's selection and commands to the memory device, the operating conditions of the host device or memory device, the data type, the distribution of logical states that may be imprinted, etc.).

[0305] As a first instance, at 855-a, the memory device can write a set of opposite solid logic states to a subset of memory cells. This operation is possible if the memory device or host device has already written a first set of solid or identical logic states to the subset of memory cells before deactivation. For example, if a set of all logic 0s has been written to the subset of memory cells before deactivation, then at 855-a, the memory device or host device can write all logic 1s to the same subset of memory cells. In various instances, the write operation at 855-a may or may not include reading the initial state of the subset of memory cells, as the subset of memory cells may remain in a forced data mode.

[0306] As a second example, at 855-b, the memory device or host device can write a set of identical solid logic states to a subset of memory cells. This operation is possible if the memory device or host device has already written a first set of solid or identical logic states to the subset of memory cells before deactivation. For example, if a set of all logic 0s has been written to the subset of memory cells before deactivation, then at 855-a, the memory device can rewrite all logic 0s to the same subset of memory cells. In some cases, because the memory cells are evaluated in the same logic states that may be imprinted, this method can be associated with initiating or triggering a recovery operation after identifying fewer mismatches than expected.

[0307] As a third example, at 855-c, the memory device or host device may write a defined (e.g., mixed) set of data to a subset of memory cells. In some cases, writing said set of mixed data may include writing a pattern (e.g., a checkerboard pattern, alternating logic states) to a subset of the memory array, writing random data, writing multiple logic states of a certain distribution or proportion, reading and writing back the same logic state (e.g., read logic state, unreversed logic state, reading a subset of memory cells based on the default reference voltage 702), or other logic states.

[0308] As a fourth example, at 855-d, the memory device or host device may write a set of solid logic states to a subset of memory cells. In some cases, this may involve writing each cell to represent logic 0. In other cases, the memory device or host device may write each cell to represent logic 1. The memory device or host device may write a set of solid logic states without reading or determining the current logic state written to each cell.

[0309] In some instances, the memory device or host device may record or track which logic states are written to the corresponding memory cells. The memory device or host device may record or track a first set of logic states for comparison at a later time in the imprint detection procedure (e.g., during an evaluation operation).

[0310] In some cases, different portions of one or more memory arrays can be used to perform different parts (e.g., sub-operations) of the imprint evaluation process 800-b. For example, a memory device or host device may write a first portion of a first set of logical states to a first portion of a subset of memory cells, and write a second (e.g., remaining) portion of the first set of logical states to a second portion of the subset of memory cells. In some instances, a memory device or host device may write the same pattern or the same set of logical states to multiple portions of a subset of memory cells. For example, a subset of memory cells may contain multiple sets of repeating logical states. In this regard, the memory device or host device may use different sets of logical states written to different portions of the array to perform different parts of subsequent read operations (e.g., at 815).

[0311] At 860, the memory device or host device may read a subset of memory cells, which may include reading the logic states that were written to or attempted to be written to at step 850 (e.g., test data, evaluation data) to obtain a second set of logic states. In some cases, the memory device or host device may write an entire set of test data at 850 and then perform a read operation on the subset of memory cells at 860. In some cases, the memory device or host device may wait for a defined or predetermined duration or delay between writing and reading the test data (e.g., between the write at 855 and the read at 860).

[0312] The memory device or host device may use one or more reference voltages (e.g., default reference voltage 702 or one or more offset reference voltages 705) to read test data (e.g., read a subset of memory cells) one or more times. In some cases, the reference voltage used to read test data written to a subset of memory cells may depend on the analysis method used to assess whether an imprint has occurred or whether the memory device should perform a recovery procedure (e.g., selected or determined based at least in part on this analysis method).

[0313] At 865, the memory device or host device may perform an imprint evaluation method (e.g., to determine whether to perform imprint retrieval) based at least in part on the test data read or determined at 860. Imprint evaluation process 800-b illustrates three instances for performing imprint detection evaluation (e.g., method 1, method 2, and method 3, which may include references). Figure 8AThe imprint evaluation process 800-a may employ similar techniques, one or more of which may be selected and performed based on various criteria, such as the configuration of the memory device or host device, the pre-configuration of the memory device or host device, the selection and command of the host device to the memory device, the operating conditions of the host device or memory device, the data type, the distribution of logical states that may be imprinted, etc. For example, step 865-a may include one or more techniques described with reference to step 820-a, step 865-b may include one or more techniques described with reference to step 820-b, and step 865-c may include one or more techniques described with reference to step 820-c. As described herein, any function associated with any of method 1, method 2, or method 3 may be recombined with any other function described as associated with any other method.

[0314]

[0315]

[0316] Table 1 - Array Imprinting and Imprint Evaluation Scenarios

[0317] Table 1 illustrates the anticipated scenarios for selecting imprinted data conditions, imprinted data distribution, evaluation data conditions, and evaluation methods as described in reference imprint evaluation processes 800-a and 800-b, where any one of these scenarios can be supported by operations at the memory device, operations at the host device, or coordinated operations at the memory device. Each of the described scenarios may have various advantages or other considerations for implementing imprint management in a memory system.

[0318] Regarding the examples described for imprinted data conditions, in some scenarios, forced data can support improved imprint detection because known or otherwise assumed imprint conditions provide a good understanding of potential imprinted conditions. However, non-forced data conditions (e.g., random data, data not specifically configured for imprint management) may be relatively faster or more power-efficient because forced write operations may not be required. In some instances, forced data conditions can be imposed in finite conditions (e.g., during memory device shutdown or idle periods), which can mitigate the slowdown or power consumption associated with forced data modes. Furthermore, in some cases, non-forced data conditions can be randomized sufficiently to support adequate observability of imprint conditions. For example, for n pages, the variance of the "worst-case" condition compared to the solid data mode can be equal to 1 / 2. nWhen data conditions are associated with wear leveling operations using (32x8) pages, the probability that more than 70% of the data will be in the same state is approximately 1 / 257, or almost zero. Therefore, in some scenarios with 256 pages, random data is assumed to be reasonable regardless of what is actually written. Thus, while the described technique can support solid, non-forced overprinted data conditions, such conditions are unlikely.

[0319] Regarding the examples described for imprinted data distributions, mixed data distributions can support relatively greater observability when the imprinting phenomenon has a relatively consistent probability for different logic states or when the imprint detection method depends on different offset reference voltages 705 on either side of the default reference voltage (e.g., according to an example of evaluation method 3). In some instances, solid data can provide advantages when the imprinting phenomenon or occurrence rate is relatively biased towards one logic state, or when the evaluation method does not depend on different offset reference voltages 705 on either side of the default reference voltage (e.g., according to examples of evaluation methods 1, 2, or 3). In some cases, under solid imprinted data distributions or evaluation data distributions in opposite or identical states, evaluation method 2 or 3 may be more suitable than evaluation method 1 because solid imprinted data distributions may not be associated with kink feature 740 and therefore may not be associated with detectable changes in slope after imprinting (e.g., may not support detection by method 1).

[0320] Regarding the examples described for the evaluation data conditions, in some cases, a solid evaluation data pattern can support relatively greater or deeper observability for both solid and mixed imprinted data distributions, depending on the evaluation method used. In some cases, it may be advantageous to match a solid imprinted data pattern with the opposite solid evaluation pattern, for example, when performing a one-sided configuration of evaluation method 3. In some cases, when evaluating the imprinting of multiple states, a mixed evaluation data pattern may be preferred, and the mixed data may be pre-configured or selectively configured to the same state, different states, or non-mandatory (e.g., random). In some scenarios, the imprinted logic state may not be known when non-mandatory execution (e.g., when imprinting itself causes the loss of the stored logic state), in which case it may be preferable to impose mandatory data conditions when relying on the opposite state evaluation data conditions.

[0321] Regarding the examples described for the evaluation method, by performing various evaluations related to slope or gradient (e.g., between conditions at different reference voltages), evaluation method 1 can provide relatively strong observability of imprinted features (e.g., related to kinked imprinted features 740), which can support the differentiation between memory cell imprints and other faults or phenomena. Such methods can be supported by relatively complex curve fitting or chip-level evaluation of the expected number of mismatches identified based at least in part on the measured number of mismatches and the expected slope (e.g., for different reference voltages).

[0322] In some instances, if both logic states have similar sensitivity to the imprint, or if relatively robust computation is required, then evaluation method 1 may be configured with slope or gradient calculations on both sides of the default reference voltage 702. In some instances, if one logic state is more sensitive to the imprint than the other, or if a single slope or gradient calculation provides suitable observability, then evaluation method 1 may be configured with slope or gradient calculations on one side of the default reference voltage 702. In some cases, evaluation method 3 may be pre-configured to be performed using a single slope or gradient calculation, or may be selectively performed using a single slope or gradient calculation based on the imprint data (e.g., when only one side of the default reference voltage 702 is read to indicate whether imprinting has occurred, or when only one condition in the imprinted logic state or the evaluated logic state is expected).

[0323] In some instances, evaluation method 2 can be used with a mismatch threshold below the ECC correction lower limit (e.g., below the fault correction capability of the ECC algorithm or a threshold within the fault correction capability of the ECC algorithm), and the system can be configured to allow a certain non-zero level or ratio of mismatch or ECC correction before initiating imprint recovery operations. While such techniques may have relatively low visibility or observability for specific fault modes associated with the imprint (e.g., because evaluation method 2 may not be able to distinguish between hard faults and imprint faults), they can be relatively fast and effective. In some situations, method 2 may have unmeasurable results or otherwise lack sensitivity, but recovery operations can be triggered after any mismatch is detected using evaluation method 2. In other words, using evaluation method 2 may be relatively conservative for imprinting (e.g., it may be possible to trigger or initiate imprint recovery at frequencies exceeding the desired frequency).

[0324] In some instances, evaluation method 3 may be associated with adding a margin to the reference voltage level to a level that represents the expected number of non-zero mismatches. In some instances, the calculations for evaluation method 3 may be similar to those for evaluation method 2, but the use of an offset reference voltage 705 provides better visibility or observability of the imprint compared to the use of a default reference voltage in evaluation method 2. In some cases, if the memory device 540 degrades during its operation, a corresponding increase in the expected number of mismatches may be expected, which may not be explicitly related to the imprint. Therefore, later in the operational lifetime, performing evaluation method 3 may result in false alarms about the imprint (e.g., incorrectly detecting read window collapse due to wear), which may trigger or initiate imprint recovery more frequently than required. However, in some instances, various thresholds for evaluation method 3 may be adjusted over time (e.g., based on detected or monitored newness or wear).

[0325] In some instances, evaluation method 3 can be configured to perform read operations at two different offset reference voltages, and imprint recovery can be initiated if the mismatch under either condition exceeds the hard decoding limit. However, unlike evaluation method 1, evaluation method 3 can omit slope calculations, which may support certain hardware or computational efficiencies when compared with evaluation method 1. In some cases, it may be another indication of the asymmetry or comparison. In some instances, evaluation method 3 can be configured to have two offset reference voltages if two logic states have similar sensitivity to the imprint, or to have one offset reference voltage if one logic state is more sensitive to the imprint than the other. In some cases, evaluation method 3 can be pre-configured to be performed using a single offset reference voltage 705, or it can be selectively performed using a single offset reference voltage 705 based on the imprint data (e.g., when only one side of the default reference voltage 702 is read to indicate whether imprinting has occurred, or when only one condition of the imprinted logic state or the evaluated logic state is anticipated).

[0326] In some instances, performing evaluation method 3 or using a hybrid imprinted data distribution configuration system to perform evaluation method 3 may be preferred, whether mandatory or probabilistic (e.g., non-mandatory). When the imprinted data conditions are non-mandatory, evaluation method 1 or 2 may be advantageous if solid evaluation data conditions are used (e.g., according to scenario 10 or 11), or method 3 may be advantageous if hybrid evaluation data conditions are used (e.g., according to scenario 18). When the imprinted data conditions are mandatory, using evaluation method 1 or 3 under the opposite state evaluation data conditions may be preferred (e.g., according to scenario 31 or 33). However, these are merely illustrative examples, and any of the described scenarios can be used to support the imprint management techniques described herein. In some cases, various choices or configurations may be based on the number of memory cells in the evaluated subset, the number of subsets, and the probability of data in such a state (e.g., in non-mandatory or probabilistic cases).

[0327] In some instances of the described techniques, the selection or identification of either imprint evaluation process 800-a or imprint evaluation process 800-b can be based at least in part on the results of previous steps. For example, if the memory device 540 has a known worst-case data state of the imprint, then the memory device 540 can be configured to write a forced solid imprint data mode and perform evaluation method 3 based on the evaluation data state written in the opposite solid state. In other cases, a more conservative approach may be preferred, ...

Claims

1. A method for operating a memory device, comprising: A set of memory cells contained in the memory device is imprinted in a corresponding first logic state; Instructing a host device coupled to the memory device to imprint the set of memory cells into the corresponding first logic state; The host device receives approval to perform an imprint recovery procedure on the set of memory cells, the imprint recovery procedure improving the ability of the set of memory cells to switch between storing the corresponding first logical state and storing the corresponding second logical state; The imprint recovery procedure is performed on the set of memory cells, at least in part based on the approval received from the host device; Receive an instruction to pause the imprint recovery procedure from the host device; and The imprint recovery procedure is suspended at least in part based on the suspension instruction.

2. The method of claim 1, further comprising: Indicate the severity of the set of memory cells imprinted in the corresponding first logic state to the host device.

3. The method of claim 1, further comprising: Indicate to the host device the corresponding first logic state of the set of memory cells being imprinted.

4. The method of claim 1, further comprising: Select the imprint recovery program from a plurality of imprint recovery programs supported by the memory device; and The host device is instructed to perform the imprint recovery procedure, wherein receiving the approval to perform the imprint recovery procedure is based at least in part on instructing the host device to perform the imprint recovery procedure.

5. The method of claim 1, further comprising: The host device receives an instruction for the imprint recovery procedure, wherein the imprint recovery procedure is one of a plurality of imprint recovery procedures supported by the memory device.

6. The method of claim 1, further comprising: The host device receives an indication of constraints on the imprint restoration procedure, wherein the constraints include an amount of time available to perform the imprint restoration procedure, an amount of power available to perform the imprint restoration procedure, or any combination thereof.

7. The method of claim 1, further comprising: Instruct the host device on the duration of the imprint restoration procedure.

8. A method for operating a memory device, comprising: A set of memory cells contained in the memory device is imprinted in a corresponding first logic state; Instructing a host device coupled to the memory device to imprint the set of memory cells into the corresponding first logic state; The host device receives approval to perform an imprint recovery procedure on the set of memory cells, the imprint recovery procedure improving the ability of the set of memory cells to switch between storing the corresponding first logical state and storing the corresponding second logical state; The imprint recovery procedure is performed on the set of memory cells, at least in part based on the approval received from the host device; It is determined that the second set of memory cells contained in the memory device is imprinted in the corresponding third logic state; Determine whether the severity of the second group of memory cells imprinted in the corresponding third logic state meets the threshold; and The second imprint recovery procedure is performed on the second set of memory cells in a manner independent of any approval from the host device.

9. A method for operating a memory device, comprising: A set of memory cells contained in the memory device is imprinted in a corresponding first logic state; Read the corresponding first logic state from the set of memory cells; The corresponding first logic state is stored in a second location outside the set of memory cells; and After storing the corresponding first logical state outside the set of memory cells, an imprint recovery procedure is performed on the set of memory cells, the imprint recovery procedure being configured to improve the ability of the set of memory cells to switch between storing the corresponding first logical state and storing the corresponding second logical state.

10. The method according to claim 9, wherein: The second location includes a second set of memory cells within the memory device; or The second location is contained in the second memory device and is at a different level of the memory hierarchy within the system that includes the memory device and the second memory device.

11. The method of claim 9, wherein the second position comprises a set of latches coupled to a set of sense amplifiers for reading the corresponding first logic state.

12. The method of claim 11, further comprising: While the corresponding first logic state is stored in the set of latches, one or more voltage pulses are applied to each memory cell in the set of memory cells.

13. The method of claim 9, further comprising: After the imprint recovery procedure is executed on the set of memory cells, the corresponding first logic state is written to the set of memory cells.

14. The method of claim 9, further comprising: At least in part, this is based on storing the corresponding first logical state in the second location and changing the mapping between the logical address and the physical address associated with the corresponding first logical state.

15. The method of claim 9, further comprising: The severity of the set of memory cells imprinted in the corresponding first logic state is determined to be below a threshold. and Based at least in part on the fact that the severity is below the threshold, it is determined that the corresponding first logical state will be stored in the second location.

16. The method of claim 9, further comprising: The rate of error correction procedures associated with the set of memory cells is determined to be below a threshold; and The decision to store the corresponding first logical state in the second location is based at least in part on the fact that the error correction procedure rate is below the threshold.

17. The method of claim 9, wherein both reading the corresponding first logic state and storing the corresponding first logic state in the second location occur before determining that the set of memory cells are imprinted in the corresponding first logic state.

18. A method for operating a memory device, comprising: At the memory device, a read command for data in the memory array in the memory device is received from a host device coupled to the memory device; The data identified is incorrect; The data error is determined to exceed the correction capability of the error correction procedure supported by the memory device; The memory array is switched to a safe mode, at least in part, based on the determination that the data errors exceed the correction capability of the error correction procedure; and At least in part, based on determining that the data error exceeds the correction capability of the error correction procedure, and when operating the memory array in the safe mode, performing an imprint recovery procedure on the memory array, the imprint recovery procedure improving the ability of memory cells in the memory array to switch between storing different logical states.

19. The method of claim 18, further comprising: At least in part, this is based on switching the memory array to the secure mode and deactivating the address decoder for the memory array.

20. The method of claim 18, further comprising: After switching the memory array to the secure mode, a read command for the memory array is received from the host device; and The read command is ignored or at least one of random data or an anomaly indication is transmitted to the host device, and the ignore or transmit is in response to the read command and is at least in part based on operating the memory array in the security mode.

21. The method of claim 18, further comprising: The instruction for the address associated with the data error is transmitted to the host device; or The indication of the data error is transmitted to the host device.

22. A method for operating a memory device, comprising: A read command for data in a memory device coupled to a host device is sent from the host device to the memory device; The host device receives an indication of a data error in the read command from the memory device. and At the host device, a data recovery procedure for the data is executed at least in part based on the instruction received that the data is incorrect.

23. The method of claim 22, wherein performing the data recovery procedure for the data comprises: Access the address table at the host device to obtain replacement data for the data; and A write command for the replacement data is sent from the host device to the memory device.

24. The method of claim 22, wherein performing the data recovery procedure for the data comprises: Parity check data for the data is obtained through the host device, wherein the parity check data is stored externally to the memory device. and The host device performs an error correction procedure for the parity data, which is stored externally to the memory device, at least in part.

25. A memory device comprising: Means for determining a set of memory cells contained in a memory device that are imprinted in a corresponding first logic state; Means for instructing a host device coupled to the memory device to imprint the set of memory cells in the corresponding first logic state; Means for receiving from the host device approval for performing an imprint recovery procedure on the set of memory cells, the imprint recovery procedure improving the ability of the set of memory cells to switch between storing a corresponding first logical state and storing a corresponding second logical state; A means for performing the imprint restoration procedure on the set of memory cells, based at least in part on the approval received from the host device; A means for receiving from the host device an instruction to pause the imprint recovery procedure; and A means for suspending the imprint recovery procedure at least in part based on the suspension instruction.

26. The memory device of claim 25, further comprising: A means for selecting an imprint recovery program from a plurality of imprint recovery programs supported by the memory device; and A means for instructing the imprint restoration procedure to the host device, wherein receiving the approval to perform the imprint restoration procedure is based at least in part on instructing the imprint restoration procedure to the host device.

27. The memory device of claim 25, further comprising: A means for receiving an instruction for the imprint recovery procedure from the host device, wherein the imprint recovery procedure is one of a plurality of imprint recovery procedures supported by the memory device.

28. The memory device of claim 25, further comprising: A means for receiving from the host device an indication of constraints on the imprint restoration procedure, wherein the constraints include an amount of time available for performing the imprint restoration procedure, an amount of power available for performing the imprint restoration procedure, or any combination thereof.

29. The memory device of claim 25, further comprising: A means for instructing the host device on the duration of the imprint restoration procedure.

30. A memory device comprising: Means for determining a set of memory cells contained in a memory device that are imprinted in a corresponding first logic state; A means for reading the corresponding first logic state from the set of memory cells; A means for storing the corresponding first logic state in a second location outside the set of memory cells; and A means for performing an imprint recovery procedure on a set of memory cells after storing the corresponding first logical state outside the set of memory cells, the imprint recovery procedure being configured to improve the ability of the set of memory cells to switch between storing the corresponding first logical state and storing the corresponding second logical state.

31. The memory device according to claim 30, wherein: The second location includes a second set of memory cells within the memory device; or The second location is contained in the second memory device and is at a different level of the memory hierarchy within the system that includes the memory device and the second memory device.

32. The memory device of claim 30, wherein the second location includes a set of latches coupled to a set of sense amplifiers for reading the corresponding first logic state.

33. A memory device comprising: A means for receiving, at a memory device, a read command for data in a memory array coupled to the memory device from a host device coupled to the memory device; A means for identifying data errors in the data; A means for determining that the data error exceeds the correction capability of the error correction procedure supported by the memory device; A means for switching the memory array to a safe mode based at least in part on the determination that the data errors exceed the correction capability of the error correction procedure; and A means for performing a trace recovery procedure on a memory array, at least in part, based on determining that the data error exceeds the correction capability of the error correction procedure, and when operating the memory array in a safe mode, the trace recovery procedure improving the ability of memory cells in the memory array to switch between storing different logical states.

34. A memory device comprising: A means for sending a read command for data in a memory device coupled to a host device from the host device to the memory device; Means for receiving, at the host device, an indication of a data error in the read command from the memory device; and A means for performing a data recovery procedure for the data at the host device, at least in part, based on the instruction that the data error has been received.

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