Semiconductor device

Abstract

A semiconductor device includes a first-conductivity-type semiconductor layer having a main surface and including a device region, a second-conductivity-type base region formed in a surface layer portion of the main surface in the device region, a first-conductivity-type source region formed in the surface layer portion of the base region at intervals inward from an edge portion of the base region, a second-conductivity-type base contact region formed in the surface layer portion of the base region, a first-conductivity-type well region formed in the surface layer portion of the main surface at intervals from the base region in the device region, a first-conductivity-type drain region formed in the surface layer portion of the well region, a second-conductivity-type impurity region formed in the surface layer portion of the well region and electrically connected to the drain region, and a gate structure having a gate insulating film covering the channel region on the main surface and a gate electrode electrically connected to the source region and the base contact region and opposed to the channel region on the gate insulating film.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device provided with an EIS (Electrode-Insulator-Semiconductor) type diode structure having a stacked structure of an electrode, an insulator, and a semiconductor. BACKGROUND

[0002] Patent Document 1 discloses a semiconductor device provided with an EIS type diode structure. The semiconductor device includes an n-type semiconductor substrate, a p-type base region, an n-type source region, a p-type anode region, an n-type cathode region, a gate insulating film, and a gate electrode.

[0003] The base region is formed in a surface layer portion of the semiconductor substrate. The source region is formed in the surface layer portion of the base region spaced apart from an edge portion of the base region inwardly, and divides a channel region between the semiconductor substrate. The anode region is formed in a different region from the source region in the surface layer portion of the base region. The cathode region is formed in the surface layer portion of the semiconductor substrate spaced apart from the base region, and divides a drift region between the base region. The gate insulating film covers the channel region on the semiconductor substrate. The gate electrode is formed on the gate insulating film, and opposes the channel region through the gate insulating film. The gate electrode is electrically connected to the source region and the anode region.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT DOCUMENT

[0006] Patent Document 1: Japanese Patent Application Publication No. 2007-27228 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] The EIS type diode structure has a configuration feature that the electrostatic surge tolerance is low. The electrostatic surge tolerance is also referred to as ESD (electro static discharge) tolerance.

[0009] One embodiment of the present application provides a semiconductor device provided with an EIS type diode structure and capable of improving the electrostatic surge tolerance.

[0010] TECHNICAL MEANS FOR SOLVING THE PROBLEMS

[0011] One embodiment of the present application provides a semiconductor device including: a semiconductor layer of a first conductivity type having a main surface and including a device region; a base region of a second conductivity type formed in a surface layer portion of the main surface in the device region; a source region of the first conductivity type formed apart from an edge portion of the base region inwardly in a surface layer portion of the base region, a channel region being divided between the source region and the semiconductor layer; a base contact region of the second conductivity type formed in a region different from the source region in the surface layer portion of the base region, having an impurity concentration larger than that of the base region; a well region of the first conductivity type formed apart from the base region inwardly in a surface layer portion of the main surface in the device region, a drift region being divided between the well region and the base region; a drain region of the first conductivity type formed in a surface layer portion of the well region; an impurity region of the second conductivity type formed in a surface layer portion of the well region and electrically connected to the drain region; and a gate structure having a gate insulating film covering the channel region over the main surface and a gate electrode opposing the channel region over the gate insulating film and electrically connected to the source region and the base contact region.

[0012] The semiconductor device includes an EIS type diode structure in the device region. The diode structure specifically includes the base region, the source region, the base contact region, the well region, the drain region, and the gate structure. In addition, the semiconductor device includes a silicon controlled structure electrically connected to the diode structure in the device region. The silicon controlled structure specifically includes, in order along the main surface of the semiconductor layer, the impurity region (second conductivity type), the semiconductor layer (first conductivity type), the base region (second conductivity type), and the source region (first conductivity type).

[0013] The silicon controlled structure further specifically includes a first transistor structure of a first polarity on the well region side, and a second transistor structure of a second polarity on the base region side. The first transistor structure includes, in order along the main surface of the semiconductor layer, the impurity region (second conductivity type), the semiconductor layer (first conductivity type), and the base region (second conductivity type). The second transistor structure includes, in order along the main surface of the semiconductor layer, the source region (first conductivity type), the base region (second conductivity type), and the semiconductor layer (first conductivity type).

[0014] When a forward voltage is applied to the diode structure, the diode structure becomes an on state, and the thyristor structure becomes an off state. The thyristor structure becomes the off state because the drain region and the impurity region are fixed to the same potential. Thus, the diode structure is turned on, and a forward current flows to the diode structure. This forward voltage further flows to the first transistor structure electrically connected to the diode structure. Therefore, in a case where a forward overvoltage caused by static electricity or the like is applied to the diode structure, a forward overcurrent can be handled by the diode structure and the first transistor structure.

[0015] On the other hand, in a case where a reverse voltage is applied to the diode structure, the diode structure becomes an off state, and the thyristor structure becomes an on state. Thus, the thyristor structure is turned on, and a reverse current flows to the thyristor structure. Therefore, in a case where a reverse overvoltage caused by static electricity or the like is applied to the diode structure, a reverse overcurrent can be handled by the thyristor structure. Thus, the electrostatic surge tolerance can be improved according to the semiconductor device.

[0016] The above and other objects, features and effects of the present application will become clearer from the following description of the embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a circuit diagram showing a main part of an electrical configuration of a semiconductor device according to an embodiment of the present application.

[0018] Figure 2 is a circuit diagram showing a main part of an electrical configuration of a semiconductor device according to an embodiment of the present application. Figure 1 is a perspective view of the semiconductor device shown in

[0019] Figure 3 is an enlarged view of the region III shown in Figure 2

[0020] Figure 4 is an enlarged view of a main part of the configuration shown in Figure 3

[0021] Figure 5 is a diagram showing a configuration excluding a structure above a semiconductor layer from the configuration shown in Figure 4

[0022] Figure 6 is an enlarged view of the region VI shown in Figure 5

[0023] Figure 7 is a diagram showing a main part of the configuration shown in Figure 5 ​​​​A cross-sectional view of the line VII-VII shown.

[0024] Figure 8 is a graph showing the current-voltage characteristics of the reverse current blocking diode of the comparative example. Figure 5 A cross-sectional view of the line VIII-VIII shown.

[0025] Figure 9 is a graph showing the current-voltage characteristics of the reverse current blocking diode of the comparative example.

[0026] Figure 10 is a graph showing the current-voltage characteristics of the reverse current blocking diode of the comparative example. DETAILED DESCRIPTION

[0027] Figure 1 is a circuit diagram showing the main part of the electric configuration of the semiconductor device 1 of one embodiment of the present application. The semiconductor device 1 is a transceiver integrated circuit device used in a CAN (Controller Area Network) which is one of in-vehicle networks. The semiconductor device 1 includes an input terminal IN, an output terminal OUT, a power supply terminal VCC, a ground terminal GND, a high-side terminal CANH, a low-side terminal CANL, a control circuit 2, a high-side output circuit 3, a low-side output circuit 4, and a gate drive circuit 5.

[0028] The number of the input terminal IN is arbitrary. In Figure 1 an example in which the input terminal IN includes a first input terminal IN1 and a second input terminal IN2 is shown. In Figure 1 an example in which a microcomputer 6 is connected to the input terminal IN and the output terminal OUT, a resistance dividing circuit 7, a capacitor 8, and a terminal resistor 9 are connected between the high-side terminal CANH and the low-side terminal CANL is shown.

[0029] The control circuit 2 is electrically connected to the plurality of input terminals IN, the output terminal OUT, and the ground terminal GND. The control circuit 2 includes an electric signal generation circuit 10 and a function circuit 11. The electric signal generation circuit 10 generates prescribed electric signals for driving various circuits on the basis of input signals from the input terminal IN and outputs to the various circuits. The function circuit 11 generates electric signals for monitoring the various circuits on the basis of input signals from the input terminal IN or electric signals from the various circuits and outputs to the output terminal OUT.

[0030] The function circuit 11 includes, for example, one or a plurality of protection circuits for protecting the various circuits. The function circuit 11 can include, as an example of the protection circuit, at least one of an overcurrent protection circuit, an overheat protection circuit, and a low-voltage malfunction suppression circuit. The overcurrent protection circuit protects the various circuits against overcurrent. The overheat protection circuit protects the various circuits against heating. The low-voltage malfunction suppression circuit suppresses malfunctions of the various circuits in a low-voltage state.

[0031] The high-side output circuit 3 is electrically connected to the power supply terminal VCC, the high-side terminal CANH, and the gate drive circuit 5. The high-side output circuit 3 has a series circuit including a first drive transistor 12, a first reverse current blocking diode 13, and a first protection transistor 14. The first drive transistor 12 and the first protection transistor 14 are each formed of a p-type (first polarity type or second polarity type) MISFET (Metal Insulator Field Effect Transistor).

[0032] The gate of the first drive transistor 12 is electrically connected to the gate drive circuit 5. The source of the first drive transistor 12 is connected to the power supply terminal VCC. The anode of the first reverse current blocking diode 13 is connected to the drain of the first drive transistor 12. The gate of the first protection transistor 14 is electrically connected to the ground terminal GND. The source of the first protection transistor 14 is connected to the cathode of the first reverse current blocking diode 13. The drain of the first protection transistor 14 is connected to the high-side terminal CANH. The first protection transistor 14 suppresses the outflow of current from the high-side terminal CANH to the outside (terminal resistor 9 side) in the case where the high-side terminal CANH becomes a negative voltage.

[0033] The low-side output circuit 4 is electrically connected to the ground terminal GND, the low-side terminal CANL, and the gate drive circuit 5. The low-side output circuit 4 has a series circuit including a second drive transistor 15, a second protection transistor 16, and a second reverse current blocking diode 17. The second drive transistor 15 and the second protection transistor 16 are each formed of an n-type MISFET of a polarity type opposite to the p-type.

[0034] The gate of the second drive transistor 15 is electrically connected to the gate drive circuit 5. The source of the second drive transistor 15 is connected to the ground terminal GND. The gate of the second protection transistor 16 is connected to the power supply terminal VCC. The source of the second protection transistor 16 is connected to the drain of the second drive transistor 15. The cathode of the second reverse current blocking diode 17 is connected to the drain of the second protection transistor 16. The anode of the second reverse current blocking diode 17 is connected to the low-side terminal CANL. The second protection transistor 16 suppresses the inflow of current from the outside (terminal resistor 9 side) to the low-side terminal CANL in the case where the low-side terminal CANL becomes a positive voltage.

[0035] The gate drive circuit 5 is electrically connected to the control circuit 2, the high-side output circuit 3, the low-side output circuit 4, and the ground terminal GND. The gate drive circuit 5 generates a first control signal H / L having a prescribed pulse waveform and a second control signal L / H having a prescribed pulse waveform in accordance with an electric signal from the control circuit 2. The second control signal L / H is constituted by an inverted signal of the first control signal H / L. The first control signal H / L is input to the gate of the first drive transistor 12, and the second control signal L / H is input to the gate of the second drive transistor 15.

[0036] The resistance dividing circuit 7 includes a first resistor Rl and a second resistor R2. One end of the first resistor Rl is connected to the high-side terminal CANH. One end of the second resistor R2 is connected to the other end of the first resistor Rl. The other end of the second resistor R2 is connected to the low-side terminal CANL. One end of the capacitor 8 is connected to the connection portion of the first resistor Rl and the second resistor R2. The other end of the capacitor 8 is grounded. One end of the termination resistor 9 is connected to the high-side terminal CANH via the first bus line Ll. The other end of the termination resistor 9 is connected to the low-side terminal CANL via the second bus line L2.

[0037] In a case where the first control signal H / L of the low level is input to the first drive transistor 12 and the second control signal L / H of the high level is input to the second drive transistor 15, the first drive transistor 12 and the second drive transistor 15 become the on state. Thereby, the bus signal SH of 3.5 V (standard value) is output to the high-side terminal CANH, and the bus signal SL of 1.5 V (standard value) is output to the low-side terminal CANL (dominant state).

[0038] On the other hand, in a case where the first control signal H / L of the high level is input to the first drive transistor 12 and the second control signal L / H of the low level is input to the second drive transistor 15, the first drive transistor 12 and the second drive transistor 15 become the off state. Thereby, the bus signal SH of 2.5 V (standard value) is output to the high-side terminal CANH, and the bus signal SL of 2.5 V (standard value) is output to the low-side terminal CANL (recessive state). Hereinafter, the configuration of the semiconductor device 1 will be described.

[0039] Figure 2 is a perspective view of the semiconductor device 1 shown in Figure 1 is a perspective view of the semiconductor device 1 shown in Figure 2 In the drawing, the input terminal IN, the power supply terminal VCC, the ground terminal GND, the high-side terminal CANH, and the low-side terminal CANL described above are omitted.

[0040] Reference is made to Figure 2, the semiconductor device 1 includes a semiconductor chip 20 made of silicon in this embodiment. The semiconductor chip 20 is formed in a cuboid shape. The semiconductor chip 20 has a first main surface 21 on one side, a second main surface 22 on the other side, and first to fourth side surfaces 23A to 23D connecting the first main surface 21 and the second main surface 22.

[0041] The first main surface 21 and the second main surface 22 are formed in a quadrangular shape when viewed from the normal direction Z thereof (hereinafter, simply referred to as "when viewed from above"). The first side surface 23A and the second side surface 23B extend in a first direction X and are opposite to each other in a second direction Y orthogonal to the first direction X. The third side surface 23C and the fourth side surface 23D extend in the second direction Y and are opposite to each other in the first direction X.

[0042] The semiconductor chip 20 has, in this mode, a stacked structure including a p-type (first conductive type) semiconductor substrate 24 formed in this order from the second main surface 22 side to the first main surface 21 side, and an n-type (second conductive type) semiconductor layer 25 made of a conductive type opposite to the p-type. The semiconductor substrate 24 forms a part of the second main surface 22 and the first to fourth side surfaces 23A to 23D. The semiconductor layer 25 forms a part of the first main surface 21 and the first to fourth side surfaces 23A to 23D.

[0043] The p-type impurity concentration of the semiconductor substrate 24 can be 1 x 10 13 cm -3 or more and 1 x 10 16 cm -3 or less. The thickness of the semiconductor substrate 24 can be 100 μm or more and 1000 μm or less. The thickness of the semiconductor substrate 24 can also be 200 μm or more and 700 μm or less.

[0044] The semiconductor layer 25 is made of an epitaxial layer formed on the semiconductor substrate 24 in this mode. The n-type impurity concentration of the semiconductor layer 25 can be 1 x 10 14 cm -3 or more and 1 x 10 16 cm -3 or less. The thickness of the semiconductor layer 25 is smaller than the thickness of the semiconductor substrate 24. The thickness of the semiconductor layer 25 can be 1 μm or more and 50 μm or less. The thickness of the semiconductor layer 25 is preferably 5 μm or more and 20 μm or less.

[0045] The semiconductor chip 20 includes a plurality of device regions 26 divided by the first main surface 21. The plurality of device regions 26 includes one or a plurality (in this mode, a plurality) of functional device regions 27 and one or a plurality (in this mode, two) of diode regions 28. The number and arrangement of the functional device regions 27 and the diode regions 28 are arbitrary.

[0046] The functional device region 27 is a region in which various functional devices constituting part or all of the control circuit 2, gate drive circuit 5, first drive transistor 12, first protection transistor 14, second drive transistor 15, and second protection transistor 16 described above are formed. The functional devices are formed using the first main surface 21 and / or the surface portion of the first main surface 21. The functional devices may also include at least one of semiconductor switching devices, semiconductor rectifier devices, and driven devices. The functional devices may also include a circuit network combining semiconductor switching devices, semiconductor rectifier devices, and driven devices.

[0047] The semiconductor switching device may also include at least one of MISFET, CMIS (Complementary-MISFET), BJT (Bipolar Junction Transistor), IGBT (Insulated Gate Bipolar Junction Transistor), and JFET (Junction Field Effect Transistor). The semiconductor switching device includes the first driving transistor 12, the first protection transistor 14, the second driving transistor 15, and the second protection transistor 16 described above.

[0048] Semiconductor rectifiers may also include at least one of pn junction diodes, pin junction diodes, Zener diodes, Schottky barrier diodes, and fast recovery diodes. Driven devices may also include at least one of resistors, capacitors, and inductors.

[0049] Multiple diode regions 28 are spaced apart from multiple functional device regions 27. The multiple diode regions 28 are regions where the aforementioned first reverse current blocking diode 13 and second reverse current blocking diode 17 are respectively formed. The structures within the multiple diode regions 28 are identical. Hereinafter, the diode region 28 on the side of the first reverse current blocking diode 13 (…) Figure 2 Taking region III as an example, the specific structure of diode region 28 will be explained. The explanation of diode region 28 on the side of the second reverse current blocking diode 17 can be applied to the explanation of diode region 28 on the side of the first reverse current blocking diode 13.

[0050] Figure 3 yes Figure 2 An enlarged view of region III shown. Figure 4 yes Figure 3 Enlarged view of the main parts of the structure shown. Figure 5 From Figure 4 The diagram shown is of the structure after removing the structure on semiconductor layer 25. Figure 6 yes Figure 5An enlarged view of the region VI shown. Figure 7 is along Figure 5 A cross-sectional view along the line VII-VII shown. Figure 8 is along Figure 5 A cross-sectional view along the line VIII-VIII shown.

[0051] Referring to Figures 3-8 , the semiconductor device 1 includes a region separation structure 30 that divides a portion of the semiconductor layer 25 as a diode region 28 in the first main surface 21. The region separation structure 30 electrically separates the diode region 28 from a plurality of functional device regions 27. The region separation structure 30 is formed in a ring shape (in this mode, a quadrangular ring shape) that surrounds the diode region 28 in plan view. The planar shape of the diode region 28 can be adjusted by the inner edge of the region separation structure 30. The region separation structure 30 divides the diode region 28 into a quadrangular shape in plan view in this mode.

[0052] The region separation structure 30 is composed of a column region 31 of p-type formed in a wall shape in the semiconductor layer 25 in electrical connection with the semiconductor substrate 24 in this mode. The column region 31 includes a column buried region 32, a column well region 33, and a column contact region 34.

[0053] The column buried region 32 is formed across the boundary between the semiconductor substrate 24 and the semiconductor layer 25, and is electrically connected to the semiconductor substrate 24. In this state, there is one column buried region 32, but the number of column buried regions 32 is arbitrary as long as it is electrically connected to the semiconductor substrate 24. A plurality of column buried regions 32 can also be stacked from the above-mentioned boundary toward the first main surface 21 side. The p-type impurity concentration of the column buried region 32 can be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 16 -3 20 -3

[0054] The column well region 33 is formed in the surface layer portion of the first main surface 21. The column well region 33 is specifically formed in the semiconductor layer 25 in a region between the first main surface 21 and the column buried region 32, and is electrically connected to the column buried region 32. The column well region 33 can also have a p-type impurity concentration that is lower than the p-type impurity concentration of the column buried region 32. The p-type impurity concentration of the column well region 33 can be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 15 -3 17 -3

[0055] ​​​​​​​​The column contact region 34 is formed in the surface layer portion of the column well region 33 at a position spaced apart from the bottom of the column well region 33 toward the first main face 21 side. The column contact region 34 has a p-type impurity concentration greater than that of the column well region 33. The p-type impurity concentration of the column contact region 34 can be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 18 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 20 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less.

[0056] The semiconductor device 1 includes an n-type buried region 35 formed in the diode region 28 across the boundary between the semiconductor substrate 24 and the semiconductor layer 25. In the Figures 3-5 The buried region 35 is indicated by a broken line. The buried region 35 has an n-type impurity concentration greater than that of the semiconductor layer 25. The n-type impurity concentration of the buried region 35 can also be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 16 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 20 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less.

[0057] The buried region 35 is formed spaced apart from the first main face 21 toward the semiconductor substrate 24 side, facing the first main face 21 across a portion of the semiconductor layer 25. The buried region 35 is formed spaced apart inward from the region separation structure 30. In this case, a portion of the n-type impurity of the buried region 35 can also diffuse to the peripheral edge of the diode region 28. That is, the buried region 35 can also have a concentration gradient in which the n-type impurity concentration on the peripheral edge side of the diode region 28 is lower than that on the inner portion side of the diode region 28.

[0058] The semiconductor device 1 includes one or a plurality (in this mode, a plurality) of p-type base regions 40 formed in the diode region 28 in the surface layer portion of the first main face 21. The plurality of base regions 40 are each formed as a portion of the anode region of the first reverse flow blocking diode 13. The p-type impurity concentration of each base region 40 can be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 15 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 17 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less.

[0059] The plurality of base regions 40 are specifically formed, respectively, in regions surrounded by the edge portion of the buried region 35 when viewed from above. The plurality of base regions 40 are formed spaced apart from the buried region 35 toward the first main face 21 side, facing the buried region 35 across a portion of the semiconductor layer 25. The plurality of base regions 40 are formed, in this mode, respectively, in strip shapes extending in the first direction X, formed spaced apart in the second direction Y. Due to this, the plurality of base regions 40 are formed in a strip shape extending in the first direction X when viewed from above.

[0060] The semiconductor device 1 includes one or a plurality of (in this embodiment, a plurality of) n-type source regions 41 formed in the surface layer portion of each base region 40. Each source region 41 has an n-type impurity concentration greater than the n-type impurity concentration of the semiconductor layer 25. The n-type impurity concentration of each source region 41 can be 1 x 1018cm-3or more and 1 x 1021cm-3or less. 18 cm -3 -3or more and 1 x 1021cm-3or less. 20 cm -3 -3or more and 1 x 1021cm-3or less.

[0061] The plurality of source regions 41 are formed in the surface layer portion of each base region 40 at intervals in the first direction X. The plurality of source regions 41 are respectively formed at intervals inward from the edge portion of each base region 40, dividing a channel region 42 composed of the surface layer portion of the base region 40 from the semiconductor layer 25. The plurality of source regions 41 are formed at intervals inward from both edge portions of each base region 40 with respect to the first direction X, causing both edge portions of each base region 40 to be exposed from the first main surface 21.

[0062] The planar shape of the plurality of source regions 41 is arbitrary. The plurality of source regions 41 can be formed in a square shape when viewed from above, or can be formed in a circular shape (including an elliptical shape). The plurality of source regions 41 are respectively formed in a strip shape extending in the second direction Y in this embodiment.

[0063] The semiconductor device 1 includes one or a plurality of (in this embodiment, a plurality of) p-type base contact regions 43 formed in a region different from the source regions 41 in the surface layer portion of each base region 40. The plurality of base contact regions 43 are respectively formed as a part of the anode region of the first antiparallel diode 13. Each base contact region 43 has a p-type impurity concentration greater than the p-type impurity concentration of each base region 40. The p-type impurity concentration of each base contact region 43 can be 1 x 1018cm-3or more and 1 x 1021cm-3or less. 18 cm -3 -3or more and 1 x 1021cm-3or less. 20 cm -3 -3or more and 1 x 1021cm-3or less.

[0064] The plurality of base contact regions 43 are respectively formed at intervals in the first direction X in the surface layer portion of each base region 40 in this embodiment. The plurality of base contact regions 43 are specifically formed alternately with the plurality of source regions 41 in a manner sandwiching one source region 41. Thus, a cyclic arrangement including the plurality of source regions 41 and the plurality of base contact regions 43 is formed in the surface layer portion of each base region 40. In this embodiment, both the start point and the end point of the cyclic arrangement are formed by the source regions 41. However, either or both of the start point and the end point of the cyclic arrangement can be formed by the base contact regions 43.

[0065] The planar shape of the plurality of base contact regions 43 is arbitrary. The plurality of base contact regions 43 can be formed in a square shape or a circular shape (including an elliptical shape) when viewed from above. The plurality of base contact regions 43 are respectively formed in a band shape extending in the second direction Y in this mode.

[0066] The semiconductor device 1 includes one or a plurality (in this mode, a plurality) of n-type well regions 50 formed in the surface layer portion of the first main face 21 at intervals from the base regions 40 in the diode region 28. The number of the well regions 50 can be adjusted in correspondence with the number of the base regions 40. The plurality of well regions 50 are respectively formed as a part of the cathode region of the first reverse flow blocking diode 13. Each well region 50 divides a drift region 51 with each base region 40. The drift region 51 is adjacent to the channel region 42. Each well region 50 has an n-type impurity concentration greater than that of the semiconductor layer 25. The n-type impurity concentration of each well region 50 is 1 x 1018cm-3or more and 1 x 1020cm-3or less. 15 cm -3 -3or more and 1 x 1020cm-3or less. 17 cm -3 -3or more and 1 x 1020cm-3or less.

[0067] The plurality of well regions 50 are formed at intervals from the buried region 35 toward the first main face 21 side, opposite the buried region 35 with the semiconductor layer 25 interposed therebetween. The plurality of well regions 50 are respectively formed in a ring shape (in this mode, a quadrilateral ring shape) surrounding the corresponding one base region 40 when viewed from above. Thus, each drift region 51 is divided in a ring shape when viewed from above. The planar shape of the well regions 50 is arbitrary, formed in an elliptical ring shape.

[0068] Referring Figure 6 , the plurality of well regions 50 respectively have a well width W. The well width W is the width in a direction orthogonal to the direction in which the well region 50 extends. The well width W can be 0.5 μm or more and 5 μm or less. The well width W is preferably 1 μm or more and 4 μm or less.

[0069] The plurality of well regions 50 respectively include a first region 52 and a second region 53 extending in mutually different directions. The first region 52 extends along the long side (i.e., the first direction X) of the base region 40. The second region 53 extends along the short side (i.e., the second direction Y) of the base region 40. The well width W of the second region 53 can also be different from the well width W of the first region 52. The well width W of the second region 53 is smaller than the well width W of the first region 52 in this mode. Of course, the well width W of the second region 53 can be equal to the well width W of the first region 52 or can be greater than the well width W of the first region 52.

[0070] The first regions 52 of the plurality of well regions 50 are integrally formed between the plurality of base regions 40 adjacent to each other in this mode. By this, the plurality of well regions 50 form one ladder well region that surrounds the plurality of base regions 40 in a ladder shape in plan view. The plurality of first regions 52 are alternately formed with the plurality of base regions 40 in the second direction Y in a manner sandwiching one drift region 51.

[0071] The semiconductor device 1 includes one or a plurality of (in this mode, a plurality of) n-type drain regions 54 formed in a surface layer portion of the plurality of well regions 50. The plurality of drain regions 54 are respectively formed as a part of a cathode region of the first antiflow breakdown diode 13. Each drain region 54 has an n-type impurity concentration greater than an n-type impurity concentration of each well region 50. The n-type impurity concentration of each drain region 54 can be 1 x 1018cm-3or more. 18 cm -3 -3or less. 20 cm -3 -3or less.

[0072] The plurality of drain regions 54 are spaced apart from the second regions 53 of each well region 50 and formed in the surface layer portion of the first regions 52 of each well region 50. The plurality of drain regions 54, specifically, are formed only in the surface layer portion of the first regions 52 of each well region 50 and not formed in the second regions 53. The plurality of drain regions 54 are formed only in regions opposite to the base regions 40 in the second direction Y in the surface layer portion of the first regions 52 in this mode. The first regions 52 of the well regions 50 are formed as effective regions that form a main current path by the plurality of drain regions 54.

[0073] The plurality of drain regions 54 are formed spaced apart in the first direction X in the surface layer portion of the first regions 52 of each well region 50. The plurality of drain regions 54 oppose the plurality of source regions 41 in a one-to-one corresponding relationship in the second direction Y. In accordance with this configuration, the plurality of drain regions 54 form current paths that link the plurality of source regions 41 at the shortest distance in the drift region 51. Therefore, it is possible to reduce a resistance component in the current paths. The plurality of drain regions 54 do not necessarily oppose the plurality of source regions 41 in a one-to-one corresponding relationship. The plurality of drain regions 54 can oppose the plurality of base contact regions 43 in a one-to-one corresponding relationship in the second direction Y.

[0074] The plurality of drain regions 54 are formed spaced apart inward from an edge portion of the first regions 52 of each well region 50 with respect to the second direction Y. The planar shape of the plurality of drain regions 54 is arbitrary. The plurality of drain regions 54 can be formed in a square shape in plan view or in a circular shape (including an elliptical shape). The plurality of drain regions 54 are respectively formed in a strip shape extending in the second direction Y in this mode.

[0075] ReferringFigure 6 The plurality of drain regions 54 each have a first drain width WD1 with respect to the first direction X and a second drain width WD2 with respect to the second direction Y. The first drain width WD1 can be 0.1 μm or more and 3 μm or less. The first drain width WD1 is preferably 0.5 μm or more and 2.5 μm or less. The first drain width WD1 can also be equal to the width of the source region 41 in the first direction X. The second drain width WD2 is preferably smaller than the well width W of the well region 50. The second drain width WD2 can also be 0.1 μm or more and 4 μm or less. The second drain width WD2 is preferably 0.5 μm or more and 3.5 μm or less.

[0076] The semiconductor device 1 includes a plurality of n-type outer drain regions 55 formed in regions outside the plurality of drain regions 54 in the surface layer portion of the plurality of well regions 50. Each of the outer drain regions 55 has an n-type impurity concentration greater than the n-type impurity concentration of each of the well regions 50. Each of the outer drain regions 55 has an n-type impurity concentration equal to the n-type impurity concentration of the drain regions 54.

[0077] The plurality of outer drain regions 55 are each formed in the surface layer portion of the second region 53 of the plurality of well regions 50. The plurality of outer drain regions 55 are further led out from the second region 53 toward the first region 52 in each of the well regions 50, and are formed integrally with the two drain regions 54 located at both ends among the plurality of drain regions 54. The plurality of outer drain regions 55 are formed spaced apart inward from the edge portion of each of the well regions 50. The plurality of outer drain regions 55 suppress unwanted channel inversion in the well regions 50.

[0078] The semiconductor device 1 includes one or a plurality (in this mode, a plurality) of p-type impurity regions 56 formed in the surface layer portion of the plurality of well regions 50. Each of the impurity regions 56 has a p-type impurity concentration greater than the p-type impurity concentration of each of the base regions 40. The p-type impurity concentration of each of the impurity regions 56 can be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 18 -3 The p-type impurity concentration of each of the impurity regions 56 is preferably 1 x 1019cm-3or more and 1 x 1020cm-3or less. 20 -3 The p-type impurity concentration of each of the impurity regions 56 is preferably 1 x 1019cm-3or more and 1 x 1020cm-3or less.

[0079] The plurality of impurity regions 56 are formed in the surface layer portion of the first region 52 of each of the well regions 50, spaced apart from the second region 53. The plurality of impurity regions 56 are formed specifically only in the surface layer portion of the first region 52 of each of the well regions 50, and are not formed in the second region 53. The plurality of impurity regions 56 are formed in this mode only in the region of the surface layer portion of the first region 52 of each of the well regions 50 that is opposite the base region 40 in the second direction Y.

[0080] ​​The plurality of impurity regions 56 are formed in the surface layer portion of the first region 52 of each of the well regions 50 at intervals in the first direction X. The plurality of impurity regions 56 are specifically formed in the surface layer portion of the first region 52 of each of the well regions 50 in such a manner as to alternate with the plurality of drain regions 54 in a manner of sandwiching one drain region 54. That is, the plurality of impurity regions 56 are electrically connected to the plurality of drain regions 54 in the first direction X and are not electrically connected to the plurality of drain regions 54 in the second direction Y.

[0081] The plurality of impurity regions 56 are formed at intervals from the edge portion of the first region 52 of each of the well regions 50 toward the inside. That is, the plurality of impurity regions 56 are electrically connected to the well regions 50 in the second direction Y. The edge portion of the base region 40 side of the plurality of impurity regions 56 is preferably formed inside the well region 50 with respect to the edge portion of the base region 40 side of the plurality of drain regions 54. In this manner, with respect to the second direction Y, both edge portions of the plurality of impurity regions 56 are formed inside the well region 50 with respect to both edge portions of the drain regions 54.

[0082] The plurality of impurity regions 56 are opposed to the plurality of base contact regions 43 in a one-to-one correspondence in the second direction Y. The plurality of impurity regions 56 are not necessarily opposed to the plurality of base contact regions 43 in a one-to-one correspondence. The plurality of impurity regions 56 can also be opposed to the plurality of source regions 41 in a one-to-one correspondence in the second direction Y in accordance with the arrangement of the plurality of drain regions 54.

[0083] The planar shape of the plurality of impurity regions 56 is arbitrary. The plurality of impurity regions 56 are formed in a square shape when viewed from above, and can also be formed in a circular shape (including an elliptical shape). The plurality of impurity regions 56 are in this manner each formed in a strip shape extending in the second direction Y.

[0084] With reference to Figure 6 , the plurality of impurity regions 56 each have a first width W1 with respect to the first direction X and a second width W2 with respect to the second direction Y. The first width W1 can be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 2.5 μm or less. The first width W1 can also be equal to the first drain width WD1 of the drain regions 54. The first width W1 can also be equal to the width of the base contact regions 43 in the first direction X. The second width W2 is smaller than the second drain width WD2 of the drain regions 54. The second width W2 can also be 0.1 μm or more and 3.5 μm or less. The second width W2 is preferably 0.5 μm or more and 3 μm or less.

[0085] The semiconductor device 1 includes, in the diode region 28, p-type guard regions 60 formed in the surface layer portion of the first main face 21 at intervals from the plurality of well regions 50 to the side opposite the plurality of base regions 40. The guard regions 60 are specifically formed in the surface layer portion of the first main face 21 between the region separation structure 30 and the plurality of well regions 50.

[0086] The guard regions 60 are formed at intervals from the buried regions 35 to the first main face 21 side, opposite the buried regions 35 through a portion of the semiconductor layer 25. The guard regions 60 are formed in a ring shape (in this case, a quadrilateral ring shape) that encloses the plurality of well regions 50 in plan view. The guard regions 60 block the leakage current path formed between the region separation structure 30 and the plurality of base regions 40.

[0087] The guard regions 60 include guard well regions 61 and guard contact regions 62. The guard well regions 61 are formed in the surface layer portion of the first main face 21. The guard well regions 61 are specifically formed at a depth position between the first main face 21 and the column buried regions 32 in the semiconductor layer 25. The p-type impurity concentration of the guard well regions 61 can be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 15 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 17 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less.

[0088] The guard well regions 61 can be formed at the same depth as the column well regions 33. The guard well regions 61 can have the same p-type impurity concentration as the p-type impurity concentration of the column well regions 33. According to this configuration, the guard well regions 61 and the column well regions 33 can be formed by the same process.

[0089] The guard contact regions 62 are formed in the surface layer portion of the guard well regions 61 at intervals from the bottom of the guard well regions 61 to the first main face 21 side. The guard contact regions 62 have a p-type impurity concentration greater than the p-type impurity concentration of the guard well regions 61. The p-type impurity concentration of the guard contact regions 62 can also be 1 x 1018cm-3or more and 1 x 1020cm-3or less. 18 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 20 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less.

[0090] The guard contact regions 62 can be formed at the same depth as the column contact regions 34. The guard contact regions 62 can have the same p-type impurity concentration as the p-type impurity concentration of the column contact regions 34. According to this configuration, the guard contact regions 62 and the column contact regions 34 can be formed by the same process.

[0091] The semiconductor device 1 includes an n-type channel stop region 65 formed in the semiconductor layer 25 at a position spaced apart from the guard region 60 toward the side opposite to the plurality of well regions 50 in the diode region 28. Hereinafter, "channel stop" is abbreviated as "CS". The CS region 65 is formed in the diode region 28 in a region between the region separation structure 30 and the guard region 60 in the surface layer portion of the first main face 21. The CS region 65 is formed along the peripheral edge of the diode region 28. The CS region 65 is specifically formed in a ring shape (in this case, a four-sided ring shape) surrounding the guard region 60 in plan view.

[0092] The CS region 65 is formed in the semiconductor layer 25 in a wall shape in electrical connection with the buried region 35. The CS region 65 specifically includes a CS buried region 66, a CS well region 67, and a CS surface layer region 68.

[0093] The CS buried region 66 is formed across the boundary between the buried region 35 and the semiconductor layer 25, in electrical connection with the buried region 35. In this case, one CS buried region 66 is formed, but the number of CS buried regions 66 is arbitrary as long as it is in electrical connection with the buried region 35. A plurality of CS buried regions 66 can be stacked from the buried region 35 toward the first main face 21 side. The n-type impurity concentration of the CS buried region 66 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less. 16 cm -3 The n-type impurity concentration of the CS buried region 66 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less. 20 cm -3 The n-type impurity concentration of the CS buried region 66 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less.

[0094] The CS well region 67 is formed in the surface layer portion of the first main face 21. The CS well region 67 is specifically formed in the semiconductor layer 25 in a region between the first main face 21 and the CS buried region 66, in electrical connection with the CS buried region 66. The CS buried region 66 can have an n-type impurity concentration smaller than the n-type impurity concentration of the CS buried region 66. The n-type impurity concentration of the CS well region 67 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less. 16 cm -3 The n-type impurity concentration of the CS well region 67 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less. 20 cm -3 The n-type impurity concentration of the CS well region 67 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less.

[0095] The CS surface layer region 68 is formed in the surface layer portion of the CS well region 67 at a position spaced apart from the bottom of the CS well region 67 toward the first main face 21 side. The CS surface layer region 68 has an n-type impurity concentration greater than the n-type impurity concentration of the CS well region 67. The n-type impurity concentration of the CS surface layer region 68 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less. 18 cm -3 The n-type impurity concentration of the CS surface layer region 68 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less. 20 cm -3 The n-type impurity concentration of the CS surface layer region 68 can be 1 x 1016cm-2or more and 1 x 1020cm-3or less. The CS surface layer region 68 can have an n-type impurity concentration equal to that of the source region 41 (drain region 54).

[0096] The semiconductor device 1 includes an insulating film 70 that selectively covers the first main face 21. The insulating film 70 is composed of a field oxide film in this mode. The field oxide film is also called a LOCOS (local oxidation of silicon) film. The insulating film 70 exposes the region separation structure 30, the plurality of base regions 40, the plurality of well regions 50, the guard region 60, and the CS region 65, and is formed on the first main face 21 in a manner of covering the drift region 51. The insulating film 70 specifically includes a plurality of first insulating films 70A, one second insulating film 70B, one third insulating film 70C, one fourth insulating film 70D, and one fifth insulating film 70E.

[0097] The plurality of first insulating films 70A are respectively formed in regions between the corresponding base regions 40 and the well regions 50 in a manner of respectively covering the corresponding drift regions 51. Each first insulating film 70A is formed in a ring shape that surrounds the corresponding base region 40 in plan view. An inner end portion of each first insulating film 70A covers an edge portion of the base region 40, and exposes the channel region 42, the source region 41, and the base contact region 43.

[0098] An outer end portion of each first insulating film 70A covers an inner edge portion of the well region 50, and exposes an inner portion of the well region 50, the drain region 54, the outer side drain region 55, and the impurity region 56. The outer end portion of each first insulating film 70A specifically covers edge portions of the plurality of drain regions 54 (the outer side drain region 55), and exposes edge portions of the plurality of impurity regions 56. Thereby, the outer end portion of each first insulating film 70A exposes the well region 50 from a region between the edge portions of the plurality of impurity regions 56.

[0099] The second insulating film 70B is formed in a region between the well region 50 and the guard region 60. The second insulating film 70B is formed in a ring shape that surrounds the well region 50 in plan view. An inner end portion of the second insulating film 70B covers an outer edge portion of the well region 50, and exposes the outer side drain region 55. The inner end portion of the second insulating film 70B specifically covers edge portions of the plurality of outer side drain regions 55, and exposes inner portions of the plurality of outer side drain regions 55.

[0100] The inner end portion of the second insulating film 70B further covers the outer edge portion of the outermost well region 50, and exposes the inner portion of the well region 50, the drain region 54, the outer drain region 55, and the impurity region 56. The inner end portion of the second insulating film 70B specifically covers the edge portions of the plurality of drain regions 54 (the outer drain region 55), and exposes the edge portions of the plurality of impurity regions 56. Thus, the inner end portion of the second insulating film 70B exposes the well region 50 from the region between the edge portions of the plurality of impurity regions 56. The outer end portion of the second insulating film 70B covers the edge portion of the guard region 60, and exposes the inner portion of the guard region 60.

[0101] The third insulating film 70C is formed in the region between the guard region 60 and the CS region 65. The third insulating film 70C is formed in a ring shape that surrounds the guard region 60 in plan view. The inner end portion of the third insulating film 70C covers the outer edge portion of the guard region 60, and exposes the inner portion of the guard region 60. The outer end portion of the third insulating film 70C covers the inner edge portion of the CS region 65, and exposes the inner portion of the CS region 65.

[0102] The fourth insulating film 70D is formed in the region between the CS region 65 and the region separation structure 30 (the column region 31). The fourth insulating film 70D is formed in a ring shape that surrounds the CS region 65 in plan view. The inner end portion of the fourth insulating film 70D covers the outer edge portion of the CS region 65, and exposes the inner portion of the CS region 65. The outer end portion of the fourth insulating film 70D covers the inner edge portion of the region separation structure 30 (the column region 31), and exposes the inner portion of the region separation structure 30 (the column region 31).

[0103] The fifth insulating film 70E is formed in the region outside the region separation structure 30 (the column region 31). The fifth insulating film 70E covers the outer edge portion of the region separation structure 30 (the column region 31), and exposes the inner portion of the region separation structure 30 (the column region 31).

[0104] The semiconductor device 1 includes a plurality of gate structures 71 formed on the first main face 21 in the diode region 28. The plurality of gate structures 71 are respectively formed on the plurality of channel regions 42 exposed from the insulating film 70. That is, the plurality of gate structures 71 are respectively formed in the regions surrounded by the inner end portions of the plurality of first insulating films 70A. The plurality of gate structures 71 respectively have a stacked structure including a gate insulating film 72 and a gate electrode 73 stacked in this order from the first main face 21 side.

[0105] The gate insulating film 72 has a thickness smaller than that of the insulating film 70. The gate insulating film 72 can include silicon oxide. The gate insulating film 72 covers the channel region 42, the edge portion of the source region 41, and the edge portion of the base contact region 43. The gate insulating film 72 is specifically formed in a ring shape including an inner end portion and an outer end portion in plan view.

[0106] The inner end portion of the gate insulating film 72 divides the contact opening 74. The contact opening 74 exposes the inner portion of the base region 40, the inner portions of the plurality of source regions 41, and the inner portions of the plurality of base contact regions 43. The contact opening 74 is formed in a belt shape extending in the first direction X in this mode. The outer end portion of the gate insulating film 72 is connected to the insulating film 70 (the inner end portion of the first insulating film 70A).

[0107] The gate electrode 73 contains conductive polysilicon in this mode. The gate electrode 73 is formed on the gate insulating film 72 and opposes the channel region 42 with the gate insulating film 72 interposed therebetween. The gate electrode 73 has an extraction portion 75 extracted from the gate insulating film 72 to the insulating film 70 (the first insulating film 70A). The extraction portion 75 of the gate electrode 73 opposes the drift region 51 with the insulating film 70 (the first insulating film 70A) interposed therebetween.

[0108] The gate electrode 73 specifically includes an inner end portion and an outer end portion in plan view and is formed in a ring shape surrounding the base region 40. The inner end portion of the gate electrode 73 divides the contact opening 74 together with the inner end portion of the gate insulating film 72.

[0109] The outer end portion of the gate electrode 73 is formed by the extraction portion 75 and is formed on the insulating film 70 spaced apart from the inner end portion of the well region 50 inward in plan view. The outer end portion of the gate electrode 73 is in a region between the base region 40 and the well region 50 in plan view in this mode. The outer end portion of the gate electrode 73 is formed in a quadrangular shape (specifically, an oblong shape extending in the first direction X) in plan view. The planar shape of the outer end portion of the gate electrode 73 is arbitrary and can be formed in an oblong shape.

[0110] The plurality of source regions 41 and the plurality of base contact regions 43 can be formed in self-alignment with respect to the gate electrode 73, respectively. That is, the plurality of source regions 41 and the plurality of base contact regions 43 can be formed by introducing n-type impurities and p-type impurities through ion implantation masks that expose at least the inner end portion of the gate electrode 73. In this case, a cyclic arrangement of n-type regions and p-type regions corresponding to the cyclic arrangement of the plurality of source regions 41 and the plurality of base contact regions 43 is formed at least in the inner end portion of the gate electrode 73.

[0111] The semiconductor device 1 includes an interlayer insulating film 80 formed on the first main face 21. The interlayer insulating film 80 is formed on the insulating film 70, and covers portions of the region separation structure 30 (the column region 31), the plurality of base regions 40, the plurality of source regions 41, the plurality of base contact regions 43, the plurality of well regions 50, the plurality of drain regions 54, the plurality of outer drain regions 55, the plurality of impurity regions 56, the guard region 60, and the CS region 65 that are exposed from the insulating film 70.

[0112] The semiconductor device 1 includes one or a plurality (in this mode, one) of region separation connection electrodes 81, a plurality of source connection electrodes 82, a plurality of drain connection electrodes 83, one or a plurality (in this mode, one) of guard connection electrodes 84, and a plurality of gate connection electrodes 86.

[0113] The region separation connection electrode 81 penetrates the interlayer insulating film 80, and is electrically connected to the region separation structure 30 (the column contact region 34). The region separation connection electrode 81 is fixed to a substrate potential (for example, a ground potential). The region separation connection electrode 81 can be formed in a band shape (specifically, a ring shape) extending along the region separation structure 30 in plan view. A plurality of region separation connection electrodes 81 can also be formed spaced apart along the region separation structure 30 in plan view.

[0114] The plurality of source connection electrodes 82 penetrate the interlayer insulating film 80, and are respectively electrically connected to the corresponding base regions 40, the corresponding plurality of source regions 41, and the corresponding plurality of base contact regions 43. The plurality of source connection electrodes 82 are fixed to a gate potential. That is, the plurality of source connection electrodes 82 are fixed to the same potential as the gate electrode 73.

[0115] The plurality of source connection electrodes 82 are respectively formed in a band shape that cuts the plurality of source regions 41 and the plurality of base contact regions 43 in the first direction X within the corresponding contact opening 74. Both end portions of the plurality of source connection electrodes 82 are respectively electrically connected to both edge portions of the corresponding base region 40. Thus, the base region 40, the source region 41, and the base contact region 43 are fixed to the same potential (the gate potential).

[0116] The plurality of drain connection electrodes 83 penetrate the interlayer insulating film 80, and are respectively electrically connected to the corresponding plurality of drain regions 54 and the corresponding plurality of impurity regions 56. The plurality of drain connection electrodes 83 are fixed to a drain potential. The plurality of drain connection electrodes 83 are respectively formed in a band shape that cuts the plurality of drain regions 54 and the plurality of impurity regions 56 in the first direction X.

[0117] Two end portions of the plurality of drain connection electrodes 83 are connected to the both end drain regions 54, respectively. That is, the plurality of drain connection electrodes 83 are electrically connected to the plurality of outer drain regions 55 via the both end drain regions 54. Thereby, the well region 50, the drain region 54, the outer drain region 55 and the impurity region 56 are fixed to the same potential (drain potential).

[0118] The guard connection electrode 84 penetrates the interlayer insulating film 80, and is electrically connected to the guard region 60. The guard connection electrode 84 is fixed to the same potential (drain potential) as the plurality of drain connection electrodes 83. That is, the guard region 60 is fixed to the same potential as the drain region 54 or the like. The guard connection electrode 84 can be formed in a band shape (specifically, a ring shape) extending along the guard region 60 in plan view. The plurality of guard connection electrodes 84 can be formed at intervals along the guard region 60 in plan view.

[0119] The plurality of gate connection electrodes 86 penetrate the interlayer insulating film 80, and are electrically connected to the corresponding gate electrodes 73, respectively. The plurality of gate connection electrodes 86 are specifically electrically connected to an arbitrary position of the lead-out portion 75 of the corresponding gate electrode 73, respectively. The plurality of gate connection electrodes 86 are electrically connected to both end portions of the plurality of gate electrodes 73 with respect to the first direction X, respectively, in this mode. In Figure 7 and Figure 8 In the and, the gate connection electrode 86 is illustrated for the sake of convenience in order to indicate the connection mode. The plurality of gate connection electrodes 86 are fixed to the gate potential. That is, the gate electrode 73 is fixed to the same potential as the base region 40, the source region 41 and the base contact region 43 or the like.

[0120] Referring to Figure 7 , the first reverse flow blocking diode 13 includes an EIS (Electrode-Insulator-Semiconductor) type diode configuration 90. The diode configuration 90 specifically includes the p-type base region 40, the n-type source region 41, the p-type base contact region 43, the n-type well region 50, the n-type drain region 54 and the gate configuration 71.

[0121] Referring to Figure 8 , the first reverse flow blocking diode 13 includes a silicon controlled configuration 91 electrically connected to the diode configuration 90. The silicon controlled configuration 91 specifically includes the p-type impurity region 56, the n-type semiconductor layer 25, the p-type base region 40 and the n-type source region 41 formed in this order along the first main face 21 of the semiconductor layer 25.

[0122] The thyristor structure 91 specifically further includes a first transistor structure 92 of pnp type (first polarity type) on the side of the well region 50, and a second transistor structure 93 of npn type (second polarity type) on the side of the base region 40. The first transistor structure 92 includes, in order along the first main face 21 of the semiconductor layer 25, a p-type impurity region 56, an n-type semiconductor layer 25, and a p-type base region 40. The second transistor structure 93 includes, in order along the first main face 21 of the semiconductor layer 25, an n-type source region 41, a p-type base region 40, and an n-type semiconductor layer 25.

[0123] When a forward voltage VF of the diode structure 90 is applied to the source connection electrode 82 (gate electrode 73) and the drain connection electrode 83, the diode structure 90 becomes an on state, and the thyristor structure 91 becomes an off state. The thyristor structure 91 becomes an off state because the drain region 54 and the impurity region 56 are fixed to the same potential. Thereby, the diode structure 90 is turned on, and a forward current IF flows to the diode structure 90. This forward voltage VF further flows to the first transistor structure 92 electrically connected to the diode structure 90.

[0124] On the other hand, when a reverse voltage VR of the diode structure 90 is applied to the source connection electrode 82 (gate electrode 73) and the drain connection electrode 83, the diode structure 90 becomes an off state, and the thyristor structure 91 becomes an on state. Thereby, the thyristor structure 91 is turned on, and a reverse current IR flows to the thyristor structure 91.

[0125] Figure 9 is a graph showing the current-voltage characteristics of the reverse current blocking diode of the comparative example. Figure 10 is a graph showing the current-voltage characteristics of the first reverse current blocking diode 13 of the present embodiment. Figure 9 and Figure 10 The current-voltage characteristics shown in and were investigated using a known TLP (Transmission Line Pulse) measurement method.

[0126] In Figure 9 and Figure 10 The vertical axis is current [A] and the horizontal axis is voltage [V] in and. Positive current means forward current IF, and negative current means reverse current IR. Positive voltage means forward voltage VF, and negative voltage means reverse voltage VR. The reverse current blocking diode of the comparative example does not have the impurity region 56. That is, the reverse current blocking diode of the comparative example has only the diode structure 90, and does not have the thyristor structure 91.

[0127] In the reverse current blocking diode of the comparative example, the forward current IF that causes electrostatic breakdown is +5 A or so, and the reverse current IR that causes electrostatic breakdown is -0.5 A or so. In contrast, in the first reverse current blocking diode 13 of the present embodiment, the forward current IF that causes electrostatic breakdown is +25 A or so, and the reverse current IR that causes electrostatic breakdown is -24 A or so. In the first reverse current blocking diode 13 of the present embodiment, the electrostatic surge resistance is improved in both the forward and reverse directions compared to the reverse current blocking diode of the comparative example.

[0128] In the first reverse current blocking diode 13 of the present embodiment, unlike the reverse current blocking diode of the comparative example, in the case where a forward overvoltage caused by static electricity or the like is applied, a forward overcurrent can be handled by the diode configuration 90 and the first transistor configuration 92.

[0129] In addition, in the first reverse current blocking diode 13 of the present embodiment, in the case where a reverse overvoltage caused by static electricity or the like is applied, a reverse overcurrent can be handled by the thyristor configuration 91. As a result, in the first reverse current blocking diode 13 of the present embodiment, the electrostatic surge resistance is improved compared to the reverse current blocking diode of the comparative example.

[0130] Thus, according to the semiconductor device 1, the electrostatic surge resistance can be improved. In particular, in the configuration in which the thyristor configuration 91 is assembled, the effect of improving the electrostatic surge resistance on the forward voltage VF (forward current IF) side caused by the first transistor configuration 92 is a different property that cannot be achieved by a conventional thyristor device that is used as a protection device against a reverse voltage VR.

[0131] In addition, according to the semiconductor device 1, the impurity region 56 is formed in the surface layer portion of the well region 50 at intervals from the edge portion of the well region 50 toward the inner side. According to this configuration, with respect to the lateral direction parallel to the first main surface 21, a portion of the well region 50 exists in the region between the impurity region 56 and the semiconductor layer 25, and a base resistance of the first transistor configuration 92 is formed by this portion of the well region 50. Thus, the thyristor configuration 91 can be caused to operate properly.

[0132] For example, in the case where a drain region 54 is formed in the surface layer portion of the well region 50 in the region between the impurity region 56 and the semiconductor layer 25, the base of the first transistor configuration 92 is short-circuited to the emitter of the first transistor configuration 92 by the drain region 54 that is a comparatively low resistance. Therefore, the operation of the thyristor configuration 91 becomes unstable.

[0133] Therefore, in the semiconductor device 1, the edge portion of the base region 40 side of the impurity region 56 is formed inward of the well region 50 with respect to the edge portion of the base region 40 side of the drain region 54. According to this configuration, it is possible to appropriately suppress a condition in which the base and the emitter of the first transistor configuration 92 are short-circuited through the drain region 54. Thus, it is possible to make the silicon controlled rectifier configuration 91 more appropriately function. In addition, according to this configuration, in a case where an overvoltage is applied between the drain region 54 and the source region 41, it is possible to suppress breakdown between the drain region 54 and the source region 41. Thus, it is possible to suppress a decrease in the breakdown voltage.

[0134] In addition, according to the semiconductor device 1, the impurity region 56 is opposed to the drain region 54 in a direction orthogonal to the opposite directions of the base region 40 and the well region 50. According to this configuration, it is possible to form the silicon controlled rectifier configuration 91 on a line connecting the base region 40 and the impurity region 56. Thus, it is possible to appropriately suppress the function of the silicon controlled rectifier configuration 91 from being hindered by the drain region 54.

[0135] In addition, the semiconductor device 1 includes a p-type guard region 60 formed in a region of the column region 31 and the well region 50 in a surface layer portion of the first main surface 21. The guard region 60 is fixed to the same potential as the drain region 54 or the like. Specifically, the semiconductor device 1 includes a drain connection electrode 83 connected to the drain region 54 or the like on the first main surface 21, and a guard connection electrode 84 electrically connected to the guard region 60 on the first main surface 21, which is fixed to the same potential as the drain connection electrode 83.

[0136] In a region between the column region 31 and the base region 40 in the diode region 28, a first parasitic transistor of a pnp type (first polarity type) including the p-type base region 40, the n-type semiconductor layer 25, and the p-type column region 31 is formed. In a case where a forward voltage VF of the diode configuration 90 is applied to the source connection electrode 82 (gate electrode 73) and the drain connection electrode 83, a leakage current flows to the column region 31 via the first parasitic transistor.

[0137] Therefore, in the semiconductor device 1, the guard region 60 is formed in a region between the column region 31 and the well region 50. According to this configuration, in a region between the column region 31 and the base region 40 in the diode region 28, a second parasitic transistor of a pnp type (first polarity type) including the p-type base region 40, the n-type semiconductor layer 25, and the p-type guard region 60 is formed.

[0138] Thus, in the case where the forward voltage VF of the diode configuration 90 is applied, the leakage current can flow into the guard connection electrode 84 via the second parasitic transistor. As a result, the leakage current can be reduced without being hindered by the thyristor configuration 91. Reducing the leakage current is effective in improving the electrical characteristics of the diode region 28, and is also effective in suppressing variations in the electrical characteristics of the other functional device region 27 caused by the leakage current.

[0139] The embodiments of the present application can be further implemented in other ways.

[0140] In the above-described embodiments, the example in which the insulating film 70 is formed of a field oxide film has been described. However, the insulating film 70 can also be embedded in a trench. In this case, an STI (shallow trench isolation) configuration can also be formed by the trench and the insulating film 70.

[0141] In the above-described embodiments, the example in which the "first conductivity type" is "p-type" and the "second conductivity type" is "n-type" has been described, but the "first conductivity type" can also be "n-type" and the "second conductivity type" can be "p-type". The specific structure in this case can be obtained by replacing the "n-type region" with a "p-type region" and replacing the "p-type region" with an "n-type region" in the above-described description and the drawings. In the above-described embodiments, the example in which the "p-type" is indicated as the "first conductivity type" and the "n-type" is indicated as the "second conductivity type" has been described for the order of clear description, but the "p-type" can also be indicated as the "second conductivity type" and the "n-type" can be indicated as the "first conductivity type".

[0142] In the above-described embodiments, the example in which the first reverse current blocking diode 13 (the second reverse current blocking diode 17) is assembled in the circuit portion of the CAN has been described. However, the first reverse current blocking diode 13 (the second reverse current blocking diode 17) can also be assembled in the circuit portion of various applications other than the CAN. For example, the first reverse current blocking diode 13 (the second reverse current blocking diode 17) can be assembled in the circuit portion of a vehicle-mounted network such as a LIN (Local Interconnect Network), FlexRay, etc., the circuit portion of a vehicle-mounted switch IC, the circuit portion of a DC / DC converter, etc. The first reverse current blocking diode 13 (the second reverse current blocking diode 17) can also be assembled in the circuit portion of an application other than a vehicle-mounted application.

[0143] The following shows examples of features extracted from the specification and drawings. The EIS-type diode configuration has a configuration feature of low electrostatic surge tolerance. The electrostatic surge tolerance is also referred to as ESD (electro static discharge) tolerance. The following [A1] to [A17] provide a semiconductor device that has an EIS-type diode configuration and that is capable of improving the electrostatic surge tolerance.

[0144] [A1] A semiconductor device, comprising: a semiconductor layer of a first conductivity type having a main face and including a device region; a base region of a second conductivity type formed in a surface layer portion of the main face in the device region; a source region of the first conductivity type formed apart from an edge portion of the base region inwardly in a surface layer portion of the base region, a channel region being divided between the source region and the semiconductor layer; a base contact region of the second conductivity type formed in a region different from the source region in the surface layer portion of the base region, having an impurity concentration greater than an impurity concentration of the base region; a well region of the first conductivity type formed apart from the base region inwardly in a surface layer portion of the main face in the device region, a drift region being divided between the well region and the base region; a drain region of the first conductivity type formed in a surface layer portion of the well region; an impurity region of the second conductivity type formed in a surface layer portion of the well region, and electrically connected to the drain region; and a gate configuration having a gate insulating film covering the channel region over the main face, and a gate electrode opposing the channel region over the gate insulating film, and electrically connected to the source region and the base contact region.

[0145] The semiconductor device includes the EIS-type diode configuration in the device region. The diode configuration specifically includes the base region, the source region, the base contact region, the well region, the drain region, and the gate configuration. In addition, the semiconductor device includes a thyristor configuration electrically connected to the diode configuration in the device region. The thyristor configuration specifically includes the impurity region (second conductivity type), the semiconductor layer (first conductivity type), the base region (second conductivity type), and the source region (first conductivity type) formed in this order along the main face of the semiconductor layer.

[0146] The thyristor configuration further specifically includes a first transistor configuration of a first polarity on the well region side, and a second transistor configuration of a second polarity on the base region side. The first transistor configuration includes the impurity region (second conductivity type), the semiconductor layer (first conductivity type), and the base region (second conductivity type) formed in this order along the main face of the semiconductor layer. The second transistor configuration includes the source region (first conductivity type), the base region (second conductivity type), and the semiconductor layer (first conductivity type) formed in this order along the main face of the semiconductor layer.

[0147] When a forward voltage is applied to the diode configuration, the diode configuration becomes an on state, and the thyristor configuration becomes an off state. The thyristor configuration becomes an off state because the drain region and the impurity region are fixed to the same potential. Thus, the diode configuration is turned on, and a forward current flows to the diode configuration. This forward voltage further flows to the first transistor configuration electrically connected to the diode configuration. Therefore, in a case where a forward overvoltage caused by static electricity or the like is applied to the diode configuration, a forward overcurrent can be handled by the diode configuration and the first transistor configuration.

[0148] On the other hand, in a case where a reverse voltage is applied to the diode configuration, the diode configuration becomes an off state, and the thyristor configuration becomes an on state. Thus, the thyristor configuration is turned on, and a reverse current flows to the thyristor configuration. Therefore, in a case where a reverse overvoltage caused by static electricity or the like is applied to the diode configuration, a reverse overcurrent can be handled by the thyristor configuration. Thus, the electrostatic surge tolerance can be improved according to the semiconductor device.

[0149] [A2] In the semiconductor device according to A1, the impurity region is formed inwardly from an edge portion of the well region with a gap.

[0150] [A3] In the semiconductor device according to A1 or A2, the impurity region is connected to the drain region in a direction orthogonal to the relative direction of the base region and the well region.

[0151] [A4] In the semiconductor device according to any one of A1 to A3, a plurality of the impurity regions are formed in a manner of sandwiching one of the drain regions.

[0152] [A5] In the semiconductor device according to any one of A1 to A4, a plurality of the drain regions are formed with a gap.

[0153] [A6] In the semiconductor device according to any one of A1 to A5, the base region is formed in a band shape extending in one direction in plan view, and the impurity region is formed in the well region in a region opposite to the long side of the base region.

[0154] [A7] In the semiconductor device according to any one of A1 to A6, the well region is formed in a ring shape surrounding the base region in plan view, and the gate electrode is formed in a ring shape surrounding the base region in a region between the base region and the well region in plan view.

[0155] [A8] The semiconductor device according to any one of A1 to A7, further comprising a region separation structure formed on the main surface and electrically separating the device region from another region.

[0156] [A9] The semiconductor device according to A8, wherein the region separation structure is constituted by a pillar region of the second conductivity type formed in the semiconductor layer.

[0157] [A10] The semiconductor device according to A9, further comprising a guard region of the second conductivity type formed in a region between the well region and the pillar region in a surface layer portion of the main surface, and electrically connected to the drain region.

[0158] [A11] The semiconductor device according to any one of A1 to A10, wherein the base contact region is formed in a surface layer portion of the base region spaced apart from an edge portion of the base region inwardly, and electrically connected to the source region.

[0159] [A12] The semiconductor device according to any one of A1 to A11, further comprising an insulating film covering the drift region on the main surface, the gate insulating film having a thickness smaller than a thickness of the insulating film, and being continuous with the insulating film.

[0160] [A13] The semiconductor device according to A12, wherein the gate electrode includes a lead-out portion led out from above the gate insulating film to above the insulating film, and opposing the drift region through the insulating film.

[0161] [A14] The semiconductor device according to any one of A1 to A13, further comprising a semiconductor substrate of the second conductivity type, the semiconductor layer being laminated on the semiconductor substrate.

[0162] [A15] The semiconductor device according to A14, further comprising a buried region of the first conductivity type formed in the device region across a boundary between the semiconductor substrate and the semiconductor layer, the base region and the well region opposing the buried region through a portion of the semiconductor layer.

[0163] [A16] The semiconductor device according to A15, further comprising a channel stop region of the first conductivity type formed in the semiconductor layer in the device region in a manner along a peripheral edge of the device region.

[0164] [A17] The semiconductor device according to A16, wherein the channel stop region extends in a wall shape toward the buried region, and is electrically connected to the buried region.

[0165] This application corresponds to Japanese Patent Application No. 2019-217069, filed November 29, 2019, to the Japan Patent Office, the disclosure of which is incorporated herein by reference in its entirety. Embodiments of the present invention are described in detail, which are specific examples used to make the technical content of the present invention more apparent, the present invention should not be interpreted by these specific examples, the scope of the present invention is defined by the scope of the additional technical solutions.

[0166] Explanation of Reference Signs

[0167] 1 Semiconductor Device

[0168] 3 First Main Surface

[0169] 6 Semiconductor Substrate

[0170] 7 Semiconductor Layer

[0171] 28 Diode Region (Device Region)

[0172] 31 Column Region

[0173] 35 Buried Region

[0174] 40 Base Region

[0175] 41 Source Region

[0176] 42 Channel Region

[0177] 43 Base Contact Region

[0178] 50 Well Region

[0179] 51 Drift Region

[0180] 54 Drain Region

[0181] 56 Impurity Region

[0182] 60 Guard Region

[0183] 65 Channel Stop Region

[0184] 70 Insulating Film

[0185] 71 Gate Structure

[0186] 72 Gate Insulating Film

[0187] 73 Gate Electrode

[0188] 73 Lead-Out Portion

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer of a first conductivity type, having a main surface and including a device region; The base region of the second conductivity type is formed in the surface portion of the main surface in the device region; The source region of the first conductivity type is formed in the surface portion of the base region at intervals from the edge of the base region inward, and a channel region is defined between the source region and the semiconductor layer. The base contact region of the second conductivity type is formed in the surface portion of the base region in a region different from the source region, and has an impurity concentration that is greater than that of the base region. A first conductivity type well region is formed on the surface portion of the main surface in the device region at a distance from the base region, and a drift region is defined between the well region and the base region. The drain region of the first conductivity type is formed on the surface portion of the well region; A second conductivity type of impurity region is formed on the surface of the well region and is electrically connected to the drain region. and A gate configuration having a gate insulating film and a gate electrode, the gate insulating film covering the channel region on the main surface, and the gate electrode facing the channel region on the gate insulating film. The gate electrode is electrically connected to the source region and the base contact region.

2. The semiconductor device as described in claim 1, characterized in that: The impurity regions are formed at intervals from the edge of the trap region inward.

3. The semiconductor device as described in claim 1, characterized in that: The base region and the well region are spaced apart from each other in a first direction. The impurity region extends in a second direction orthogonal to the first direction and is connected to the drain region.

4. The semiconductor device as claimed in claim 1, characterized in that: The plurality of said impurity regions are formed in such a way that they sandwich the said drain region.

5. The semiconductor device as claimed in claim 1, characterized in that: Multiple drain regions are formed at intervals.

6. The semiconductor device as claimed in claim 1, characterized in that: The base region, when viewed from above, forms a band extending in one direction. The impurity region is formed in the well region in the region opposite to the long side of the base region.

7. The semiconductor device as claimed in claim 1, characterized in that: The well region, when viewed from above, forms a ring surrounding the base region. When viewed from above, the gate electrode is formed in a ring shape surrounding the base region in the region between the base region and the well region.

8. The semiconductor device as claimed in claim 1, characterized in that: It also includes a region separation structure formed on the main surface that electrically separates the device region from other regions.

9. The semiconductor device as claimed in claim 8, characterized in that: The region separation structure is composed of pillar regions of a second conductivity type formed in the semiconductor layer.

10. The semiconductor device as claimed in claim 9, characterized in that: It also includes a second conductive type of protective region, which is formed in the surface portion of the main surface in the region between the well region and the pillar region, and is electrically connected to the drain region.

11. The semiconductor device as claimed in claim 1, characterized in that: The base contact region is formed in the surface portion of the base region at intervals from the edge of the base region inward, and is electrically connected to the source region.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that: It also includes an insulating film covering the drift region on the main surface. The gate insulating film has a thickness smaller than that of the insulating film and is connected to the insulating film.

13. The semiconductor device as claimed in claim 12, characterized in that: The gate electrode includes a lead-out portion that extends from the gate insulating film onto the insulating film and is opposite to the drift region across the insulating film.

14. The semiconductor device according to any one of claims 1 to 11, characterized in that: It also includes semiconductor substrates of the second conductivity type. The semiconductor layer is stacked on the semiconductor substrate.

15. The semiconductor device as claimed in claim 14, characterized in that: It also includes a buried region of a first conductivity type, which is formed across the boundary between the semiconductor substrate and the semiconductor layer in the device region. The base region and the well region are opposite the buried region, separated by a portion of the semiconductor layer.

16. The semiconductor device as claimed in claim 15, characterized in that: It also includes a channel stop region of a first conductivity type, which is formed in the semiconductor layer in the device region in such a manner as to follow the peripheral edge of the device region.

17. The semiconductor device as claimed in claim 16, characterized in that: The trench stopping area extends into the burial area in a wall-like shape and is electrically connected to the burial area.

18. The semiconductor device according to any one of claims 1 to 11, characterized in that, Also includes: An interlayer insulating film is formed on the main surface; and A connecting electrode that penetrates the interlayer insulating film and is electrically connected to the base region, the source region, and the base contact region. The connection electrode is fixed at the same potential as the gate electrode.

Images