A method, system and related components for determining test cases

Abstract

The present application discloses a test case determination method, system and related components. The method includes: receiving target test parameters; querying whether there is a test excitation sequence corresponding to the target test parameters in the excitation pool; if not, generating the test excitation sequence according to the target test parameters and test functions; and outputting the test excitation sequence to generate a test case for verifying the design under test. The present application automatically outputs a test excitation sequence according to the target test parameters, and the excitation sequence can directly generate a test case for verifying the design under test, avoiding complicated manual configuration and process sorting, and having the advantages of flexible reuse and utilization of project iteration.

Description

Technical Field

[0001] The present invention relates to the field of system testing, and particularly to a method, a system and related components for determining test cases. Background Art

[0002] Currently, test verification is a crucial process in the chip development process and is the key point for determining whether the design under test works properly and correctly. At present, the most common verification method is to use the UVM (Universal Verification Methodology) method. From building a UVM verification platform to developing test cases based on the SV language, the stimulus sequence is the most important part, which is used to generate test stimuli to make the device under test work and then observe the test results.

[0003] When the device under test is at the SoC (System on Chip) level, due to its large scale, a large number of debugging resources need to be debugged, which will undoubtedly increase the debugging complexity of the verification personnel. When compiling test cases developed based on the SV (System Verilog) language, it will involve the compilation of the entire UVM verification environment and then generate an executable file (simv). This process takes a long time and consumes a large amount of server resources. It is not suitable to modify test cases frequently, and it lacks flexibility for devices under test with high test case requirements.

[0004] Therefore, how to provide a solution to solve the above technical problems is what those skilled in the art need to solve currently. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide an efficient and fast method, a system and related components for determining test cases. The specific solutions are as follows:

[0006] A method for determining test cases includes:

[0007] Receiving target test parameters;

[0008] Querying whether there is a test stimulus sequence corresponding to the target test parameters in the stimulus pool;

[0009] If not, generating the test stimulus sequence according to the target test parameters and test functions;

[0010] Outputting the test stimulus sequence to generate a test case for verifying the design under test.

[0011] Preferably, the process of generating the test stimulus sequence according to the target test parameters and test functions includes: generating the test stimulus sequence through the JTAG interface chain according to the target test parameters and test functions.

[0012] Preferably, the test excitation sequence is specifically an IR sequence and a DR sequence.

[0013] Preferably, the design under test is a design under test including a DAP.

[0014] Preferably, the process of generating the test excitation sequence according to the target test parameters and the test function includes:

[0015] Generating and outputting the test excitation sequence according to the target test parameters and the test function and combining with the DPI-C interface method.

[0016] Preferably, the test function includes:

[0017] VIP reset and de-reset function;

[0018] IR / DR loading function;

[0019] TDO check function;

[0020] Basic test case function.

[0021] Preferably, the test case is a C language test case;

[0022] Correspondingly, the process of verifying the design under test by the test case includes: sending a preset format file generated during the compilation of the test case to an executable file to start verifying the design under test.

[0023] Correspondingly, the present application also discloses a test case determination system, including:

[0024] A parameter interface for receiving target test parameters;

[0025] An action module for querying whether there is a test excitation sequence corresponding to the target test parameters in the excitation pool; if not, generating the test excitation sequence according to the target test parameters and the test function;

[0026] An output module for outputting the test excitation sequence to generate a test case for verifying the design under test.

[0027] Correspondingly, the present application also discloses a test case determination device, including:

[0028] A memory for storing a computer program;

[0029] A processor for implementing the steps of the test case determination method as described in any one of the above when executing the computer program.

[0030] Correspondingly, the present application also discloses a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the test case determination method described in any one of the above are implemented.

[0031] The present application discloses a test case determination method, including: receiving target test parameters; querying whether there is a test excitation sequence corresponding to the target test parameters in an excitation pool; if not, generating the test excitation sequence according to the target test parameters and a test function; and outputting the test excitation sequence to generate a test case for verifying a design under test. The present application automatically outputs a test excitation sequence according to target test parameters, and this excitation sequence can directly generate a test case for verifying a design under test, avoiding complicated manual configuration and process sorting, and having the advantages of flexible reuse and utilization of project iteration. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0033] Figure 1 It is a flowchart of the steps of a test case determination method in an embodiment of the present invention;

[0034] Figure 2 It is a schematic diagram of the process of a test case determination method in an embodiment of the present invention;

[0035] Figure 3 It is a structural distribution diagram of a test case determination system in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] When the device under test is at the SoC level, due to its large scale, numerous debugging resources need to be debugged, which will undoubtedly increase the debugging complexity for verification personnel. When compiling test cases developed based on the SV language, it will involve compiling the entire UVM verification environment, and then generating an executable file (simv). This process takes a long time and consumes a large amount of server resources. It is not suitable to modify test cases frequently, and it lacks flexibility for devices under test with high test case requirements.

[0038] This application automatically outputs a test stimulus sequence according to target test parameters. This stimulus sequence can directly generate test cases for verifying the design under test, avoiding complicated manual configuration and process sorting, and having the advantages of flexible reuse and leveraging project iterations.

[0039] An embodiment of the present invention discloses a method for determining a test case. Refer to Figure 1 as shown, including:

[0040] S1: Receive target test parameters;

[0041] S2: Query whether there is a test stimulus sequence corresponding to the target test parameters in the stimulus pool; if not, sequentially execute steps S3 and S4; if so, directly execute step S4;

[0042] S3: Generate a test stimulus sequence according to the target test parameters and test functions;

[0043] S4: Output the test stimulus sequence to generate a test case for verifying the design under test.

[0044] It can be understood that the test stimulus sequence generated in step S3 can be stored in the stimulus pool. If this test stimulus sequence is needed again in subsequent tests, it can be directly output for use.

[0045] It can be understood that the basic process of traditional access to system resources based on DAP (Debug Access Port) is similar, but the process of implementing the debugging function is complex. That is, according to the position of DAP in the JTAG (Joint Test Action Group) chain, the type of DP (Debug Port), the position and type of AP (Access Port), the access object, etc., for different verification targets, the required test stimuli are different, and these test stimuli need to be manually set by staff, which is extremely cumbersome and time-consuming.

[0046] Through the test case determination method in this embodiment, the test stimulus sequence corresponding to the target test parameters can be directly output, thereby generating the test case corresponding to the target test parameters to complete the relevant verification of the design under test, without the need for staff to manually modify the test case code, and it can be flexibly reused.

[0047] In some specific embodiments, the target test parameters include, but are not limited to, the verification target parameter verf_obj, and / or the structural parameters dap_offset / ap_offset / ap_type, and / or the object parameters obj_id / obj_reg_addr.

[0048] In some specific embodiments, the process of generating the test stimulus sequence according to the target test parameters and the test function includes: generating the test stimulus sequence through the JTAG interface chain according to the target test parameters and the test function. Specifically, the JTAG interface chain is formed by connecting multiple devices in series through the JTAG interface. The output of the previous device serves as the input of the next device, and separate debugging of each device in the system can be achieved according to this chain structure; further, the test stimulus sequence is specifically an IR sequence and a DR sequence; at this time, the Design Under Test (DUT) of the test case in this embodiment can be a DUT including DAP, or a DUT that can be debugged in other forms. Generally, DAP receives JTAG data from an external port, converts it into a selection of the AP inside DAP, and the AP then converts it into a memory-mapped bus access to access internal resources of the system.

[0049] As Figure 2 shown, each device TAP1 - TAP3 has its own IR and DR widths and its position in the JTAG chain. Assume that the DAP of the DUT is located at the position in the figure, and the corresponding position is set as dap_offset, and the widths of the IR (Instruction Register) and DR (Data Register) are ir_width and dr_width respectively. Taking these structural parameters and parameters such as the debug object to be accessed and the bypass requirement as target test parameters, and splicing the IR and DR contents respectively, the structure of the JTAG chain can be determined, and the IR sequence and the DR sequence can be determined.

[0050] When verifying a DUT including DAP, usually compiling a test case developed based on the SV language involves compiling the entire UVM verification environment and then generating an executable file simv, which makes the pre-verification process time-consuming and consumes a large amount of server resources.

[0051] However, for the test cases based on C language, there is no need to recompile the entire UVM verification environment. Only the.so file generated during this compilation process needs to be passed as a parameter to the previously generated executable file simv to start the simulation. Therefore, in this embodiment, DPI-C interface is selected to generate C language test cases, which can greatly save the time of recompiling the verification environment and quickly start the subsequent verification. Therefore, the process of generating the test stimulus sequence according to the target test parameters and test functions described in step S3 includes: generating and combining the DPI-C interface method according to the target test parameters and test functions to output the test stimulus sequence.

[0052] Specifically, the test functions include:

[0053] VIP reset and de - reset function;

[0054] IR / DR loading function;

[0055] TDO checking function;

[0056] Basic test case function.

[0057] Specifically, the VIP reset and de - reset function provides the function jtag_reset() for resetting and de - resetting the JTAG VIP. The specific working process of the function includes: instantiating a reset stimulus sequence; starting the stimulus sequence. Where id represents the configuration parameter of the VIP.

[0058] Specifically, when performing an effective write access to the DAP input according to the JTAG protocol, it is necessary to update the pre - specified instruction to the instruction register through the protocol interface input signal, and then transfer it bit - by - bit to the DAP input signal. At this time, the DAP selects the corresponding DP register by parsing the instruction. Therefore, the IR / DR loading function provides the functions tag_load_ir() / jtag_load_dr(). The specific working process of the function includes: inputting the width of the IR / DR chain; instantiating a sequence for loading IR / DR; setting the internal parameters of the sequence (such as IR / DR data, etc.); starting the sequence. Where ir represents the pre - specified input instruction, and IR_CHAIN_WIDTH represents the maximum bit width of the IR chain.

[0059] Specifically, when it is necessary to capture the output signal (TDO) of DAP to obtain debug information, it is necessary to sample the TDO of JTAG_VIP. This sampling process can be completed in the Shift_IR state or in the Shift_DR state and output through JTAGVIP. Compare the output value with the expected value, and further analyze the debug information based on the comparison result. Therefore, the TDO check function provides the functions jtag_check_ir() / jtag_check_dr(). The working process of the function includes: inputting the width of the IR / DR chain, inputting the IR / DR instruction; setting the DR value of the expected output; instantiating a sequence for checking DR; setting the internal parameters of the sequence (such as IR / DR data, etc.); comparing the currently output DR value with the expected value, and printing the comparison result; starting the sequence.

[0060] It can be understood that after defining the SV task in this embodiment, it is necessary to establish a DPI link between C language and SV language. All SV function interfaces are implemented in the SV header file. When used in DPI-C test cases, the above interfaces are imported into the DPI-C test case side by using the DPI method. Just create a C function interface based on SV through the "export" keyword. The general function definition is as follows:

[0061] export "DPI-C" dpi_jtag_load_ir = task jtag_load_ir;

[0062] Furthermore, all the above-defined functions can be encapsulated in the DPI-C library file (dpi_lib.h) for easy calling and reuse.

[0063] Furthermore, since the entire verification environment is built based on the UVM verification platform, it is necessary to create basic test cases to use the DPI-C interface. Create the DPI test case top_dpi_test.sv in SV language, and communicate with the DPI-C test case my_test.c through dpi_c_thread(). This function is defined in the DPI-C test case, and the content is the custom test stimulus. Therefore, the basic test case function provides the function import "DPI-C" context task dpi_c_thread(). dpi_c_thread() creates an SV task or function interface based on C language through the "import" keyword.

[0064] In addition, this embodiment can also achieve synchronization between the DPI test case and the UVM environment by writing, reading memory, delaying, etc. Specifically, the synchronization interface function can be extended according to the needs of the verification personnel.

[0065] It is understandable that the test case is a C language test case;

[0066] Correspondingly, the process of verifying the design under test using the test case includes: sending a preset format file generated during the compilation of the test case to an executable file to start the verification of the design under test.

[0067] As mentioned above, for a test case based on C language, there is no need to recompile the entire UVM verification environment. Only the.so file generated during this compilation process needs to be passed as a parameter to the previously generated executable file simv to start the simulation. The preset format file is the.so file, and the executable file is simv.

[0068] This application discloses a method for determining a test case, including: receiving target test parameters; querying whether there is a test excitation sequence corresponding to the target test parameters in an excitation pool; if not, generating the test excitation sequence according to the target test parameters and a test function; outputting the test excitation sequence to generate a test case for verifying the design under test. This application automatically outputs a test excitation sequence according to target test parameters, and this excitation sequence can directly generate a test case for verifying the design under test, avoiding complicated manual configuration and process sorting, and having the advantages of flexible reuse and utilization of project iteration.

[0069] Correspondingly, an embodiment of this application also discloses a test case determination system, as shown in Figure 3 shown, including:

[0070] A parameter interface 1 for receiving target test parameters;

[0071] An action module 2 for querying whether there is a test excitation sequence corresponding to the target test parameters in the excitation pool; if not, generating the test excitation sequence according to the target test parameters and a test function;

[0072] An output module 3 for outputting the test excitation sequence to generate a test case for verifying the design under test.

[0073] An embodiment of this application automatically outputs a test excitation sequence according to target test parameters, and this excitation sequence can directly generate a test case for verifying the design under test, avoiding complicated manual configuration and process sorting, and having the advantages of flexible reuse and utilization of project iteration.

[0074] In some specific embodiments, the process of the action module 2 generating the test excitation sequence according to the target test parameters and a test function includes: generating the test excitation sequence through a JTAG interface chain according to the target test parameters and the test function.

[0075] In some specific embodiments, the test excitation sequence is specifically an IR sequence and a DR sequence.

[0076] In some specific embodiments, the design under test is a design under test including a DAP.

[0077] In some specific embodiments, the process in which the action module 2 generates the test excitation sequence according to the target test parameters and the test function includes: generating and combining the DPI-C interface method according to the target test parameters and the test function to output the test excitation sequence.

[0078] In some specific embodiments, the test function includes: a VIP reset and de-reset function; an IR / DR loading function; a TDO check function; a basic test case function.

[0079] In some specific embodiments, the test case is a C language test case; correspondingly, the process of verifying the design under test by the test case includes: sending a preset format file generated during the compilation of the test case to an executable file to start the verification of the design under test.

[0080] Correspondingly, an embodiment of the present application also discloses a test case determination device, including:

[0081] A memory for storing a computer program;

[0082] A processor for implementing the steps of the test case determination method as described in any one of the above when executing the computer program.

[0083] Correspondingly, an embodiment of the present application also discloses a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the test case determination method as described in any one of the above are implemented.

[0084] Among them, the specific content of the test case determination method in this embodiment can be referred to the relevant descriptions in the above embodiments, and will not be elaborated here.

[0085] Among them, the test case determination device and the readable storage medium in this embodiment have the same technical effects as the test case determination method in the above embodiments, and will not be elaborated here.

[0086] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0087] The above has introduced in detail a method, system and related components for determining test cases provided by the present invention. Specific examples are used in this text to illustrate the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A test case determination method, characterized in that, including: Receiving target test parameters; Querying whether there is a test excitation sequence corresponding to the target test parameters in the excitation pool; If not, generating the test excitation sequence according to the target test parameters and test functions; Outputting the test excitation sequence to generate a test case for verifying the design under test; The process of generating the test excitation sequence according to the target test parameters and test functions includes: generating the test excitation sequence through the JTAG interface chain according to the target test parameters and test functions; The test excitation sequence is specifically an IR sequence and a DR sequence; The test case is a C language test case; Correspondingly, the process of verifying the design under test by the test case includes: sending a preset format file generated during the compilation of the test case to an executable file to start verifying the design under test.

2. The test case determination method according to claim 1, wherein The design under test is a design under test including a DAP.

3. The test case determination method according to claim 1 or 2, characterized in that, The process of generating the test excitation sequence according to the target test parameters and test functions includes: Generating and outputting the test excitation sequence according to the target test parameters and test functions by combining the DPI-C interface method.

4. The test case determination method according to claim 3, wherein The test functions include: VIP reset and de-reset function; IR / DR loading function; TDO check function; Basic test case function.

5. A test case determination system, characterized in that, including: A parameter interface for receiving target test parameters; An action module for querying whether there is a test excitation sequence corresponding to the target test parameters in the excitation pool; If not, generating the test excitation sequence according to the target test parameters and test functions; An output module for outputting the test excitation sequence to generate a test case for verifying the design under test; The process of the action module generating the test excitation sequence according to the target test parameters and test functions includes: generating the test excitation sequence through the JTAG interface chain according to the target test parameters and test functions; The test excitation sequence is specifically an IR sequence and a DR sequence; The test case is a C language test case; correspondingly, the process of verifying the design under test by the test case includes: sending a preset format file generated during the compilation of the test case to an executable file to start verifying the design under test.

6. A test case determination device, characterized in that, including: A memory for storing a computer program; A processor for implementing the steps of the test case determination method according to any one of claims 1 to 4 when executing the computer program.

7. A readable storage medium, characterized in that, A computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the steps of the test case determination method according to any one of claims 1 to 4 are implemented.

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