Hybrid memory device and method of forming the same

Abstract

The present disclosure relates to hybrid memory devices and methods for forming the same. A memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory and a resistive-type memory. The transistor-type memory includes: a memory film extending over a gate electrode; a channel layer extending over the memory film; a first source / drain electrode extending over the channel layer; and a second source / drain electrode extending along the channel layer, and the resistive-type memory includes a resistive memory layer extending between the second source / drain electrode and the channel layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly to a hybrid memory device and a method for forming the same. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications such as radios, televisions, cell phones, and personal computing devices. Semiconductor memory falls into two main categories: volatile memory and non-volatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories: static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose their stored information when power is removed.

[0003] On the other hand, non-volatile memory can store data on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include its fast write / read speed and small size. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a memory array is provided, comprising: a plurality of hybrid memory cells, wherein each of the plurality of hybrid memory cells comprises: a transistor-type memory, comprising: a memory film, extending on a gate electrode; a channel layer, extending on the memory film; a first source / drain electrode, extending on the channel layer; and a second source / drain electrode, extending along the channel layer; and a resistive-type memory, comprising: a resistive memory layer, wherein the resistive memory layer extends between the second source / drain electrode and the channel layer.

[0005] According to an embodiment of the present disclosure, a device is provided, comprising: a semiconductor substrate; a word line extending over the semiconductor substrate; a ferroelectric layer extending along the word line, wherein the ferroelectric layer is in contact with the word line; an oxide semiconductor (OS) layer extending along the ferroelectric layer, wherein the ferroelectric layer is located between the oxide semiconductor (OS) layer and the word line; a plurality of source lines extending along the ferroelectric layer, wherein the ferroelectric layer is located between the plurality of source lines and the word lines; a plurality of bit lines extending along the ferroelectric layer, wherein the ferroelectric layer is located between the plurality of bit lines and the word lines; and a plurality of resistance memory layers, wherein each of the plurality of resistance memory layers is located between a corresponding bit line of the plurality of bit lines and the word line.

[0006] According to an embodiment of the present disclosure, a method is provided, comprising: patterning a first trench extending through a first conductive line; depositing a memory film along the sidewalls and bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the memory film, wherein the OS layer extends along the sidewalls and bottom surface of the first trench; depositing a first dielectric material on the OS layer, wherein the first dielectric material fills a remaining portion of the first trench; patterning a second trench in the first dielectric material; depositing a resistive memory material on the sidewalls of the second trench; and depositing a first conductive material on the resistive memory material within the second trench, wherein the first conductive material fills the second trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood by the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A 、 Figure 1B and Figure 1C A perspective view, a circuit diagram, and a top-down view of a hybrid memory array are shown, according to some embodiments.

[0009] Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 Figure 11 Figure 12A 、 Figure 12B 、 Figure 13 、 Figure 14A 、 Figure 14B 、 Figure 15 、 Figure 16 、 Figure 17A Figure 17B Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 24A 、 Figure 24BFigure 24C Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 27A Figure 27B Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 29A 、 Figure 29B 、 Figure 29C and Figure 29D Different views are shown of intermediate steps in fabricating a hybrid memory array according to some embodiments.

[0010] Figure 30A 、 Figure 30B 、 Figure 31A 、 Figure 31B 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 Figure 36A Figure 36B 、 Figure 36C and Figure 36D Different views are shown of intermediate steps in fabricating a hybrid memory array according to some embodiments.

[0011] Figure 37 A schematic diagram of a hybrid memory cell is shown in accordance with some embodiments.

[0012] Figure 38A 、 Figure 38B and Figure 38C The read / write operations of a transistor-type memory of a hybrid memory cell according to some embodiments are shown.

[0013] Figure 39A 、 Figure 39B and Figure 39C A read / write operation of a resistive memory of a hybrid memory cell according to some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat the figure numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, spatially relative terms (e.g., "below," "beneath," "down," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] Various embodiments provide a 3D memory array having multiple vertically stacked memory cells. Each memory cell includes a transistor-type memory and a resistive-type memory, so many memory cells are considered "hybrid memory cells." The transistor-type memory of the memory cell includes a transistor having a word line region serving as a gate electrode, a bit line region serving as a first source / drain electrode, and a source line region serving as a second source / drain electrode. The transistor can be, for example, a thin film transistor (TFT). Each transistor also includes an insulating memory film (e.g., as a gate dielectric) and an oxide semiconductor (OS) channel region. The resistive-type memory of the memory cell includes a resistive memory layer formed on the bit line region so that the current flowing between the bit line and the source line also flows through the resistive memory layer. The transistor-type memory and the resistive-type memory of each memory cell can be programmed or read using the same word line, bit line, and source line corresponding to the memory cell. In this way, different types of memory can be used for different purposes within the same memory array. For example, transistor-type memory can be used for relatively frequent read / write operations, while resistive memory can be used for relatively static data storage.

[0017] Figure 1A 、 Figure 1B and Figure 1CAn example of a hybrid memory array 200 is shown in accordance with some embodiments. The hybrid memory array 200 includes a resistive memory layer 107 formed around conductive lines 106, which will be described in greater detail below. Figure 1A An example of a portion of a hybrid memory array 200 is shown in perspective view; Figure 1B shows a circuit diagram of a hybrid memory array 200; and Figure 1C A top-down view (e.g., a plan view) of a hybrid memory array 200 according to some embodiments is shown. The hybrid memory array 200 includes a plurality of memory cells 202 that can be arranged in a grid of rows and columns. The memory cells 202 can be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. In some embodiments, each memory cell 202 of the hybrid memory array 200 includes both transistor-type memory and resistive-type memory, and thus may be referred to herein as a "hybrid memory cell 202." The transistor-type memory and resistive-type memory of each hybrid memory cell 202 can be independently programmed and read, as described in more detail below. The hybrid memory array 200 can be provided in the back-end of the line (BEOL) of a semiconductor die. For example, the hybrid memory array 200 can be provided in an interconnect layer of the semiconductor die, such as above one or more active devices (e.g., transistors, etc.) formed on a semiconductor substrate.

[0018] The transistor-type memory of the hybrid memory array 200 may include, for example, a flash memory array, such as a NOR flash memory array, a thin-film transistor (TFT) memory array, another charge storage-based memory array, or the like. For example, each hybrid memory cell 202 may include a transistor 204 having an insulating memory film 90 as a gate dielectric. In some embodiments, the gate of each transistor 204 is electrically coupled to a corresponding word line (e.g., conductive line 72), the first source / drain region of each transistor 204 is electrically coupled to a corresponding bit line (e.g., conductive line 106), and the second source / drain region of each transistor 204 is electrically coupled to a corresponding source line (e.g., conductive line 108), which electrically couples the second source / drain region to ground. Hybrid memory cells 202 in the same horizontal row of the hybrid memory array 200 may share a common word line (e.g., 72), while hybrid memory cells 202 in the same vertical column of the hybrid memory array 200 may share a common source line (e.g., 108) and a common bit line (e.g., 106).

[0019] The hybrid memory array 200 includes a plurality of vertically stacked conductive lines 72 (eg, word lines). The conductive lines 72 are arranged parallel to the underlying substrate ( Figure 1A and 1BThe conductive lines 72 may have a stepped configuration such that the lower conductive lines 72 are longer than the upper conductive lines 72 and extend laterally beyond the end points of the upper conductive lines 72. Figure 1A , a plurality of stacked conductive lines 72 are shown, wherein the top conductive line 72 is the shortest and the bottom conductive line 72 is the longest. The respective lengths of the conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each conductive line 72 may be accessed from above the hybrid memory array 200, and a conductive contact may be made to the exposed portion of each conductive line 72 (e.g., see FIG. 1 ). Figure 29A -D).

[0020] The hybrid memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). The conductive lines 106 and 108 can each extend in a direction perpendicular to the conductive lines 72. A dielectric material 98 is disposed between and isolates adjacent conductive lines 106 and 108. The pairs of conductive lines 106 and 108 and the intersecting conductive lines 72 define the boundaries of each hybrid memory cell 202. In some embodiments, the conductive lines 108 are electrically coupled to ground. Although Figure 1A A particular arrangement of conductive lines 106 relative to conductive lines 108 is shown, but it should be understood that in other embodiments, the arrangement of conductive lines 106 and 108 may be reversed.

[0021] As described above, the hybrid memory array 200 may further include an oxide semiconductor (OS) layer 92. The OS layer 92 may provide a channel region for the transistor 204 of the hybrid memory cell 202. For example, when a suitable voltage (e.g., higher than the corresponding threshold voltage (V th ), the area where OS layer 92 intersects conductive line 72 can allow current to flow from conductive line 106 to conductive line 108 (e.g., along the direction indicated by arrow 207). Therefore, in some cases, OS layer 92 can be considered a channel layer.

[0022] The memory film 90 is disposed between the conductive line 72 and the OS layer 92, and the memory film 90 can provide a gate dielectric for the transistor 204. In some embodiments, the memory film 90 includes a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc. Therefore, the hybrid memory array 200 can also be referred to as a ferroelectric random access memory (FeRAM) array. Alternatively, the memory film 90 can be a multilayer structure including a plurality of layers disposed between two SiO layers. x SiN between layers xlayers (e.g., ONO structures), different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

[0023] In embodiments where the memory film 90 comprises a ferroelectric material, the memory film 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference across the memory film 90 and generating an appropriate electric field. The polarization can be relatively localized (e.g., generally contained within each boundary of the hybrid memory cell 202), and a continuous region of the memory film 90 can extend across multiple hybrid memory cells 202. Depending on the polarization direction of a particular region of the memory film 90, the threshold voltage of the corresponding transistor 204 varies, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 90 has a first electrical polarization direction, the corresponding transistor 204 can have a relatively low threshold voltage, and when the region of the memory film 90 has a second electrical polarization direction, the corresponding transistor 204 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift can improve the efficiency of reading digital values ​​stored in the transistor-type memory of the corresponding hybrid memory cell 202 and can reduce the likelihood of erroneous reads.

[0024] As described above, in addition to transistor-type memory, each hybrid memory cell 202 of the hybrid memory array 200 also includes resistive memory. For example, each hybrid memory cell 202 may include a resistive memory layer 107 extending between the corresponding conductive line 106 (e.g., bit line) and the OS layer 92. Therefore, the current flowing from the conductive line 106 to the conductive line 108 (e.g., the current indicated by arrow 207) also flows through the resistive memory layer 107. In some embodiments, the resistance of the resistive memory layer 107 can be controlled by applying an appropriate voltage and / or current to the resistive memory layer 107. For example, the resistive memory layer 107 can be controlled to be in a high resistance state or a low resistance state. Depending on the resistance state of the resistive memory layer 107, the current flowing through the corresponding transistor 204 changes, and a digital value (e.g., 0 or 1) can be stored. In this manner, both the transistor-type memory and the resistor-type memory of the hybrid memory cell 202 can be written to or read from by applying appropriate voltages to the conductive line 106 (e.g., bit line), the conductive line 108 (e.g., source line), and the conductive line 72 (e.g., word line) corresponding to the hybrid memory cell 202. Figure 1B , which schematically illustrates that the resistive memory layer 107 of each hybrid memory cell 202 is electrically coupled between the corresponding conductive line 106 and the corresponding transistor 204. Figures 37 to 39CThe read / write operations of the resistive memory described herein are explained in more detail.

[0025] The resistive memory of the hybrid memory array 200 may be, for example, resistive random access memory (RRAM or ReRAM), PCRAM, CBRAM, etc. The type and physical mechanism of the resistive memory of the memory array may depend on the specific material of the resistive memory layer 107. For example, some types of resistive memory may be set to a specific resistance state by applying an electric field to the resistive memory layer 107 (e.g., by controlling the voltage across the resistive memory layer 107), and other types of resistive memory may be set to a specific resistance state by heating the resistive memory layer 107 (e.g., by controlling the current through the resistive memory layer 107). In some embodiments, the resistive memory layer 107 may be formed of or include a metal-containing high-k dielectric material, which may be a metal oxide. The metal may be a transition metal. In some embodiments, the resistive memory layer 107 includes HfO x 、ZrO x 、TaO x 、TiO x , VO x 、NiO x 、NbO x 、LaO x In other embodiments, the resistive memory layer 107 includes AlO x 、 SnO x , GdO x , IGZO, Ag2S, etc., or a combination thereof. In other embodiments, the resistive memory layer 107 includes a chalcogenide material, such as GeS2, GeSe, AgGeSe, GeSbTe, doped GeSbTe (e.g., doped with N, Si, C, Ga, In, etc., or a combination thereof), etc., or a combination thereof. These are examples, and other resistive memories, other resistive memory layer 107 materials or combinations of materials, and other read / write technologies are possible, and all of these are also considered within the scope of the present disclosure.

[0026] Figure 1AReference cross sections of hybrid memory array 200 are further shown and are used in subsequent figures. Reference cross section BB' is along the longitudinal axis of conductive line 72 and, for example, in a direction parallel to the current flow direction of transistor 204 (e.g., arrow 207). Reference cross section CC' is perpendicular to cross section BB' and perpendicular to the longitudinal axis of conductive line 72. Reference cross section CC' extends through conductive line 106 and resistive memory layer 107. Reference cross section DD' is parallel to reference cross section CC' and extends through conductive line 108. For clarity, subsequent figures refer to these reference cross sections.

[0027] exist Figure 2 In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0028] Figure 2 Further shown is a circuit that can be formed on the substrate 50. The circuit includes an active device (e.g., a transistor) located at the top surface of the substrate 50. The transistor may include a gate dielectric layer 203 located above the top surface of the substrate 50 and a gate electrode 205 located above the gate dielectric layer 203. Source / drain regions 206 are provided in the substrate 50 on opposite sides of the gate dielectric layer 203 and the gate electrode 205. Gate spacers 208 are formed along the sidewalls of the gate dielectric layer 203 and separate the source / drain regions 206 from the gate electrode 205 by an appropriate lateral distance. In some embodiments, the transistor may be a planar field effect transistor (FET), a fin field effect transistor (FINFET), a nano field effect transistor (nanoFET), etc.

[0029] A first ILD 210 surrounds and isolates the source / drain regions 206, the gate dielectric layer 203, and the gate electrode 205, and a second ILD 212 is located above the first ILD 210. Source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 206, and a gate contact 216 extends through the second ILD 212 and is electrically coupled to the gate electrode 205. An interconnect structure 220 including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224 is located above the second ILD 212, the source / drain contacts 214, and the gate contact 216. Although Figure 2 Two stacked dielectric layers 224 are shown, but it should be understood that the interconnect structure 220 may include any number of dielectric layers 224 having conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contact 216 and the source / drain contacts 214 to form a functional circuit. In some embodiments, the functional circuit formed by the interconnect structure 220 may include a logic circuit, a memory circuit, a sense amplifier, a controller, an input / output circuit, an image sensor circuit, the like, or a combination thereof. Although Figure 2 While transistors formed over substrate 50 are discussed, other active devices (eg, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may also be formed as part of the functional circuitry.

[0030] Figures 3A to 29D Shows the manufacturing and Figure 1A -C shows various views of intermediate steps of a similar hybrid memory array 200. First, go to Figure 3A and Figure 3B 2 , a multilayer stack 58 is formed on top of the structure of FIG. For simplicity and clarity, the substrate 50, transistors, ILDs, and interconnect structure 220 may be omitted from subsequent figures. Although the multilayer stack 58 is shown in contact with the dielectric layer 224 of the interconnect structure 220, any number of intermediate layers may be provided between the substrate 50 and the multilayer stack 58. For example, one or more additional interconnect layers may be provided between the substrate 50 and the multilayer stack 58, the additional interconnect layers including conductive features in an insulating layer (e.g., a low-k dielectric layer). In some embodiments, the conductive features may be patterned to provide a conductive layer for active devices on the substrate 50 and / or the hybrid memory array 200 (see FIG. Figure 1A and 1B ) provides power, ground and / or signal lines.

[0031] Multilayer stack 58 includes alternating layers of conductive lines 54A-D (collectively, conductive layers 54) and dielectric layers 52A-C (collectively, dielectric layers 52). Conductive layers 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). Conductive layers 54 may include conductive materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, and dielectric layers 52 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. Conductive layers 54 and dielectric layers 52 may each be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), and the like. Although Figure 3A and Figure 3B A particular number of conductive layers 54 and dielectric layers 52 are shown, but other embodiments may include different numbers of conductive layers 54 and dielectric layers 52 .

[0032] In some embodiments, the multilayer stack 58 may be formed as alternating layers of dummy dielectric layers (not separately shown) and dielectric layers 52. Dummy dielectric layers may be formed in place of Figures 3A-3B The conductive layer 54 shown in FIG, and then the dummy dielectric layer is removed and replaced with a conductive layer to form the conductive line 72 (see FIG. Figure 17A -B). The material of the dummy dielectric layer can have a different etch selectivity than the material of dielectric layer 52, so that the dummy dielectric layer can be selectively removed while leaving dielectric layer 52. For example, in some embodiments, the dummy dielectric layer can include a nitride while dielectric layer 52 includes an oxide. Other materials are also possible. In embodiments where multilayer stack 58 includes a dummy dielectric layer, the dummy dielectric layer can be replaced with a conductive layer before the conductive layer replaces the dummy dielectric layer. Figure 4-16 The multilayer stack 58 is processed in a similar manner.

[0033] Figures 4 to 12B is a diagram of an intermediate stage in the fabrication of a stepped structure of a hybrid memory array 200 according to some embodiments. Figures 4 to 11 and Figure 12B The diagram is shown along reference section BB' shown in FIG. 1 . Figure 12A The diagram is presented in perspective. Figure 4 , a photoresist 56 is formed on a multilayer stack 58. As described above, the multilayer stack 58 may include alternating layers of conductive layers 54 (labeled 54A, 54B, 54C, and 54D) and dielectric layers 52 (labeled 52A, 52B, and 52C). For example, the photoresist 56 may be formed using a spin coating technique.

[0034] exist Figure 5, photoresist 56 is patterned to expose multilayer stack 58 in region 60 while masking the remainder of multilayer stack 58. For example, the topmost layer of multilayer stack 58 (e.g., conductive layer 54D) may be exposed in region 60. Photoresist 56 may be patterned using acceptable photolithography techniques.

[0035] exist Figure 6 In the embodiment of the present invention, the exposed portions of the multilayer stack 58 in the region 60 are etched using the photoresist 56 as a mask. The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. The etching can remove the portions of the conductive layer 54D and the dielectric layer 52C in the region 60 and define the opening 61. Because the conductive layer 54D and the dielectric layer 52C have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52C acts as an etch stop layer when etching the conductive layer 54D, while the conductive layer 54C acts as an etch stop layer when etching the dielectric layer 52C. As a result, portions of the dielectric layer 52C and the conductive layer 54D can be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 can be extended to a desired depth. Alternatively, a timed etching process can be used to stop etching the opening 61 after the opening 61 reaches the desired depth. In the resulting structure, conductive layer 54C is exposed in region 60 .

[0036] exist Figure 7 In the embodiment of the present invention, photoresist 56 is trimmed to expose additional portions of multilayer stack 58. The photoresist can be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60 and 62 can be exposed. For example, the top surface of conductive layer 54C can be exposed in region 60, and the top surface of conductive layer 54D can be exposed in region 62.

[0037] exist Figure 8In the embodiment of the present invention, conductive layer 54D, dielectric layer 52C, and portions of conductive layer 54C and dielectric layer 52B in regions 60 and 62 are removed by an acceptable etching process using photoresist 56 as a mask. The etching process may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching process may be anisotropic. The etching process may extend opening 61 further into multilayer stack 58. Because conductive layers 54D / 54C and dielectric layers 52C / 52B have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52C acts as an etch stop when etching conductive layer 54D; conductive layer 54C acts as an etch stop when etching dielectric layer 52C; dielectric layer 52B acts as an etch stop when etching conductive layer 54C; and conductive layer 54B acts as an etch stop when etching dielectric layer 52B. As a result, portions of conductive layers 54D / 54C and dielectric layers 52C / 52B can be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 can be extended to a desired depth. Furthermore, during the etching process, the unetched portions of conductive layer 54 and dielectric layer 52 act as a mask for the underlying layers, and as a result, conductive layer 54D and dielectric layer 52C (see FIG. Figure 7 ) can be transferred to underlying conductive layer 54C and dielectric layer 52B. In the resulting structure, conductive layer 54B is exposed in region 60, and conductive layer 54C is exposed in region 62.

[0038] exist Figure 9 In the embodiment of the present invention, photoresist 56 is trimmed to expose additional portions of multilayer stack 58. The photoresist can be trimmed using acceptable photolithographic techniques. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 can be exposed in regions 60, 62, and 64. For example, the top surface of conductive layer 54B can be exposed in region 60; the top surface of conductive layer 54C can be exposed in region 62; and the top surface of conductive layer 54D can be exposed in region 64.

[0039] exist Figure 10, using photoresist 56 as a mask, portions of conductive layers 54D, 54C, and 54B in regions 60, 62, and 64 are removed by an acceptable etching process. The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. The etching can extend the opening 61 further into the multilayer stack 58. In some embodiments, dielectric layer 52C acts as an etch stop layer when etching conductive layer 54D; dielectric layer 52B acts as an etch stop layer when etching conductive layer 54C; and dielectric layer 52A acts as an etch stop layer when etching conductive layer 54B. As a result, portions of conductive layers 54D, 54C, and 54B can be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 can be extended to a desired depth. In addition, during the etching process, each dielectric layer 52 acts as a mask for the underlying layer, and as a result, dielectric layers 52C / 52B (see Figure 9 ) can be transferred to the underlying conductive layer 54C / 54B. In the resulting structure, dielectric layer 52A is exposed in region 60; dielectric layer 52B is exposed in region 62; and dielectric layer 52C is exposed in region 64.

[0040] exist Figure 11 In the process, photoresist 56 can be removed, for example, by an acceptable ashing or wet stripping process. Thus, a stair-step structure is formed in multilayer stack 58. The stair-step structure includes a stack of alternating layers of conductive layers 54 and dielectric layers 52. Lower conductive layers 54 are wider and extend laterally beyond upper conductive layers 54, and the width of each conductive layer 54 increases in a direction toward substrate 50. For example, conductive layer 54A can be longer than conductive layer 54B; conductive layer 54B can be longer than conductive layer 54C; and conductive layer 54C can be longer than conductive layer 54D. As a result, in subsequent processing steps, conductive contacts can be formed from above stair-step structure 58 to each conductive layer 54.

[0041] exist Figure 12A and Figure 12BIn the embodiment of the present invention, an intermetallic dielectric (IMD) 70 is deposited over multilayer stack 58. IMD 70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. IMD 70 extends along the sidewalls of conductive layer 54 and the sidewalls of dielectric layer 52. In addition, IMD 70 may contact the top surface of each dielectric layer 52.

[0042] like Figure 12A As further shown in FIG. 1B , a removal process may be performed on IMD 70 to remove excess dielectric material above multilayer stack 58. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), a grinding process, an etch-back process, or a combination thereof may be used. The planarization process exposes multilayer stack 58 so that the top surfaces of multilayer stack 58 and IMD 70 are flush after the planarization process is completed.

[0043] Figures 13 to 21C is a diagram of an intermediate stage in the fabrication of a hybrid memory array 200 according to some embodiments. Figures 13 to 21C In the embodiment of the present invention, a multilayer stack 58 is formed, and trenches 86 are formed in the multilayer stack 58, thereby defining conductive lines 72. The conductive lines 72 may correspond to word lines in the hybrid memory array 200, and the conductive lines 72 may further provide gates for the resulting transistors 204 of the hybrid memory array 200. Figure 14A 、 Figure 17A 、 Figure 18A 、 Figure 19A and Figure 21A The diagram is presented in perspective. Figure 13 、 Figure 14B 、 Figure 15 、 Figure 16 、 Figure 17B 、 Figure 18B Figure 19B Figure 20 and Figure 21C Along Figure 1A The reference section CC' shown in FIG is illustrated. Figure 21B The diagram is presented in the form of a plan view.

[0044] exist Figure 13In the embodiment of the present invention, a hard mask 80 and a photoresist 82 are deposited over the multilayer stack 58. The hard mask 80 may include, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. For example, the photoresist 82 may be formed by using a spin coating technique.

[0045] exist Figure 14A and Figure 14B In the embodiment of the present invention, photoresist 82 is patterned to form trenches 86. Photoresist 82 can be patterned using acceptable photolithography techniques. For example, photoresist 82 can be exposed to light to be patterned. After the exposure process, photoresist 82 can be developed to remove the exposed or unexposed portions of photoresist 82, depending on whether a negative resist or a positive resist is used, thereby defining the pattern of trenches 86.

[0046] exist Figure 15 In the embodiment of the present invention, the pattern of the photoresist 82 is transferred to the hard mask 80 using an acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. Thus, trenches 86 are formed extending through the hard mask 80. For example, the photoresist 82 can be removed by an ashing process.

[0047] exist Figure 16 In the embodiment of the present invention, the pattern of the hard mask 80 is transferred to the multilayer stack 58 using one or more acceptable etching processes, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process can be anisotropic. As a result, trenches 86 extend through the multilayer stack 58, and conductive lines 72 (e.g., word lines) are formed from the conductive layer 54. By etching trenches 86 through the conductive layer 54, adjacent conductive lines 72 can be separated from each other.

[0048] exist Figure 17A and Figure 17B 10. In the embodiment of the present invention, hard mask 80 is removed by an acceptable process, such as a wet etching process, a dry etching process, a planarization process, a combination thereof, or the like. Due to the stepped shape of multilayer stack 58 (see, for example, FIG. 12 ), conductive lines 72 may have different lengths that increase in a direction toward substrate 50. For example, conductive line 72A may be longer than conductive line 72B; conductive line 72B may be longer than conductive line 72C; and conductive line 72C may be longer than conductive line 72D. In some embodiments, trench 86 may be formed to have a width W1 in a range of about 50 nm to about 100 nm, although other widths are possible.

[0049] In forming a dummy dielectric layer (as previously described for Figure 3AIn the embodiment described in FIG-B ), the dummy dielectric layer can be removed before or after removing the hard mask 80. For example, the dummy dielectric layer can be removed by an acceptable process that is selective to the material of the dummy dielectric layer above the material of the dielectric layer 52, such as a wet etch process or a dry etch process, thereby leaving a gap (not shown) between the dielectric layers 52. Portions of the dummy dielectric layer (e.g., at the periphery of the multilayer stack 58) can remain between the dielectric layers 52 to provide physical support and define the gap between the dielectric layers 52. Subsequently, the conductive layer 54 can be removed using the process previously described for the conductive layer 54 (see FIG. Figure 3A -B) similar process and materials are used to deposit the conductive material of the conductive line 72 in the gap. After replacing the dummy dielectric layer with the conductive line 72, a multilayer stack is formed, which can be similar to Figure 17A - The multilayer stack 58 shown in B and subsequent processing can be similar to the following Figures 18A to 29D In other embodiments, the dummy dielectric layer may be formed in a manner similar to that described in the multilayer stack 58. Figure 17A -B shows steps where different steps are replaced by conductive wire 72 .

[0050] exist Figure 18A and Figure 18B In the embodiment of the present invention, a memory film 90 is conformally deposited in the trench 86. The memory film 90 may include a material capable of storing a bit, such as a material capable of switching between two different polarization directions by applying an appropriate voltage difference across the memory film 90. For example, the polarization of the memory film 90 may change due to an electric field generated by the applied voltage difference. In some embodiments, the memory film 90 includes a high-k dielectric material, such as a hafnium (Hf)-based dielectric material. In some embodiments, the memory film 90 includes a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc. In other embodiments, the memory film 90 may be a multilayer structure including a plurality of layers disposed between two SiO layers. x A layer of SiN between the layers x (e.g., an ONO structure). In other embodiments, the memory film 90 includes a different ferroelectric material or a different type of memory material. The memory film 90 can be deposited by CVD, PVD, ALD, PECVD, etc. to extend along the sidewalls and bottom surface of the trench 86. In some embodiments, an annealing step can be performed after depositing the memory film 90. In some embodiments, the memory film 90 can be deposited to a thickness in the range of about 5 nm to about 15 nm, although other thicknesses are possible.

[0051] exist Figure 19A and Figure 19BIn the embodiment, OS layer 92 is conformally deposited in trench 86 over memory film 90. OS layer 92 includes a plurality of layers suitable for transistors (e.g., transistor 204, see FIG. Figure 1A ) provides a material for the channel region. In some embodiments, the OS layer 92 includes a material containing indium, such as In x Ga y Zn z MO, where M can be Ti, Al, Sn, W, etc. X, Y, and Z can each be any value between 0 and 1. For example, the OS layer 92 can include indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, indium oxide, etc., or a combination thereof. In other embodiments, semiconductor materials different from these examples can be used for the OS layer 92. The OS layer 92 can be deposited by CVD, PVD, ALD, PECVD, etc. The OS layer 92 can extend along the sidewalls of the memory film 90 within the trench 86. In other embodiments, the OS layer 92 can also extend on the bottom surface of the memory film 90 within the trench 86 (not shown). In some embodiments, after depositing the OS layer 92, an annealing step (e.g., at a temperature in the range of about 300°C to about 450°C) can be performed in an oxygen-related environment to activate the charge carriers of the OS layer 92. In some embodiments, the OS layer 92 can be deposited to a thickness in the range of about 1 nm to about 15 nm, but other thicknesses are also possible. In some embodiments, after depositing the OS layer 92 , the trenches 86 may have a width W2 in a range from about 20 nm to about 70 nm, although other widths are possible.

[0052] exist Figure 20 In the embodiment, dielectric material 98 is deposited on the sidewalls and bottom surface of trench 86. Dielectric material 98 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. Figure 20 As shown, dielectric material 98 may fill trench 86 and may cover multilayer stack 58 .

[0053] exist Figure 21A 、 Figure 21B and Figure 21C In accordance with some embodiments, a removal process is performed to remove excess dielectric material 98 over multilayer stack 58 . Figure 21A shows a perspective view, Figure 21B shows a plan view, and Figure 21C Shown through Figure 1A and Figure 21BIn some embodiments, a planarization process such as chemical mechanical polishing (CMP), a grinding process, an etch-back process, or a combination thereof may be used to expose the multilayer stack 58 such that the top surface of the multilayer stack 58 is flat after the planarization process is completed.

[0054] exist Figure 22A 、 Figure 22B and Figure 22C In FIG. 1 , trenches 100 are patterned through dielectric material 98 according to some embodiments. Figure 22A The diagram is presented in perspective. Figure 22B It is illustrated in plan view, and Figure 22C Along Figure 22B The reference cross section CC' is shown in cross-sectional view. The trench 100 may be provided between opposite sidewalls of the multilayer stack 58 and define a region where a resistive memory layer 107 (see FIG. 1 ) may be subsequently formed. Figure 23A -C) and conductive wire 106 (see Figure 24A -C). In some embodiments, trench 100 can be patterned using a combination of photolithography and etching. For example, a photoresist can be deposited over multilayer stack 58. The photoresist can be formed using a suitable technique (e.g., spin coating). The photoresist can then be patterned to define openings that expose areas of dielectric material 98. The photoresist can be patterned using acceptable photolithography techniques.

[0055] The portion of dielectric material 98 exposed by the opening can then be removed by etching, thereby forming a trench 100 in dielectric material 98. In some embodiments, trench 100 in dielectric material 98 can expose the sidewall surface of OS layer 92. Etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. In some embodiments, trench 100 can have a depth in the range of about 1000 nm to about 2000 nm, but other depths are also possible. After patterning trench 100, the photoresist can be removed, for example, by ashing.

[0056] exist Figure 23A 、 Figure 23B and Figure 23CIn some embodiments, the resistive memory layer 107 is conformally deposited in the trench 100. The resistive memory layer 107 may include a material capable of storing bits, such as a material capable of switching between two different resistance states by applying an appropriate voltage difference across the resistive memory layer 107 or allowing an appropriate current to flow through the resistive memory layer 107. For example, the resistive memory layer 107 may include one or more layers of metal oxide, phase change material, or other suitable materials. The resistive memory layer 107 may be deposited by CVD, PVD, ALD, PECVD, etc., and may extend along the sidewalls and bottom surface of the trench 100. Therefore, the resistive memory layer 107 may be deposited on the sidewall surfaces of the OS layer 92 exposed by the trench 100. In other embodiments, the resistive memory layer 107 is not deposited on the bottom surface of the trench 100. Figure 23A As shown in FIG. 1-C, the resistive memory layer 107 may be deposited to a thickness that does not completely fill the trench 100. In some embodiments, the resistive memory layer 107 may be deposited to a thickness in a range of about 3 nm to about 20 nm, such as about 10 nm, although other thicknesses are possible. In some embodiments, a planarization process is performed to remove excess material of the resistive memory layer 107.

[0057] Figures 24A to 26C An intermediate step in fabricating conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines) in a hybrid memory array 200 is shown, according to some embodiments. Conductive lines 106 may correspond to bit lines in a memory array, and conductive lines 108 may correspond to source lines in the hybrid memory array 200. Conductive lines 106 and 108 may extend in a direction perpendicular to conductive lines 72, such that individual hybrid memory cells 202 of the hybrid memory array 200 may be selected for read and write operations. Depending on the applied voltage (described in more detail below), the read and write operations may be applied to either the resistive type memory (e.g., resistive memory layer 107) or the transistor type memory (e.g., transistor 204) of the hybrid memory cell 202. Figure 24A , Figure 25A and Figure 26A A perspective view is shown. Figure 24B 、 Figure 25B and Figure 26B Figure 24C shows a plan view of the Figure 1A and Figure 24A A cross-sectional view of reference section CC' is shown. Figure 25C and Figure 26C Shown along Figure 1A 、 Figure 25B and Figure 26B A cross-sectional view with reference to section DD' is shown.

[0058] exist Figure 24A 、 Figure 24B and Figure 24C In some embodiments, trench 100 is filled with a conductive material, thereby forming conductive line 106. The conductive material covers resistive memory layer 107 and may be separated from OS layer 92 and / or dielectric material 98 by resistive memory layer 107. The conductive material may include one or more materials, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, molybdenum, combinations thereof, and the like, each of which may be formed using, for example, CVD, ALD, PVD, PECVD, and the like. After depositing the conductive material, a planarization process may be performed to remove excess conductive material. In some embodiments, excess material of resistive memory layer 107 may be removed using the same planarization process as the excess conductive material. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, dielectric material 98, resistive memory layer 107, and conductive line 106 may be substantially flush (e.g., coplanar within process variations).

[0059] exist Figure 25A 、 Figure 25B and Figure 25C , trench 105 is patterned for conductive line 108. Trench 105 may be patterned using techniques similar to those used to pattern trench 100 (see Figure 22A -C). For example, trench 105 can be formed by patterning dielectric material 98 using a combination of photolithography and etching. In some embodiments, trench 105 in dielectric material 98 can expose sidewall surfaces of OS layer 92.

[0060] exist Figure 26A 、 Figure 26B and Figure 26C In some embodiments, trench 105 is filled with a conductive material to form conductive line 108. The conductive material may be similar to the conductive material of conductive line 106 and may be formed in a similar manner. After depositing the conductive material, a planarization process may be performed to remove excess conductive material. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, dielectric material 98, resistive memory layer 107, conductive line 106, and conductive line 108 may be substantially flush (e.g., coplanar within process variations).

[0061] Figures 22A to 26C One embodiment is shown in which the resistive memory layer 107 and the conductive line 106 are formed before the conductive line 108 is formed. However, in other embodiments, these features can be formed in a different order or using different techniques. For example, in other embodiments, a single lithography and etching sequence can be used to form the trench 100 (see FIG. Figure 22A -C) and groove 105 (see Figure 25A -C) Both. In other embodiments, conductive line 108 can be formed before forming resistive memory layer 107 and / or conductive line 106. In other embodiments, the conductive materials for conductive line 106 and conductive line 108 can be deposited in a single deposition step. These and other variations are considered within the scope of the present invention.

[0062] Figures 27A to 28C The formation of dielectric material 121 is shown in accordance with some embodiments. Dielectric material 121 is formed in hybrid memory array 200 to separate and isolate adjacent hybrid memory cells 202. In other embodiments, dielectric material 121 may be formed during a different process step, such as before forming resistive memory layer 107, conductive line 106, and / or conductive line 108. Figure 27A and Figure 28A The diagram is presented in perspective. Figure 27B 、 Figure 28B and Figure 28C The diagram is presented in the form of a plan view. Figure 28C The embodiment shown is Figure 28B The embodiment is similar to that of , except that the arrangement of the conductive lines 106 and the conductive lines 108 is different.

[0063] exist Figure 27A and Figure 27B In some embodiments, trenches 120 are patterned through dielectric material 98 and OS layer 92. In some embodiments, a combination of photolithography and etching can be used to pattern trenches 120. For example, a photoresist can be deposited over multilayer stack 58. The photoresist can be formed using a suitable technique (e.g., spin coating). The photoresist can then be patterned to define openings that expose areas of dielectric material 98 and OS layer 92. The photoresist can be patterned using acceptable photolithography techniques.

[0064] The portions of dielectric material 98 and OS layer 92 exposed by the openings can then be removed by etching, thereby forming trenches 120 in dielectric material 98. In some embodiments, trenches 120 in dielectric material 98 can expose sidewall surfaces of memory film 90. The etching process can be any acceptable etching process, such as wet or dry etching, RIE, NBE, or a combination thereof. The etching process can be anisotropic. After patterning trenches 120, the photoresist can be removed, for example, by ashing.

[0065] exist Figure 28A and Figure 28BIn some embodiments, dielectric material 121 is deposited in trench 120. Dielectric material 121 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof. The material of dielectric material 121 may be the same as or different from the material of dielectric material 98. Dielectric material 121 may be deposited using a suitable technique (e.g., CVD, PVD, ALD, PECVD, etc.). Dielectric material 121 may extend along the sidewalls and bottom surface of memory film 90 within trench 120. After deposition, a planarization process (e.g., CMP, etch back, etc.) may be performed to remove excess portions of dielectric material 121. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, resistive memory layer 107, conductive lines 106, conductive lines 108, and dielectric material 121 may be substantially flush. In this manner, adjacent conductive lines 106 and conductive lines 108 are separated by isolation regions formed by dielectric material 121 and dielectric material 98.

[0066] Go to Figure 28C , a plan view illustrating an intermediate step in forming a hybrid memory array 200 is shown, according to some embodiments. Figure 28C The hybrid memory array 200 shown in FIG. Figure 28B , except that the hybrid memory cells 202 are formed in a "staggered" or "interleaved" arrangement. Figure 28B In the hybrid memory array 200, the conductive lines 106 and the conductive lines 108 in the same row are aligned, but Figure 28C , conductive lines 106 and conductive lines 108 are offset. This is an example arrangement, and other configurations or arrangements are possible.

[0067] exist Figure 29A 、 Figure 29B 、 Figure 29C and Figure 29D In some embodiments, a contact 110 is made for the conductive line 72 . Figure 29A -D shows the arrangement of the hybrid memory cell 202 similar to Figure 28C The "staggered" arrangement shown in . Figure 29A shows a perspective view of a hybrid memory array 200; Figure 29B A top-down view of a hybrid memory array 200 is shown; Figure 29C Shown along Figure 29A A cross-sectional view of the device and underlying substrate taken along line 29C-29C'; and Figure 29D Shown along Figure 1A5 '. In some embodiments, the stepped shape of the conductive lines 72 can provide a surface on each conductive line 72 for connection of the conductive contact 110. Forming the contact 110 can include, for example, patterning an opening in the IMD 70 and the dielectric layer 52 using a combination of photolithography and etching to expose a portion of the conductive layer 54. A liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as a CMP process, can be performed to remove excess material from the surface of the IMD 70. The remaining liner and conductive material form the contact 110 in the opening.

[0068] like Figure 29A , conductive contacts 112 may also be made for conductive lines 106 and 108, respectively, as shown in the perspective view of FIG. 1 . Conductive contacts 112 may be electrically connected to conductive lines 116A and 116B. Conductive contacts 110 may be electrically connected to conductive lines 116C, which connect the memory array to lower / upper level circuitry (e.g., control circuitry) and / or signal, power, and ground lines in the semiconductor die. For example, conductive vias 118 may extend through IMD 70 to electrically connect conductive lines 116C to lower level circuitry of interconnect structure 220 and active devices on substrate 50, such as Figure 29C As shown. Other conductive vias can be formed through IMD 70 to electrically connect conductive lines 116A and 116B to underlying circuitry of interconnect structure 220. In alternative embodiments, wiring and / or power lines to and from hybrid memory array 200 can be provided by interconnect structures formed above hybrid memory array 200 in addition to or in lieu of interconnect structure 220. In this manner, a hybrid memory array 200 including hybrid memory cells 202 can be formed according to some embodiments, wherein each hybrid memory cell 202 is a hybrid memory cell including resistive-type memory (e.g., resistive memory layer 107) and transistor-type memory (204).

[0069] Figures 30A to 36D Various views are shown of intermediate steps in fabricating a hybrid memory array 300 according to some embodiments. The hybrid memory array 300 is similar to Figure 28A -C, except that the conductive line 72 is recessed before the memory film 90 and the OS layer 92 are deposited. For example, the hybrid memory array 300 includes a memory cell 302 having both transistor-type memory (e.g., transistor 204) and resistive-type memory (e.g., resistive memory layer 107) (see FIG. Figure 36DIn some cases, by forming the hybrid memory array 300 in this manner, parasitic coupling between adjacent memory cells 302 can be reduced, and the memory cell density of the hybrid memory array 300 can be increased. Figure 30A and Figure 31A shows a perspective view, and FIG. 30B, Figure 31B 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 、 Figure 36B and Figure 36C A cross-sectional view is shown. Figure 36A and Figure 36D Specifically, Figure 36B Shown through Figure 36A A cross-sectional view of reference section CC' is shown. Figure 36C Shown through Figure 36A The cross-sectional view of the reference section EE' is shown, and Figure 36D Shown through Figure 36B A plan view of reference section FF' is shown.

[0070] Figure 30A and Figure 30B A multi-layer stack 358 is shown in accordance with some embodiments. Figure 30A - The multi-layer stack 358 shown in B is similar to Figure 17A -B shows a multilayer stack 58. In some embodiments, the top layer of the multilayer stack 358 can be a dielectric layer 52, such as Figure 30A -B. Figure 30A -B can be constructed in the same Figure 17A For example, multilayer stack 358 may be formed from alternating layers of conductive layers 54 and dielectric layers 52. Multilayer stack 358 may then be patterned to have a stepped structure, and trenches 86 may then be patterned in multilayer stack 358 to form conductive lines 72.

[0071] exist Figure 31A and Figure 31BIn some embodiments, the sidewalls of the conductive line 72 are recessed to form a lateral recess 154. The recessing can be performed using an acceptable process (e.g., wet and / or dry etching). The recessing of the conductive line 72 can allow the memory film 90 and the OS layer 92 to be subsequently formed within the recess 154, which can reduce parasitic coupling between the memory cells 302. In some embodiments, the sidewalls of the conductive line 72 are recessed by wet etching using KOH, NH4OH, H2O2, etc., or a combination thereof. In some embodiments, the sidewalls of the conductive line 72 are recessed by dry etching using NH3, NF3, HF, etc., or a combination thereof. The distance D1 between the lateral recess 154 and the sidewalls of the dielectric layer 52 can be in the range of about 10 nm to about 100 nm. Other distances are also possible.

[0072] exist Figure 32 In the embodiment of the present invention, the memory film 90 is conformally deposited in the trench 86 over the exposed surface of the dielectric layer 52 and the conductive line 72. The memory film 90 can be similar to the previously described embodiment of the present invention. Figure 18A -B and can be formed in a similar manner. Memory film 90 covers the surface of conductive line 72 within lateral recess 154 and can partially or completely fill lateral recess 154. In some embodiments, memory film 90 can be formed on the sidewalls of conductive line 72 to a thickness ranging from about 3 nm to about 20 nm.

[0073] Go to Figure 33 According to some embodiments, portions of memory film 90 are removed. For example, portions of memory film 90 along the surface of dielectric layer 52 can be removed using an acceptable etching process. For example, the removal process can include wet etching using KOH, NH4OH, H2O2, or the like, or combinations thereof, and / or dry etching using Cl2, CF4, CH3F, CH2F2, or the like, or combinations thereof. Other wet or dry etching methods are possible, and the etching can include isotropic etching, anisotropic etching, or combinations thereof. In some embodiments, the etching process can remove portions of memory film 90 along the surface of dielectric layer 52, while retaining portions of memory film 90 on the sidewalls of conductive line 72. The remaining portions of memory film 90 on the sidewalls of conductive line 72 can have a thickness in a range of approximately 3 nm to approximately 15 nm, although other thicknesses are possible. In some embodiments, the removal process thins memory film 90 but leaves portions of memory film 90 on the surface of dielectric layer 52. Removing portions of memory film 90 is optional and is not performed in other embodiments.

[0074] exist Figure 3419A-B , OS layer 92 is conformally deposited in trench 86 over dielectric layer 52 and the exposed surface of memory film 90 within recess 154. OS layer 92 can be similar to OS layer 92 previously described with respect to FIG. 19A-B and can be formed in a similar manner. OS layer 92 covers the surface of memory film 90 within lateral recess 154 and can partially or completely fill lateral recess 154.

[0075] exist Figure 35 In some embodiments, portions of OS layer 92 are removed. Portions of OS layer 92 along the surface of dielectric layer 52 can be removed, for example, using an acceptable etching process. The etching process can include any acceptable etching process, such as wet etching, dry etching, RIE, NBE, etc., or a combination thereof. In some cases, the etching process can be anisotropic. In some embodiments, the etching process can remove portions of OS layer 92 along the surface of dielectric layer 52 while retaining portions of OS layer 92 on the sidewalls of memory film 90. The remaining portions of OS layer 92 may have sidewalls that are recessed from the sidewalls of dielectric layer 52, are substantially flush with the sidewalls of dielectric layer 52, or protrude from the sidewalls of dielectric layer 52. In some embodiments, the removal process thins OS layer 92 but leaves portions of OS layer 92 on the surface of dielectric layer 52. Removal of portions of OS layer 92 is optional and is not performed in other embodiments. Removal of portions of OS layer 92 is optional and is not performed in other embodiments.

[0076] Figure 36A 、 36B , 36C, and 36D illustrate the hybrid memory array 300 after subsequent processing according to some embodiments. Figure 36AThe structure shown in FIG-D includes dielectric material 98, resistive memory layer 107, conductive line 106, conductive line 108, and dielectric material 121. Dielectric material 98, resistive memory layer 107, conductive line 106, conductive line 108, and dielectric material 121 are similar to those shown in, for example, FIG28A-B and can be formed in a similar manner. For example, dielectric material 98 can be deposited in trench 86. A first set of trenches can then be formed in dielectric material 98, and resistive memory layer 107 and conductive line 106 can be formed in the trenches. A second set of trenches can then be formed in dielectric material 98, and conductive line 108 can be formed in these trenches. A third set of trenches can then be formed, and dielectric material 121 can be formed in these trenches to form isolation regions. Conductive line 106, conductive line 108, conductive line 72, memory film 90, and OS layer 92 form a transistor similar to transistor 204 described previously. In this manner, a hybrid memory array 300 including memory cells 302 may be formed according to some embodiments, wherein each memory cell 302 is a hybrid memory cell including resistive-type memory (eg, resistive memory layer 107 ) and transistor-type memory.

[0077] The memory arrays described herein (e.g., hybrid memory array 200, hybrid memory array 300, and other embodiments) can be considered "hybrid memory arrays" because each memory cell in the memory array is a "hybrid memory cell" that includes both resistive and transistor-type memory. As previously described, the resistive and transistor-type memory in each memory cell can be read or written independently. The embodiments described herein can allow different types of memory within a single memory array to be used for different applications.

[0078] As an example application, the hybrid memory described herein can allow for faster and more reliable training of neural networks (e.g., convolutional neural networks, deep neural networks, etc.). In some cases, the training process of a neural network (e.g., "weight training") can include performing a large number of write operations on a memory array. Therefore, a memory type that allows relatively fast and robust write operations, such as transistor-type memory, can be preferred for use during training. After the training process is complete, the final weights can be stored in the memory array for use during the operation of the neural network, which can include performing a large number of read operations on the memory array. Therefore, a memory type that allows relatively stable read operations and reliable data retention, such as resistive memory, can be preferred for use after training and during the operation of the neural network. Therefore, the embodiments described herein allow for a single hybrid memory array that includes transistor-type memory for weight training and resistive memory for weight storage. In this way, the advantages of both transistor-type memory and resistive memory can be utilized, which can improve the training speed and stability of neural networks, etc. This is an example, and other applications are also possible.

[0079] Go to Figures 37 to 39C , example read and write operations for the hybrid memory cell 202 are described, according to some embodiments. These are example operations, and different voltages, polarities, currents, etc. may be used in other cases. Figure 37 Schematic diagram of a hybrid memory cell 202 according to some embodiments is shown. The hybrid memory cell 202 may be similar to the one previously described for Figure 1A -C described hybrid memory unit 202. For example, Figure 37 The hybrid memory cell 202 shown in FIG. 1 includes a resistive type memory indicated by the resistive memory layer 107 and a transistor type memory indicated by the transistor 204. The hybrid memory cell 202 is electrically coupled to a word line (WL) indicated by the conductive line 72, a bit line (BL) indicated by the conductive line 106, and a source line (SL) indicated by the conductive line 108. Both the resistive memory layer 107 and the transistor 104 can be programmed or read using the same set of conductive lines 72, 106, and 108.

[0080] Figure 38A 、 Figure 38B and Figure 38C Write operations and read operations of a transistor-type memory (eg, transistor 204 ) of the hybrid memory cell 202 are shown in accordance with some embodiments. Figure 38A and Figure 38B An example binary write operation of a transistor-type memory of the hybrid memory cell 202 is shown. For example, Figure 38AIt can be shown that a "1" bit is written to a transistor-type memory, and Figure 38B Writing a "0" bit into a transistor-type memory can be illustrated. To write to the transistor-type memory, a write voltage is applied to the memory film 90 of the transistor 204 by applying appropriate voltages to the word line, bit line, and source line. By applying the write voltage to the memory film 90, the polarization direction of the region of the memory film 90 corresponding to the hybrid memory cell 202 can be changed. As a result, the corresponding threshold voltage of the corresponding transistor 204 can also be switched from a low threshold voltage to a high threshold voltage, or vice versa, so that a binary value can be stored in the hybrid memory cell 202. Since the word line intersects the bit line and source line, a single hybrid memory cell 202 can be selected for the write operation.

[0081] exist Figure 38A In the embodiment of the present invention, a first write operation is performed in which a positive voltage (VWL) is applied to the word line, a negative voltage (VBL) is applied to the bit line, and a negative voltage (VSL) is applied to the source line. This creates a first polarization direction within the memory film 90 of the transistor 204, so that the threshold voltage of the transistor 204 is in a low threshold voltage state. For example, the low threshold state can correspond to a "1" bit. For example, VWL can be approximately +2V, VBL can be approximately -2V, and VSL can be approximately -2V. Other voltages are also possible. In some embodiments, during the first write operation, the current flowing through the resistive memory layer 107 can be less than about 1μA, but other currents are also possible.

[0082] exist Figure 38B In the embodiment of the present invention, a second write operation is performed in which a negative voltage (VWL) is applied to the word line, a positive voltage (VBL) is applied to the bit line, and a positive voltage (VSL) is applied to the source line. This creates a second polarization direction within the memory film 90 of the transistor 204, so that the threshold voltage of the transistor 204 is in a high threshold voltage state. For example, the high threshold state may correspond to a "0" bit. For example, VWL may be approximately -2V, VBL may be approximately +2V, and VSL may be approximately +2V. Other voltages are also possible. In some embodiments, the current flowing through the resistive memory layer 107 during the second write operation may be less than approximately 1μA, but other currents are also possible.

[0083] exist Figure 38C In the embodiment of the present invention, a read operation is performed in which a read voltage is applied to the word line. For example, the read voltage can be between a low threshold voltage (e.g., Figure 38A) and a high threshold voltage (e.g., FIG. 38B ). Depending on the polarization direction of the corresponding region of the memory film 90, the transistor 204 of the hybrid memory cell 202 may be conductive or non-conductive. For example, when the transistor 204 is in a low threshold voltage state, the transistor 204 conducts current when a read voltage is applied, and when the transistor 204 is in a high threshold voltage state, the transistor 204 does not conduct current when a read voltage is applied. As a result, the current (I read ) may or may not flow through transistor 204 and may determine the binary value stored in the transistorized memory of hybrid memory cell 202. Because the word lines intersect the bit lines and source lines, a single hybrid memory cell 202 may be selected for a read operation.

[0084] exist Figure 38C In the read operation shown, a positive read voltage (VWL) is applied to the word line, a positive voltage (VBL) is applied to the bit line, and the source line is coupled to ground (VSL). The current (I read ) to determine whether transistor 204 is on, thereby determining whether transistor 204 is in a low threshold voltage state or a high threshold voltage state. As an example, VWL can be approximately +1V, VBL can be approximately +0.5V, and VSL can be grounded (approximately 0V). Other voltages are also possible. In some embodiments, during a read operation, the current flowing through the resistive memory layer 107 when transistor 204 is on can be in the range of approximately 5μA to approximately 10μA, although other currents are possible.

[0085] Figure 39A 、 Figure 39B and Figure 39C A write operation and a read operation of a resistive memory (eg, resistive memory layer 107 ) of the hybrid memory cell 202 are shown in accordance with some embodiments. Figure 39A and Figure 39B An example binary write operation of a resistive memory of the hybrid memory cell 202 is shown. For example, Figure 39A It can be shown that a "1" bit is written to a resistive memory, and Figure 39BWriting a "0" bit to a resistive memory may be illustrated. To write to the resistive memory, a write voltage is applied to the resistive memory layer 107 of the transistor 204 by applying appropriate voltages to the word line, bit line, and source line. By applying the write voltage to the resistive memory layer 107, the resistance of the region of the resistive memory layer 107 corresponding to the hybrid memory cell 202 can be changed. Thus, the resistive memory layer 107 can be placed in a high resistance state or a low resistance state, thereby allowing a binary value to be stored in the hybrid memory cell 202. Various types of resistive memory may be used in the hybrid memory cell 202, and the mechanism of the resistance change may depend on the type of resistive memory used. For example, the change in resistance state may be caused by the formation or destruction of a conductive path within the resistive memory layer 107, a phase change of the material within the resistive memory layer 107, or other mechanisms. Because the word line intersects the bit line and source line, a single hybrid memory cell 202 can be selected for a write operation.

[0086] exist Figure 39A In FIG. 1 , a first write operation is performed in which a positive voltage (VWL) is applied to the word line, a positive voltage (VBL) is applied to the bit line, and the source line is coupled to ground (VSL). The voltage applied to the word line (VWL) is higher than the threshold voltage of transistor 204, causing transistor 204 to turn on, thereby allowing current (I write1 ) flows through the resistive memory layer 107. This causes the region of the resistive memory layer 107 corresponding to the memory cell 202 to be in a low resistance state. For example, the low resistance state may correspond to a "1" bit. As an example, VWL may be approximately +2V, VBL may be a voltage in the range of approximately 1.5V to approximately 2V, and VSL may be grounded (approximately 0V). Other voltages are also possible. In some embodiments, during the first write operation, the current (I write1 ) can be greater than about 100 μA, but other currents are possible.

[0087] exist Figure 39B In the second write operation, a positive voltage (VWL) is applied to the word line, a positive voltage (VSL) is applied to the source line, and the bit line is coupled to ground (VBL). The voltage applied to the word line (VWL) is higher than the threshold voltage of transistor 204, causing transistor 204 to turn on, thereby allowing current (I write0) flows through the resistive memory layer 107. This causes the region of the resistive memory layer 107 corresponding to the memory cell 202 to be in a high resistance state. For example, the high resistance state may correspond to a "0" bit. As an example, VWL may be approximately +2V, VSL may be a voltage in the range of approximately 1.5V to approximately 2V, and VBL may be grounded (approximately 0V). Other voltages are also possible. In some embodiments, during the second write operation, the current (I write0 ) can be greater than about 100 μA, but other currents are possible.

[0088] exist Figure 39C In the embodiment, a read operation is performed, wherein a read voltage is applied to the resistive memory layer 107 of the transistor 204 by applying appropriate voltages to the word line, the bit line, and the source line. By applying the read voltage to the resistive memory layer 107, the current (I read ) flows through the resistance memory layer 107, which depends on the resistance of the resistance memory layer 107. For example, when the resistance memory layer 107 is in a low resistance state, when a read voltage is applied, the current (I read ) is relatively high, and when the resistance memory layer 107 is in a high resistance state, when a read voltage is applied, the current (I read ) is relatively low. As a result, the binary value stored in the resistive memory of the hybrid memory cell 202 can be determined. Because the word line intersects the bit line and the source line, a single hybrid memory cell 202 can be selected for a read operation.

[0089] exist Figure 39C In the read operation shown, a positive read voltage (VWL) is applied to the word line, a positive voltage (VBL) is applied to the bit line, and the source line is coupled to ground (VSL). The voltage applied to the word line (VWL) is higher than the threshold voltage of transistor 204, causing transistor 204 to turn on, thereby allowing current (I read ) flows through the resistive memory layer 107. The current (I read ) to determine whether the resistive memory layer 107 is in a low resistance state or a high resistance state. For example, VWL can be approximately +2 V, VBL can be approximately +0.2 V, and VSL can be grounded (approximately 0 V). Other voltages are possible. In some embodiments, during a read operation, the current flowing through the resistive memory layer 107 can be in the range of approximately 1 μA to approximately 5 μA, although other currents are possible.

[0090] The embodiments described herein allow for a hybrid memory array in which each cell of the hybrid memory array is a hybrid memory cell that includes a transistor-type memory (e.g., FeFET, etc.) and a resistive-type memory (e.g., ReRAM, etc.). The transistor-type memory and the resistive-type memory of each hybrid memory cell can be independently programmed. In addition, the two types of memory in the hybrid memory array are accessed using the same conductive lines (e.g., bit lines, source lines, and word lines) without forming additional conductive line groups. In some cases, a hybrid memory array with two types of memory may allow for more efficient and robust read and write operations. For example, a neural network may use transistor-type memory for weight training and resistive-type memory for weight storage. By incorporating the two types of memory into the same memory array, improvements in performance, cost, and efficiency may be achieved. The embodiments described herein also allow for the manufacture of hybrid memory arrays in some cases without requiring significant additional processing steps or costs, and without significantly increasing the overall size of the memory array. For example, in some cases, the addition of resistive-type memory uses a single additional mask. In some cases, the resistive memory layer can also be formed within the existing memory array geometry. In this way, the embodiments described herein allow for cost-effective process integration of hybrid memory arrays.

[0091] According to one embodiment, a memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory and a resistive-type memory. The transistor-type memory includes: a memory film extending over a gate electrode; a channel layer extending over the memory film; a first source / drain electrode extending over the channel layer; and a second source / drain electrode extending along the channel layer. The resistive-type memory includes a resistive memory layer, wherein the resistive memory layer extends between the second source / drain electrode and the channel layer. In one embodiment, the memory film is a different material from the resistive memory layer. In one embodiment, the resistive memory layer includes a phase-change memory material. In one embodiment, the resistive memory layer includes a metal oxide. In one embodiment, the memory film includes a ferroelectric material. In one embodiment, the gate electrode is a word line of the memory array, the first source / drain electrode is a source line of the memory array, and the second source / drain electrode is a bit line of the memory array. In one embodiment, a first hybrid memory cell among the plurality of hybrid memory cells is located above a second hybrid memory cell among the plurality of hybrid memory cells, wherein the resistive memory layer of the first hybrid memory cell and the resistive memory layer of the second hybrid memory cell are the same continuous layer. In one embodiment, the resistive memory of a third hybrid memory cell among the plurality of hybrid memory cells is laterally offset from the resistive memory of a fourth hybrid memory cell among the plurality of hybrid memory cells. In one embodiment, the thickness of the resistive memory layer is between 3 nm and 20 nm. In one embodiment, the resistive memory layer surrounds the second source / drain electrodes.

[0092] According to one embodiment, a device includes: a semiconductor substrate; a word line extending over the semiconductor substrate; a ferroelectric layer extending along the word line, wherein the ferroelectric layer is in contact with the word line; an oxide semiconductor (OS) layer extending along the ferroelectric layer, wherein the ferroelectric layer is located between the oxide semiconductor (OS) layer and the word line; a source line extending along the ferroelectric layer, wherein the ferroelectric layer is located between the source line and the word line; a bit line extending along the ferroelectric layer, wherein the ferroelectric layer is located between the bit line and the word line; and resistive memory layers, wherein each resistive memory layer is located between a corresponding bit line and a word line. In one embodiment, the resistive memory layers include a transition metal oxide. In one embodiment, each resistive memory layer laterally surrounds a corresponding bit line. In one embodiment, the resistive memory layers are in physical contact with the oxide semiconductor (OS) layer. In one embodiment, the device includes a dielectric material extending along the ferroelectric layer, wherein the dielectric material is located between a source line and a bit line adjacent to the source line, wherein the plurality of resistive memory layers are in physical contact with the dielectric material.

[0093] According to one embodiment, a method includes: patterning a first trench extending through a first conductive line; depositing a memory film along the sidewalls and bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the memory film, wherein the OS layer extends along the sidewalls and bottom surface of the first trench; depositing a first dielectric material on the OS layer, wherein the first dielectric material fills a remaining portion of the first trench; patterning a second trench in the first dielectric material; depositing a resistive memory material on the sidewalls of the second trench; and depositing a first conductive material on the resistive memory material within the second trench, wherein the first conductive material fills the second trench. In one embodiment, the method further includes: forming a lateral recess in the first conductive line after patterning the first trench, wherein the memory film is deposited within the lateral recess. In one embodiment, the method further includes performing an etching process to remove a portion of the memory film. In one embodiment, the method further includes: patterning a third trench in the first dielectric material; and depositing a second conductive material within the third trench, wherein the second conductive material fills the third trench. In one embodiment, depositing the resistive memory material includes depositing a metal oxide using atomic layer deposition (ALD).

[0094] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0095] Example 1 is a memory array comprising: a plurality of hybrid memory cells, wherein each of the plurality of hybrid memory cells comprises: a transistor-type memory comprising: a memory film extending on a gate electrode; a channel layer extending on the memory film; a first source / drain electrode extending on the channel layer; and a second source / drain electrode extending along the channel layer; and a resistive-type memory comprising: a resistive memory layer, wherein the resistive memory layer extends between the second source / drain electrode and the channel layer.

[0096] Example 2 is the memory array of Example 1, wherein the memory film is a different material than the resistive memory layer.

[0097] Example 3 is the memory array of Example 1, wherein the resistive memory layer comprises a phase change memory material.

[0098] Example 4 is the memory array of Example 1, wherein the resistive memory layer comprises a metal oxide.

[0099] Example 5 is the memory array of Example 1, wherein the memory film comprises a ferroelectric material.

[0100] Example 6 is the memory array of Example 1, wherein the gate electrode is a word line of the memory array, the first source / drain electrode is a source line of the memory array, and the second source / drain electrode is a bit line of the memory array.

[0101] Example 7 is the memory array of Example 1, wherein a first hybrid memory cell among the plurality of hybrid memory cells is located above a second hybrid memory cell among the plurality of hybrid memory cells, wherein the resistive memory layer of the first hybrid memory cell and the resistive memory layer of the second hybrid memory cell are the same continuous layer.

[0102] Example 8 is the memory array of Example 1, wherein the resistive memory of a third hybrid memory cell in the plurality of hybrid memory cells is laterally offset from the resistive memory of a fourth hybrid memory cell in the plurality of hybrid memory cells.

[0103] Example 9 is the memory array of Example 1, wherein the thickness of the resistive memory layer is between 3 nm and 20 nm.

[0104] Example 10 is the memory array of Example 1, wherein the resistive memory layer surrounds the second source / drain electrodes.

[0105] Example 11 is a device comprising: a semiconductor substrate; a word line extending over the semiconductor substrate; a ferroelectric layer extending along the word line, wherein the ferroelectric layer is in contact with the word line; an oxide semiconductor (OS) layer extending along the ferroelectric layer, wherein the ferroelectric layer is located between the oxide semiconductor (OS) layer and the word line; a plurality of source lines extending along the ferroelectric layer, wherein the ferroelectric layer is located between the plurality of source lines and the word lines; a plurality of bit lines extending along the ferroelectric layer, wherein the ferroelectric layer is located between the plurality of bit lines and the word lines; and a plurality of resistance memory layers, wherein each of the plurality of resistance memory layers is located between a corresponding bit line of the plurality of bit lines and the word line.

[0106] Example 12 is the device of Example 11, wherein the plurality of resistive memory layers comprises a transition metal oxide.

[0107] Example 13 is the device of Example 11, wherein each resistive memory layer of the plurality of resistive memory layers laterally surrounds the corresponding bit line of the plurality of bit lines.

[0108] Example 14 is the device of Example 11, wherein the plurality of resistive memory layers are in physical contact with the oxide semiconductor (OS) layer.

[0109] Example 15 is the device described in Example 11, further comprising a dielectric material extending along the ferroelectric layer, the dielectric material being located between a source line among the multiple source lines and a bit line adjacent to the source line among the multiple bit lines, wherein the multiple resistive memory layers physically contact the dielectric material.

[0110] Example 16 provides a method comprising: patterning a first trench extending through a first conductive line; depositing a memory film along the sidewalls and bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the memory film, wherein the OS layer extends along the sidewalls and bottom surface of the first trench; depositing a first dielectric material on the OS layer, wherein the first dielectric material fills a remaining portion of the first trench; patterning a second trench in the first dielectric material; depositing a resistive memory material on the sidewalls of the second trench; and depositing a first conductive material on the resistive memory material within the second trench, wherein the first conductive material fills the second trench.

[0111] Example 17 is the method of Example 16, further comprising: forming a lateral recess in the first conductive line after patterning the first trench, wherein the memory film is deposited within the lateral recess.

[0112] Example 18 is the method of Example 17, further comprising performing an etching process to remove a portion of the memory film.

[0113] Example 19 is the method of Example 16, further comprising: patterning a third trench in the first dielectric material; and depositing a second conductive material within the third trench, wherein the second conductive material fills the third trench.

[0114] Example 20 is the method of Example 16, wherein depositing the resistive memory material includes depositing a metal oxide using atomic layer deposition (ALD).

Claims

1. A memory array comprising: A plurality of hybrid memory cells, wherein each hybrid memory cell of the plurality of hybrid memory cells comprises: Transistor-type memories, including: a memory film extending over the gate electrode; a channel layer extending on the memory film; a first source / drain electrode extending over the channel layer; and a second source / drain electrode extending along the channel layer; and Resistive memories, including: A resistive memory layer extends between the second source / drain electrodes and the channel layer.

2. The memory array according to claim 1, wherein: The memory film is a different material from the resistive memory layer.

3. The memory array according to claim 1 , wherein: The resistive memory layer includes a phase change memory material.

4. The memory array according to claim 1, wherein: The resistance memory layer includes metal oxide.

5. The memory array according to claim 1, wherein The memory film includes a ferroelectric material.

6. The memory array according to claim 1, wherein: The gate electrode is a word line of the memory array, the first source / drain electrode is a source line of the memory array, and the second source / drain electrode is a bit line of the memory array.

7. The memory array according to claim 1, wherein: A first hybrid memory cell of the plurality of hybrid memory cells is located above a second hybrid memory cell of the plurality of hybrid memory cells, wherein the resistive memory layer of the first hybrid memory cell and the resistive memory layer of the second hybrid memory cell are the same continuous layer.

8. The memory array according to claim 1, wherein: The resistive memory of a third hybrid memory cell among the plurality of hybrid memory cells is laterally offset from the resistive memory of a fourth hybrid memory cell among the plurality of hybrid memory cells.

9. The memory array according to claim 1, wherein: The thickness of the resistance memory layer is between 3 nm and 20 nm.

10. The memory array according to claim 1, wherein: The resistive memory layer surrounds the second source / drain electrodes.

11. A hybrid memory device comprising: semiconductor substrates; a word line extending above the semiconductor substrate; a ferroelectric layer extending along the word line, wherein the ferroelectric layer contacts the word line; an oxide semiconductor (OS) layer extending along the ferroelectric layer, wherein the ferroelectric layer is located between the oxide semiconductor (OS) layer and the word line; a plurality of source lines extending along the ferroelectric layer, wherein the ferroelectric layer is located between the plurality of source lines and the word lines; a plurality of bit lines extending along the ferroelectric layer, wherein the ferroelectric layer is located between the plurality of bit lines and the word lines; and A plurality of resistive memory layers, wherein each of the plurality of resistive memory layers is located between a corresponding bit line of the plurality of bit lines and the word line.

12. The hybrid memory device according to claim 11, wherein: The plurality of resistive memory layers include a transition metal oxide.

13. The hybrid memory device according to claim 11, wherein: Each of the plurality of resistive memory layers laterally surrounds the corresponding bit line of the plurality of bit lines.

14. The hybrid memory device according to claim 11, wherein: The plurality of resistance memory layers are in physical contact with the oxide semiconductor (OS) layer.

15. The hybrid memory device according to claim 11, further comprising a dielectric material extending along the ferroelectric layer, the dielectric material being located between a source line among the plurality of source lines and a bit line adjacent to the source line among the plurality of bit lines, wherein The plurality of resistive memory layers physically contact the dielectric material.

16. A method of forming a hybrid memory device, comprising: patterning a first trench extending through the first conductive line; depositing a memory film along the sidewalls and bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the memory film, wherein the OS layer extends along sidewalls and a bottom surface of the first trench; depositing a first dielectric material on the OS layer, wherein the first dielectric material fills a remaining portion of the first trench; patterning a second trench in the first dielectric material; depositing a resistive memory material on sidewalls of the second trench; and A first conductive material is deposited on the resistive memory material in the second trench, wherein the first conductive material fills the second trench.

17. The method according to claim 16, further comprising: After patterning the first trench, a lateral recess is formed in the first conductive line, wherein the memory film is deposited within the lateral recess.

18. The method of claim 17, further comprising performing an etching process to remove a portion of the memory film.

19. The method according to claim 16, further comprising: patterning a third trench in the first dielectric material; as well as A second conductive material is deposited in the third trench, wherein the second conductive material fills the third trench.

20. The method according to claim 16, wherein Depositing the resistive memory material includes depositing a metal oxide using atomic layer deposition (ALD).

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