Shielded gate trench field-effect transistor and its fabrication method

Abstract

This application relates to a shielded gate trench field-effect transistor and its fabrication method. The shielded gate trench field-effect transistor includes: providing a substrate and forming an initial trench within the substrate; forming a first sacrificial protective layer on the sidewalls of the initial trench; further etching the substrate to form a first trench at the bottom of the initial trench; forming a shielded gate dielectric layer on the surface of the trench wall of the first trench; removing the first sacrificial protective layer and further etching the substrate to expand the initial trench to form a second trench; forming a shielded gate, an isolation structure, a control gate dielectric layer, and a control gate. The shielded gate is formed within the first trench, the control gate is formed within the second trench, the isolation structure is formed between the shielded gate and the control gate, and the control gate dielectric layer is formed between the control gate and the sidewalls of the second trench. This application can effectively guarantee the shielding function of the shielded gate while achieving good polysilicon filling.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a shielded gate trench field-effect transistor and its fabrication method. Background Technology

[0002] In existing processes for fabricating shielded-gate trench field-effect transistors, a trench is typically formed first, followed by the formation of the shielding gate structure and the control gate structure within the trench. The shielding gate structure usually uses polysilicon as the shielding gate. To prevent gaps from forming due to poor filling of the polysilicon within the trench, a specific trench tilt angle is usually set to ensure proper polysilicon filling within the trench.

[0003] However, this method requires precise control of the trench tilt angle. If the trench tilt angle is too large, it will cause uneven electric field distribution on the shielding gate, thereby reducing its shielding function and increasing the risk of leakage. If the trench tilt angle is too small, the polysilicon filling capacity will be poor. Summary of the Invention

[0004] Based on this, embodiments of this application provide a shielded gate trench field-effect transistor and its fabrication method, which can effectively ensure the shielding function of the shielded gate while achieving good polysilicon filling.

[0005] A method for fabricating a shielded gate trench field-effect transistor, characterized by comprising:

[0006] Provide a substrate and form initial trenches within the substrate;

[0007] A first sacrificial protective layer is formed on the sidewall of the initial trench;

[0008] The substrate is further etched to form a first trench at the bottom of the initial trench;

[0009] A shielding grid dielectric layer is formed on the surface of the trench wall of the first trench;

[0010] The first sacrificial protective layer is removed, and the substrate is further etched to expand the initial trench to form a second trench;

[0011] A shielding gate, an isolation structure, a control gate dielectric layer, and a control gate are formed. The shielding gate is formed in a first trench, the control gate is formed in a second trench, the isolation structure is formed between the shielding gate and the control gate, and the control gate dielectric layer is formed between the control gate and the sidewall of the second trench.

[0012] In one embodiment, the sidewall of the second trench is inclined, and the inclination angle of the second trench is greater than that of the first trench.

[0013] In one embodiment, forming the shielding gate, the isolation structure, the control gate dielectric layer, and the control gate includes:

[0014] A second sacrificial protective layer is formed on the sidewall of the second trench;

[0015] A shielding gate material layer is deposited in the second trench and the first trench, and the shielding gate material layer is etched back to form a shielding gate in the first trench.

[0016] An isolation structure is formed on the shielding gate;

[0017] A control gate dielectric layer is formed on the sidewall surface of the second trench;

[0018] A control gate is formed within the second trench.

[0019] In one embodiment, before forming a control gate dielectric layer between the control gate and the sidewall of the second trench, the method further includes:

[0020] Remove the second sacrificial protective layer.

[0021] In one embodiment, the isolation structure is located within the first trench.

[0022] In one embodiment, the thickness of the second sacrificial protective layer is less than the thickness of the shielding gate dielectric layer.

[0023] In one embodiment, the angle between the first trench and the bottom surface of the substrate is 89° to 90°.

[0024] A shielded gate trench field-effect transistor, comprising:

[0025] Base;

[0026] A second trench is formed within the substrate;

[0027] The first trench is formed at the bottom of the second trench, and the second trench is formed by etching extending from above the first trench;

[0028] A shielding gate is located within the first trench;

[0029] A shielding gate dielectric layer is formed between the sidewall of the first trench and the shielding gate.

[0030] The control gate is located within the second trench;

[0031] A control gate dielectric layer is formed between the second trench sidewall and the control gate;

[0032] An isolation structure is located between the shielding gate and the control gate.

[0033] In one embodiment, the isolation structure is located within the first trench.

[0034] In one embodiment, the angle between the first trench and the bottom surface of the substrate is 89° to 90°.

[0035] The above-mentioned method for fabricating a shielded gate trench field-effect transistor involves etching the substrate three times: the first trench is formed by etching the bottom of the initial trench, and the second trench is formed by etching the sidewall of the initial trench.

[0036] Therefore, this application can achieve sufficient filling capacity of the shielding gate by adjusting the opening and tilt angle of the second trench. Simultaneously, the first trench can have a smaller tilt angle compared to existing methods that form trenches through a single etching process. Thus, this application allows for a more uniform electric field distribution on the shielding gate, resulting in better shielding. Furthermore, it can increase the number of trenches per unit area. Additionally, the method of this application does not require additional photomask processing, resulting in lower processing costs. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic flowchart of a method for fabricating a shielded gate trench field-effect transistor according to one embodiment;

[0039] Figures 2 to 16 This is a schematic diagram of the fabrication process of a shielded gate trench field-effect transistor provided in one embodiment. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0045] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shape of the area shown herein, but rather include shape deviations due to, for example, manufacturing techniques.

[0046] Please see Figure 1 This application provides a method for fabricating a shielded gate trench field-effect transistor, comprising the following steps:

[0047] Step S100: Provide a substrate 100 and form an initial trench 100a within the substrate 100. (See [link to relevant documentation]). Figure 2 ;

[0048] Step S200: A first sacrificial protective layer 200 is formed on the sidewall of the initial trench 100a. Please refer to [link to relevant documentation]. Figure 4 ;

[0049] Step S300: The substrate 100 is further etched to form a first trench 101a at the bottom of the initial trench 100a. Please refer to [link to relevant documentation]. Figure 5 ;

[0050] In step S400, a shielding grid dielectric layer 300 is formed on the surface of the trench wall of the first trench 101a. Please refer to [link to relevant documentation]. Figure 6 ;

[0051] In step S500, the first sacrificial protective layer 300 is removed, and the substrate 100 is further etched to expand the initial trench 100a to form the second trench 102a. (See also...) Figure 7 as well as Figure 8 ;

[0052] In step S600, a shielding gate 400, an isolation structure 500, a control gate dielectric layer 600, and a control gate 700 are formed. The shielding gate 400 is formed within a first trench 101a, the control gate 700 is formed within a second trench, the isolation structure 500 is formed between the shielding gate 400 and the control gate 700, and the control gate dielectric layer 600 is formed between the control gate 700 and the sidewall of the second trench 102a. (See also...) Figure 16 .

[0053] In step S100, please refer to Figure 2 The substrate 100 may include, but is not limited to, a silicon substrate.

[0054] Forming a patterned mask layer 800 on the substrate 100 may specifically include:

[0055] First, a mask material layer is formed on the surface of the substrate 100. The mask material layer can be a silicon oxide layer, a silicon nitride layer, a carbon layer, or other hard mask layers.

[0056] Then, the mask material layer is patterned using processes such as photolithography and etching to obtain a patterned mask layer 800. The patterned mask layer 800 has an opening that exposes the substrate 100 and defines the shape and position of the initial trench 100a.

[0057] Then, the substrate 100 is etched based on the patterned mask layer 800 to form an initial trench 100a within the substrate 100.

[0058] In step S200, please refer to Figure 4 The material of the first sacrificial protective layer 200 may include insulating protective materials such as silicon nitride.

[0059] Specifically, a first protective material layer 201 can be formed on the surface of the trench wall of the initial trench 100a and the surface of the patterned mask layer 800. Please refer to [link to relevant documentation]. Figure 3 .

[0060] Then, the first protective material layer 201 at the bottom of the initial trench 100a and on the surface of the patterned mask layer 800 is removed, and the remaining first protective material layer 201 constitutes the first sacrificial protective layer 200.

[0061] Specifically, the first protective material layer 201 at the bottom of the initial trench 100a and on the surface of the patterned mask layer 800 can be removed by dry etching. Since dry etching has anisotropic characteristics, the first protective material layer 201 at the bottom of the initial trench 100a and on the surface of the patterned mask layer 800 can be removed, while the first protective material layer 201 on the sidewalls of the initial trench 100a is retained as the first sacrificial protective layer 200.

[0062] In step S300, please refer to Figure 5 The substrate 100 can continue to be etched based on the patterned mask layer 800, thereby forming the first trench 101a at the bottom of the initial trench 100a.

[0063] In step S400, please refer to Figure 6 A high-quality shielding grid dielectric layer 300 can be formed on the surface of the wall of the first trench 101a using a furnace tube method. Specifically, it can be an oxide layer.

[0064] In step S500, please refer to Figure 7 After the shielding barrier dielectric layer 300 is formed, the first sacrificial protective layer 200 is removed, thereby exposing the sidewalls of the initial trench 100a.

[0065] Then, please see Figure 7 as well as Figure 8 After the sidewalls of the initial trench 100a are exposed, the substrate 100 can be etched to extend the initial trench 100a to form the second trench 102a.

[0066] As an example, after removing the first sacrificial protective layer 200, the patterned mask layer 800 can be etched first by acid etching or the like to expose the upper surface of the substrate 100 on both sides of the initial trench 100a. Then, the exposed part of the substrate 100 can be etched by dry etching or the like to expand the initial trench 100a to form the second trench 102a.

[0067] In step S600, please refer to Figure 16 The materials of the shielding gate 400 and / or the control gate 700 may include, but are not limited to, polysilicon. The material of the isolation structure 500 may be oxide or the like. The control gate dielectric layer 600 may also be an oxide layer. Its material may be the same as or different from that of the shielding gate dielectric layer 300; there is no limitation on this.

[0068] In this embodiment, by etching the substrate 100 three times, the first trench 101a is formed by etching the bottom of the initial trench 101, and the second trench 102a is formed by etching the sidewall of the initial trench 100a.

[0069] Therefore, this embodiment can achieve sufficient filling capacity for the shielding gate 400 by adjusting the opening and tilt angle of the second trench 102a. Simultaneously, the first trench 101a can have a smaller tilt angle compared to existing methods that form trenches through a single etching process. Therefore, this embodiment can achieve a more uniform electric field distribution on the shielding gate 400, resulting in better shielding. Furthermore, it can increase the number of trenches per unit area. Additionally, this embodiment does not require additional photomask processing, resulting in lower processing costs.

[0070] In one embodiment, the angle between the sidewall of the first trench 101a and the bottom surface of the substrate 100 is 89° to 90°.

[0071] At this point, the trench inclination angle of the first trench 101a is as small as 0° to 1°, thereby effectively ensuring the shielding function of the shielding gate 400. It can be understood that the trench inclination angle is the angle at which the trench sidewall is tilted relative to the vertical direction. The vertical direction is the direction perpendicular to the bottom surface of the substrate 100.

[0072] In one embodiment, the angle between the sidewall of the first trench 101a and the bottom surface of the substrate 100 is 89.2° to 89.7°. In this case, the trench inclination angle of the first trench 101a is as small as 0.3° to 0.2°.

[0073] This embodiment can ensure the shielding function of the shielding gate 400, and further ensure the filling capacity of the shielding gate 400 in the first trench 101a.

[0074] As an example, the angle between the sidewall of the first trench 101a and the bottom surface of the base 100 can be 89.5°. That is, the trench inclination angle of the first trench 101a is 0.5°.

[0075] In one embodiment, the sidewalls of the second trench 102a are inclined. Furthermore, the inclination angle of the second trench 102a is greater than that of the first trench 101a, thereby facilitating the fabrication of the first trench 101a and the filling of the shielding gate within the first trench 101a. It can be understood that the inclination angle of the first trench 101a can be 0°.

[0076] In one embodiment, step S600 includes:

[0077] Step S610: A second sacrificial protective layer 900 is formed on the sidewall of the second trench 102a. (See also...) Figure 9 ;

[0078] In step S620, a shielding gate material layer 401 is deposited in the second trench 102a and the first trench 101a, and the shielding gate material layer 401 is etched back to form a shielding gate 400 in the first trench 101a. (See also...) Figure 10 as well as Figure 11 ;

[0079] Step S630: An isolation structure 500 is formed on the shielding gate 400. Please refer to [link to relevant documentation]. Figure 13 ;

[0080] In step S650, a control gate dielectric layer 600 is formed on the sidewall surface of the second trench 102a. (See also...) Figure 15 ;

[0081] In step S660, a control gate 700 is formed in the second trench 102a. Please refer to [link to relevant documentation]. Figure 16 .

[0082] In step S610, a second sacrificial protective layer 900 can be formed on the sidewall of the second trench 102a by thermal oxidation.

[0083] In step S620, specifically, a shielding gate material layer 401 can be deposited simultaneously on the surface of the patterned mask layer 800, in the second trench 102a, and in the first trench 101a. Then, the shielding gate material layer 401 is etched back to remove the shielding gate material layer 401 on the surface of the patterned mask layer 800 and in the second trench 102a, thereby forming a shielding gate 400 in the first trench 101a.

[0084] As an example, the thickness of the second sacrificial protective layer 900 is less than the thickness of the shielding gate dielectric layer 300. In this case, the second trench 102a can have a larger remaining opening area, thereby allowing the shielding gate material layer 401 to better fill the first trench 101a without forming filling gaps.

[0085] In step S630, an isolation material 601 can be deposited on the surface of the patterned mask layer 800, the surface of the shielding gate 400, and within the second trench 102a by high-density plasma (HDP) chemical vapor deposition. (See also...) Figure 12 .

[0086] Then, the isolation material 601 on the surface of the patterned mask layer 800 and within the second trench 102a is removed, and the remaining isolation material 601 constitutes the isolation structure 500. Please refer to [link to relevant documentation]. Figure 13 .

[0087] In step S650, a high-quality control grid dielectric layer 600 can be formed on the sidewall of the second trench 102a by means of a furnace tube method.

[0088] In step S660, a control gate material layer 501 can first be formed on the surface of the patterned mask layer 800 and within the second trench 102a. Then, the control gate material layer 501 on the surface of the patterned mask layer 800 is removed, and the remaining control gate material layer 501 constitutes the control gate 700.

[0089] In this embodiment, by forming a second sacrificial protection layer 900 on the sidewall of the second trench 102a, the substrate 100 (such as a silicon substrate) can be effectively protected when the shielding gate material layer 401 (such as a polysilicon layer) is removed and the shielding gate 400 is formed in the first trench 101a.

[0090] In one embodiment, prior to step S650, the method further includes:

[0091] Step S640, remove the second sacrificial protection layer 900, please refer to Figure 14 .

[0092] The thickness of the second sacrificial protective layer 900 can be set to be relatively small, making it easy to remove.

[0093] The second sacrificial protective layer 900 can effectively protect the substrate 100 when the shielding gate material layer 401 is removed to form the shielding gate 400. However, its own structure may be damaged during this process, thus affecting its quality performance.

[0094] Therefore, in this embodiment, the second sacrificial protective layer 900 is removed, and then the control gate dielectric layer 600 is formed on the sidewall of the second trench 102a, thereby making the device performance more reliable.

[0095] In one embodiment, the isolation structure 500 is located within the first trench 101a.

[0096] At this time, the isolation structure 500 does not cover the second sacrificial protective layer 900 located on the sidewall of the second trench 102a, thereby facilitating the removal of the second sacrificial protective layer 900.

[0097] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0098] In one embodiment, see Figure 16 A shielded gate trench field-effect transistor is also provided, comprising: a substrate 100, a second trench 102a, a first trench 101a, a shielded gate 400, a shielded gate dielectric layer 300, a control gate 700, a control gate dielectric layer 600, and an isolation structure 500. The second trench 102a is formed within the substrate 100;

[0099] A first trench 101a is formed at the bottom of a second trench 102a, and the second trench is etched and etched extending from above the first trench 101a. A shielding gate 400 is located within the first trench 101a. A shielding gate dielectric layer 300 is formed between the sidewall of the first trench 101a and the shielding gate 400. A control gate 700 is located within the second trench 102a. A control gate dielectric layer 600 is formed between the sidewall of the second trench 102a and the control gate 700. An isolation structure 500 is located between the shielding gate 400 and the control gate 700.

[0100] In this embodiment, the second trench 102a is formed by etching an extension from above the first trench 101a. Therefore, by adjusting the opening and tilt angle of the second trench 102a, the shielding gate 400 can have sufficient filling capacity. Simultaneously, the first trench 101a can have a smaller tilt angle compared to existing methods that form trenches through a single etching process. Therefore, this embodiment allows for a more uniform electric field distribution on the shielding gate 400, resulting in better shielding. Furthermore, it increases the number of trenches per unit area.

[0101] In one embodiment, the isolation structure 500 is located within the first trench 101a.

[0102] In one embodiment, the angle between the first trench 101a and the bottom surface of the substrate 100 is 89° to 90°.

[0103] In one embodiment, the groove inclination angle of the second groove is greater than that of the first groove.

[0104] For specific limitations on shielded gate trench field-effect transistors, please refer to the above section on specific limitations on shielded gate trench field-effect transistors, which will not be elaborated further here.

[0105] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a shielded gate trench field effect transistor, characterized by, The method comprises: providing a substrate and forming an initial trench in the substrate; forming a first sacrificial protection layer on the sidewall of the initial trench; continuing etching the substrate to form a first trench in the bottom of the initial trench; forming a shield gate dielectric layer on the sidewall surface of the first trench by a tube furnace method; removing the first sacrificial protection layer and continuing etching the substrate to expand the initial trench to form a second trench, the sidewall of the second trench is inclined, and the trench inclination angle of the second trench is greater than the trench inclination angle of the first trench; forming a shield gate, an isolation structure, a control gate dielectric layer and a control gate, the shield gate is formed in the first trench, the control gate is formed in the second trench, the isolation structure is formed between the shield gate and the control gate, and the control gate dielectric layer is formed between the control gate and the sidewall of the second trench; the isolation structure is located in the first trench; the forming of the shield gate, the isolation structure, the control gate dielectric layer and the control gate comprises: forming a second sacrificial protection layer on the sidewall of the second trench; the thickness of the second sacrificial protection layer is less than the thickness of the shield gate dielectric layer, a shield gate material layer is deposited in the second trench with the second sacrificial protection layer and the first trench with the shield gate dielectric layer, and the shield gate material layer is etched back to form a shield gate in the first trench; forming an isolation structure on the shield gate, the isolation structure does not cover the second sacrificial protection layer located on the sidewall of the second trench; forming a control gate dielectric layer on the sidewall surface of the second trench; forming a control gate in the second trench; before forming the control gate dielectric layer between the control gate and the sidewall of the second trench, further comprising: removing the second sacrificial protection layer.

2. The method of manufacturing a shielded gate trench field effect transistor according to claim 1, wherein The included angle between the first trench and the bottom surface of the substrate is 89° to 90°.

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