Semiconductor device with high driving capability and steep SS characteristics and manufacturing method

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. According to embodiments, the semiconductor device may include: a substrate; a channel portion comprising: a first portion including a fin-shaped structure protruding relative to the substrate; a second portion, above and spaced apart from the first portion, including one or more nanowires or nanosheets spaced apart from each other; source / drain portions disposed on opposite sides of the channel portion in a first direction and connected to the channel portion; and a gate stack extending on the substrate in a second direction intersecting the first direction to intersect the channel portion.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device with high driving capability and steep subthreshold swing (SS) and a method for manufacturing the same. Background Art

[0002] Fin field-effect transistors (FinFETs) are the current mainstream devices. However, as devices are further miniaturized, their gate control capabilities weaken and the short channel effect deteriorates, which manifests as a deterioration in subthreshold swing (SS), an increase in leakage current, and especially an increase in power consumption during the switching process. To improve device performance, nanowire or nanosheet gate-all-around devices can be used. Gate-all-around (GAA) devices, especially nanowire gate-all-around devices, have significantly improved SS, but their driving performance is reduced. To improve driving performance, more nanowires need to be stacked (which is difficult to process) or more devices need to be arranged in parallel (which occupies a large area). Summary of the Invention

[0003] In view of the above, an object of the present disclosure is at least partially to provide a semiconductor device having high driving capability and a steep subthreshold swing (SS) and a method for manufacturing the same.

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a channel portion, comprising: a first portion, comprising a fin-shaped structure protruding relative to the substrate; a second portion, above and spaced apart from the first portion, comprising one or more nanowires or nanosheets spaced apart from each other; a source / drain portion, arranged on opposite sides of the channel portion in a first direction and connected to the channel portion; and a gate stack, extending on the substrate along a second direction intersecting the first direction to intersect with the channel portion.

[0005] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a ridge structure extending along a first direction on a substrate, wherein the ridge structure has a first stack of a first plurality of semiconductor layers at least at an upper portion; forming a dummy gate on the substrate extending along a second direction intersecting the first direction to intersect with the ridge structure; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer exposing the dummy gate; removing the dummy gate to form a gate groove in the interlayer dielectric layer; in the gate groove, removing a portion of the semiconductor layer from the first stack of the ridge structure to form one or more nanowires or nanosheets separated from each other, and the lower portion of the ridge structure is separated from the nanowires or nanosheets to form a fin structure; and forming a gate stack in the gate groove to intersect with the nanowires or nanosheets and the fin structure.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned semiconductor device.

[0007] According to an embodiment of the present disclosure, the semiconductor device can be similar to a fin field effect transistor (FinFET) at the bottom and similar to a gate-all-around (GAA) nanowire or nanosheet device at the top. During the switching process, the advantages of the upper GAA device can be utilized to obtain a steeper SS, thereby reducing leakage current and power consumption. When fully turned on, the lower FinFET and the upper GAA device can provide a conduction current together, achieving a larger current than when the device fully adopts a GAA structure, thereby improving the driving performance of the device. Therefore, the power consumption, speed and other performance of the semiconductor device according to the embodiment of the present disclosure or the integrated circuit (IC) chip including the same are improved. In addition, the manufacturing method according to the embodiment of the present disclosure is compatible with the mainstream FinFET process and is not much different from the GAA device process, and can be achieved by adding a few process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0009] Figures 1 to 11(c) Schematically illustrates some stages in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0010] Figures 12(a) to 13(b) Schematically illustrates some stages in a process of manufacturing a semiconductor device according to another embodiment of the present disclosure;

[0011] Figures 14 to 17 Schematically illustrates some stages in a process of manufacturing a semiconductor device according to yet another embodiment of the present disclosure,

[0012] in,

[0013] Figure 2(a) 、 2(b) 5(a), 6(a), 7(a), and 11(a) are top views, showing the positions of line AA′ and line BB′, respectively;

[0014] Figure 1 、 3(a) , 4(a), 5(b), 6(b), 7(b), 8(a), 9(a), 10(a), 11(b), 12(a), and 13(a) are cross-sectional views along line AA′;

[0015] Figure 3(b) 、 4(b) , 5(c), 6(c), 7(c), 8(b), 9(b), 10(b), 11(c), 12(b), 13(b), 14 to 17 are cross-sectional views along line BB′. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0017] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clarity, certain details are magnified and certain details may be omitted. The shapes of the various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0018] According to an embodiment of the present disclosure, a semiconductor device is provided. According to an embodiment of the present disclosure, the semiconductor device may include a channel portion and a source / drain portion located on opposite sides of the channel portion. The source / drain portions may be electrically connected through the channel portion. The channel portion may have different forms in the upper and lower portions, respectively. Specifically, the upper portion of the channel portion may include (one) nanowire or nanosheet or (multiple) nanowires or nanosheets spaced apart from each other, and the lower portion of the channel portion may include a fin-shaped structure protruding relative to the substrate. The fin-shaped structure may be integral or a stack of multiple semiconductor layers, such as an alternating stack of two or more semiconductor layers. The nanowires or nanosheets in the upper portion of the channel portion may have the same semiconductor material as the lower portion of the channel portion or a portion of the layer in the lower portion. In addition, the upper and lower portions of the channel portion may be self-aligned in the vertical direction.

[0019] The gate stack can be formed to intersect the channel portion. On the one hand, the gate stack can surround the nanowire or nanosheet on the upper portion of the channel portion, thereby forming a gate-all-around (GAA) configuration, and thus can achieve a steeper subthreshold swing (SS) characteristic. On the other hand, the gate stack can cover the sidewall (and optionally, the top surface) of the lower portion of the fin-shaped channel portion, thereby being similar to a fin field effect transistor (FinFET) configuration, and thus can achieve higher driving performance.

[0020] Such a semiconductor device can be manufactured, for example, as follows. A ridge structure extending in a first direction can be provided on a substrate. The ridge structure has a stack of several semiconductor layers at least at the top, for example, an alternating stack of two (or more) semiconductor layers having etching selectivity relative to each other, so that a channel portion in the form of a separate nanosheet or nanosheet can be subsequently released at the top. The ridge structure can similarly have the form of a semiconductor layer stack at the bottom (which can have the same or similar configuration as the semiconductor layer stack at the top, or can have a different configuration), or it can also be integral.

[0021] Semiconductor devices can be manufactured based on such a ridge structure. The manufacturing method according to the embodiment of the present disclosure is compatible with mainstream FinFET processes because such a ridge structure is similar to a fin.

[0022] For example, a dummy gate extending in a second direction intersecting (e.g., perpendicular) to the first direction may be formed on the substrate. The portion of the ridge structure covered by the dummy gate may subsequently define a channel portion. Source / drain portions may be formed on opposite sides of the dummy gate in the first direction. For example, the source / drain portion may be formed by ion implantation into the portion of the ridge structure exposed by the dummy gate, or may be formed by etching the ridge structure using the dummy gate as a mask and then growing an epitaxial layer (which may be in-situ doped during growth).

[0023] Afterwards, an interlayer dielectric layer can be formed on the substrate to cover the source / drain portion, while exposing the dummy gate so that a replacement gate process can be performed. In the replacement gate process, the dummy gate can be removed, so that a gate groove can be formed in the interlayer dielectric layer, and thus the portion of the ridge structure previously covered by the dummy gate (the portion between the source / drain portion) can be exposed to define the channel portion. The difference from the FinFET process is that one or more semiconductor layers can be released on the upper part of the ridge structure. Here, "release" can refer to separating the corresponding semiconductor layer from other semiconductor layers between the source / drain portion. In this way, the gate stack formed subsequently can surround the released semiconductor layer. The lower part of the ridge structure can remain substantially unaffected, and thus a fin-shaped structure is formed. Thus, the channel portion can include a lower fin structure and one or more (separated from each other) nanowires or nanosheets above and separated from the fin structure.

[0024] A gate stack may be formed to intersect the channel portion. More specifically, the gate stack may be formed in the gate trench, thereby surrounding the nanowires or nanosheets in the upper portion of the channel portion and covering the top surface and sidewalls (in the second direction) of the fin structure in the lower portion of the channel portion. Gate stacks of different configurations may be formed for the upper and lower portions of the channel portion, respectively.

[0025] The present disclosure can be presented in various forms, some of which are described below. In the following description, reference is made to the selection of various materials. In addition to considering its function (for example, semiconductor materials are used to form active areas and dielectric materials are used to form electrical isolation), the selection of materials also takes into account etching selectivity. In the following description, the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when the following mentions etching a certain material layer, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0026] Figures 1 to 11(c) Some stages in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0027] like Figure 1 As shown, a substrate 1001 is provided. The substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SO1) substrates, and compound semiconductor substrates such as SiGe substrates. For ease of explanation, the following description uses a bulk Si substrate as an example. Here, a silicon wafer is provided as substrate 1001.

[0028] On the substrate 1001, a plurality of stacks S1, S2, S3, and S4 may be formed, each stack comprising two or more semiconductor layers. Figure 1 As shown, the first stack S1 may include a stack of a first semiconductor layer 1003-1 and a second semiconductor layer 1005-1, the second stack S2 may include a stack of a first semiconductor layer 1003-2 and a second semiconductor layer 1005-2, the third stack S3 may include a stack of a first semiconductor layer 1003-3 and a second semiconductor layer 1005-3, and the fourth stack S4 may include a stack of a first semiconductor layer 1003-4 and a second semiconductor layer 1005-4. That is, in this example, the stacks S1, S2, S3, and S4 are implemented by alternating the first and second semiconductor layers, which is more convenient in terms of process.

[0029] Here, four stacks S1, S2, S3, and S4 are shown. However, the present disclosure is not limited thereto. For example, more or fewer stacks may be formed. Furthermore, each stack is not limited to including two semiconductor layers, but may include more semiconductor layers. The thickness of each semiconductor layer in each stack may be the same or different, and the thickness of semiconductor layers in different stacks may be the same or different.

[0030] Here, the lower M (in Figure 1In the example, M=2) stacks (ie, S1 and S2) can then be used to define the fin, while the upper N (in Figure 1 In the example of (N=2), multiple stacks (ie, S3 and S4) can then be used to define nanowires or nanosheets. The values ​​of M and N can be set differently depending on the device design.

[0031] These semiconductor layers can be formed on the substrate 1001 by, for example, epitaxial growth. Thus, each semiconductor layer can have good crystal quality and can be a single crystal structure. Adjacent semiconductor layers among these semiconductor layers can have etching selectivity. In the case where the substrate 1001 is a silicon wafer, each stacked layer can be Si / Si 1-x Ge x stacked, Si / Ge stacked, Si 1-x Ge x / Ge stacked layers, etc. (0<x<1). For example, the first semiconductor layers 1003-1, 1003-2, 1003-3, and 1003-4 may include Si 1-x Ge x (0<x<1), and the second semiconductor layers 1005-1, 1005-2, 1005-3, and 1005-4 may include Si. Typically, the semiconductor layers are not intentionally doped. According to other embodiments of the present disclosure, the semiconductor layers may also be in-situ doped during epitaxial growth to achieve certain doping characteristics. For example, the doping characteristics in the channel portion (later formed from portions of these semiconductor layers) may be used to adjust the threshold voltage (Vt).

[0032] In this example, each stack has the same or similar configuration, for example, each stack has two semiconductor layers, and the corresponding first semiconductor layer in each stack can have the same material (and the thickness can be equal) and the corresponding second semiconductor layer can also have the same material (and the thickness can be equal). However, the present disclosure is not limited to this. For example, there can be some stacks with different configurations, such as different in at least one aspect such as the number of stacked semiconductor layers, the material of the semiconductor layer, and the thickness of the semiconductor layer. In particular, the lower M stacks (i.e., S1 and S2) and the upper N stacks (i.e., S3 and S4) can have different configurations, and even the lower M stacks can be implemented by a single layer (e.g., Si layer).

[0033] Subsequent processes may be performed similarly to conventional GAA nanowire or nanosheet device fabrication processes until the channel portion is released.

[0034] For example, Figure 2(a) and 2(b)As shown, a mask layer 1007a or 1007b can be formed on the stacked layers. The mask layer 1007a or 1007b can be patterned into a nanowire (FIG. 2(a)) or nanosheet (FIG. 2(b)), such as a line or strip extending in the horizontal direction (referred to as the "first direction") in the figure. For example, the mask layer 1007a or 1007b can include a photoresist or a hard mask (e.g., an oxide, a nitride, or a stack thereof). The following description primarily uses the case of nanosheets as an example, but the description is equally applicable to the case of nanowires.

[0035] Then, if Figure 3(a) and 3(b) As shown, mask layer 1007a or 1007b can be used as an etching mask to selectively etch each layer on substrate 1001 sequentially, for example, through vertical reactive ion etching (RIE) or self-aligned double patterning (SADP). Furthermore, etching can be performed into substrate 1001 to form trenches therein for subsequent isolation formation. In this way, each layer on substrate 1001 is patterned into a ridge structure corresponding to mask layer 1007a or 1007b. Mask layer 1007a or 1007b can then be removed as needed.

[0036] For electrical isolation purposes, such as Figure 4(a) and 4(b) As shown, an isolation portion 1009, such as a shallow trench isolation (STI), can be formed on the substrate 1001, for example, in the aforementioned trench. The isolation portion 1009 can achieve electrical isolation of the device and can include, for example, an oxide (e.g., silicon oxide). For example, the isolation portion 1021 can be formed by depositing an oxide on the substrate 1001, performing a planarization process such as chemical mechanical polishing (CMP) on the deposited oxide, and etching back the planarized oxide such as RIE.

[0037] like Figure 5(a) 、 5(b) As shown in Figures 5(c) and 5(d), a dummy gate 1011 extending along a second direction (e.g., a vertical direction within the paper in Figure 5(a), a direction perpendicular to the paper in Figure 5(b), and a horizontal direction within the paper in Figure 5(c)) that intersects (e.g., is perpendicular to) the first direction can be formed on the isolation portion 1009 to intersect with the ridge structure. The dummy gate 1011 can include a material having an etching selectivity relative to the ridge structure, such as polycrystalline silicon, amorphous silicon, etc. The pattern of the dummy gate 1011 (generally a hard mask is also formed on it, not shown in the figure) can be used as a mask to perform ion implantation on the ridge structure to achieve the desired source / drain doping characteristics.

[0038] In addition, a sidewall spacer (not shown in the figure) may be formed on the sidewall of the dummy gate. The sidewall spacer and its manufacturing method may be the same as in conventional technology, and will not be described in detail here.

[0039] like Figure 6(a) 、 6(b) As shown in FIG6( c ), an interlayer dielectric layer 1013 may be formed on the substrate 1001. For example, the interlayer dielectric layer 1013 may be formed by depositing oxide and performing a planarization process, such as CMP, on the deposited oxide. The CMP may stop at the dummy gate 1011 to expose the dummy gate 1011.

[0040] Here, an interlayer dielectric layer 1013 is directly formed to cover the ridge structure on two opposite sides of the dummy gate 1011 ( Figure 6(a) and 6(b) The covered ridge structure portions may then be used as source / drain portions of the device. However, the present disclosure is not limited thereto. For example, before forming the interlayer dielectric layer 1013, the pseudo gate 1011 (and the hard mask thereon and the sidewalls on the sidewalls) may be used as a mask to selectively etch each stack so that each stack remains below the pseudo gate 1011 (and the sidewalls on the sidewalls). Additional source / drain portions may be formed by epitaxial growth on the sidewalls of each stack on opposite sides of the pseudo gate 1011. The material of the grown source / drain portion may be selected to optimize device performance. For example, semiconductor materials with different lattice constants may be selected to apply stress to the channel portion implemented by each stack.

[0041] like Figure 7(a) 、 7(b) As shown in FIG7( c ), the dummy gate 1011 can be removed by selective etching, thereby forming a gate trench (the space originally occupied by the dummy gate 1011) in the interlayer dielectric layer 1013. This exposes the portion of the ridge structure previously covered by the dummy gate 1011. This portion can be used to define the channel portion.

[0042] Next, the channel release operation can be performed. In a GAA nanowire or nanosheet device, to achieve a GAA configuration, it is necessary to release a certain amount of space around the nanowire or nanosheet channel so that the gate stack subsequently formed in this space can surround the nanowire or nanosheet channel. This is the so-called "channel release" operation.

[0043] Unlike conventional GAA nanowire or nanosheet manufacturing processes, according to embodiments of the present disclosure, the channel release operation can be performed only on the upper N stacks (i.e., S3 and S4), and not on the lower M stacks (i.e., S1 and S2). Note that the values ​​of M and N can be set differently depending on the device design and can be smaller (e.g., 1) or larger.

[0044] In order to achieve different treatment of the upper and lower parts, such as Figure 8(a) and 8(b)As shown, a mask layer 1015 can be formed on the substrate. The mask layer 1015 can have an etch selectivity relative to the interlayer dielectric layer 1013, the isolation portion 1009 (and the various semiconductor layers in the ridge structure), and can include, for example, spin-on carbon (SOC), advanced patterned film (APF), or amorphous silicon. The mask layer 1015 can be formed within the gate trench. For example, a mask material can be deposited to fully fill the space left in the interlayer dielectric layer 1013 due to the removal of the dummy gate 1011. The deposited mask material can then be planarized, such as by CMP. The CMP process can stop at the interlayer dielectric layer 1013, thereby forming the mask layer 1015.

[0045] It should be noted that, in this embodiment, the mask layer 1015 is re-formed after the dummy gate 1011 is removed. However, the present disclosure is not limited thereto. For example, the dummy gate 1011 can be directly used as a mask without forming the mask layer 1015 separately. Alternatively, according to another embodiment, if the etching recipe used in the operation of releasing the channel portion is selective for each semiconductor layer in the M stacked layers at the bottom (or for the single semiconductor layer when the bottom is a single semiconductor layer), the operation of releasing the channel portion can be performed directly after removing the dummy gate 1011 without forming a mask layer.

[0046] like Figure 9(a) and 9(b) As shown, the mask layer 1015 thus formed can be etched back to lower its top surface, thereby exposing the upper N stacked layers (i.e., S3 and S4). The etch back can be performed using a dry etching process such as RIE, or a wet etching process. The etching recipe used not only has a certain selectivity for the interlayer dielectric layer 1013, but also has a high selectivity (e.g., greater than 20:1) for the exposed stacked layers. When the mask layer 1015 comprises amorphous silicon, an alkaline solution such as aqueous ammonia can be used for wet etching to achieve high selectivity.

[0047] In FIG9( b ), after etching back, the top surface of the mask layer 1015′ is shown to be (slightly) lower than the top surface of the uppermost semiconductor layer 1005-2 of the lower M stacks (i.e., S1 and S2). This can fully expose the upper N stacks (i.e., S3 and S4) to release the channel portion.

[0048] Here, M and N can be adjusted by controlling the etch-back depth of the mask layer 1015. For example, a smaller etch-back depth results in a smaller N and a larger M; a larger etch-back depth results in a larger N and a smaller M. Here, both M and N are natural numbers greater than zero.

[0049] For the exposed N stacks (ie, S3 and S4), the channel portion can be released. Figure 10(a) and 10(b)As shown, at least one semiconductor layer in each stack S3, S4 can be removed by selective etching, leaving at least one other semiconductor layer. For example, the first semiconductor layer 1003-3, 1003-4 in each stack S3, S4 can be removed, and the second semiconductor layer 1005-3, 1005-4 can be left. In this way, the middle part of the second semiconductor layer 1005-3, 1005-4 (the part originally covered by the pseudo gate 1011) can be formed in a suspended form, and the channel portion defined thereby can be surrounded by the gate stack from all sides to form a GAA structure. The second semiconductor layer 1005-3, 1005-4, whose middle part serves as the channel portion, can have a suitable semiconductor material, such as Si or Si as described above. 1-x Ge x , in Si 1-x Ge x In this case, the mobility is higher, which is beneficial to improving device performance. Of course, for the sake of device performance consistency, the upper N stacks (i.e., S3 and S4) can have the same configuration, so that the same semiconductor layer in each of the N stacks can be released to define the channel portion.

[0050] The lower M stacked layers (i.e., S1 and S2) are covered by the mask layer 1015′ and can remain substantially unaffected, thereby forming a fin-shaped structure protruding relative to the substrate 1001. The mask layer 1015′ can then be removed by selective etching. The selective etching can be performed using dry or wet etching. For example, in the case of SOC or APF, oxygen plasma can be used; in the case of amorphous silicon, an alkaline solution such as ammonia water (e.g., at approximately 60 to 70°C and a concentration greater than 1:100) can be used.

[0051] Afterwards, a gate stack can be fabricated.

[0052] For example, Figure 11(a) 、 11(b) As shown in FIG11( c ), a gate dielectric layer 1019 and a gate metal layer (e.g., including a work function adjustment layer 1021 and a gate conductor layer 1023) may be sequentially formed in the gate trench. For example, the gate dielectric layer 1019 may include a high-k gate dielectric such as HfO2, Al2O3, ZrO2, or a stack thereof; the work function adjustment layer 1021 may include TiN, TiAlN, TaN, or a stack thereof such as TiN / TaN / TiN, TiN / TaN / TiN / TiAlN / TiN, etc.; and the gate conductor layer 1023 may include W, Co, Ru, etc. Before forming the high-k gate dielectric, an interfacial layer may be formed, such as an oxide formed by an oxidation process or deposition method such as atomic layer deposition (ALD).

[0053] In addition, before forming the gate stack, inner sidewalls (not shown) can be formed on the sidewalls of the upper first semiconductor layers 1003-3 and 1003-4 exposed by the operation of releasing the channel portion. The inner sidewalls and their fabrication methods can be the same as those in conventional techniques and will not be described in detail here.

[0054] As shown by the dotted circle in Figure 11(c), the channel portion of the resulting semiconductor device can include two parts, upper and lower: in the upper part, the channel portion is in the form of separated nanosheets or nanowires, the number of which is N, and they are respectively surrounded by gate stacks, thereby forming a GAA configuration; while in the lower part, the channel portion is in the form of a fin-shaped structure protruding relative to the substrate 1001, and the gate stack surrounds the sidewalls and top surface of the fin-shaped structure, thus similar to a FinFET configuration. Therefore, on the one hand, a steeper SS characteristic can be achieved through the GAA configuration of the upper part; on the other hand, enhanced driving performance can be achieved through the FinFET configuration of the lower part. Moreover, the upper and lower parts of the semiconductor device are manufactured in the same process, except that an additional channel release operation is performed on the upper part.

[0055] In addition, as shown in FIG11( b ), the positions of the source / drain portion and the channel portion are schematically shown by dotted lines. Specifically, the channel portion is located in the middle, while the source / drain portions are located on opposite sides of the channel portion. Although the channel portion has different forms at the top and bottom as described above, the source / drain portions on each side are integrated.

[0056] Since the channel portion has different forms at the upper and lower portions, in order to optimize device performance, the configuration of the gate stack may also be optimized for the upper and lower portions.

[0057] The gate stack (gate dielectric layer 1019 / work function adjustment layer 1021 / gate conductor layer 1023) formed above can be configured for the lower channel portion to achieve a certain equivalent work function or threshold voltage (Vt). A different gate stack can be configured for the upper channel portion, for example, with at least one of the gate dielectric layer and the gate metal layer (including the work function adjustment layer and the gate conductor layer) being different to achieve a certain equivalent work function or threshold voltage (Vt). The entire semiconductor device can have a substantially uniform threshold voltage (Vt).

[0058] For example, Figure 12(a) and 12(b) As shown, the previously formed gate stack can be etched back to expose the upper channel portion. In this example, the gate dielectric layer 1019 and the gate metal layer (work function adjustment layer 1021, gate conductor layer 1023) are both etched back. However, the present disclosure is not limited to this. For example, only the gate metal layer can be etched back, while the gate dielectric layer 1019 remains.

[0059] Afterwards, if Figure 13(a) and13(b) As shown, another gate stack can be similarly formed in the space created by etching back in the interlayer dielectric layer 1013, including a gate dielectric layer 1019′ (if the gate dielectric layer 1019 is retained, no additional formation is required) and a gate metal layer (including a work function adjustment layer 1021′ and a gate conductor layer 1023′). In addition, the gate conductor layer 1023′ can include the same material as the gate conductor layer 1023, and the work function or Vt can be adjusted by the work function adjustment layer 1021′.

[0060] In the case where the gate dielectric layer 1019' is additionally formed, the two gate conductor layers formed successively may be separated by the gate dielectric layer 1019'. In a subsequent metallization process, the gate conductor layers may be connected to each other through interconnection.

[0061] In the above embodiment, the channel portion is released first and then the gate stack is formed. However, the present disclosure is not limited thereto.

[0062] For example, Figure 14 As shown, the gate stack (gate dielectric layer 1019 / work function regulating layer 1021 / gate conductor layer 1023) can be directly formed without releasing the channel portion at the upper portion. Figure 15 As shown, the gate stack can be etched back so that its top surface is lowered to expose the upper N stacks (i.e., S3 and S4). That is, in this embodiment, the gate stack can be used as a mask layer in the channel release operation without the need to additionally form the mask layer 1015 as described above. Here, the top surface of the gate stack (gate dielectric layer 1019″ / work function adjustment layer 1021″ / gate conductor layer 1023″) after etching back can be (slightly) higher than the top surface of the uppermost semiconductor layer 1009 of the lower M stacks (i.e., S1 and S2), which allows the gate stack (gate dielectric layer 1019″ / work function adjustment layer 1021″ / gate conductor layer 1023″) after etching back to well cover the entire sidewalls of the lower M stacks. As shown Figure 16 As shown, for the exposed stack, the channel portion can be released as described above. Figure 17 As shown, another gate stack may be formed, including a gate dielectric layer 1019', a work function regulating layer 1021' and a gate conductor layer 1023'. Here, the gate stacks formed successively may have the same configuration as each other, or different configurations.

[0063] The semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such a semiconductor device, and an electronic device can be constructed therefrom. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device. The electronic device may also include a display screen that cooperates with the integrated circuit and components such as a wireless transceiver that cooperates with the integrated circuit. Such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, mobile power supplies, etc.

[0064] According to an embodiment of the present disclosure, a method for manufacturing a system-on-chip (SoC) is also provided. The method may include the above method. Specifically, multiple devices may be integrated on a chip, at least some of which are manufactured according to the method of the present disclosure.

[0065] While the above description does not provide detailed technical details regarding the patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0066] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a ridge structure extending along a first direction on a substrate, wherein the ridge structure has a first stack of a first plurality of semiconductor layers at least on an upper portion; forming a dummy gate on the substrate and extending along a second direction intersecting the first direction to intersect the ridge structure; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer exposes the dummy gate; removing the dummy gate, thereby forming a gate trench in the interlayer dielectric layer; In the gate trench, a portion of the semiconductor layer is removed from the first stack of the ridge structure to form one or more nanowires or nanosheets separated from each other, and a lower portion of the ridge structure is separated from the nanowires or nanosheets to form a fin structure; as well as A gate stack is formed in the gate trench to intersect the nanowire or nanosheet and the fin structure.

2. The method according to claim 1, wherein Providing the ridge structure includes: One semiconductor layer or a second stack having a second plurality of semiconductor layers is formed by epitaxial growth, and the first stack is formed on the one semiconductor layer or the second stack.

3. The method according to claim 2, wherein: The nanowires or nanosheets each include the same material as the one semiconductor layer or at least one semiconductor layer in the second stack.

4. The method according to claim 2, wherein: The first stack and the second stack each include an alternating stack of a first semiconductor layer and a second semiconductor layer, and the nanowire or nanosheet each includes one of the first semiconductor layer and the second semiconductor layer.

5. The method according to claim 1, wherein Removing a portion of the semiconductor layer from the first stack of the ridge structure includes: forming a mask layer in the gate groove to shield the lower portion of the ridge structure; removing the portion of the semiconductor layer from the first stack by selective etching; and The mask layer is removed.

6. The method according to claim 1, wherein Forming a gate stack includes: A first gate dielectric layer and a first gate metal layer are sequentially formed in the gate trench.

7. The method according to claim 6, further comprising: recessing the first gate metal layer to expose the nanowires or nanosheets; as well as A second gate metal layer is further formed in the gate trench to surround the nanowire or nanosheet.

8. The method according to claim 7, wherein: In the operation of exposing the nanowires or nanosheets, the method further comprises: recessing the first gate dielectric layer, The method further includes: further forming a second gate dielectric layer in the gate trench, wherein the second gate metal layer is formed on the second gate dielectric layer.

9. The method according to claim 1, wherein: Removing a portion of the semiconductor layer from the first stack of the ridge structure includes: In the gate trench, forming a first gate dielectric layer and a first gate metal layer in sequence; recessing the first gate dielectric layer and the first gate metal layer to expose the first stack; removing the portion of the semiconductor layer from the first stack by selective etching, and Forming a gate stack includes: A second gate dielectric layer and a second gate metal layer are further formed in sequence in the gate trench to surround the nanowire or nanosheet.

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