Time-varying gain circuit

Abstract

The present invention provides a time-varying gain circuit, which includes a gain control start-up circuit and a gain recovery circuit over time. The gain control start-up circuit and the gain recovery circuit over time are electrically connected. It is a time-varying gain circuit with low noise, low power consumption, and continuously variable gain. At the same time, the circuit is not limited by the supply voltage, solving the design problem of time-varying gain circuits with low noise, low power consumption, low voltage, and continuously variable gain in existing active sonar detection technologies, and has important research significance and application value. It has important research significance and application value.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and more specifically, particularly relates to a time-varying gain circuit. Background Art

[0002] Briefly speaking, a time-varying gain amplifier circuit is an amplifier circuit whose gain is a function of time (distance). Since in an active sonar detection system, time actually corresponds to the distance of the target from the antenna, from this perspective, in an active sonar detection system, it can be called a distance gain amplifier circuit by people.

[0003] The working mechanism of a time-varying gain amplifier circuit is to attenuate or amplify the scattered echo of a near target with a lower gain, while amplify the scattered echo of a far target with a higher gain, so that the echo signal entering the data acquisition circuit becomes relatively stable. Eventually, the strong signal of the shallow target echo is attenuated or suppressed, avoiding the amplifier from saturating and overloading or the amplifier output exceeding the input range of the A / D converter; the weak signal of the deep target echo is effectively amplified to ensure the acquisition and discrimination of the target signal. It is mainly to eliminate the propagation attenuation difference of the echo signal when the distance between the target and the detection system is different, make the echo signal entering the processing system relatively stable, and ultimately ensure the recognition and judgment of the target signal.

[0004] There are many schemes for designing a time-varying gain amplifier. Time-varying gain amplifiers produced by many foreign companies can adjust the gain and gain range, and the gain value (dB) changes linearly with the external control voltage, which can meet the requirements of the original radar system. Currently, the more widely used is a programmable gain amplifier with a linear relationship between the control voltage and the gain, and a variable gain amplifier with a linear relationship between the control voltage and the gain is used to achieve gain control. However, in the field of active sonar detection systems, it is required that the reference voltage must be relatively stable, which cannot be achieved by the existing technology, and it is sensitive to capacitive loads, prone to self-excitation, cannot be powered by a low voltage (3V), the gain change is stepwise, the input voltage range is narrow, and the power consumption is large. These are all serious problems currently faced. Obviously, with the development of science and technology, the traditional time-varying gain circuit can no longer meet the current needs. Therefore, there is an urgent need for a new time-varying gain circuit to solve the technical problems in the current industry field.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these technical solutions are described in the technical background part of the present invention. Summary of the Invention

[0006] (1) Technical Problem

[0007] In summary, how to solve the design problem of the time-varying gain circuit in the active sonar detection technology of the prior art, which has different frequencies, requires low noise, low power consumption, low voltage, and continuously variable gain, has become an urgent problem to be solved by those skilled in the art.

[0008] (2) Technical solution

[0009] The purpose of the present invention is to provide a time-varying gain circuit. In the present invention, the time-varying gain circuit includes:

[0010] A gain control start circuit (E1) and a gain recovery circuit over time (E2), and the gain control start circuit (E1) and the gain recovery circuit over time (E2) are electrically connected.

[0011] The gain control start circuit (E1) includes a capacitor (C5), a resistor (R4), a monostable flip-flop (M), a capacitor (C6), a resistor (R5), and a power supply (VDD). The control signal input line (L1) is electrically connected to one end of the capacitor (C5), and the other end of the capacitor (C5) is electrically connected to the input terminal 5-pin B terminal of the monostable flip-flop (M). One end of the resistor (R4) is electrically connected to both the 5-pin B terminal of the monostable flip-flop (M) and the capacitor (C5), and the other end of the resistor (R4) is connected to the 4-pin A terminal of the monostable flip-flop (M) and grounded.

[0012] The 1-pin C terminal of the monostable flip-flop (M) is grounded and electrically connected to one end of the capacitor (C6). The other end of the capacitor (C6) is electrically connected to the 2-pin RC terminal of the monostable flip-flop (M). The 2-pin of the monostable flip-flop (M) is electrically connected to one end of the resistor (R5). The other end of the resistor (R5) is electrically connected to the 3-pin CLR terminal of the monostable flip-flop (M) and is connected to the power supply (VDD). The gain control start circuit (E1) further includes an analog switch (N) and a resistor (R6). The 6-pin Q terminal of the monostable flip-flop (M) is electrically connected to the analog switch (N) through the control terminal 1-pin of the analog switch (N). The common terminal 10-pin of the analog switch (N) is electrically connected to one end of the resistor (R6), and the other end of the resistor (R6) is connected to the power supply (VDD). The capacitor (C5) and the resistor (R4) form a differentiating circuit, and the capacitor (C6) and the resistor (R5) form an integrating circuit.

[0013] The gain recovery circuit over time (E2) includes a resistor (R1), a resistor (R2), a resistor (R3), and a capacitor (C4). The 2-pin NIA terminal of the analog switch (N) is electrically connected to one end of the resistor (R2), the resistor (R3), and the capacitor (C4) respectively. The other ends of the resistor (R3) and the capacitor (C4) are both grounded. The gain recovery circuit over time (E2) further includes an amplifier circuit (P). A signal input (Vi) is connected to one end of the resistor (R1) through a first capacitor (C1). The other end of the resistor (R1) is connected to one end of a second capacitor (C2), a diode V1, and a diode V2 respectively. The other end of the second capacitor (C2) is electrically connected to the amplifier circuit (P). The other end of the diode V2 is grounded. The other end of the diode V1 is electrically connected to one end of the resistor (R2) and a capacitor (C3) respectively. The other end of the capacitor (C3) is grounded.

[0014] Preferably, in the time-varying gain circuit provided by the present invention, the first capacitor (C1) includes a plurality of first capacitor groups, namely C11, C12, C13, C14... C1n, where n≥1 and n is a positive integer.

[0015] Preferably, in the time-varying gain circuit provided by the present invention, the first capacitor groups are connected in parallel with each other, and one end of each first capacitor group is electrically connected to the signal input (Vi) terminal, and the other end of each first capacitor group is electrically connected to the resistor (R1).

[0016] Preferably, in the time-varying gain circuit provided by the present invention, each first capacitor group includes a control switch and a fixed capacitor with a fixed capacitance value, and the control switch and the corresponding fixed capacitor are connected in series.

[0017] Preferably, in the time-varying gain circuit provided by the present invention, the second capacitor (C2) includes a plurality of second capacitor groups, namely C21, C22, C23, C24... C2n, where n≥1 and n is a positive integer.

[0018] Preferably, in the time-varying gain circuit provided by the present invention, the second capacitor groups are connected in parallel with each other, and one end of each second capacitor group is electrically connected to the signal input (Vi) terminal, and the other end of each second capacitor group is electrically connected to the resistor (R1).

[0019] Preferably, in the time-varying gain circuit provided by the present invention, each second capacitor group includes a control switch and a fixed capacitor with a fixed capacitance value, and the control switch and the corresponding fixed capacitor are connected in series.

[0020] Preferably, in the time-varying gain circuit provided by the present invention, the resistor (R2) and the resistor (R3) in the time-varying gain circuit are adjustable resistors.

[0021] Preferably, in the time-varying gain circuit provided by the present invention, the resistor (R5) and the resistor (R6) are adjustable resistors.

[0022] Preferably, in the time-varying gain circuit provided by the present invention, the monostable flip-flop M is a retriggerable monostable flip-flop.

[0023] (III) Beneficial effects

[0024] The present invention provides a time-varying gain circuit, comprising: a gain control start circuit and a gain recovery circuit over time. The gain control start circuit and the gain recovery circuit over time are electrically connected. The gain control start circuit includes a capacitor C5, a resistor R4, a monostable flip-flop M, a capacitor C6, a resistor R5, and a power supply VDD. A control signal input line L1 is electrically connected to one end of the capacitor C5. The other end of the capacitor C5 is electrically connected to the input terminal 5 (pin B) of the monostable flip-flop M. One end of the resistor R4 is electrically connected to both the 5th pin B of the monostable flip-flop M and the capacitor C5. The other end of the resistor R4 is electrically connected to the 4th pin A of the monostable flip-flop M and grounded. The 1st pin C of the monostable flip-flop M is grounded and electrically connected to one end of the capacitor C6. The other end of the capacitor C6 is electrically connected to the 2nd pin RC of the monostable flip-flop M. The 2nd pin of the monostable flip-flop M is electrically connected to one end of the resistor R5. The other end of the resistor R5 is electrically connected to the 3rd pin CLR of the monostable flip-flop M and both are connected to the power supply VDD. The gain control start circuit E1 further includes an analog switch N and a resistor R6. The 6th pin Q of the monostable flip-flop M is electrically connected to the analog switch N through the control terminal 1 of the analog switch N. The common terminal 10 of the analog switch N is electrically connected to one end of the resistor R6. The other end of the resistor R6 is connected to the power supply VDD. The capacitor C5 and the resistor R4 form a differentiating circuit. The capacitor C6 and the resistor R5 form an integrating circuit. The gain recovery circuit E2 over time includes a resistor R1, a resistor R2, a resistor R3, and a capacitor C4. The 2nd pin NIA of the analog switch N is electrically connected to one ends of the resistor R2, the resistor R3, and the capacitor C4 respectively. The resistor R3 and the other end of the capacitor C4 are both grounded. The gain recovery circuit E2 over time further includes an amplifying circuit P. A signal input Vi is connected to one end of the resistor R1 through a first capacitor C1. The other end of the resistor R1 is connected to one ends of a second capacitor C2, a diode V1, and a diode V2 respectively. The other end of the second capacitor C2 is electrically connected to the amplifying circuit P. The other end of the diode V2 is grounded. The other end of the diode V1 is electrically connected to one ends of the resistor R2 and a capacitor C3 respectively. The other end of the capacitor C3 is grounded. Therefore, the resistor R4 and the capacitor C5 constitute a differentiating link in the input loop, which can make the pulse width input to the 5th pin of the monostable flip-flop M less than the output pulse width of the monostable flip-flop M. The output pulse width of the monostable flip-flop M is determined by a delay circuit composed of the resistor R5 and the capacitor C6, that is, the time maintained after the monostable flip-flop M flips from the stable state to the quasi-stable state. This time is represented by t, where t = 1.1R6 * C5. That is to say, the output pulse width of the monostable flip-flop M is determined by the delay circuit composed of the resistor R5 and the capacitor C6.During the quasi - stable state of the monostable flip - flop M, the high level is output from the output terminal pin 6 to the control terminal pin 1 of the analog switch N, causing the common terminal pin 10 of the analog switch N to conduct with the normally open terminal pin 2. The power supply VDD charges the capacitor C4 through the resistor R6 and charges the capacitor C3 through the series connection of resistors R2 and R6. As the voltage of C3 increases, the impedance of the diode V1 gradually changes from high to low. The voltage of Vi' will rapidly decrease due to the voltage division of the diode V1 and R1. When the charging voltage VDD is constant, the minimum voltage value that Vi' can reach can be adjusted by the quasi - stable state time t of the monostable flip - flop M or the resistance value of R6 to control the interference of reverberation and target noise during active reception. When the integration delay time formed by R6C5 in the circuit reaches, the monostable flip - flop M will return from the quasi - stable state to its original stable state, and the low level is output from the output terminal pin 6. The analog switch N is disconnected, and the voltages of capacitors C3 and C4 discharge through resistors R2 and R3. The impedance of the diode V1 gradually changes from low to high, and the value of Vi' gradually increases. To achieve the relationship between time and attenuation in the time - variable gain circuit, it can be adjusted by resistors R2 and R3. The relationship between time and attenuation is due to the relationships between the reverberation sound pressure value PR and the target echo signal sound pressure value PT returned from different distances after active transmission and the distance R, which are approximately: PR∝1 / R, PT∝1 / R2. If converted to the time starting from transmission, then there is PR∝1 / t, PT∝1 / t2. Therefore, the time - variable gain control gain change should be between G(t0)t / t0~G(t0)t2 / t02. When t≥t0, G(t) = G(t0). In the circuit, V2 acts as a clamping function to prevent damage to the subsequent circuit caused by excessive signals. Since the circuit realizes the attenuation of the signal and then completes the gain change of the circuit by the different impedance caused by the different voltage across the diode V1 changing with time, the gain change is continuous and has a relatively wide frequency band. The power consumption of the devices required for the time - variable gain control circuit is in the micro - ampere level, and the power consumption of the entire circuit is small, within dozens of micro - amperes. Since the used devices such as resistors, capacitors, and diodes are low - noise devices, the noise of the entire time - variable gain circuit is extremely low, which is extremely beneficial for detecting small signals. Therefore, the circuit structure of the present invention is simple, not limited by the signal frequency, has low noise and power consumption, the relative gain can be adjusted conveniently and continuously with time, and provides a method for a system with a long active detection distance, small echo signals, and long service time, having excellent research value. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 This is a schematic diagram of the circuit structure of the time-varying gain circuit in the embodiment of the present invention.

[0027] In Figure 1 : E1, gain control start circuit; E2, gain recovery circuit over time; capacitor C5, resistor R4, monostable flip-flop M, capacitor C6, resistor R5, power supply VDD, resistor R1, resistor R2, resistor R3, capacitor C4, amplifier circuit P, second capacitor C2, diode V1, diode V2, capacitor C5, resistor R4, monostable flip-flop M, capacitor C6. Specific embodiments

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will further describe in detail the embodiments of the present invention with reference to the accompanying drawings.

[0029] In addition, in the description of the present invention, the orientation or positional relationships indicated by the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for facilitating the description of the present invention rather than requiring the present invention to be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. The terms "connected" and "coupled" used in the present invention should be understood in a broad sense. For example, it may be a fixed connection or a detachable connection; it may be directly connected or indirectly connected through an intermediate component. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0030] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of the time-varying gain circuit in the embodiment of the present invention.

[0031] The present invention provides a time-varying gain circuit, as shown in Figure 1 : including:

[0032] A gain control start circuit E1 and a gain recovery circuit E2 over time, and the gain control start circuit E1 and the gain recovery circuit E2 are electrically connected;

[0033] Regarding the structure of the gain control start circuit E1:

[0034] The gain control startup circuit includes capacitor C5, resistor R4, monostable flip-flop M, capacitor C6, resistor R5, and power supply VDD. The control signal input line L1 is electrically connected to one end of capacitor C5. The other end of capacitor C5 is electrically connected to the input terminal 5 (pin B) of monostable flip-flop M. One end of resistor R4 is electrically connected to both the 5 (pin B) of monostable flip-flop M and capacitor C5, and the other end of resistor R4 is connected to the 4 (pin A) of monostable flip-flop M and grounded.

[0035] The 1 (pin C) of monostable flip-flop M is grounded and electrically connected to one end of capacitor C6. The other end of capacitor C6 is electrically connected to the 2 (pin RC) of monostable flip-flop M. The 2 (pin) of monostable flip-flop M is electrically connected to one end of resistor R5. The other end of resistor R5 is electrically connected to the 3 (pin CLR) of monostable flip-flop M and both are connected to power supply VDD. The gain control startup circuit E1 further includes analog switch N and resistor R6. The 6 (pin Q) of monostable flip-flop M is electrically connected to analog switch N through the control terminal 1 (pin) of analog switch N. The common terminal 10 (pin) of analog switch N is electrically connected to one end of resistor R6, and the other end of resistor R6 is connected to power supply VDD. Capacitor C5 and resistor R4 form a differentiating circuit, and capacitor C6 and resistor R5 form an integrating circuit.

[0036] Regarding the structure of the gain recovery circuit E2 over time:

[0037] The gain recovery circuit E2 over time includes resistor R1, resistor R2, resistor R3, and capacitor C4. The 2 (pin NIA) of analog switch N is electrically connected to one ends of resistor R2, resistor R3, and capacitor C4 respectively. The other ends of resistor R3 and capacitor C4 are both grounded. The gain recovery circuit E2 over time further includes amplifier circuit P. The signal input Vi is connected to one end of resistor R1 through the first capacitor C1. The other end of resistor R1 is connected to one ends of the second capacitor C2, diode V1, and diode V2 respectively. The other end of the second capacitor C2 is electrically connected to amplifier circuit P. The other end of diode V2 is grounded. The other end of diode V1 is electrically connected to one ends of resistor R2 and capacitor C3 respectively. The other end of capacitor C3 is grounded.

[0038] Based on the above structure, therefore, capacitor C6 and resistor R5 form an integrating circuit. Resistor R4 and capacitor C5 constitute the differentiating link of the input loop. The differentiating link of the input loop formed by resistor R4 and capacitor C5 can make the pulse width input to the 5 (pin) of monostable flip-flop M less than the output pulse width of monostable flip-flop M. The output pulse width of monostable flip-flop M is determined by the delay circuit composed of resistor R5 and capacitor C6, that is, the time maintained after monostable flip-flop M flips from the stable state to the quasi-stable state. This time is represented by t, where t = 1.1R6 * C5. That is to say, the output pulse width of monostable flip-flop M is determined by the delay circuit composed of resistor R5 and capacitor C6.

[0039] As shown Figure 1 in the figure, during the quasi-stable state of the monostable flip-flop M, the output terminal pin 6 outputs a high level to the control terminal pin 1 of the analog switch N, causing the common terminal pin 10 of the analog switch N to conduct with the normally open terminal pin 2. The power supply VDD charges the capacitor C4 through the resistor R6 and charges the capacitor C3 through the series connection of the resistors R2 and R6. As the voltage of C3 increases, the impedance of the diode V1 gradually decreases from high. The voltage of Vi' will rapidly decrease due to the voltage division of the diode V1 and R1. When the charging voltage VDD is constant, the minimum voltage value that Vi' can reach can be adjusted by the quasi-stable state time t of the monostable flip-flop M or the resistance value of R6 to control the interference of reverberation and target noise during active reception. When the integration delay time formed by R6C5 in the circuit reaches, the monostable flip-flop M will return from the quasi-stable state to its original stable state, and the output terminal pin 6 outputs a low level. The analog switch N disconnects, and the voltages of the capacitors C3 and C4 discharge through the resistors R2 and R3. The impedance of the diode V1 gradually increases from low, and the value of Vi' gradually increases. To achieve the relationship between time and attenuation in the time-varying gain circuit, it can be adjusted through the resistors R2 and R3. The relationship between time and attenuation is due to the fact that the relationship between the reverberation sound pressure value PR and the target echo signal sound pressure value PT returning from different distances after active transmission and the distance R is approximately: PR∝1 / R, PT∝1 / R2. If converted to the time starting from transmission, then there is PR∝1 / t, PT∝1 / t2. Therefore, the time-varying gain control gain change should be between G(t0)t / t0 and G(t0)t2 / t02. When t≥t0, G(t) = G(t0). In the circuit, V2 acts as a clamping function to avoid damage to the subsequent circuit caused by excessive signals. Since the circuit realizes the attenuation of the signal and then completes the gain change of the circuit by the different impedance caused by the voltage change at the diode V1 end over time, the gain change is continuous and the frequency band range is relatively wide. The power consumption of the devices required to complete the time-varying gain control circuit is in the microampere level, and the power consumption of the entire circuit is small, within dozens of microamperes. Since the used devices such as resistors, capacitors, and diodes are low-noise devices, the noise of the entire time-varying gain circuit is extremely low. These are extremely beneficial for detecting small signals. Therefore, the circuit structure of the present invention is simple, not limited by the signal frequency, has low noise and power consumption, is convenient and continuous to adjust the relative gain with time, and provides a method for a system with a long active detection distance, small echo signals, and long usage time, and has excellent research value.

[0040] In a specific embodiment of the present invention, the first capacitor C1 includes a plurality of first capacitor groups, namely C11, C12, C13, C14...C1n, where n≥1 and n is a positive integer. With such a setting, the capacitance value can be better adjusted for targeted adjustment to make it always controllable.

[0041] For the convenience of capacitance value adjustment, in a specific embodiment of the present invention, each first capacitor group is connected in parallel with each other, and one end of each first capacitor group is electrically connected to the signal input Vi terminal, and the other end of each first capacitor group is electrically connected to the resistor R1. That is, the signal input Vi terminal is connected to one end of the resistor R1 through each first capacitor C1 arranged in parallel with each other, which is convenient for adjusting the capacitance value.

[0042] In a specific embodiment of the present invention, for more convenient control and adjustment of the capacitance value, each first capacitor group includes a control switch and a fixed capacitor with a fixed capacitance value, and the control switch and the corresponding fixed capacitor are connected in series. That is, the value of the first capacitor C1 can be adjusted by closing the control switch.

[0043] In a specific embodiment of the present invention, the second capacitor C2 includes a plurality of second capacitor groups, namely C21, C22, C23, C24... C2n, where n≥1 and n is a positive integer. With such a setting, the capacitance value can be adjusted better, so as to be adjusted targeted and keep it controllable all the time.

[0044] For the convenience of capacitance value adjustment, in a specific embodiment of the present invention, each second capacitor group is connected in parallel with each other, and one end of each second capacitor group is electrically connected to the Vi' terminal, and the other end of each second capacitor group is electrically connected to the resistor R1. That is, the Vi' terminal is connected to one end of the resistor R1 through each first capacitor C1 arranged in parallel with each other, which is convenient for adjusting the capacitance value.

[0045] In a specific embodiment of the present invention, for more convenient control and adjustment of the capacitance value, each second capacitor group includes a control switch and a fixed capacitor with a fixed capacitance value, and the control switch and the corresponding fixed capacitor are connected in series. That is, the value of the first capacitor C1 can be adjusted by closing the control switch.

[0046] In a specific embodiment of the present invention, the resistors R2 and R3 in the time-varying gain circuit are adjustable resistors. Therefore, as Figure 1As shown, the common terminal 10 of the analog switch N is conducted with the normally open terminal 2. The power supply VDD charges the capacitor C4 through the resistor R6, and charges the capacitor C3 after the resistors R2 and R6 are connected in series. As the voltage of C3 increases, the impedance of the diode V1 gradually decreases from high to low. The voltage of Vi' will rapidly decrease due to the voltage division of the diode V1 and R1. When the charging voltage VDD is constant, the minimum voltage value that Vi' can reach can be adjusted by the monostable time t of the monostable flip-flop M or the resistance value of R6, so as to control the interference of reverberation and target noise during active reception. When the integral delay time formed by R6C5 in the circuit reaches, the monostable flip-flop M will return from the monostable state to the original stable state, and the output terminal 6 outputs a low level, the analog switch N is disconnected, and the voltages of the capacitors C3 and C4 are discharged through the resistors R2 and R3. The impedance of the diode V1 gradually increases from low to high, and the value of Vi' gradually increases. To achieve the relationship between time and attenuation in the time-varying gain circuit can be adjusted by the resistors R2 and R3.

[0047] In a specific embodiment of the present invention, the resistors R5 and R6 are adjustable resistors. As Figure 1 shown, the output pulse width of the monostable flip-flop M is determined by the delay circuit composed of the resistor R5 and the capacitor C6, that is, the time maintained after the monostable flip-flop M flips from the stable state to the monostable state, and this time is represented by t, where t = 1.1R6*C5. That is to say, the output pulse width of the monostable flip-flop M is determined by the delay circuit composed of the resistor R5 and the capacitor C6. Therefore, the value of t is closely related to the value of R6. During the monostable state of the monostable flip-flop M, the output terminal 6 outputs a high level to the control terminal 1 of the analog switch N, so that the common terminal 10 of the analog switch N is conducted with the normally open terminal 2. The power supply VDD charges the capacitor C4 through the resistor R6, and charges the capacitor C3 after the resistors R2 and R6 are connected in series. As the voltage of C3 increases, the impedance of the diode V1 gradually decreases from high to low. The voltage of Vi' will rapidly decrease due to the voltage division of the diode V1 and R1. When the charging voltage VDD is constant, the minimum voltage value that Vi' can reach can be adjusted by the monostable time t of the monostable flip-flop M or the resistance value of R6. By changing the monostable time t or the resistance value of R6, the interference of reverberation and target noise during active reception can be better controlled.

[0048] In a specific embodiment of the present invention, the monostable flip-flop M is a retriggerable monostable flip-flop. The time-varying gain circuit provided by the present invention includes: a gain control start circuit and a gain recovery circuit over time, and the gain control start circuit and the gain recovery circuit over time are electrically connected; the gain control start circuit includes a capacitor C5, a resistor R4, a monostable flip-flop M, a capacitor C6, a resistor R5, and a power supply VDD. The control signal input line L1 is electrically connected to one end of the capacitor C5, and the other end of the capacitor C5 is electrically connected to the input terminal 5 (pin B) of the monostable flip-flop M. One end of the resistor R4 is electrically connected to both the 5 (pin B) of the monostable flip-flop M and the capacitor C5, and the other end of the resistor R4 is electrically connected to the 4 (pin A) of the monostable flip-flop M and grounded; the 1 (pin C) of the monostable flip-flop M is grounded and electrically connected to one end of the capacitor C6, the other end of the capacitor C6 is electrically connected to the 2 (pin RC) of the monostable flip-flop M, the 2 (pin) of the monostable flip-flop M is electrically connected to one end of the resistor R5, and the other end of the resistor R5 is electrically connected to the 3 (pin CLR) of the monostable flip-flop M and both are connected to the power supply VDD; the gain control start circuit E1 further includes an analog switch N and a resistor R6. The 6 (pin Q) of the monostable flip-flop M is electrically connected to the analog switch N through the control terminal 1 (pin) of the analog switch N. The common terminal 10 (pin) of the analog switch N is electrically connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply VDD; the capacitor C5 and the resistor R4 form a differentiating circuit, and the capacitor C6 and the resistor R5 form an integrating circuit; the gain recovery circuit over time E2 includes a resistor R1, a resistor R2, a resistor R3, and a capacitor C4. The 2 (pin NIA) of the analog switch N is electrically connected to one ends of the resistor R2, the resistor R3, and the capacitor C4 respectively. The resistor R3 and the other end of the capacitor C4 are both grounded. The gain recovery circuit over time E2 further includes an amplifier circuit P. The signal input Vi is connected to one end of the resistor R1 through a first capacitor C1. The other end of the resistor R1 is connected to one ends of a second capacitor C2, a diode V1, and a diode V2 respectively. The other end of the second capacitor C2 is electrically connected to the amplifier circuit P. The other end of the diode V2 is grounded. The other end of the diode V1 is electrically connected to one ends of the resistor R2 and a capacitor C3 respectively. The other end of the capacitor C3 is grounded. Therefore, the resistor R4 and the capacitor C5 constitute a differentiating link in the input loop, which can make the pulse width input to the 5 (pin) of the monostable flip-flop M less than the output pulse width of the monostable flip-flop M. The output pulse width of the monostable flip-flop M is determined by the delay circuit composed of the resistor R5 and the capacitor C6, that is, the time that the monostable flip-flop M maintains after flipping from the stable state to the quasi-stable state, and this time is represented by t, where t = 1.1R6*C5. That is to say, the output pulse width of the monostable flip-flop M is determined by the delay circuit composed of the resistor R5 and the capacitor C6.During the quasi-stable state of the monostable flip-flop M, the output terminal pin 6 outputs a high level to the control terminal pin 1 of the analog switch N, causing the common terminal pin 10 of the analog switch N to conduct with the normally open terminal pin 2. The power supply VDD charges the capacitor C4 through the resistor R6 and charges the capacitor C3 through the series connection of resistors R2 and R6. As the voltage of C3 increases, the impedance of the diode V1 gradually decreases from high. The voltage of Vi' will rapidly decrease due to the voltage division of the diode V1 and R1. When the charging voltage VDD is constant, the minimum voltage value that Vi' can reach can be adjusted by the quasi-stable state time t of the monostable flip-flop M or the resistance value of R6 to control the interference of reverberation and target noise during active reception. When the integration delay time formed by R6C5 in the circuit reaches, the monostable flip-flop M will return from the quasi-stable state to its original stable state, and the output terminal pin 6 outputs a low level. The analog switch N disconnects, and the voltages of the capacitors C3 and C4 discharge through the resistors R2 and R3. The impedance of the diode V1 gradually increases from low, and the value of Vi' gradually increases. To achieve the relationship between time and attenuation in the time-varying gain circuit, it can be adjusted by the resistors R2 and R3. The relationship between time and attenuation is due to the relationship between the reverberation sound pressure value PR and the target echo signal sound pressure value PT returned from different distances after active transmission and the distance R, which are approximately: PR∝1 / R, PT∝1 / R2. If converted to the time counted from the transmission, then there is PR∝1 / t, PT∝1 / t2. Therefore, the time-varying gain control gain change should be between G(t0)t / t0~G(t0)t2 / t02. When t≥t0, G(t)=G(t0). In the circuit, V2 acts as a clamping function to avoid damage to the subsequent circuit due to excessive signals. Since the circuit realizes the attenuation of the signal and then completes the gain change of the circuit by the different impedance caused by the different voltage changes over time applied to the diode V1 terminal, the gain change is continuous and has a relatively wide frequency band. The power consumption of the devices required for the time-varying gain control circuit is in the microampere level, and the power consumption of the entire circuit is small, within dozens of microamperes. Since the used devices such as resistors, capacitors, and diodes are low-noise devices, the noise of the entire time-varying gain circuit is extremely low. These are extremely beneficial for detecting small signals. Therefore, the circuit structure of the present invention is simple, not limited by the signal frequency, has low noise and power consumption, is convenient and continuous to adjust the relative gain with respect to time change, and provides a method for a system with a long active detection distance, small echo signals, and long usage time, and has excellent research value.

[0049] As is known by technical common sense, the present invention can be implemented by other embodiments without departing from its spiritual essence or essential features. Therefore, the above-disclosed embodiments are illustrative in all aspects and not exclusive. All changes within the scope of the present invention or within the scope equivalent to the present invention are encompassed by the present invention.

Claims

1. A time-varying gain circuit, characterized in that, Comprising: A gain control start circuit (E1) and a gain recovery circuit over time (E2), the gain control start circuit (E1) and the gain recovery circuit over time (E2) being electrically connected by an electrical signal; The gain control start circuit (E1) includes a capacitor (C5), a resistor (R4), a monostable flip-flop (M), a capacitor (C6), a resistor (R5), a power supply (VDD). A control signal input line (L1) is electrically connected to one end of the capacitor (C5). The other end of the capacitor (C5) is electrically connected to the input terminal 5 pin B of the monostable flip-flop (M). One end of the resistor (R4) is electrically connected to both the 5 pin B of the monostable flip-flop (M) and the capacitor (C5). The other end of the resistor (R4) is connected to the 4 pin A of the monostable flip-flop (M) and grounded; The 1 pin C of the monostable flip-flop (M) is grounded and electrically connected to one end of the capacitor (C6). The other end of the capacitor (C6) is electrically connected to the 2 pin RC of the monostable flip-flop (M). The 2 pin of the monostable flip-flop (M) is electrically connected to one end of the resistor (R5). The other end of the resistor (R5) is electrically connected to the 3 pin CLR of the monostable flip-flop (M) and both are connected to the power supply (VDD); The gain control start circuit (E1) further includes an analog switch (N), a resistor (R6). The 6 pin Q of the monostable flip-flop (M) is electrically connected to the analog switch (N) through the control terminal 1 pin of the analog switch (N). The common terminal 10 pin of the analog switch (N) is electrically connected to one end of the resistor (R6). The other end of the resistor (R6) is connected to the power supply (VDD); The capacitor (C5) and the resistor (R4) form a differentiating circuit, and the capacitor (C6) and the resistor (R5) form an integrating circuit; The gain recovery circuit over time (E2) includes a resistor (R1), a resistor (R2), a resistor (R3), and a capacitor (C4). The 2 pin NIA of the analog switch (N) is electrically connected to one end of the resistor (R2), the resistor (R3), and the capacitor (C4) respectively. The other ends of the resistor (R3) and the capacitor (C4) are both grounded. The gain recovery circuit over time (E2) further includes an amplifier circuit (P). A signal input (Vi) is connected to one end of the resistor (R1) through a first capacitor (C1). The other end of the resistor (R1) is connected to one end of a second capacitor (C2), a diode V1, and a diode V2 respectively. The other end of the second capacitor (C2) is electrically connected to the amplifier circuit (P). The other end of the diode V2 is grounded. The other end of the diode V1 is electrically connected to one end of the resistor (R2) and a capacitor (C3) respectively. The other end of the capacitor (C3) is grounded.

2. The time-varying gain circuit according to claim 1, wherein The first capacitor (C1) includes a plurality of first capacitor groups, namely C11, C12, C13, C14... C1n, where n≥1 and n is a positive integer.

3. The time-varying gain circuit according to claim 2, wherein Each of the first capacitor groups is connected in parallel with each other, and one end of each of the first capacitor groups is electrically connected to the signal input (Vi) terminal, and the other end of each of the first capacitor groups is electrically connected to the resistor (R1).

4. The time-varying gain circuit according to claim 3, wherein Each of the first capacitor groups includes a control switch and a fixed capacitor having a fixed capacitance value, and the control switch and the corresponding fixed capacitor are connected in series.

5. The time-varying gain circuit according to claim 1, characterized in that The second capacitor (C2) includes a plurality of second capacitor groups, namely C21, C22, C23, C24... C2n, where n≥1 and n is a positive integer.

6. The time-varying gain circuit according to claim 5, characterized in that Each of the second capacitor groups is connected in parallel with each other, and one end of each of the second capacitor groups is electrically connected to the signal input (Vi) terminal, and the other end of each of the second capacitor groups is electrically connected to the resistor (R1).

7. The time-varying gain circuit according to claim 6, wherein Each of the second capacitor groups includes a control switch and a fixed capacitor having a fixed capacitance value, and the control switch and the corresponding fixed capacitor are connected in series.

8. The time-varying gain circuit according to claim 1, wherein The resistors (R2) and (R3) in the time-varying gain circuit are adjustable resistors.

9. The time-varying gain circuit according to claim 1, wherein The resistors (R5) and (R6) are adjustable resistors.

10. The time-varying gain circuit according to any one of claims 1-9, characterized in that, The monostable flip-flop M is a retriggerable monostable flip-flop.

Images