Dual-channel numerical delay chip

Abstract

The application provides a double-channel digital delay chip, which comprises a delay control circuit, a double delay channel and a digital control circuit; a coarse delay control module of the delay control circuit is connected with a reference clock, a clock output end of the coarse delay control module outputs a clock signal, and a signal output end of the coarse delay control module outputs a first control voltage; a fine delay control module of the delay control circuit outputs a second control voltage based on the clock signal; the digital control circuit generates a mode control instruction and a delay control instruction; the double delay channel is electrically connected with the delay control circuit and the digital control circuit; the double delay channel comprises two delay channels and supports a double delay mode and an extended delay mode; the double delay channel makes the double-channel digital delay control chip work in the double delay mode or the extended delay mode based on the mode control instruction; and the double delay channel executes the delay control instruction based on the first control voltage and the second control voltage, so that a differential signal is output as a high-speed signal after the delay of the double delay channel. The application can accurately control the delay size.

Description

Technical Field

[0001] This invention relates to the field of delay control technology, and in particular to a dual-channel numerical control delay control chip. Background Technology

[0002] High-precision delay control is in high demand in fields such as phased array antennas, quantum key distribution, and high-precision measurement. 5G and even 6G wireless communication base station antennas commonly employ phased array beamforming technology to improve signal spectral efficiency. Phased array antennas obtain the main lobe direction of the beam by adjusting the phase shift between different array elements, i.e., the signal delay. Digital delay control becomes an indispensable circuit. In the light source of a quantum key distribution system, multiple lasers generate multiple optical signals. These optical signals must have no delay difference before reaching the laser beam combiner to achieve so-called security. This necessitates applying necessary delays to the signals in different optical paths to eliminate the delay difference caused by differences in their physical paths.

[0003] Currently, there are two main control methods for signal delay control: analog and digital. The analog method uses delay networks such as microstrip lines and fiber optic lines to achieve signal transmission delay. The digital method uses a dedicated delay chip, and according to the required delay amount, the chip is configured with corresponding digital control quantities so that the signal can obtain the corresponding delay when passing through the delay chip.

[0004] While analog delays are simple to implement, they have several drawbacks: First, the delay consistency is poor, making it impossible to ensure that each delay line has the same delay amount, and each delay network itself exhibits delay variations due to changes in PCB ambient temperature, humidity, and pressure. Second, high-precision (less than 100 picoseconds) delay control and delay amount control are not possible. These drawbacks of analog delay methods can be effectively addressed in digitally controlled delay chips. When designing delay chips, the first thought is to use delay cells from CMOS process libraries to construct the delay network. The most basic delay cell is a CMOS inverter, whose intrinsic delay is no less than 15 picoseconds. Obviously, directly using basic semiconductor process cells to build the delay chain cannot achieve the expected 10 picosecond accuracy. Moreover, even with chip technology, the problems inherent in analog delay networks also exist within the chip due to process inconsistencies, voltage fluctuations, and temperature variations (PVT).

[0005] Therefore, a dedicated circuit design is urgently needed to achieve the expected accuracy. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a dual-channel numerically controlled delay chip to solve the problem of inaccurate delay control in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a dual-channel digitally controlled delay chip, comprising a delay control circuit, dual delay channels, and a digital control circuit;

[0008] The delay control circuit includes a coarse delay control module and a fine delay control module; the signal input terminal of the coarse delay control module is connected to a reference clock, and the clock output terminal of the coarse delay control module outputs a clock signal; the signal output terminal of the coarse delay control module outputs a first control voltage; the signal input terminal of the fine delay control module is connected to the clock output terminal of the coarse delay control module, and the fine delay control module outputs a second control voltage based on the clock signal;

[0009] The digital control circuit generates mode control commands and delay control commands;

[0010] The dual delay channel is electrically connected to the delay control circuit and the digital control circuit; the dual delay channel includes two delay channels and supports dual delay mode and extended delay mode;

[0011] The dual-delay channel enables the dual-channel digital delay control chip to operate in dual-delay mode or extended delay mode based on the mode control command.

[0012] The dual-delay channel executes the delay control command based on the first control voltage and the second control voltage, so that the differential signal is output as a high-speed signal after being delayed by the dual-delay channel.

[0013] Preferably, the two delay channels of the dual delay channel are a first delay channel and a second delay channel;

[0014] When the dual-channel digital delay control chip is working in dual-delay mode, the first delay channel and the second delay channel work independently;

[0015] When the dual-channel digital delay control chip is operating in extended delay mode, the first delay channel and the second delay channel work in cascade.

[0016] Preferably, the coarse delay control module includes a frequency and phase detector, a first delay module, a first delay link module, a first charge pump, and a first control module;

[0017] The signal input terminal of the first delay module is connected to a reference clock, and the control terminal of the first delay module is connected to the output terminal of the first charge pump. Under the action of the first control voltage output by the first charge pump, the first delay module outputs a first delay signal from its first output terminal and a second delay signal from its second output terminal.

[0018] The signal input terminal of the first delay link module is connected to the first output terminal of the first delay module, and the control terminal of the first delay link module is connected to the output terminal of the first charge pump; under the action of the first control voltage output by the first charge pump, the first delay link module further delays the first delay signal to obtain a delay feedback signal.

[0019] The first control module receives a power supply voltage signal and an enable signal as inputs, and its output is connected to the enable terminal of the frequency and phase detector. The first control module generates a first enable control signal to control the frequency and phase detector based on the power supply voltage signal and the enable signal.

[0020] The first input terminal of the frequency and phase detector is connected to the first output terminal of the first delay module, and the second input terminal of the frequency and phase detector is connected to the output terminal of the first delay link module; based on the control effect of the first enable control signal, the frequency and phase detector outputs a first phase difference signal according to the second delay signal and the delay feedback signal;

[0021] The input terminal of the first charge pump is connected to the output terminal of the frequency and phase detector; it is used to obtain the first control voltage based on the first phase difference signal.

[0022] Preferably, the first delay link module includes N coarse delay units, which are cascaded together, and the control terminal of each coarse delay unit is connected to the output terminal of the charge pump; wherein, N≥3;

[0023] The coarse delay unit includes two identical delay sub-units, which are cascaded; the delay sub-unit includes a half-current-starved inverter and a buffer circuit.

[0024] The half-current-starved inverter includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are the input terminals of the delay unit. The source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor and the drain of the third NMOS transistor are connected. The gate of the third NMOS transistor is the control terminal of the delay unit, and the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the power supply voltage, and the drains of the second NMOS transistor and the drain of the third NMOS transistor are grounded. The half-current-starved inverter is used to output a discharge current according to the control voltage.

[0025] The buffer circuit includes a Schmitt inverter and a third inverter; the input terminal of the Schmitt inverter is connected to the junction formed by the drain of the first PMOS transistor and the drain of the third NMOS transistor; the output terminal of the Schmitt inverter is connected to the input terminal of the third inverter; the buffer circuit buffers the discharge current before outputting it.

[0026] Preferably, the system further includes a second delay module. The first input terminal of the second delay module is connected to the second output terminal of the first delay module for receiving the first delay signal. The second input terminal of the second delay module is connected to the output terminal of the delay link module for receiving the delay feedback signal. The control terminal of the second delay module is connected to the output terminal of the first charge pump. Under the action of the first control voltage output by the first charge pump, the second delay module further delays the second delay signal and further delays the delay feedback signal.

[0027] Preferably, the fine delay control module includes a second delay link module, a frequency and phase detector, a second charge pump, and a second control module;

[0028] The second delay link module includes a first delay branch and a second delay branch; the input terminal of the first delay branch is connected to the clock output terminal of the coarse delay control module, and is used to receive the rising edge signal of the clock signal. Under the action of the second control voltage output by the second charge pump, the first delay branch performs delay control on the rising edge signal and outputs a first delay signal; the input terminal of the second delay branch is connected to the clock output terminal of the coarse delay control module, and is used to receive the falling edge signal of the clock signal. Under the action of the second control voltage output by the second charge pump, the second delay branch performs delay control on the falling edge signal and outputs a second delay signal.

[0029] The input of the second control module is connected to the power supply voltage signal and the enable signal, and the output of the second control module is connected to the enable terminal of the frequency and phase detector; the second control module generates a second enable control signal to control the frequency and phase detector according to the power supply voltage signal and the enable signal.

[0030] The first input terminal of the frequency and phase detector is connected to the output terminal of the first delay branch, and the second input terminal of the frequency and phase detector is connected to the output terminal of the second delay branch; based on the control effect of the second enable control signal, the frequency and phase detector outputs a second phase difference signal according to the second delay signal and the delay feedback signal;

[0031] The input terminal of the second charge pump is connected to the output terminal of the frequency and phase detector; the second charge pump obtains the second control voltage based on the second phase difference signal.

[0032] Preferably, the first control module and the second control module have the same structure, including a first switch, a second switch, a first AND gate, a first inverter, a second inverter, and a NOR gate;

[0033] The input terminal of the first switch is connected to the output terminal of the first inverter, the output terminal of the first switch is connected to the input terminal of the first inverter and the first input terminal of the first AND gate, the first source terminal of the first switch is connected to the power supply voltage, and the second source terminal of the first switch is connected to the output terminal of the charge pump.

[0034] The input terminal of the second switch is connected to the output terminal of the second inverter, the output terminal of the second switch is connected to the input terminal of the second inverter, the first source terminal of the first switch is connected to the chip pin voltage, and the second source terminal of the first switch is connected to the output terminal of the charge pump.

[0035] The first input terminal of the NOR gate is connected to the output terminal of the first inverter, the second input terminal of the NOR gate is connected to the second input terminal of the first AND gate, and the output terminal of the NOR gate is connected to the input terminal of the second inverter; the output terminal of the first AND gate is connected to the enable terminal of the frequency and phase detector.

[0036] Preferably, the frequency and phase detector includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, and an enable control unit;

[0037] The clock terminal of the first flip-flop is the first input terminal of the frequency and phase detector; the input terminal of the first flip-flop is connected to the power supply voltage, and the output terminal of the first flip-flop is connected to the input terminal of the second flip-flop; the clock terminal of the second flip-flop is connected to the clock terminal of the first flip-flop; the clock terminal of the third flip-flop is the second input terminal of the frequency and phase detector; the input terminal of the third flip-flop is connected to the power supply voltage, and the output terminal of the third flip-flop is connected to the input terminal of the fourth flip-flop; the clock terminal of the fourth flip-flop is connected to the clock terminal of the third flip-flop; the reset terminal of the third flip-flop is grounded.

[0038] The output of the enable control unit is connected to the reset terminals of the first trigger, the second trigger, and the fourth trigger; the input terminal of the enable control unit is connected to the output terminal of the control module.

[0039] The frequency and phase detector outputs a phase difference signal through the output terminals of the second trigger and the fourth trigger according to the enable control signal.

[0040] Preferably, the enable control unit includes a fourth inverter, a second AND gate, and an OR gate;

[0041] The input terminal of the fourth inverter is connected to the output terminal of the control module. The output terminal of the fourth inverter is connected to the reset terminal of the first inverter and the first input terminal of the OR gate. The first input terminal of the second AND gate is connected to the output terminal of the second inverter. The second input terminal of the second AND gate is connected to the output terminal of the fourth inverter. The output terminal of the second AND gate is connected to the second input terminal of the OR gate. The output terminal of the OR gate is connected to the reset terminal of the second inverter and the reset terminal of the fourth inverter.

[0042] Preferably, the first charge pump and the second charge pump have the same structure, including a bias circuit and a main circuit;

[0043] The input of the bias circuit is connected to a constant current source, and the output is connected to the main circuit; the bias circuit provides a bias voltage to the main circuit based on the constant current source.

[0044] The main circuit outputs a first control voltage based on the bias voltage, according to the first phase difference signal, and outputs a second control voltage based on the second phase difference signal.

[0045] Preferably, the main circuit includes a switching unit, an operational amplifier, a first current mirror, and a second current mirror;

[0046] The first current mirror is connected to the bias circuit, the power supply voltage, and the first node of the switching unit;

[0047] The second current mirror connects the bias current, the second node of the switching unit, and the ground terminal;

[0048] The switching unit includes two switching branches, and the operational amplifier is connected in parallel between the switching branches;

[0049] The non-inverting input terminal of the operational amplifier is the output terminal of the first charge pump.

[0050] Preferably, the delay channel includes a coarse delay link unit, a control unit, and a fine delay link unit.

[0051] The signal input terminal of the coarse delay link unit receives the differential signal, the power supply terminal of the coarse delay unit is connected to the first control voltage, and the coarse delay link unit performs coarse delay on the differential signal based on the first control voltage;

[0052] The input terminal of the control unit is connected to the signal output terminal of the coarse delay unit, and the output terminal of the control unit is connected to the input terminal of the fine delay unit. The control unit outputs the delay range after coarse delay by the coarse delay link unit according to the control command.

[0053] The power supply terminal of the fine delay unit is connected to the second control voltage. Based on the second control voltage, the fine delay unit performs a fine delay within the delay range and then outputs the high-speed signal.

[0054] As described above, the dual-channel numerically controlled delay chip of the present invention has the following beneficial effects:

[0055] The dual-channel digital delay control chip of the present invention adopts a digital control method, enabling the dual-channel digital delay control chip to operate in dual delay mode or extended delay mode. Based on the first control voltage and the second control voltage generated by the delay control circuit for controlling the delay range, the differential signal input to the dual delay channel is precisely delayed and then output as a high-speed signal, thereby achieving precise digital delay control, that is, achieving a programmable delay range of 5ns and a delay accuracy of 10ps for a single channel. Attached Figure Description

[0056] Figure 1 The diagram shown is a schematic block diagram of the dual-channel numerically controlled delay chip of this invention.

[0057] Figure 2 The diagram shown is a schematic block diagram of the delay control circuit of this invention.

[0058] Figure 3 The diagram shown is a schematic diagram of the circuit structure of the coarse delay control module of the present invention.

[0059] Figure 4 The diagram shown is a schematic diagram of the circuit structure of the coarse delay unit of the present invention.

[0060] Figure 5 The diagram shown is a schematic representation of the frequency and phase detector of this invention.

[0061] Figure 6 The diagram shows the circuit structure of the first and third flip-flops of this invention.

[0062] Figure 7 The diagram shows the circuit structure of the second and fourth flip-flops of this invention.

[0063] Figure 8 The diagram shown is a schematic diagram of the circuit structure of the first charge pump of the present invention.

[0064] Figure 9 The diagram shown is a schematic diagram of the fine delay control module of this invention.

[0065] Figure 10 The diagram shown is a schematic diagram of the circuit structure of the fine delay unit of the present invention.

[0066] Figure 11 The diagram shown is a schematic diagram of the phase-locked loop of this invention.

[0067] Figure 12 The diagram shown is a circuit structure diagram of the oscillator of this invention.

[0068] Figure 13 The diagram shows the circuit structure of the frequency and phase detector in the phase-locked loop of this invention.

[0069] Figure 14 The diagram shown is a structural schematic of a dual-channel delay link in an embodiment of the present invention.

[0070] Figure 15 The diagram shown is a block diagram of a single-channel delay link structure in an embodiment of the present invention.

[0071] Figure 16 The diagram shown is a schematic representation of the link structure of the coarse delay link unit in an embodiment of the present invention.

[0072] Figure 17 The diagram shown is a schematic representation of the link structure of a fine-delay link unit in an embodiment of the present invention.

[0073] Component labeling: 1. First delay module; 2. Second delay module; 3. Frequency and phase detector; 4. First delay link module; 5. First control module; 6. Inverter chain; 7. Second delay link module; 8. Second control module. Detailed Implementation

[0074] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] Please see Figures 1-17 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] like Figure 1 The diagram shown is a schematic block diagram of the dual-channel digital delay control chip of the present invention. Figure 2 The diagram shown is a schematic block diagram of the delay control circuit of this invention. The following is a summary of the principles of the circuit. Figure 1 and Figure 2 This invention introduces a dual-channel digital delay control chip, comprising a delay control circuit DLL, dual delay channels (PD0 and PD1), and a digital control circuit;

[0077] The delay control circuit includes a coarse delay control module and a fine delay control module; the signal input terminal of the coarse delay control module is connected to a reference clock, and the clock output terminal of the coarse delay control module outputs a clock signal; the signal output terminal of the coarse delay control module outputs a first control voltage; the signal input terminal of the fine delay control module is connected to the clock output terminal of the coarse delay control module, and the fine delay control module outputs a second control voltage based on the clock signal;

[0078] The digital control circuit generates mode control commands and delay control commands;

[0079] The dual delay channel is electrically connected to the delay control circuit and the digital control circuit; the dual delay channel includes two delay channels and supports dual delay mode and extended delay mode;

[0080] The dual-delay channel enables the dual-channel digital delay control chip to operate in dual-delay mode or extended delay mode based on the mode control command.

[0081] The dual-delay channel executes the delay control command based on the first control voltage and the second control voltage, so that the differential signal is output as a high-speed signal after being delayed by the dual-delay channel.

[0082] The dual-channel digital delay control chip of the present invention adopts a digital control method. The delay control circuit accurately generates a first control voltage and a second control voltage for controlling the delay range. This enables the dual-channel digital delay control chip to operate in a dual-delay mode or an extended delay mode. Based on the first and second control voltages generated by the delay control circuit, the differential signal input to the dual delay channel is precisely delayed and then output as a high-speed signal, thereby achieving precise digital delay control.

[0083] This invention provides bias voltages, namely the first control voltage and the second control voltage, to the first delay channel PD0 and the second delay channel PD1 respectively through a delay control circuit. These bias voltages are automatically adjusted according to changes in PVT, ensuring that the first and second delay channels do not change with PVT during the delay process. The proposed implementation goals of the delay control circuit are: 1) to output a stable voltage within a certain range under various PVT conditions; 2) to provide a low-jitter reference clock; 3) to minimize static phase error; and 4) to minimize control voltage ripple.

[0084] To achieve the second objective, the dual-channel numerically controlled delay chip of this invention also includes a phase-locked loop (PLL). The PLL input is connected to a reference clock, and the PLL output is connected to the input of the delay control circuit. The PLL multiplies the reference clock and outputs a high-frequency clock signal, Fref. This invention uses a PLL to multiply the 25MHz input clock CLK_REF provided by an external crystal oscillator, outputting a 200MHz reference clock, Fref, thereby providing a stable reference clock, Fref, for both the coarse and fine delay control modules in the delay control circuit.

[0085] The phase-locked loop (PLL) in the embodiments of the present invention is as follows: Figure 11 As shown, it consists of a phase and frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a frequency divider (DIV), and an oscillator (VCO).

[0086] To cope with process corners and certain temperature variations, while ensuring a certain level of jitter performance, the oscillator VCO is tuned. The oscillator VCO circuit structure is as follows: Figure 12 As shown. The circuit structure of the frequency and phase detector (PFD) is as follows. Figure 13 As shown, pull-down transistors for enable control are added to QA and QB. Before enabling, QA and QB are pulled down to 0 to determine their initial state, thus avoiding false lockout. The phase difference signal output by the phase-frequency discriminator PFD is converted into a change in the bias voltage of the oscillator VCO by the charge pump CP and the loop filter LPF. The charge pump can be the same as the first charge pump structure described below. Under the action of the loop, a 200MHz clock output is achieved by ensuring that the reference signal and the feedback signal are in phase. At the same time, relatively low jitter performance is achieved by compromising the loop bandwidth, the slope of the voltage-controlled tuning curve, and the charge pump current. In addition, voltage LDO1 provides the operating voltage for the charge pump CP and the phase-frequency discriminator PFD, and voltage LDO2 provides the operating voltage for the bias filter and the oscillator VCO.

[0087] like Figure 3 The diagram shown is a schematic diagram of the circuit structure of the coarse delay control module of the present invention. Figure 3 The coarse delay control module of the present invention is described below; in the embodiments of the present invention, the coarse delay control module includes a frequency and phase detector 3, a first delay module 1, a first delay link module 4, a first charge pump, and a first control module 5;

[0088] The signal input terminal of the first delay module 1 is connected to a reference clock, and the control terminal of the first delay module 1 is connected to the output terminal of the first charge pump. Under the action of the first control voltage VC1 output by the first charge pump, the first delay module 1 outputs a first delay signal from its first output terminal and a second delay signal from its second output terminal.

[0089] The signal input terminal of the first delay link module 4 is connected to the first output terminal of the first delay module 1, and the control terminal of the first delay link module 4 is connected to the output terminal of the first charge pump. Under the action of the first control voltage output by the first charge pump, the first delay link module 4 further delays the first delay signal to obtain a delay feedback signal.

[0090] The first control module 5 is connected to a power supply voltage signal and an enable signal as inputs, and the output terminal of the first control module 5 is connected to the enable terminal of the frequency and phase detector. The first control module generates a first enable control signal to control the frequency and phase detector 3 according to the power supply voltage signal and the enable signal.

[0091] The first input terminal of the frequency and phase detector 3 is connected to the first output terminal of the first delay module 1, and the second input terminal of the frequency and phase detector 3 is connected to the output terminal of the first delay link module 4; based on the control effect of the first enable control signal, the frequency and phase detector 3 outputs a first phase difference signal according to the second delay signal and the delay feedback signal;

[0092] The input terminal of the first charge pump is connected to the output terminal of the frequency and phase detector 3; it is used to obtain the first control voltage based on the first phase difference signal.

[0093] The coarse delay control module of the present invention inputs the reference clock to the first delay link module and the frequency and phase detector respectively under the same environment through the first delay module. The coarse delay control module of the present invention can accurately control the first control voltage to improve the accuracy of delay range control.

[0094] In this invention, the first control module 5 includes a first switch M1, a second switch M2, a first AND gate Y1, a first inverter N1, a second inverter N2, and a NOR gate H1;

[0095] The input terminal of the first switch is connected to the output terminal of the first inverter, the output terminal of the first switch is connected to the input terminal of the first inverter and the first input terminal of the first AND gate, the first source terminal of the first switch is connected to the power supply voltage, and the second source terminal of the first switch is connected to the output terminal of the charge pump.

[0096] The input terminal of the second switch is connected to the output terminal of the second inverter, the output terminal of the second switch is connected to the input terminal of the second inverter, the first source terminal of the first switch is connected to the chip pin voltage, and the second source terminal of the first switch is connected to the output terminal of the charge pump.

[0097] The first input terminal of the NOR gate is connected to the output terminal of the first inverter, the second input terminal of the NOR gate is connected to the second input terminal of the first AND gate, and the output terminal of the NOR gate is connected to the input terminal of the second inverter; the output terminal of the first AND gate is connected to the enable terminal of the frequency and phase detector.

[0098] The first control module of this invention is connected to the power supply voltage via a first switch. It obtains the power supply voltage detection signal PWR_DET_1P2 through the first input terminal of a first AND gate, and an enable signal through the second input terminal of the same gate. Internally, it combines the power supply voltage detection signal PWR_DET_1P2 and the enable signal EN_CDLL to generate an enable control signal to control the frequency and phase detector. Specifically, during power supply power-on, the control voltage VCTL is connected to VDD through a transmission gate (M1) to minimize its delay. When the power supply stabilizes, the detection signal PWR_DET_1P2 jumps high, the first switch M1 opens, and the control voltage VCTL is determined by a coarse delay phase-locked loop. If the phase-locked loop of the coarse delay control module fails to function properly, the coarse delay phase-locked loop DLL is turned off by configuring the digital enable signal EN_CDLL to be low. The second switch M2 is then turned on, allowing the first control voltage VC1 to be directly supplied from the external chip pin voltage START_VC. This invention avoids the situation where the actual on-chip voltage value does not match the external voltage input due to the large voltage drop when transmitting high voltage during the process of using the external start signal to control the frequency and phase detector. Therefore, the enable signal generated by the control module based on the power supply voltage of the internal circuit is more accurate.

[0099] In this invention, the first delay module 1 includes two coarse delay units. The input terminal of each coarse delay unit is connected to the reference clock Fref through a buffer. The input terminal of the buffer is also connected to the reference clock Fref, and the output terminal of the buffer is connected to the input terminal of the coarse delay unit. The control terminal of each coarse delay unit is connected to the output terminal of the first charge pump. The output terminal of each coarse delay unit is connected to the buffer. Under the action of the first control voltage output by the first charge pump, each coarse delay unit delays the reference clock Fref and then outputs a first delay signal and a second delay signal. The output terminal of the buffer is left floating. Setting a buffer at the output terminal can reduce the impact of the load on the delay unit.

[0100] In the first delay module 1 of the present invention, a buffer is provided at the input end of each coarse delay unit to ensure that the input environment is consistent. The buffer matched at the output end of the coarse delay unit is actually built into the coarse delay unit. Under the buffering effect of the buffer, the environment of the output to the first delay link module 4 and the frequency and phase detector 3 can be consistent, thereby ensuring the uniformity of the delay.

[0101] In this invention, the first delay link module 4 is composed of N voltage-controllable coarse delay units cascaded together. The control terminal of each coarse delay unit is connected to the output terminal of the charge pump; wherein, N≥3, and in this embodiment, N=16; each stage of the coarse delay unit achieves a delay of 312.5ps, and the total delay is 5ns. Based on the high 4 bits of the delay control command, after digital decoding, a multiplexer is used to select the corresponding delay output, generating the corresponding delay time. Under the action of the first control voltage output by the first charge pump, the environmental consistency and delay uniformity of each stage of the coarse delay unit can be guaranteed.

[0102] Because the delay chain contains many stages of coarse delay units, inconsistent delays for the rising and falling edges of the input signal in each stage can cause significant changes in the output signal's duty cycle. With very high input signal frequencies (up to 1.5 GHz) and very narrow pulse widths (333 ps), the output signal may disappear after multiple delay stages, becoming either constantly high or constantly low. To avoid this, the design of the coarse delay units must ensure consistent delays for the rising and falling edges of the input signal, maintaining a stable output signal duty cycle.

[0103] Therefore, the coarse delay unit proposed in this invention includes two identical delay sub-units, such as... Figure 4 As shown, two delay sub-units are cascaded, and each delay sub-unit includes a half-current-starved inverter and a buffer circuit.

[0104] The half-current-starved inverter includes a first PMOS transistor (P1_a and P1_b), a first NMOS transistor (N1_a and N1_b), a second NMOS transistor (N2_a and N2_b), and a third NMOS transistor (Nc_a and Nc_b). The gates of the first PMOS transistor and the first NMOS transistor serve as the input terminals of the delay unit. The source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor serves as the control terminal of the delay unit, and the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the power supply voltage, and the drains of the second NMOS transistor and the drain of the third NMOS transistor are grounded. The half-current-starved inverter is used to output a discharge current according to the control voltage.

[0105] The buffer circuit includes Schmitt inverters (SMT_a and SMT_b) and a third inverter (INV_a and INV_b); the input terminal of the Schmitt inverter is connected to the junction formed by the drain of the first PMOS transistor and the drain of the third NMOS transistor; the output terminal of the Schmitt inverter is connected to the input terminal of the third inverter; the buffer circuit buffers the discharge current before outputting it.

[0106] Specifically, the two delay sub-units are half delaycell A for delaying the rising edge and half delaycell B for delaying the falling edge. Taking half delaycell A as an example, this half-current-starved inverter consists of four transistors: a first PMOS transistor P1_a, a first NMOS transistor N1_a, a third NMOS transistor Nc_a, and a second NMOS transistor N2_a. The gates of the first PMOS transistor P1_a and the first NMOS transistor N1_a are connected to the input signal IN. The source of the first NMOS transistor N1_a is connected to ground through the third NMOS transistor Nc_a and the second NMOS transistor N2_a. The gate of the third NMOS transistor Nc_a is the control terminal of the delay unit, which is connected to the control voltage VCTL. The control voltage VCTL signal is generated by the coarse delay phase-locked loop (DLL) and can control the magnitude of the discharge current of this half-current-starved inverter to its output node nd1_a.

[0107] When the input signal IN jumps from low to high, node nd1_a jumps from high to low. Its fall time is controlled by the control voltage VCTL. Changing the voltage of the control voltage VCTL can achieve different delays. Since the control voltage VCTL signal is generated by DLL, its voltage varies greatly under different process, voltage, and temperature (PVT) conditions to ensure that the total delay of the delay unit remains constant.

[0108] When the control voltage VCTL is lower than the threshold voltage of the third NMOS transistor Nc_a, the discharge current is very small, and the low-level voltage of node nd1_a is relatively high, which may cause the next stage circuit to fail to flip properly. To avoid this situation, a second NMOS transistor N2_a is added, which is much smaller than the third NMOS transistor Nc_a. The gate of the second NMOS transistor N2_a is connected to VDD, and the second NMOS transistor N2_a is always on, providing the basic discharge current for the half-current-starved inverter, so that the delay sub-unit still has a signal output when the control voltage VCTL is lower than the threshold voltage controlling the third NMOS transistor Nc_a. Then, after the buffer output of the Schmitt trigger inverter SMT_a and the third inverter INV_a, the intermediate signal OUT_a is output first. In addition to serving as the input signal of the half delay cell B, the intermediate signal OUT_a is also connected to a buffer BUF_a. The circuit structure of the delay sub-unit halfdelaycell B is exactly the same as that of the delay sub-unit half delaycell A. The two constitute a complete coarse delay unit, and its output terminal OUT is directly connected to the input terminal of the next stage delay unit.

[0109] To prevent subsequent circuits from affecting the delay of the delay unit and to ensure that the load environment of each delay unit in the delay chain is completely consistent, thereby achieving delay uniformity, the output signal OUT passes through buffer BUF_b and is then output from the (rising edge or falling edge) terminal O_BUF to the subsequent multiplexer circuit. Only the rising edge of the input causes nd1_a to discharge, which is then converted back to a steep falling edge by the second-stage Schmitt trigger. For the falling edge of the input, there is no discharge process, and it is delayed by t2. In this way, nd2_a is out of phase with the input, and through the third-stage inverter, the input and output phases are made consistent, completing half of the delay. After the input signal IN passes through halfdelaycell A, its output OUT_a is out of phase with the input signal, and it is delayed by t1 for the rising edge of the input signal IN and by t2 for the falling edge of the input signal IN. Since the first control voltage VC1 controls the discharge current of the half-current starved inverter, its high-level to low-level transition transmission time is... Greater than the transmission time of the low-to-high level transition Therefore, the delay t1 of the rising edge of the input signal in half delay cell A is greater than the delay t2 of the falling edge of the input signal. Similarly, the output signal OUT_a of half delay cell A serves as the input signal of the second-stage half delay cell B. Half delay cell B will generate delays of t1 and t2 for the rising and falling edges of its input signal OUT_a, respectively. Thus, the total delay of the entire coarse delay unit for the rising and falling edges of the input signal IN is equal, both being t1 + t2, thereby ensuring that the duty cycle of the final output signal OUT and the input signal IN remains unchanged.

[0110] The coarse delay unit of the present invention is divided into two identical cascaded parts, which delay the rising edge and falling edge of each input signal respectively, so as to minimize the difference in delay between the rising edge and the falling edge, thereby keeping the pulse width of each signal constant.

[0111] In the coarse delay control module, to ensure that the paths of the third delay signal and the delay feedback signal reaching the frequency and phase detector 3PF in the phase-locked loop of the coarse delay control module are completely consistent, the coarse delay phase-locked loop circuit of the present invention further includes a second delay module 2. The first input terminal of the second delay module 2 is connected to the second output terminal of the first delay module for receiving the first delay signal; the second input terminal of the second delay module 2 is connected to the output terminal of the first delay link module 4 for receiving the delay feedback signal; the control terminal of the second delay module 2 is connected to the output terminal of the first charge pump; under the action of the first control voltage VC1 output by the first charge pump, the second delay module further delays the second delay signal to output a third delay signal and further delays the delay feedback signal to output a fourth delay signal. Correspondingly, the first input terminal of the frequency and phase detector 3 is connected to the first output terminal of the second delay module 2, and the second input terminal of the frequency and phase detector 3 is connected to the second output terminal of the second delay module 2 for outputting a first phase difference signal based on the third delay signal and the fourth delay signal.

[0112] In embodiments of the present invention, such as Figure 5The diagram shows the structure of the frequency and phase detector (PFD) of the present invention. The PFD includes a first flip-flop (DFF1), a second flip-flop (DFF2), a third flip-flop (DFF3), a fourth flip-flop (DFF4), and an enable control unit. The clock terminal of the first flip-flop is the first input terminal of the PFD. The input terminal of the first flip-flop is connected to the power supply voltage VDD, and the output terminal of the first flip-flop is connected to the input terminal of the second flip-flop. The clock terminal of the second flip-flop is connected to the clock terminal of the first flip-flop. The clock terminal of the third flip-flop is the second input terminal of the PFD. The input terminal of the third flip-flop is connected to the power supply voltage VDD, and the output terminal of the third flip-flop is connected to the input terminal of the fourth flip-flop. The clock terminal of the fourth flip-flop is connected to the clock terminal of the third flip-flop. The reset terminal of the third flip-flop is grounded to VSS. The output of the enable control unit is connected to the reset terminals of the first, second, and fourth flip-flops. The input terminal of the enable control unit is connected to the output terminal of the control module. The PFD outputs a phase difference signal through the output terminal UP of the second flip-flop and the output terminal DN of the fourth flip-flop according to the enable control signal. In this embodiment of the invention, the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, and the fourth flip-flop DFF4 are all D-type flip-flops. Under the action of the clock signal, the output result changes according to the state of the input terminal D.

[0113] In this embodiment of the invention, the enable control unit includes a fourth inverter, a second AND gate, and an OR gate; the input terminal of the fourth inverter is connected to the output terminal of the control module, the output terminal of the fourth inverter is connected to the reset terminal of the first inverter and the first input terminal of the OR gate, the first input terminal of the second AND gate is connected to the output terminal of the second inverter, the second input terminal of the second AND gate is connected to the output terminal of the fourth inverter, the output terminal of the second AND gate is connected to the second input terminal of the OR gate, and the output terminal of the OR gate is connected to the reset terminal of the second inverter and the reset terminal of the fourth inverter.

[0114] The phase-frequency detector (PFD) of this invention compares the phase relationship between a reference clock signal (the third delayed signal) and a feedback signal (the delayed feedback signal), and outputs a phase difference signal representing their phase relationship. This phase difference signal is converted into a change in the first control voltage VC1 of the first delayed link module by the first charge pump CP and the loop low-pass filter LPF (the loop low-pass filter is composed of the output impedance of the charge pump CP and the capacitor C1). Under the action of the loop, by continuously adjusting the first control voltage VC1 of the first delayed link module, the reference clock signal and the feedback signal are made to be in phase.

[0115] In this embodiment of the invention, the first trigger and the third trigger have the same structure, and the second trigger and the fourth trigger have the same structure. The first trigger and the second trigger form a first trigger branch for processing the third delayed signal, and the third trigger and the fourth trigger form a second trigger branch for processing the fourth delayed signal. The first trigger branch and the second trigger branch are symmetrical, so that the load of the reference clock signal (third delayed signal) and the feedback signal (delay feedback signal) is the same, and they have the same environment and better performance.

[0116] In this embodiment of the invention, the first flip-flop and the second flip-flop have the same structure; for example... Figure 6 The diagram shows the circuit structure of the first and third flip-flops.

[0117] The first flip-flop structure includes a second PMOS transistor P2, a third PMOS transistor P3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a seventh NMOS transistor N7, a sixth PMOS transistor P6, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a seventh PMOS transistor P7, and a tenth NMOS transistor N10; the source of the second PMOS transistor P2 is connected to the power supply voltage VDD, and the drain of the second PMOS transistor P2 is connected to the source of the third PMOS transistor P3, and the drain of the third PMOS transistor P3 is connected to... The drain of the fourth NMOS transistor N4; the source of the fourth NMOS transistor N4 is grounded; the connection point between the gate of the second PMOS transistor P2 and the gate of the fourth NMOS transistor N4 is the input terminal of the first flip-flop structure; the gate of the third PMOS transistor P3 is connected to the third delay signal CLK_REF; the connection point between the drain of the third PMOS transistor P3 and the drain of the fourth NMOS transistor N4 is connected to the gate of the sixth NMOS transistor N6; the source of the sixth NMOS transistor N6 is connected to the drain of the fifth NMOS transistor N5; the source of the fifth NMOS transistor N5 is grounded; the fifth The gate of NMOS transistor N5 is connected to the third delay signal CLK_REF; the drain of the sixth NMOS transistor N6 is connected to the drain of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 is connected to the output of the fourth inverter N4, the source of the fourth PMOS transistor P4 is connected to the drain of the fifth PMOS transistor P5, the source of the fifth PMOS transistor P5 is connected to the power supply voltage VDD, and the gate of the fifth PMOS transistor P5 is connected to the third delay signal CLK_REF; the connection point between the drain of the fourth PMOS transistor P4 and the drain of the sixth NMOS transistor N6 is the midpoint. The intermediate point connects the drain of the seventh NMOS transistor N7, the gate of the sixth PMOS transistor P6, and the gate of the ninth NMOS transistor N9; the gate of the seventh NMOS transistor N7 is connected to the output of the fourth inverter N4; the source of the sixth PMOS transistor P6 is connected to the power supply voltage VDD; the drain of the sixth PMOS transistor P6 is connected to the drain of the eighth NMOS transistor N8; the drain of the eighth NMOS transistor N8 is connected to the drain of the ninth NMOS transistor N9; the source of the ninth NMOS transistor N9 is grounded; and the gate of the eighth NMOS transistor N8 is connected to the output of the fourth inverter N4.The connection point between the drain of the sixth PMOS transistor P6 and the drain of the eighth NMOS transistor N8 is connected to the gate of the seventh PMOS transistor P7 and the gate of the tenth NMOS transistor N10. The source of the seventh PMOS transistor P7 is connected to the power supply voltage, and the source of the tenth NMOS transistor N10 is grounded. The drains of the seventh PMOS transistor P7 and the tenth NMOS transistor N10 are the output terminal Q of the first flip-flop.

[0118] When the fourth PMOS transistor of the first flip-flop of this invention is driven by the reset signal and RST is high, the connected sixth NMOS transistor N6 and fifth NMOS transistor N5 are turned on, causing the voltage at the intermediate point A to drop. At this time, if CLK_REF goes low, the fourth PMOS transistor is turned off, isolating the high level connected to the intermediate point A when CLK_REF goes low, thereby eliminating the intermediate state that may occur at point A, avoiding logic errors in the first flip-flop, and preventing incorrect output results, thereby improving the accuracy of the control results of the coarse delay phase-locked loop circuit.

[0119] The second and fourth flip-flops of this invention have the same structure, as shown below. Figure 7 The diagram shows the circuit structure of the second and fourth flip-flops; the second flip-flop is shown in detail below.

[0120] The difference between the second flip-flop and the first flip-flop is the addition of an inverter chain 6. The input of the inverter chain 6 is connected to the drain of the eleventh PMOS transistor and the drain of the fifteenth NMOS transistor N15. The output of the inverter chain 6 is connected to the gate of the twelfth PMOS transistor P12 and the gate of the eighteenth NMOS transistor N18. The inverter chain 6 includes four identical inverter branches. Each inverter branch includes a PMOS transistor and an NMOS transistor connected in series. The gates of the NMOS transistor and the PMOS transistor are connected to form the input of the inverter branch. The drains of the NMOS transistor and the PMOS transistor are connected to form the output of the inverter branch. The source of the PMOS transistor is connected to the power supply voltage, and the source of the NMOS transistor is grounded. The inverter branches are cascaded through the input and output terminals.

[0121] When the tenth PMOS transistor of the second flip-flop of this invention is driven by the reset signal and RST is high, the connected thirteenth NMOS transistor N13 and twelfth NMOS transistor N12 are turned on, causing the voltage at the intermediate point B to drop. At this time, if CLK_REF goes low, since the tenth PMOS transistor P10 is turned off, the high level connected to the intermediate point B due to CLK_REF going low is isolated, thereby eliminating the intermediate state that may occur at point B, avoiding logic errors of the second flip-flop, and preventing the second flip-flop from outputting incorrect results, further improving the accuracy of the control results of the coarse delay phase-locked loop circuit.

[0122] The frequency and phase detector of the present invention can avoid leakage and intermediate level, and the fourth flip-flop is controlled by logic gate control. Compared with the prior art that uses a reset circuit, the coarse delay phase-locked loop has higher control accuracy.

[0123] The charge pump converts the phase difference signal (i.e., the pulse width signal of the switching control signal) generated by the phase-frequency detector (PFD) into a voltage signal proportional to the pulse width. Several non-ideal factors exist in the charge pump, such as channel length modulation effect, clock feedthrough, and charge sharing, all of which affect the phase accuracy during DLL or PLL locking. To reduce the impact of these non-ideal factors, the first charge pump includes a bias circuit and a main circuit. The bias circuit's input is connected to a constant current source, and its output is connected to the main circuit. The bias circuit provides a bias voltage to the main circuit based on the constant current source. The main circuit outputs a first control voltage based on the bias voltage and according to the first phase difference signal.

[0124] The structural schematic diagram of the first charge pump proposed in this invention is as follows: Figure 8 As shown, the part to the left of the dashed line is the bias circuit, and the part to the right of the dashed line is the main circuit. UP / UPB and DN / DNB are two sets of differential switch control signals generated by the PFD, used to control the transmission gate switches TG0 to TG7.

[0125] Furthermore, the main circuit includes a switching unit, an operational amplifier, a first current mirror, and a second current mirror;

[0126] The first current mirror is connected to the bias circuit, the power supply voltage, and the first node X of the switching unit;

[0127] The second common-source common-gate current is connected to the bias current, the second node Y of the switching unit, and the ground terminal;

[0128] The switching unit includes two switching branches, and the operational amplifier is connected in parallel between the switching branches;

[0129] The non-inverting input terminal of the operational amplifier is the output terminal of the first charge pump, that is, it outputs the first control voltage.

[0130] Specifically, the first current mirror includes two PMOS transistors, namely PMOS transistor PM1 and PMOS transistor PM2. The gate of PMOS transistor PM1 is connected to the first output terminal of the bias circuit, the source of PMOS transistor PM1 is connected to the power supply voltage, the drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM2, the gate of PMOS transistor PM2 is connected to the second output terminal of the bias circuit, and the drain of PMOS transistor PM2 is connected to the first node X of the switching unit.

[0131] Specifically, the second common-source common-gate current includes two NMOS transistors, namely NMOS transistor NM1 and NMOS transistor NM2. The gate of NMOS transistor NM1 is connected to the third output terminal of the bias circuit, and the drain of NMOS transistor NM1 is connected to the second node Y of the switch. The source of NMOS transistor NM1 is connected to the drain of NMOS transistor NM2, the gate of NMOS transistor NM2 is connected to the fourth output terminal of the bias circuit, and the source of NMOS transistor NM2 is grounded.

[0132] Specifically, the switching unit includes a main switch and an auxiliary switch. The main switch includes a first transmission gate switch TG1, a fifth transmission gate switch TG5, a fourth transmission gate switch TG4, and an eighth transmission gate switch TG8. The auxiliary switch includes a second transmission gate switch TG2, a third transmission gate switch TG3, a sixth transmission gate switch TG6, and a seventh transmission gate switch TG7.

[0133] The two switch branches are the first switch branch and the second switch branch; the first switch branch includes the first transmission gate switch TG1, the second transmission gate switch TG2, the third transmission gate switch TG3 and the fourth transmission gate switch TG4 connected in series; the second switch branch includes the fifth transmission gate switch TG5, the sixth transmission gate switch TG6, the seventh transmission gate switch TG7 and the eighth transmission gate switch TG8 connected in series.

[0134] The non-inverting input of the op-amp is connected between the second transmission gate TG2 and the third transmission gate TG3. The negative-inverting input of the op-amp OPA and the output of the op-amp are connected between the sixth transmission gate switch TG6 and the seventh transmission gate switch TG7. The non-inverting input of the op-amp is the output of the first charge pump, which outputs the first control voltage VC1.

[0135] In this invention, in order to suppress the charge sharing effect, the first charge pump adopts a differential structure and uses a unity-gain operational amplifier (OPA) to clamp the voltages at both ends to be equal.

[0136] The control signals for the first transmission gate switch TG1 and the fifth transmission gate switch TG5 are opposite, as are the control signals for the fourth transmission gate switch TG4 and the eighth transmission gate switch TG8. When the first transmission gate switch TG1 and the fourth transmission gate switch TG4 are open, the fifth transmission gate switch TG5 and the eighth transmission gate switch TG8 are closed; when the fifth transmission gate switch TG5 and the eighth transmission gate switch TG8 are open, the first transmission gate switch TG1 and the fifth transmission gate switch TG5 are closed. In both cases, the voltages at nodes X and Y are approximately equal to VC1, effectively suppressing the charge-sharing effect.

[0137] Because MOSFETs have parasitic capacitances Cgs and Cgd, the clock signal applied to the gate of the MOSFET will couple to the drain of the MOSFET through the parasitic capacitance, thus affecting the output voltage of the loop filter. To reduce clock feedthrough, dummy switches, namely the second transmission gate switch TG2, the third transmission gate switch TG3, the sixth transmission gate switch TG6, and the seventh transmission gate switch TG7, are introduced. Their size is half that of the main switch, and their control signals are opposite to those of the main switch. The signals fed through the parasitic capacitance cancel out the clock feedthrough signal of the main switch.

[0138] To reduce the channel length effect, the first current source D1 and the second current mirror D2 adopt a common source and common gate structure, which increases the output impedance of the charge and discharge current source and reduces the mismatch of charge and discharge current.

[0139] The charge pump operates as follows: When the UP signal is high and the DN signal is low, the first transmission gate switch TG1 is turned on, and the fourth transmission gate switch TG4 is turned off. The pull-up current IUP provided by the first current mirror D1 charges the capacitor of the subsequent loop filter, increasing the first control voltage VC1. When the UP signal is low and the DN signal is high, the first transmission gate switch TG1 is turned off, and the fourth transmission gate switch TG4 is turned on. The pull-down current IDN provided by the second current mirror D2 discharges the capacitor of the loop filter, decreasing the first control voltage VC1. When the loop is locked, the first control voltage VC1 reaches a stable state.

[0140] In the embodiments of the present invention, the fine delay control module is as follows: Figure 9As shown, the fine delay control module includes a second delay link module 7, a frequency and phase detector, a second charge pump, and a second control module 8. The second delay link module 7 includes a first delay branch and a second delay branch. The input terminal of the first delay branch is connected to the clock output terminal of the coarse delay control module, and is used to receive the rising edge signal of the clock signal. Under the action of the second control voltage output by the second charge pump, the first delay branch performs delay control on the rising edge signal and outputs a first delay signal. The input terminal of the second delay branch is connected to the clock output terminal of the coarse delay control module, and is used to receive the falling edge signal of the clock signal. Under the action of the second control voltage output by the second charge pump, the second delay branch performs delay control on the falling edge signal and outputs a second delay signal. The second control module 8 has a delay signal; its input is connected to a power supply voltage signal and an enable signal, and its output is connected to the enable terminal of the frequency-phase detector; the second control module generates a second enable control signal to control the frequency-phase detector based on the power supply voltage signal and the enable signal; the first input of the frequency-phase detector is connected to the output of the first delay branch, and its second input is connected to the output of the second delay branch; based on the control effect of the second enable control signal, the frequency-phase detector outputs a second phase difference signal based on the second delay signal and the delay feedback signal; the input of the second charge pump is connected to the output of the frequency-phase detector; the second charge pump obtains the second control voltage based on the second phase difference signal.

[0141] The fine delay control module of this invention controls the rising edge and falling edge signals (the rising edge and falling edge signals form the delay dynamic range) of the clock signal output by the first delay link module in the coarse delay control module through two delay branches of the second delay link module. Based on the enable control signal generated by the control module, it controls the frequency and phase detector. After the delay is completed, the signals are combined into one signal. Under the action of the loop, the second control voltage of the second delay control link is continuously adjusted to make the two delay signals in phase, and finally achieve precise control of the delay accuracy.

[0142] In this embodiment of the invention, the first delay branch (fine stage 3 and fine stage 4) and the second delay branch (fine stage 1 and fine stage 2) of the second delay link module 7 have the same structure. The first delay branch delays the rising edge signal of the clock signal, and the second delay branch delays the falling edge signal of the clock signal for the same amount of time. Then, the fine delay control module combines the two delayed rising edge signals and falling edge signals to output a signal with the same duty cycle as the input clock signal.

[0143] Taking the first delay branch as an example, the delay branch in the second delay link module 7 of the present invention is introduced.

[0144] The first delay branch includes two fine delay units, which are cascaded and have identical structures. For a clearer and more detailed description, the two fine delay units are introduced as the first delay unit (fine stage 3) and the second delay unit (fine stage 4), respectively. Figure 10 The diagram shows a fine delay unit in an embodiment of the present invention. The fine delay unit includes a first transmission branch, a second transmission branch, and a load branch. The first transmission branch includes a first half-current-starved inverter X3, a first inverter X1, a second inverter X2, a fourth inverter X4, a fifth inverter X5, and a PMOS transistor PMO. The input terminal of the first inverter X1 is connected to the input signal. The output terminal of the first inverter X1 is connected to the input terminal of the second inverter X2, the input terminal of the second inverter X2 is connected to the input terminal of the first half-current-starved inverter X3, the output terminal of the first half-current-starved inverter X3 is connected to the input terminal of the fourth inverter X4, the output terminal of the fourth inverter X4 is connected to the input terminal of the fifth inverter X5, the output terminal of the fifth inverter X5 is connected to the gate terminal of the PMOS transistor PMO, and the drain terminal of the PMOS transistor PMO is connected to the output signal. The second transmission branch includes a first half-current-starved inverter X3, a first inverter X1, a second inverter X2, a fourth inverter X4, a fifth inverter X5, and a load branch. The output branch includes a second half-current-starved inverter X7, a sixth inverter X6, an eighth inverter X8, a ninth inverter X9, a tenth inverter X10, and an NMOS transistor NM0. The input terminal of the sixth inverter X6 is connected to the input signal, the output terminal of the sixth inverter X6 is connected to the input terminal of the second half-current-starved inverter X7, the output terminal of the second half-current-starved inverter X7 is connected to the input terminal of the eighth inverter X8, the output terminal of the eighth inverter X8 is connected to the input terminal of the ninth inverter X9, the output terminal of the ninth inverter X9 is connected to the input terminal of the tenth inverter X10, the output terminal of the tenth inverter X10 is connected to the gate terminal of the NMOS transistor NM0, and the drain terminal of the NMOS transistor NM0 is connected to the output signal. One end of the load branch is connected to the input terminal of the fourth inverter X4, and the other end of the load branch is connected to the input terminal of the eighth inverter X8.

[0145] In this embodiment of the invention, the load branch includes two sets of loads, each set comprising 16 NMOS transistors. These 16 NMOS transistors form a MOSCAP, i.e., C0<15:0> and C1<15:0>. The gate of the first set of loads is connected to the input of the fourth inverter X4, and the gate of the second set of loads is connected to the input of the eighth inverter X8. The source-drain connection point of the first set of loads is connected to the source-drain connection point of the second set of loads, and is also connected to the output of the twelfth inverter. The input of the twelfth inverter is the digital control terminal of the delay unit, used to receive digital control signals. Using the superposition of multiple NMOS transistors improves the stability of the capacitance value and reduces tolerance.

[0146] In this invention, the gate terminal of the first load group is connected to point B of the first transmission branch as the positive terminal of a capacitor, and the gate terminal of the second load group is connected to point E of the second transmission branch as the negative terminal of a capacitor. The source-drain terminals of the first and second load groups are short-circuited and simultaneously serve as the negative terminals of the capacitors. When the digital control signal D... <x>When (x:15~0) is high, C0 <x>and C1 <x>The negative terminal is at a low level, and its equivalent capacitance is Ca; when the digital control signal D... <x>When C0 is low, <x>and C1 <x>The negative terminal is high, and its equivalent capacitance is Cb. When points B and E are high, according to the MOSCAP characteristic, Ca>Cb. Therefore, by changing the number of high-level bits in the 16-bit control signal D<15:0>, the load capacitance at points B and E can be changed, thereby altering the fall time of the output signal.

[0147] In this invention, since the load capacitor of the second delay link module needs to be controlled, in order to keep the delay consistent with that in the second delay link module, the load capacitor connection method of the fine delay unit in the fine delay control module is also consistent with the delay link of the fine delay control module, and the negative terminal of the capacitor of the load branch is connected to the output terminal of the twelfth inverter.

[0148] In this embodiment of the invention, the first half-current-starved inverter and the second half-current-starved inverter are identical, and both have the same circuit structure as the half-current-starved inverter in the coarse delay unit. In application, the fine delay unit controls the magnitude of the discharge current of the first half-current-starved inverter to its output node (point B in the first output branch) and the second half-current-starved inverter to its output node (point E in the second output branch) through the second control voltage VC2, thereby controlling the fall time. Specifically, assuming the first transmission time for the high-to-low level transition of the first half-current-starved inverter X3 and the second half-current-starved inverter X7 is... The second transmission time for the low-to-high level transition is The propagation time of the remaining inverters in the delay unit is... Since the discharge current of the first half-current-starved inverter X3 and the first half-current-starved inverter X7 is controlled by the control voltage VCTL, therefore and It varies with the control voltage and load capacitance. After the fine-delay phase-locked loop (DLL) is locked, when the control voltage VCTL is constant, and the digital control signal D<15:0> is all 0 (i.e., all low), the total load capacitance is at its minimum, and the first transmission time is... The minimum; however, for each additional bit of 1 in the digital control signal, the transmission delay increases by 9.77 ps; when the digital control signal D<15:0> is all 1s, the total load capacitance is at its maximum, and the second transmission time is... maximum.

[0149] The fine delay unit of the present invention also includes an inverter X0. The rising edge of the clock signal passes through the inverter X0 and is connected to the first transmission branch and the second transmission branch respectively. The signal on the first transmission branch passes through the first inverter X1, the second inverter X2, the first half-current-starved inverter X3, the fourth inverter X4 and the fifth inverter in sequence and reaches the gate terminal C of the PMOS transistor PMO. The signal on the second transmission branch passes through the sixth inverter X6, the second half-current-starved inverter X7, the eighth inverter X8, the ninth inverter X9 and the tenth inverter X10 in sequence and reaches the gate terminal F of the NMOS transistor NMO.

[0150] To ensure that the pre-stage drive and post-stage load of the first half-current-starved inverter X3 and the second half-current-starved inverter X7 are consistent, and to guarantee that the signals of the first transmission branch and the second transmission branch pass through the same gate circuit, the inverters X1, X2, X4, X6, X8, and X9 must have the same size, and the inverters X5 and X10 must have the same size.

[0151] In the first delay branch, the signal arriving at point D is in phase with the input signal IN. The second half of the current-starved inverter X7 will produce a relatively large delay for the rising edge of point D (i.e., the rising edge of the input signal), meaning CLK_START passes through a delay unit of the relative full-scale load (e.g., N=17). In the second delay branch, the signal arriving at point A is out of phase with the input signal IN. The first half of the current-starved inverter X3 will produce a relatively large delay for the rising edge of the input terminal A (i.e., the falling edge of the input signal), meaning CLK_STOP passes through a delay unit of the relative no-load load (N=1). Therefore, the phase relationship between the signals arriving at gate C of PM0 and gate F of NM0 is as follows: Figure 7 As shown, the falling edge of the signal at point C and the rising edge of the signal at point F are combined at point G by PMOS transistor PM0 and NMOS transistor NM0 respectively, and then output after passing through the eleventh inverter X11. The total delay t of the rising edge of the signal from the input terminal IN to the output terminal OUT is... dr Total delay t of the falling edge of the signal df Equal, both are Therefore, the duty cycle of the output signal at the OUT terminal is the same as that of the input signal IN.

[0152] In this embodiment of the invention, the frequency and phase detector has the same structure as the frequency and phase detector in the coarse delay control module, and the second charge pump and the second control module are also the same as the first charge pump and the first control module in the coarse delay control module, respectively. Further details will not be provided here; as other embodiments, the frequency and phase detector, the second charge pump, and the second control module can also be implemented using other circuit structures.

[0153] like Figure 14 The diagram shown is a structural schematic of a dual-channel delay link in an embodiment of the present invention. The two delay channels of the dual-delay channel are a first delay channel and a second delay channel. When the dual-channel digital delay control chip is working in dual-delay mode, the first delay channel and the second delay channel work independently. When the dual-channel digital delay control chip is working in extended delay mode, the first delay channel and the second delay channel work in cascade.

[0154] Specifically, when operating in dual delay mode, the first delay channel PD0 and the second delay channel PD1 operate independently. That is, under the delay control command (including DCW0 and DCW1), the first delay channel PD0 delays the first differential signal (INP0 and INN0) and outputs the first high-speed signal (OUTP0 and OUTN0), and the second delay channel PD1 delays the second differential signal (INP1 and INN1) and outputs the second high-speed signal (OUTP1 and OUTN1). When operating in extended delay mode, the first delay channel PD0 and the second delay channel PD1 operate in cascade. That is, under the delay control command (including DCW0 and DCW1), the first delay channel PD0 delays the first differential signal (INP0 and INN0) and then inputs it to the cascaded second delay channel PD1 for further delay before outputting the high-speed signal (OUTP1 and OUTN1).

[0155] In this embodiment of the invention, the two delay channels of the dual-delay channel have the same structure, that is, the delay link structure of the first delay channel and the second delay channel is the same. For example... Figure 15 The diagram shown is a block diagram of a single-channel delay link structure in an embodiment of the present invention.

[0156] The delay channel includes a coarse delay link unit, a control unit, and a fine delay link unit.

[0157] The signal input terminal of the coarse delay link unit receives the differential signal, the power supply terminal of the coarse delay unit is connected to the first control voltage VC1, and the coarse delay link unit performs coarse delay on the differential signal based on the first control voltage;

[0158] The input terminal of the control unit is connected to the signal output terminal of the coarse delay unit, and the output terminal of the control unit is connected to the input terminal of the fine delay unit. The control unit outputs the delay range after coarse delay by the coarse delay link unit according to the control command (4 bits).

[0159] The power supply terminal of the fine delay unit is connected to the second control voltage VC2. Based on the second control voltage, the fine delay unit performs a fine delay within the delay range according to the control command (5 bits) and then outputs the high-speed signal.

[0160] In this embodiment of the invention, the fine delay unit and the coarse delay unit are controlled by the first control voltage and the second control voltage, respectively. Since the delay control circuit is a delay loop with a negative feedback mechanism, it can suppress the influence of process, voltage, temperature (PVT) deviation on the delay of its internal delay unit, thereby obtaining higher delay accuracy.

[0161] Specifically, such as Figure 16 The diagram shows the link structure of the coarse delay link unit. The circuit structure of the coarse delay link unit is the same as that of the first delay link module 4 in the delay control circuit. That is, the coarse delay unit also consists of 16 cascaded voltage-controllable delay units. The high 4 bits of the delay control word are digitally decoded to control the multiplexer to select the corresponding delay output, generating the corresponding delay time range. For example... Figure 17 The diagram shows the link structure of the fine delay link unit. The circuit structure of the fine delay link unit is the same as that of the second delay link module 7 in the delay control circuit. The fine delay link consists of two cascaded fine delay units, each with 16 controllable MOSCAP capacitor loads. The lower 5 bits of the delay control word are decoded into 32-bit thermometer code by a digital decoding circuit to control the controllable capacitor loads of the fine delay link, producing a delay accuracy of 10 ps.

[0162] In this embodiment of the invention, the digital control circuit includes control signal decoding units for two delay channels, an SPI interface, and a debugging module. The control signal decoding unit for the delay channels divides the 9-bit delay control word written by the SPI into a high 4-bit coarse adjustment control word (DW0) and a low 5-bit fine adjustment control word (DW1). The coarse adjustment control word is a 4-bit binary code, and the fine adjustment control word is decoded into a 32-bit thermometer code, used for control input to the core circuit of the delay channel. The SPI interface is responsible for reading and writing to the chip's internal control registers and reading internal debugging data. In debug mode, the debugging module outputs internal key signals and data to the external chip via the debug pin, and can also directly control the core circuit of the delay channel from the external chip. The input / output interface adopts the SPI Slave interface timing. Each data access includes two bytes of data transmission: the high byte is the control and address byte, including one read / write control bit and a 7-bit register address; the low byte is the input or output data.

[0163] In summary, the dual-channel numerically controlled delay chip of the present invention can accurately control the delay range and delay magnitude. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0164] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.< / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A dual channel digitally controlled delay chip, characterized by, Includes delay control circuitry, dual delay channels, and digital control circuitry; The delay control circuit includes a coarse delay control module and a fine delay control module; the signal input terminal of the coarse delay control module is connected to a reference clock, and the clock output terminal of the coarse delay control module outputs a clock signal; the signal output terminal of the coarse delay control module outputs a first control voltage; the signal input terminal of the fine delay control module is connected to the clock output terminal of the coarse delay control module, and the fine delay control module outputs a second control voltage based on the clock signal; The digital control circuit generates mode control commands and delay control commands; The dual delay channel is electrically connected to the delay control circuit and the digital control circuit; the dual delay channel includes two delay channels, which are a first delay channel and a second delay channel; It supports dual delay mode and extended delay mode; when the dual-channel CNC delay chip is working in dual delay mode, the first delay channel and the second delay channel work independently; when the dual-channel CNC delay chip is working in extended delay mode, the first delay channel and the second delay channel work in cascade. The dual-delay channel enables the dual-channel CNC delay chip to operate in dual-delay mode or extended delay mode based on the mode control command. The dual-delay channel executes the delay control command based on the first control voltage and the second control voltage, so that the differential signal is output as a high-speed signal after being delayed by the dual-delay channel; wherein, the delay channel includes a coarse delay link unit, a control unit and a fine delay link unit; The signal input terminal of the coarse delay link unit receives a differential signal, the power supply terminal of the coarse delay link unit is connected to the first control voltage, and the coarse delay link unit performs a coarse delay on the differential signal based on the first control voltage. The input terminal of the control unit is connected to the signal output terminal of the coarse delay link unit, and the output terminal of the control unit is connected to the input terminal of the fine delay link unit. The control unit outputs the delay range after coarse delay by the coarse delay link unit according to the control command. The power supply terminal of the fine delay link unit is connected to the second control voltage. Based on the second control voltage, the fine delay link unit outputs the high-speed signal after performing a fine delay within the delay range.

2. The dual channel digitally controlled delay chip of claim 1, wherein, The coarse delay control module includes a frequency and phase detector, a first delay module, a first delay link module, a first charge pump, and a first control module. The signal input terminal of the first delay module is connected to a reference clock, and the control terminal of the first delay module is connected to the output terminal of the first charge pump. Under the action of the first control voltage output by the first charge pump, the first delay module outputs a first delay signal from its first output terminal and a second delay signal from its second output terminal. The signal input terminal of the first delay link module is connected to the first output terminal of the first delay module, and the control terminal of the first delay link module is connected to the output terminal of the first charge pump; under the action of the first control voltage output by the first charge pump, the first delay link module further delays the first delay signal to obtain a delay feedback signal. The first control module is connected to a power supply voltage signal and an enable signal as inputs, and the output of the first control module is connected to the enable terminal of the frequency and phase detector. The first control module generates a first enable control signal to control the frequency and phase detector based on the power supply voltage signal and the enable signal; The first input terminal of the frequency and phase detector is connected to the first output terminal of the first delay module, and the second input terminal of the frequency and phase detector is connected to the output terminal of the first delay link module; based on the control effect of the first enable control signal, the frequency and phase detector outputs a first phase difference signal according to the second delay signal and the delay feedback signal; The input terminal of the first charge pump is connected to the output terminal of the frequency and phase detector; it is used to obtain the first control voltage based on the first phase difference signal.

3. The dual-channel numerically controlled delay chip according to claim 2, characterized in that, The first delay link module includes N coarse delay units, which are cascaded together. The control terminal of each coarse delay unit is connected to the output terminal of the charge pump; wherein, N≥3; The coarse delay unit includes two identical delay sub-units, which are cascaded; the delay sub-unit includes a half-current-starved inverter and a buffer circuit. The half-current-starved inverter includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are the input terminals of the delay unit. The source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor and the drain of the third NMOS transistor are connected. The gate of the third NMOS transistor is the control terminal of the delay unit, and the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the power supply voltage, and the drains of the second NMOS transistor and the drain of the third NMOS transistor are grounded. The half-current-starved inverter is used to output a discharge current according to the control voltage. The buffer circuit includes a Schmitt inverter and a third inverter; the input terminal of the Schmitt inverter is connected to the junction formed by the drain of the first PMOS transistor and the drain of the third NMOS transistor; the output terminal of the Schmitt inverter is connected to the input terminal of the third inverter; the buffer circuit buffers the discharge current before outputting it.

4. The dual channel digitally controlled delay chip of claim 3, wherein, It also includes a second delay module, the first input terminal of which is connected to the second output terminal of the first delay module for receiving the first delay signal; the second input terminal of the second delay module is connected to the output terminal of the delay link module for receiving the delay feedback signal; the control terminal of the second delay module is connected to the output terminal of the first charge pump; under the action of the first control voltage output by the first charge pump, the second delay module further delays the second delay signal and further delays the delay feedback signal.

5. The dual channel digitally controlled delay chip of claim 4, wherein, The fine delay control module includes a second delay link module, a frequency and phase detector, a second charge pump, and a second control module. The second delay link module includes a first delay branch and a second delay branch; the input terminal of the first delay branch is connected to the clock output terminal of the coarse delay control module, and is used to receive the rising edge signal of the clock signal. Under the action of the second control voltage output by the second charge pump, the first delay branch performs delay control on the rising edge signal and outputs a first delay signal. The input terminal of the second delay branch is connected to the clock output terminal of the coarse delay control module, and is used to receive the falling edge signal of the clock signal. Under the action of the second control voltage output by the second charge pump, the second delay branch is used to perform delay control on the falling edge signal and output a second delay signal. The input of the second control module is connected to the power supply voltage signal and the enable signal, and the output of the second control module is connected to the enable terminal of the frequency and phase detector. The second control module generates a second enable control signal to control the frequency and phase detector based on the power supply voltage signal and the enable signal; The first input terminal of the frequency and phase detector is connected to the output terminal of the first delay branch, and the second input terminal of the frequency and phase detector is connected to the output terminal of the second delay branch; Based on the control effect of the second enable control signal, the frequency and phase detector outputs a second phase difference signal according to the second delay signal and the delay feedback signal; The input terminal of the second charge pump is connected to the output terminal of the frequency and phase detector; the second charge pump obtains the second control voltage based on the second phase difference signal.

6. The dual channel digitally controlled delay chip of claim 5, wherein, The first control module and the second control module have the same structure, including a first switch, a second switch, a first AND gate, a first inverter, a second inverter, and a NOR gate; The input terminal of the first switch is connected to the output terminal of the first inverter, the output terminal of the first switch is connected to the input terminal of the first inverter and the first input terminal of the first AND gate, the first source terminal of the first switch is connected to the power supply voltage, and the second source terminal of the first switch is connected to the output terminal of the charge pump. The input terminal of the second switch is connected to the output terminal of the second inverter, the output terminal of the second switch is connected to the input terminal of the second inverter, the first source terminal of the first switch is connected to the chip pin voltage, and the second source terminal of the first switch is connected to the output terminal of the charge pump. The first input terminal of the NOR gate is connected to the output terminal of the first inverter, the second input terminal of the NOR gate is connected to the second input terminal of the first AND gate, and the output terminal of the NOR gate is connected to the input terminal of the second inverter; the output terminal of the first AND gate is connected to the enable terminal of the frequency and phase detector.

7. The dual channel digitally controlled delay chip of claim 6, wherein, The frequency and phase detector includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, and an enable control unit; The clock terminal of the first flip-flop is the first input terminal of the frequency and phase detector; the input terminal of the first flip-flop is connected to the power supply voltage, the output terminal of the first flip-flop is connected to the input terminal of the second flip-flop; the clock terminal of the second flip-flop is connected to the clock terminal of the first flip-flop. The clock terminal of the third flip-flop is the second input terminal of the frequency and phase detector; the input terminal of the third flip-flop is connected to the power supply voltage, and the output terminal of the third flip-flop is connected to the input terminal of the fourth flip-flop; the clock terminal of the fourth flip-flop is connected to the clock terminal of the third flip-flop. The reset terminal of the third flip-flop is grounded; The output of the enable control unit is connected to the reset terminal of the first flip-flop, the reset terminal of the second flip-flop, and the reset terminal of the fourth flip-flop. The input terminal of the enabling control unit is connected to the output terminal of the control module; The frequency and phase detector outputs a phase difference signal through the output terminals of the second trigger and the fourth trigger according to the enable control signal.

8. The dual channel digitally controlled delay chip of claim 7, wherein, The enable control unit includes a fourth inverter, a second AND gate, and an OR gate; The input terminal of the fourth inverter is connected to the output terminal of the control module. The output terminal of the fourth inverter is connected to the reset terminal of the first inverter and the first input terminal of the OR gate. The first input terminal of the second AND gate is connected to the output terminal of the second inverter. The second input terminal of the second AND gate is connected to the output terminal of the fourth inverter. The output terminal of the second AND gate is connected to the second input terminal of the OR gate. The output terminal of the OR gate is connected to the reset terminal of the second inverter and the reset terminal of the fourth inverter.

9. The dual channel digitally controlled delay chip of claim 8, wherein, The first charge pump and the second charge pump have the same structure, including a bias circuit and a main circuit; The input of the bias circuit is connected to a constant current source, and the output is connected to the main circuit. The bias circuit provides a bias voltage to the main circuit based on the constant current source; The main circuit outputs a first control voltage based on the bias voltage, according to the first phase difference signal, and outputs a second control voltage based on the second phase difference signal.

10. The dual channel digitally controlled delay chip of claim 9, wherein, The main circuit includes a switching unit, an operational amplifier, a first current mirror, and a second current mirror. The first current mirror is connected to the bias circuit, the power supply voltage, and the first node of the switching unit; The second current mirror connects the bias circuit, the second node of the switching unit, and the ground terminal; The switching unit includes two switching branches, and the operational amplifier is connected in parallel between the switching branches; The non-inverting input terminal of the operational amplifier is the output terminal of the first charge pump.

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