Analog-to-digital conversion circuit and digital power chip
By converting the voltage to be sampled into a differential voltage and performing multiple delays, combined with the output sampling code from the decoding circuit, the challenges of traditional analog-to-digital converters in terms of speed, accuracy, area, and power consumption are solved, achieving fast and high-precision analog-to-digital conversion.
Patent Information
- Application Number
- CN202210157251.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-02-21
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2042-02-21
AI Technical Summary
While improving speed and accuracy, traditional analog-to-digital converter circuits struggle to reduce area and power consumption, and are difficult to scale down proportionally as process feature sizes shrink.
A voltage conversion circuit is used to convert the voltage to be sampled into positive and negative differential voltages. Multiple delays are performed by combining a reference delay circuit, a positive delay circuit, and a negative delay circuit. The sampling code is output through a decoding circuit. The speed is determined by the delay circuit, thereby reducing area and power consumption.
It achieves fast speed and high accuracy analog-to-digital conversion with small area and low power consumption, adapts to low-power application scenarios, and makes full use of the advantages of reduced process feature size.
Smart Images
Figure CN114567328B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic technology, and in particular relates to an analog-to-digital conversion circuit and a digital power supply chip. Background Technology
[0002] Analog-to-digital converters (ADCs) convert continuous input voltages into a series of discrete step variables, which are then represented by digital codes. This quantizes the input voltage, achieving the conversion from analog to digital signals. Traditional voltage-domain ADCs, limited by voltage comparators, often require high power supply voltages, high power consumption, and large area to achieve speed improvements and noise reductions. They are also difficult to scale down proportionally as process feature sizes decrease. Summary of the Invention
[0003] The purpose of this application is to provide an analog-to-digital conversion circuit and a digital power supply chip, which aims to solve the problem that related analog-to-digital conversion circuits cannot reduce area and power consumption while improving speed and accuracy.
[0004] This application provides an analog-to-digital converter circuit, including:
[0005] The voltage conversion circuit is configured to convert the voltage to be sampled into a positive differential voltage and a negative differential voltage;
[0006] A reference delay circuit is configured to delay a reference voltage a preset number of times, each delay lasting a preset duration, and output a trigger signal upon completion of the delay; wherein the preset duration is inversely proportional to the reference voltage; and the preset number of times is 2. n n is a natural number;
[0007] A positive electrode delay circuit, connected to the voltage conversion circuit and the reference delay circuit, is configured to delay the positive electrode differential voltage multiple times, each time for a first duration, and record the first number of times the positive electrode differential voltage is delayed when the trigger signal is received, and output a first code based on the first number of times; wherein, the first duration is inversely proportional to the positive electrode differential voltage;
[0008] A negative electrode delay circuit, connected to the voltage conversion circuit and the reference delay circuit, is configured to delay the negative electrode differential voltage multiple times, each time for a second duration, and record the second number of times the negative electrode differential voltage is delayed when the trigger signal is received, and output a second code based on the second number of times; wherein, the second duration is inversely proportional to the negative electrode differential voltage;
[0009] The decoding circuit, connected to the positive delay circuit and the negative delay circuit, is configured to decode the first code and the second code to output a sampled code.
[0010] This invention also provides a digital power supply chip, which includes the analog-to-digital conversion circuit described above.
[0011] The beneficial effects of this invention compared to the prior art are as follows: Since the first duration, the second duration, and the preset duration are all inversely proportional to the delayed voltage, and the first code corresponds to the first number of times the positive differential voltage is delayed, and the second code corresponds to the second number of times the negative differential voltage is delayed, the ratio of the positive differential voltage to the reference voltage is equal to the ratio of the first code to the preset number of times, and the ratio of the negative differential voltage to the reference voltage is equal to the ratio of the second code to the preset number of times. The sampling code can be decoded according to the first code and the second code. Thus, the digital-to-analog conversion circuit is composed of a decoding circuit and a delay circuit, and the speed is completely determined by the delay. It can achieve a fast speed and high accuracy with a very small area and power consumption. Moreover, it can make full use of the advantages brought by the reduction of process feature size, reduce the area and increase the speed, and adapt to low power consumption application scenarios. Attached Figure Description
[0012] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a schematic diagram of an analog-to-digital converter circuit provided in an embodiment of this application;
[0014] Figure 2 A schematic diagram of a reference delay circuit in an analog-to-digital converter circuit provided in an embodiment of this application;
[0015] Figure 3 A schematic diagram of a positive delay circuit in an analog-to-digital converter circuit provided in an embodiment of this application;
[0016] Figure 4 A schematic diagram of a negative delay circuit in an analog-to-digital converter circuit provided in an embodiment of this application;
[0017] Figure 5 A schematic diagram of a decoding circuit in an analog-to-digital converter circuit provided in an embodiment of this application;
[0018] Figure 6 This is a schematic diagram of another structure of the analog-to-digital conversion circuit provided in one embodiment of this application;
[0019] Figure 7 This is an example circuit schematic diagram of a voltage conversion module in an analog-to-digital converter circuit provided in an embodiment of this application;
[0020] Figure 8 An example circuit schematic diagram of a startup delay component in an analog-to-digital converter circuit provided in an embodiment of this application;
[0021] Figure 9 This is an example circuit schematic diagram of a successor delay component in an analog-to-digital conversion circuit provided in an embodiment of this application. Detailed Implementation
[0022] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0023] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0024] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0026] Figure 1 A schematic diagram of the analog-to-digital conversion circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:
[0027] The aforementioned analog-to-digital conversion circuit includes a voltage conversion circuit 11, a reference delay circuit 12, a positive delay circuit 13, a negative delay circuit 14, and a decoding circuit 15.
[0028] The voltage conversion circuit 11 is configured to convert the voltage to be sampled into a positive differential voltage and a negative differential voltage;
[0029] The reference delay circuit 12 is configured to delay the reference voltage a preset number of times, with each delay lasting a preset duration, and to output a trigger signal when the delay is completed; wherein, the preset duration is inversely proportional to the reference voltage;
[0030] The positive electrode delay circuit 13 is connected to the voltage conversion circuit 11 and the reference delay circuit 12. It is configured to delay the positive electrode differential voltage multiple times, each time for a first duration, and record the first number of delays of the positive electrode differential voltage when the trigger signal is received, and output a first code based on the first number; wherein, the first duration is inversely proportional to the positive electrode differential voltage.
[0031] The negative electrode delay circuit 14 is connected to the voltage conversion circuit 11 and the reference delay circuit 12. It is configured to delay the negative electrode differential voltage multiple times, each time for a second duration, and record the second number of times the negative electrode differential voltage is delayed when the trigger signal is received, and output a second code based on the second number; wherein, the second duration is inversely proportional to the negative electrode differential voltage.
[0032] The decoding circuit 15 is connected to the positive delay circuit 13 and the negative delay circuit 14, and is configured to decode the first code and the second code to output the sampled code.
[0033] like Figure 2 As shown, the reference delay circuit 12 includes a first delay chain circuit 121, which includes a preset number of first delay units connected in sequence; the preset number of times is equal to the preset number; the preset number is N.
[0034] Multiple first delay units are configured to sequentially delay the transmission of the reference voltage according to the start signal, and output a trigger signal when the delay transmission is completed, with each delay having a preset duration.
[0035] By using multiple first delay units, the reference voltage is delayed a preset number of times.
[0036] In specific implementation, the first delay unit is configured to delay the transmission of the reference voltage according to the start signal;
[0037] The (k+1)th first delay unit is connected to the kth first delay unit and configured to delay the transmission of the reference voltage output by the kth first delay unit; there are a total of N first delay units, where k is a natural number less than N-2;
[0038] The Nth first delay unit is connected to the (N-1)th first delay unit and is configured to delay the transmission of the reference voltage output by the (N-1)th first delay unit to output a trigger signal.
[0039] like Figure 3As shown, the positive delay circuit 13 includes a second delay chain circuit 131 and a first logic unit 132;
[0040] The second delay chain circuit 131 includes a plurality of second delay units connected in sequence;
[0041] Multiple second delay units are connected to voltage conversion circuit 11 and configured to sequentially delay the transmission of positive differential voltage according to the start signal to output multiple positive sub-codes, with each second delay unit delaying for a first duration;
[0042] The first logic unit 132 is connected to multiple second delay units and decoding circuit 15, configured to output according to multiple positive sub-codes.
[0043] Multiple second delay units sequentially delay the transmission of the positive differential voltage according to the start signal to output multiple positive sub-codes, and the first logic unit 132 records the multiple positive sub-codes when the trigger signal is received to generate the first code, thereby recording the number of second delay units that have transmitted the positive differential voltage.
[0044] In specific implementation, the first logic unit 132 outputs the first code according to the number of positive sub-codes, and the value of the first code is equal to the number of positive sub-codes.
[0045] In specific implementation, the first second delay unit is connected to the voltage conversion circuit 11 and is configured to delay the transmission of the positive differential voltage according to the start signal to output the first positive sub-code;
[0046] The (i+1)th second delay unit is connected to the ith second delay unit and is configured to delay the transmission of the positive differential voltage output by the ith second delay unit to output the (i+1)th positive sub-code; there are a second delay units in total, where i is a natural number less than or equal to a.
[0047] like Figure 4 As shown, the negative delay circuit 14 includes a third delay chain circuit 141 and a second logic unit 142.
[0048] The third delay chain circuit 141 includes a plurality of third delay units connected in sequence;
[0049] Multiple third delay units are connected to voltage conversion circuit 11 and configured to sequentially delay the transmission of negative differential voltage according to the start signal to output multiple negative sub-codes, with each third delay unit delaying for a second duration.
[0050] The second logic unit 142 is connected to multiple third delay units and decoding circuit 15, and is configured to record multiple negative sub-codes when a trigger signal is received, and output a second code based on the multiple negative sub-codes.
[0051] Multiple third delay units sequentially transmit the negative differential voltage according to the start signal to output multiple negative sub-codes. The second logic unit 142 records the multiple negative sub-codes when the trigger signal is received to generate a second code, thereby recording the number of third delay units that have transmitted the negative differential voltage.
[0052] In specific implementation, the second logic unit 142 outputs the second code based on the number of multiple negative sub-codes, specifically by outputting the second code based on the number of multiple negative sub-codes, and the value of the second code is equal to the number of multiple negative sub-codes.
[0053] In specific implementation, the first third delay unit is connected to the voltage conversion circuit 11 and is configured to delay the transmission of the negative differential voltage according to the start signal to output the first negative sub-code;
[0054] The (j+1)th third delay unit is connected to the jth third delay unit and is configured to delay the transmission of the negative differential voltage output by the jth third delay unit to output the (j+1)th negative sub-code; there are a total of b third delay units, where j is a natural number less than or equal to b.
[0055] The first delay unit, the first second delay unit, and the first third delay unit can all include a start delay component, and the (k+1)th first delay unit, the Nth first delay unit, the (i+1)th second delay unit, and the (j+1)th third delay unit can all include a follow-up delay component.
[0056] The start signal can be output by the logic control circuit. After the conversion process of the analog-to-digital converter is completed, the logic control circuit receives the first control signal REF_out_shutdown1 output by the positive delay circuit 13 and the second control signal REF_out_shutdown1 output by the negative delay circuit 14. The logic control circuit issues the first shutdown signal shutdown1 to the positive delay circuit 13 and the second shutdown signal shutdown2 to the negative delay circuit 14, and the conversion process stops to prepare for the next conversion.
[0057] As an example, and not a limitation, the preset number of iterations N is 2. n n is a natural number; for example, n can be 6.
[0058] like Figure 5 As shown, the decoding circuit 15 includes a first adder 151, a first subtractor 152, and a second adder 153.
[0059] The first adder 151 is connected to the positive delay circuit 13 and is configured to add 2 to the code value of the first encoding. n To obtain the third code;
[0060] The first subtractor 152 is connected to the negative delay circuit 14 and is configured to... n Calculate the complement of the code value of the second code to obtain the fourth code;
[0061] The second adder 153 is connected to the first adder 151 and the first subtractor 152. It is configured to calculate the sum of the code values of the third code and the fourth code to obtain the fifth code, and output the high n bits of the fifth code as the sampled code.
[0062] The average of the values of the first code and the second code is calculated by the first adder 151, the first subtractor 152 and the second adder 153, thereby obtaining the sampling code of the voltage to be sampled.
[0063] like Figure 6 As shown, the analog-to-digital conversion circuit also includes a voltage generation circuit 16.
[0064] The voltage generation circuit 16 is connected to the reference delay circuit 12 and is configured to convert the supply voltage into a reference voltage.
[0065] The voltage to be sampled is a differential voltage, which includes a positive sampling voltage and a negative sampling voltage. The voltage conversion circuit 11 includes a first voltage conversion component and a second voltage conversion component.
[0066] The first voltage conversion component is connected to the positive delay circuit 13 and is configured to convert the positive sampling voltage into a positive differential voltage.
[0067] The second voltage conversion component is connected to the negative delay circuit 14 and is configured to convert the negative sampled voltage into a negative differential voltage.
[0068] By way of example and not limitation, the voltage generation circuit 16, the first voltage conversion component, and the second voltage conversion component may all include a voltage conversion module.
[0069] Figure 7 This invention illustrates an example circuit structure of a voltage conversion module in an analog-to-digital converter circuit provided in an embodiment of the present invention. Figure 8 This invention illustrates an example circuit structure of the startup delay component in the analog-to-digital converter circuit provided in an embodiment of the present invention. Figure 9 An example circuit structure of a follow-up delay component in an analog-to-digital converter circuit provided by an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:
[0070] exist Figure 7In the process, the voltage conversion module includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a first NMOS transistor M4, a second NMOS transistor M5, a third NMOS transistor M6, and a first resistor R1.
[0071] The source of the first PMOS transistor M1 and the source of the second PMOS transistor M2 are connected to the first power supply VAA. The drain and gate of the first PMOS transistor M1 and the gate of the second PMOS transistor M2 together serve as the mirror bias current Ibias input terminal of the voltage conversion module. The drain of the second PMOS transistor M2 is connected to the drain of the third PMOS transistor M3 and the first end of the first resistor R1. The gate of the third PMOS transistor M3 serves as the power supply voltage input terminal, the positive sampling voltage input terminal, or the negative sampling voltage input terminal of the voltage conversion module. The source of transistor M3, the drain of the second NMOS transistor M5, the drain of the third NMOS transistor M6, and the gate of the third NMOS transistor M6 together serve as the reference voltage output terminal, the positive differential voltage output terminal, or the negative differential voltage output terminal of the voltage conversion module. The drain of the first NMOS transistor M4, the gate of the first NMOS transistor M4, and the gate of the second NMOS transistor M5 serve as the current extraction input terminal of the voltage conversion module. The second end of the first resistor R1, the source of the first NMOS transistor M4, the source of the second NMOS transistor M5, and the source of the third NMOS transistor M6 are all connected to the power supply ground.
[0072] The first PMOS transistor M1 and the second PMOS transistor M2 form a PMOS current mirror to reflect the bias current Ibias. The third PMOS transistor M3 is biased by the PMOS current mirror and connected to the first resistor R1 to form a common-source voltage-to-current converter with active-stage negative feedback. The first NMOS transistor M4 and the second NMOS transistor M5 form an NMOS current mirror to extract the current I_shunt. The drain of the third NMOS transistor M6 outputs a signal. The bias current I_vin / I_vref is converted into an output voltage (reference voltage, positive differential voltage, or negative differential voltage) at the drain of the third NMOS transistor M6. The input voltage and the output voltage of the voltage conversion module satisfy the following relationship:
[0073]
[0074] Among them, V in+ The positive differential voltage, V in- The negative differential voltage, V sample+ The positive sampling voltage, V sample- The positive sampling voltage, V ref V is the reference voltage. cmR1 is the supply voltage, gm6 is the resistance of the first resistor, and gm6 is the transconductance of the third NMOS transistor M6. The voltage conversion module converts the input voltage into a bias current I_vin and outputs the output voltage Vin+ / Vin- / Vref controlled by the converted bias current I_vin.
[0075] exist Figure 8 In the process, the startup delay component includes a first capacitor C1, a fourth PMOS transistor M7, a fourth NMOS transistor M8, a fifth NMOS transistor M9, and a first inverter INV1.
[0076] The drain of the fourth PMOS transistor M7 is connected to the second power supply VBB. The gates of the fourth PMOS transistor M7 and the fourth NMOS transistor M8 serve as the start signal input terminals of the start delay component. The source of the fourth PMOS transistor M7 is connected to the drain of the fourth NMOS transistor M8, the first terminal of the first capacitor C1, and the input terminal of the first inverter INV1. The source of the fourth NMOS transistor M8 is connected to the drain of the fifth NMOS transistor M9. The second terminal of the first capacitor C1 and the source of the fifth NMOS transistor M9 are connected to the power supply ground.
[0077] In the first delay unit of the reference delay circuit 12, the gate of the fifth NMOS transistor M9 serves as the positive differential signal input terminal of the start-up delay component, and the output terminal of the first inverter INV1 serves as the positive differential voltage output terminal and the first positive sub-code output terminal of the start-up delay component, which is connected to the input terminal of the second delay unit.
[0078] In the first second delay unit of the positive delay circuit 13, the gate of the fifth NMOS transistor M9 serves as the positive differential voltage input terminal of the startup delay component, and the output terminal of the first inverter INV1 serves as the reference voltage output terminal of the startup delay component, which is connected to the input terminal of the second first delay unit.
[0079] In the first third delay unit of the negative delay circuit 14, the gate of the fifth NMOS transistor M9 serves as the negative differential voltage input terminal of the startup delay component, and the output terminal of the first inverter INV1 serves as the negative differential voltage output terminal and the first negative sub-code output terminal of the startup delay component, which is connected to the input terminal of the second third delay unit.
[0080] The bias current of the fifth NMOS transistor M9 is controlled by the input voltage, and the change in bias current controls the delay of the first inverter INV1.
[0081] exist Figure 9 In the middle, the subsequent delay components include the second capacitor C2, the sixth NMOS transistor M10, and the second inverter INV2.
[0082] The drain of the sixth NMOS transistor M10, the first terminal of the second capacitor C2, and the input terminal of the second inverter INV2 are connected to the third power supply VCC. The second terminal of the second capacitor C2 and the source of the sixth NMOS transistor M10 are connected to the power supply ground.
[0083] In the (k+1)th first delay unit of the reference delay circuit 12, the gate of the sixth NMOS transistor M10 serves as the reference voltage input terminal of the subsequent delay component, and the output terminal of the second inverter INV2 serves as the reference voltage output terminal of the subsequent delay component, connected to the input terminal of the (k+2)th second delay unit. In the Nth first delay unit of the reference delay circuit 12, the gate of the sixth NMOS transistor M10 serves as the reference voltage input terminal of the subsequent delay component, and the output terminal of the second inverter INV2 serves as the trigger signal output terminal of the subsequent delay component, connected to the input terminals of the positive delay circuit 13 and the negative delay circuit 14.
[0084] In the (i+1)th second delay unit of the positive delay circuit 13, the gate of the sixth NMOS transistor M10 serves as the positive differential voltage input terminal of the subsequent delay component, and the output terminal of the second inverter INV2 serves as the positive differential voltage output terminal of the subsequent delay component and the (i+1)th positive subcode output terminal, which is connected to the input terminal of the (i+2)th second delay unit.
[0085] In the (i+1)th third delay unit of the negative delay circuit 14, the gate of the sixth NMOS transistor M10 serves as the negative differential voltage input terminal of the subsequent delay component, and the output terminal of the second inverter INV2 serves as the negative differential voltage output terminal of the subsequent delay component and the (i+1)th negative sub-code output terminal, which is connected to the input terminal of the (i+2)th third delay unit.
[0086] The following is based on the working principle. Figure 8 and Figure 9 Further explanation is provided below:
[0087] exist Figure 8 and Figure 9 In this context, the conversion process from voltage to current is I(V) ref )=k*V ref ,I(V in+ )=k*V in+ ,I(V in- )=k*V in- , Where C is the load capacitance of the subsequent inverter (either the first capacitor C1 or the second capacitor C2), V T I(V) represents the threshold voltage of the subsequent inverter (either the first inverter INV1 or the second inverter INV2), and T0 represents the inherent delay of either the first inverter INV1 or the second inverter INV2, which is very small and can be ignored. ref() is controlled by the reference voltage V ref The bias current. I(V) in+ () is controlled by the positive differential voltage V in+ Bias current, I(V) in- () is controlled by the negative differential voltage V in- The bias current is denoted by D, and D represents the delay of the first delay unit, the third delay unit, and the second delay unit.
[0088] The delay (preset duration) D of the first delay unit and the delay T of the first delay chain circuit 121 are also specified. S =N*D ref The delay (first duration) of the second delay unit is... The delay (second duration) of the third delay unit is
[0089] code1*D vin+ =code2*D vin- =N*D ref =T S
[0090] Here, code1 is the value of the first encoding, and code2 is the value of the second encoding.
[0091] Since T0 can be ignored, get V can be quantified in+ and V in- .
[0092] This invention also provides a digital power chip, which includes the analog-to-digital conversion circuit described above.
[0093] This invention embodiment converts the voltage to be sampled into a positive differential voltage and a negative differential voltage using a voltage conversion circuit; a reference delay circuit delays the reference voltage a preset number of times, each delay being a preset duration, and outputs a trigger signal upon completion of the delay; wherein the preset duration is inversely proportional to the reference voltage; the positive delay circuit delays the positive differential voltage multiple times, each delaying for a first duration, and records the first number of delays of the positive differential voltage upon receiving the trigger signal, and outputs a first code based on the first number; wherein the first duration is inversely proportional to the positive differential voltage; the negative delay circuit delays the negative differential voltage multiple times, each delaying for a second duration, and records the second number of delays of the negative differential voltage upon receiving the trigger signal, and outputs a second code based on the second number; wherein the second duration is inversely proportional to the negative differential voltage; the decoding circuit decodes the first code... The first and second codes are decoded to output the sampled code. Since the first duration, the second duration, and the preset duration are all inversely proportional to the delayed voltage, and the first code corresponds to the first number of delays of the positive differential voltage, and the second code corresponds to the second number of delays of the negative differential voltage, the ratio of the positive differential voltage to the reference voltage is equal to the ratio of the first code to the preset number, and the ratio of the negative differential voltage to the reference voltage is equal to the ratio of the second code to the preset number. The sampled code can be decoded from the first code and the second code. Thus, the digital-to-analog converter circuit consists of a decoding circuit and a delay circuit. The speed is entirely determined by the delay. It can achieve high speed and high accuracy with a very small area and low power consumption. It can also make full use of the advantages brought by the reduction of process feature size, reduce the area and increase the speed, and adapt to low power consumption application scenarios.
[0094] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0095] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. An analog-to-digital conversion circuit, characterized by The application relates to a voltage sampling circuit. The voltage sampling circuit comprises: The reference delay circuit is configured to delay a reference voltage for a preset number of times, each time for a preset time length, and output a trigger signal when the delay is completed; wherein the preset time length is inversely proportional to the reference voltage; and the preset number of times is 2 n ; n is a natural number; a voltage conversion circuit configured to convert a voltage to be sampled into a positive differential voltage and a negative differential voltage; a positive delay circuit connected with the voltage conversion circuit and the reference delay circuit, configured to delay the positive differential voltage for a plurality of times, each time for a first time length, record a first number of times of delaying the positive differential voltage when the trigger signal is received, and output a first code according to the first number of times; wherein the first time length is inversely proportional to the positive differential voltage; a negative delay circuit connected with the voltage conversion circuit and the reference delay circuit, configured to delay the negative differential voltage for a plurality of times, each time for a second time length, record a second number of times of delaying the negative differential voltage when the trigger signal is received, and output a second code according to the second number of times; wherein the second time length is inversely proportional to the negative differential voltage; a decoding circuit connected with the positive delay circuit and the negative delay circuit, configured to decode the first code and the second code to output a sampling code; the decoding circuit is configured to calculate the average of the value of the first code and the value of the second code, thereby obtaining the sampling code of the voltage to be sampled; the reference delay circuit comprises a first delay chain circuit, and the first delay chain circuit comprises a plurality of first delay units connected in sequence; the preset number of times is equal to the preset number of first delay units; 2. The analog-to-digital conversion circuit of claim 1, wherein, the plurality of first delay units are configured to sequentially delay and transmit the reference voltage according to a start signal, and output the trigger signal when the delay and transmission are completed; each first delay unit delays for the preset time length. the first first delay unit is configured to delay and transmit the reference voltage according to the start signal; the i+1th first delay unit is connected with the ith first delay unit and is configured to delay and transmit the reference voltage output by the ith first delay unit; there are N first delay units in total, and i is a natural number less than N-2; 3. The analog-to-digital conversion circuit of claim 1, wherein, the Nth first delay unit is connected with the N-1th first delay unit and is configured to delay and transmit the reference voltage output by the N-1th first delay unit to output the trigger signal. the positive delay circuit comprises a second delay chain circuit and a first logic unit; the second delay chain circuit comprises a plurality of second delay units connected in sequence; the plurality of second delay units are connected with the voltage conversion circuit and are configured to sequentially delay and transmit the positive differential voltage according to the start signal to output a plurality of positive sub-codes; each second delay unit delays for the first time length; 4. The analog-to-digital conversion circuit of claim 3, wherein, the first logic unit is connected with the plurality of second delay units and the decoding circuit, and is configured to record the plurality of positive sub-codes when the trigger signal is received, and output the first code according to the plurality of positive sub-codes. the first second delay unit is connected with the voltage conversion circuit and is configured to delay and transmit the positive differential voltage according to the start signal to output a first positive sub-code; The i+1th second delay unit is connected with the ith second delay unit and configured to delay and transmit the positive differential voltage output by the ith second delay unit to output an i+1th positive sub-code; the second delay units are a total of a, and i is a natural number less than or equal to a.
5. The analog-to-digital conversion circuit of claim 1, wherein, The negative delay circuit comprises a third delay chain circuit and a second logic unit; The third delay chain circuit comprises a plurality of third delay units connected in sequence; The plurality of third delay units are connected with the voltage conversion circuit and configured to delay and transmit the negative differential voltage according to the start signal to output a plurality of negative sub-codes, and each third delay unit delays for the second time length; The second logic unit is connected with the plurality of third delay units and the decoding circuit and configured to record the plurality of negative sub-codes when the trigger signal is received, and output a second code according to the plurality of negative sub-codes.
6. The analog-to-digital conversion circuit of claim 5, wherein, The 1st third delay unit is connected with the voltage conversion circuit and configured to delay and transmit the negative differential voltage according to the start signal to output a 1st negative sub-code; The j+1th third delay unit is connected with the jth third delay unit and configured to delay and transmit the negative differential voltage output by the jth third delay unit to output a j+1th negative sub-code; the third delay units are a total of b, and j is a natural number less than or equal to b.
7. The analog-to-digital conversion circuit of claim 1, wherein, The decoding circuit comprises: a first adder connected to the positive delay circuit and configured to add 2 to the first encoded code value n to obtain a third encoding; A first subtractor, connected with the negative delay circuit, is configured to subtract the second code value from 2 n compute the complement of the second code value to obtain a fourth code; The second adder is connected with the first adder and the first subtractor and configured to calculate the sum of the code value of the third code and the code value of the fourth code to obtain a fifth code, and output the fifth code with high n bits as the sampling code.
8. The analog-to-digital conversion circuit of claim 1, wherein, Further comprising: The voltage generation circuit is connected with the reference delay circuit and configured to convert a supply voltage into the reference voltage.
9. A digital power supply chip, characterized by The digital power supply chip comprises the analog-digital conversion circuit according to any one of claims 1 to 8.
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