Gaussian surface construction method for integrated circuit interconnect capacitance extraction

Abstract

The present application discloses a Gaussian surface establishment method for integrated circuit interconnect capacitance extraction, comprising: obtaining the interconnect capacitance extraction result based on the grid division of the three-dimensional simulation area in the Gaussian surface in the main line network and the spatial data information of the conductor block information contained therein, controlling each conductor block in the main line network to expand outward to obtain the corresponding query cuboid, obtaining the conductor blocks contained in all spatial grids intersecting with each query cuboid to obtain a candidate conductor list, if the candidate conductor list is empty, then controlling the corresponding conductor block to expand outward with half of the minimum distance from the conductor block corresponding to the query cuboid to the outer boundary of the above-mentioned intersecting spatial grid to obtain the corresponding Gaussian surface, otherwise, controlling the corresponding conductor block to expand outward with half of the minimum distance from the conductor block corresponding to the query cuboid to the conductor block in the candidate conductor list to obtain the corresponding Gaussian surface. In this way, efficient processing of establishing Gaussian surfaces for conductor blocks in the main line network is achieved.

Description

Technical Field

[0001] The present application relates to the field of VLSI (Very Large Scale Integrated Circuits) physical design and verification, and in particular to a Gaussian surface establishment method for extracting interconnect capacitance of integrated circuits. Background Art

[0002] The integrated circuit design process begins with a functional description. Then, through logic design and layout design, a layout is created that describes the semiconductor process dimensions and structure. Finally, layout verification is performed, using computer software simulation to verify whether the design meets the requirements. If it does, the next step in manufacturing proceeds. Otherwise, the logic design and layout design steps are returned to make necessary corrections. A key step in layout verification is interconnect parasitic parameter extraction.

[0003] With the advancement of integrated circuit manufacturing technology, circuit scale continues to increase and feature sizes continue to shrink. Many chips today contain hundreds of millions of devices. However, the parasitic effects of interconnects in integrated circuits cause the impact of interconnects on circuit delays to exceed the impact of devices on circuit delays. Therefore, it is necessary to accurately calculate parameters such as the capacitance and resistance of interconnects to ensure the correctness and effectiveness of circuit simulation and verification. To improve calculation accuracy, the capacitance parameters between interconnects require a three-dimensional extraction method, that is, a three-dimensional field solver is used for solution. The calculation of field solvers is often time-consuming, and research on optimizing and accelerating their algorithms is of great significance.

[0004] Among the field solver methods for extracting integrated circuit capacitance parameters, the random walk capacitance extraction algorithm is a relatively popular method. This method is different from the conventional finite difference method, finite element method, and boundary element method. It does not require solving a system of linear equations. The main step in the calculation is to randomly select points in space (the process of obtaining a series of points is vividly called "random walk"). Figure 1 As shown in , each random walk starts from a Gaussian surface around a pre-specified conductor (called the main conductor), and then constructs a largest cube (called the "transfer cube") that does not overlap with the conductor with the current point as the center. The next point is randomly picked and falls on the surface of the transfer cube (such as Figure 1 S in (1) and S (2) ). This process is repeated until the position of the random point reaches the conductor surface, at which point a random walk ends. To calculate a conductor (for example Figure 1 The capacitance value between conductor i) and all other conductors in the equation needs to be determined by performing at least tens of thousands of random walks.

[0005] In their 2013 papers, "RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects" (Volume 3) and "Efficient space management techniques for large-scale interconnect capacitance extraction with floating random walks" (Volume 10), published in the international journal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the applicant disclosed a fast random walk method based on variance reduction and a space management technique. The former uses importance sampling and stratified sampling techniques to change the probability distribution required for random sampling on Gaussian surfaces and transfer cube surfaces, thereby reducing the variance of the weight sequence used to calculate the capacitance value. This reduces the number of random walks by several times while maintaining the same accuracy, thereby improving the calculation speed. The latter includes a space management data structure established based on the geometric information (position and size) of the conductor blocks in the calculated three-dimensional structure. This structure can be used to quickly determine the conductor closest to the current walk position during the random walk capacitance extraction process, thereby accelerating the construction of the transfer cube and the overall calculation speed.

[0006] While existing work has accelerated the computational speed of random walk capacitance extraction algorithms, they can only calculate the capacitance between a single, isolated conductor block (a single rectangular block in three-dimensional space) and other conductors. In actual integrated circuit interconnect structures, multiple conductor blocks are connected to form a signal path (generally called a "net"). The capacitance between the entire net and other conductors or nets must be calculated to analyze the delay time of the signal propagating along this net. Figure 2 A 3D interconnect structure considered in the integrated circuit capacitance extraction problem is shown, which includes a single 3D conductor block and a network formed by connecting multiple conductor blocks in sequence.

[0007] Therefore, when extracting the interconnect capacitance of an integrated circuit, it is necessary to first establish a Gaussian surface that only surrounds the specified line network (i.e., the main line network) and does not intersect with other lines or conductors, and then randomly select points on it.

[0008] In an invention patent filed by the applicant in 2014, “Method and system for sampling Gaussian surfaces of wire meshes for extracting interconnect capacitance of integrated circuits”, application number: 201410016439.3, a virtual Gaussian surface sampling technology is disclosed. It first establishes a Gaussian surface for each conductor block that makes up the main conductor wire mesh, and then performs random sampling on their collection, and achieves the effect of sampling directly on the Gaussian surface established for the entire wire mesh through appropriate rejection sampling. However, in actual integrated circuits, the interconnect lines are very densely distributed and the number of conductor blocks is huge. A wire mesh often includes dozens or even thousands of conductor blocks. How to efficiently establish a Gaussian surface for each conductor block in the main wire mesh is a difficult problem. Summary of the Invention

[0009] The present application provides a Gaussian surface establishment method for integrated circuit interconnect capacitance extraction, which can achieve efficient processing of large-scale layouts containing a large number of conductor blocks. The method still follows the virtual Gaussian surface sampling technology, but has innovations in establishing the Gaussian surface of each conductor block (called a "block Gaussian surface"). It can efficiently process main line networks containing thousands of conductor blocks, hundreds of times faster than the original method.

[0010] The present invention provides a method for establishing a Gaussian surface for extracting interconnect capacitance of an integrated circuit, including the following steps:

[0011] Acquire spatial data information required for establishing the main line network Gaussian surface, wherein the spatial data information is the result of meshing the three-dimensional simulation area based on which the interconnect capacitance extraction is based, and the conductor block information contained in each mesh;

[0012] Controlling each conductor block in the main line network to expand outwards with a first preset length to obtain a query cuboid corresponding to each conductor block;

[0013] For each query cuboid, obtain the conductor blocks contained in all spatial grids intersecting with it to form a candidate conductor list; if the candidate list is empty, obtain the minimum distance between the conductor block corresponding to the query cuboid and the outer boundaries of all spatial grids intersecting with the corresponding query cuboid, and control the conductor block corresponding to the query cuboid to expand outward with half of the minimum distance to obtain the Gaussian surface corresponding to the conductor block corresponding to the query cuboid; otherwise, obtain the minimum distance between the conductor block corresponding to the query cuboid and the conductor blocks in the candidate conductor list, and control the conductor block corresponding to the query cuboid to expand outward with half of the minimum distance to obtain the Gaussian surface corresponding to the conductor block corresponding to the query cuboid.

[0014] According to one embodiment of the present application, generating the spatial data information required to establish the Gaussian surface includes:

[0015] Uniformly dividing the three-dimensional simulation area to be processed and containing the interconnected conductor blocks into spatial grids to obtain the plurality of spatial grids;

[0016] Record the conductor blocks contained in or intersecting each spatial grid and obtain a list of conductors corresponding to each grid.

[0017] According to one embodiment of the present application, the distance between two conductor blocks is calculated as follows:

[0018] dist(B1,B2)=max{d x ,d y ,d z};

[0019] Among them, B1 is the first conductor block, B2 is the second conductor block, d x is the distance between the first conductor block and the second conductor block in the x direction, d y , is the distance between the first conductor block and the second conductor block in the y direction, d z , is the distance between the first conductor block and the second conductor block in the z direction.

[0020] According to one embodiment of the present application, the distance between the first conductor block and the second conductor block in the x-direction is calculated as follows:

[0021] d x =max{x min (B1)-x max (B2),x min (B2)-x max (B1)}

[0022] where x min (B1) and x max (B1) are the minimum x-coordinate and the maximum x-coordinate of the first conductor block B1, respectively;

[0023] The distance between the first conductor block and the second conductor block in the y direction is calculated as follows:

[0024] d y =max{y min (B1)-y max (B2),y min (B2)-y max (B1)}

[0025] Among them, y min (B1) and y max (B1) are the minimum y-coordinate and the maximum y-coordinate of the first conductor block B1;

[0026] The distance between the first conductor block and the second conductor block in the z direction is calculated as follows:

[0027] d z =max{z min (B1)-z max (B2),z min (B2)-z max (B1)}

[0028] Among them, z min (B1) and z max ( B1 ) are the minimum z coordinate and the maximum z coordinate of the first conductor block B1 , respectively.

[0029] According to the Gaussian surface establishment method for integrated circuit interconnect capacitance extraction according to the embodiment of the present application, the interconnect capacitance extraction result based on the grid division of the three-dimensional simulation area in the Gaussian surface of the main line network and the spatial data information of the conductor block information contained therein are obtained, and each conductor block in the main line network is controlled to expand outward to obtain the corresponding query cuboid. For each query cuboid, the conductor blocks contained in all spatial grids intersecting with it are obtained to obtain a candidate conductor list. If the candidate conductor list is empty, the corresponding conductor block is controlled to expand outward by half of the minimum distance between the conductor block corresponding to the query cuboid and the outer boundary of the intersecting spatial grid to obtain the corresponding Gaussian surface. Otherwise, the corresponding conductor block is controlled to expand outward by half of the minimum distance between the conductor block corresponding to the query cuboid and the conductor blocks in the candidate conductor list to obtain the corresponding Gaussian surface. In this way, high-efficiency processing of large-scale layouts containing a large number of conductor blocks is achieved, while still following the virtual Gaussian surface sampling technology, but with innovation in establishing the Gaussian surface of each conductor block (called "block Gaussian surface"), which can efficiently process main line networks containing thousands of conductor blocks, hundreds of times faster than the original method.

[0030] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1 A two-dimensional schematic diagram of the random walk capacitance extraction process;

[0033] Figure 2 Schematic diagram of the three-dimensional conductor blocks and wire nets considered in the extraction of interconnect capacitance of concentrated circuits;

[0034] Figure 3 A flowchart of a method for establishing a Gaussian surface for extracting interconnect capacitance of an integrated circuit according to an embodiment of the present application;

[0035] Figure 4 A two-dimensional schematic diagram of a uniform spatial grid within a simulation area provided according to one embodiment of the present application;

[0036] Figure 5 This is a schematic diagram of a conductor block in a simulation area expanding outward to a query cuboid according to one embodiment of the present application. DETAILED DESCRIPTION

[0037] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0038] The following describes a Gaussian surface establishment method for integrated circuit interconnect capacitance extraction according to an embodiment of the present application with reference to the accompanying drawings. In response to the problem mentioned in the background technology center that the parasitic effect of the interconnect in the integrated circuit causes the interconnect to have an excessive impact on the circuit delay, resulting in low efficiency and low accuracy in capacitance and resistance calculation when establishing a Gaussian surface for each conductor block in the main line network, the present application provides a Gaussian surface establishment method for integrated circuit interconnect capacitance extraction. In this method, the interconnect capacitance extraction result based on the grid division of the three-dimensional simulation area in the Gaussian surface in the main line network and the spatial data information of the conductor block information contained therein are obtained, each conductor block in the main line network is controlled to expand outward to obtain a corresponding query cuboid, and for each query cuboid, the conductor blocks contained in all spatial grids intersecting with it are obtained to obtain a candidate conductor list. If the candidate conductor list is empty, the corresponding conductor block is controlled to expand outward by half of the minimum distance from the conductor block corresponding to the query cuboid to the outer boundary of the intersecting spatial grid to obtain the corresponding Gaussian surface. Otherwise, the corresponding conductor block is controlled to expand outward by half of the minimum distance from the conductor block corresponding to the query cuboid to the conductor block in the candidate conductor list to obtain the corresponding Gaussian surface. This enables efficient processing of large-scale layouts containing a large number of conductor blocks. The method still follows the virtual Gaussian surface sampling technology, but has innovations in establishing the Gaussian surfaces of each conductor block (called "block Gaussian surfaces"). It can efficiently process main line networks containing tens of thousands of conductor blocks, hundreds of times faster than the original method.

[0039] Specifically, Figure 3 A flowchart of a method for establishing a Gaussian surface for extracting interconnect capacitance of integrated circuits provided in an embodiment of the present application.

[0040] like Figure 3 As shown, the Gaussian surface establishment method for integrated circuit interconnect capacitance extraction includes the following steps:

[0041] In step S301 , spatial data information required for establishing the main line network Gaussian surface is obtained, wherein the spatial data information is the result of meshing the three-dimensional simulation area based on which the interconnect capacitance extraction is based, and the conductor block information contained in each mesh.

[0042] Furthermore, in some embodiments, generating spatial data information required to establish a Gaussian surface includes: uniformly dividing the three-dimensional simulation area to be processed and containing interconnected conductor blocks into a spatial grid to obtain multiple spatial grids; recording the conductor blocks contained in or intersecting in each spatial grid to obtain a conductor list corresponding to each grid.

[0043] Specifically, according to the actual situation, the three-dimensional interconnected conductor blocks in the integrated circuit can be considered as rectangular parallelepipeds, and all of its faces are parallel to the coordinate plane of the three-dimensional rectangular coordinate system. In addition, multiple main line networks can be set in the capacitance extraction. Assume that the main line network considered is A, which includes N b Conductor block B i ,(i=1,2,...,N b ), the three-dimensional shape corresponding to A is the union of these conductor blocks. For each conductor block B of A i , respectively establish its Gaussian surface G i (called block Gaussian surface), G i Contains B i , and does not contain other conductors outside the wire mesh A, nor does it overlap or stick to them.

[0044] Furthermore, when establishing the Gaussian surface, the embodiment of the present application can first evenly divide the three-dimensional simulation area to be processed in the main line network and containing interconnected conductors into a spatial grid to obtain multiple spatial grids, and then record the conductor blocks contained in or intersected by each spatial grid to form a conductor list, such as Figure 4 As shown, the conductor list of the spatial grid g1 contains conductor blocks B1 and B2, while the conductor list of the spatial grid g2 only contains conductor block B2, thereby obtaining the spatial data information required for Gaussian surface establishment, thereby greatly reducing the computational complexity of the subsequent Gaussian surface establishment process.

[0045] In step S302, each conductor block in the main line network is controlled to expand outwards with a first preset length to obtain a query cuboid corresponding to each conductor block.

[0046] Specifically, in the embodiment of the present application, the candidate list L can be set to an empty set first, and an extension distance d can be set. e , which is the first preset length, and its value can be the minimum side length of the space grid. For each conductor block B in each main line network A i , set the candidate list L to an empty set, and set B i Expand outwards eThe length of the query cuboid Q is obtained, such as Figure 5 As shown, the conductor block B1 expands outwards e The query cuboid Q is obtained, and the spatial grid intersecting with Q only contains the conductor block C2.

[0047] In step S303, for each query cuboid, the conductor blocks contained in all spatial grids intersecting with it are obtained to form a candidate conductor list; if the candidate list is empty, the minimum distance between the conductor block corresponding to the query cuboid and the outer boundaries of all spatial grids intersecting with the corresponding query cuboid is obtained, and the conductor block corresponding to the query cuboid is controlled to expand outward with half of the minimum distance to obtain the Gaussian surface corresponding to the conductor block corresponding to the query cuboid; otherwise, the minimum distance between the conductor block corresponding to the query cuboid and the conductor blocks in the candidate conductor list is obtained, and the conductor block corresponding to the query cuboid is controlled to expand outward with half of the minimum distance to obtain the Gaussian surface corresponding to the conductor block corresponding to the query cuboid.

[0048] Specifically, the embodiment of the present application can obtain all spatial grids that intersect with the query cuboid Q, and put the conductors in their conductor lists into the candidate list L. If the candidate list L is an empty set, then obtain each conductor block B i The minimum value d1 among multiple distances of the outer boundaries of all spatial grids intersecting with the corresponding query cuboid Q, and controlling each conductor block to expand outward by d1 / 2, so as to obtain the Gaussian surface G corresponding to each conductor block i Otherwise, get each conductor block B i The minimum value d2 among multiple distances of the outer boundaries of all spatial grids intersecting with the corresponding query cuboid Q, and controlling each conductor block to expand outward by d2 / 2, so as to obtain the Gaussian surface G corresponding to each conductor block i .

[0049] It should be noted that the calculation formula for calculating the distance between two cuboids (i.e., conductor blocks) can be as follows:

[0050] dist(B1,B2)=max{d x ,d y ,d z};

[0051] Among them, B1 is the first conductor block, B2 is the second conductor block, d x is the distance between the first conductor block and the second conductor block in the x direction, d y , is the distance between the first conductor block and the second conductor block in the y direction, d z , is the distance between the first conductor block and the second conductor block in the z direction.

[0052] The distance between the first conductor block B1 and the second conductor block B2 in the x direction is calculated as follows:x =max{x min (B1)-x max (B2),x min (B2)-x max (B1)}, (x min (B1) and x max (B1) are the minimum x-coordinate and the maximum x-coordinate of the first conductor block B1, respectively);

[0053] The distance between the first conductor block B1 and the second conductor block B2 in the y direction is calculated as follows:

[0054] d y =max{y min (B1)-y max (B2),y min (B2)-y max (B1)},(y min (B1) and y max (B1) are the minimum y-coordinate and the maximum y-coordinate of the first conductor block B1, respectively);

[0055] The distance between the first conductor block B1 and the second conductor block B2 in the z direction is calculated as follows:

[0056] d z =max{z min (B1)-z max (B2),z min (B2)-z max (B1)},(z min (B1) and z max ( B1 ) are the minimum z coordinate and the maximum z coordinate of the first conductor block B1 , respectively).

[0057] To facilitate those skilled in the art to further understand the Gaussian surface establishment method for integrated circuit interconnect capacitance extraction according to the embodiment of the present application, it is described in detail below with reference to specific embodiments.

[0058] The Gaussian surface is established as follows:

[0059] (1) The three-dimensional simulation area to be processed, which contains interconnected conductors, is evenly divided into spatial grids. Then, for each spatial grid, the conductor blocks it contains or intersects are recorded to form a conductor list.

[0060] (2) Set an extension distance d e , its value can be the minimum side length of the space grid.

[0061] By executing the above two steps once, the spatial data information required for establishing the Gaussian surface can be obtained.

[0062] For each main line network A, the following steps are performed to establish its Gaussian surface:

[0063] (a) For each conductor block B of the main line network A i ;

[0064] 1) Set the candidate list L to an empty set;

[0065] 2) B i Expand outwards e The length of the query cuboid Q is obtained;

[0066] 3) For all spatial grids intersecting with Q, put the conductors in their conductor lists into the candidate list L;

[0067] 4) If L is an empty set, let d be B i The minimum distance to the outer boundary of all spatial grids intersecting with Q, then go to step 6;

[0068] 5) For each conductor C in L j , calculate it and B i The minimum value of these distances is d;

[0069] 6) d = d / 2;

[0070] 7) B i Expand outward by a distance of d to obtain its corresponding block Gaussian surface G i ;

[0071] (b) End.

[0072] Therefore, the spatial data information required for Gaussian surface establishment is generated through the above method, which greatly reduces the computational complexity of the subsequent Gaussian surface establishment process. For example, for an integrated circuit interconnect structure containing more than one million conductors, the algorithm running time is reduced from 335 seconds to 0.9 seconds when generating a Gaussian surface of a wire mesh containing 6,450 conductors, which is more than 300 times faster.

[0073] According to the Gaussian surface establishment method for integrated circuit interconnect capacitance extraction according to the embodiment of the present application, the interconnect capacitance extraction result based on the grid division of the three-dimensional simulation area in the Gaussian surface of the main line network and the spatial data information of the conductor block information contained therein are obtained, and each conductor block in the main line network is controlled to expand outward to obtain the corresponding query cuboid. For each query cuboid, the conductor blocks contained in all spatial grids intersecting with it are obtained to obtain a candidate conductor list. If the candidate conductor list is empty, the corresponding conductor block is controlled to expand outward by half of the minimum distance between the conductor block corresponding to the query cuboid and the outer boundary of the intersecting spatial grid to obtain the corresponding Gaussian surface. Otherwise, the corresponding conductor block is controlled to expand outward by half of the minimum distance between the conductor block corresponding to the query cuboid and the conductor blocks in the candidate conductor list to obtain the corresponding Gaussian surface. In this way, high-efficiency processing of large-scale layouts containing a large number of conductor blocks is achieved, while still following the virtual Gaussian surface sampling technology, but with innovation in establishing the Gaussian surface of each conductor block (called "block Gaussian surface"), which can efficiently process main line networks containing thousands of conductor blocks, hundreds of times faster than the original method.

[0074] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0076] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0077] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or N wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing it in a suitable manner if necessary, and then storing it in a computer memory.

[0078] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0079] Those skilled in the art will appreciate that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0080] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0081] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A Gaussian surface establishment method for extracting interconnect capacitance of integrated circuits, characterized in that: The following steps are involved: Acquire spatial data information required for establishing the main line network Gaussian surface, wherein the spatial data information is the result of meshing the three-dimensional simulation area based on which the interconnect capacitance extraction is based, and the conductor block information contained in each mesh; Controlling each conductor block in the main line network to expand outwards with a first preset length to obtain a query cuboid corresponding to each conductor block; For each query cuboid, the conductor blocks contained in all spatial grids intersecting with the query cuboid are obtained to form a candidate conductor list; if the candidate conductor list is empty, the minimum distance between the conductor block corresponding to the query cuboid and the outer boundaries of all spatial grids intersecting with the corresponding query cuboid is obtained, and the conductor block corresponding to the query cuboid is controlled to expand outward by half of the minimum distance to obtain a Gaussian surface corresponding to the conductor block corresponding to the query cuboid; otherwise, the minimum distance between the conductor block corresponding to the query cuboid and the conductor blocks in the candidate conductor list is obtained, and the conductor block corresponding to the query cuboid is controlled to expand outward by half of the minimum distance between the conductor block corresponding to the query cuboid and the conductor blocks in the candidate conductor list to obtain a Gaussian surface corresponding to the conductor block corresponding to the query cuboid.

2. The method according to claim 1, characterized in that The acquisition of spatial data information required for establishing the main line network Gaussian surface includes: Uniformly dividing the three-dimensional simulation area to be processed and containing the interconnected conductor blocks into spatial grids to obtain the plurality of spatial grids; Record the conductor blocks contained in or intersecting each spatial grid and obtain a list of conductors corresponding to each grid.

3. The method according to claim 1, characterized in that The distance between two conductor blocks is calculated as follows: dist(B1,B2)=max{d x ,d y ,d z }; Among them, B1 is the first conductor block, B2 is the second conductor block, d x is the distance between the first conductor block and the second conductor block in the x direction, d y , is the distance between the first conductor block and the second conductor block in the y direction, d z , is the distance between the first conductor block and the second conductor block in the z direction.

4. The method according to claim 3, characterized in that The distance between the first conductor block and the second conductor block in the x-direction is calculated as follows: d x =max{x min (B1)-x max (B2),x min (B2)-x max (B1)} Among them, x min (B1) and x max (B1) are the minimum x-coordinate and the maximum x-coordinate of the first conductor block B1, respectively; The distance between the first conductor block and the second conductor block in the y direction is calculated as follows: d y =max{and min (B1)-and max (B2),and min (B2)-and max (B1)} Among them, y min (B1) and y max (B1) are the minimum y-coordinate and the maximum y-coordinate of the first conductor block B1; The distance between the first conductor block and the second conductor block in the z direction is calculated as follows: d z =max{z min (B1)-z max (B2),z min (B2)-z max (B1)} Among them, z min (B1) and z max ( B1 ) are the minimum z coordinate and the maximum z coordinate of the first conductor block B1 , respectively.

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