System and method for controlling data strobe signals during read operations

Abstract

The present disclosure relates to systems and methods for controlling data strobe signals during read operations. An apparatus can include a first data strobe (DQS) output buffer (OB), a second DQS OB, and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal in response to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is provided to the DQS terminal.

Description

[0001] Related information of divisional application

[0002] This application is a divisional application. The parent application of this divisional application is Chinese Invention Patent Application Case No. 201980026141.1, entitled “System and Method for Controlling Data Strobe Signals During Read Operations,” filed on April 16, 2019. TECHNICAL FIELD

[0003] The present disclosure relates generally to memory devices, and more particularly to synchronous memory devices and techniques for controlling data strobe signals during read operations. BACKGROUND

[0004] This section is intended to introduce the reader to various aspects of art that can be related to various aspects of the present application that are described and / or claimed below. This discussion is believed to be helpful in providing the reader with a better understanding of the various aspects of the present application. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

[0005] Generally, a computing system can include electronic devices that communicate information via electrical signals in operation. For example, a computing system can include a processor that is communicatively coupled to a memory device, such as a dynamic random access memory (DRAM). In this way, the processor can communicate with the memory device using command and / or address signals (CA signals), for example, to retrieve executable instructions, to retrieve data to be processed by the processor, and / or to store data output from the processor. These CA signals can be supplied to a common bond pad, pin, external terminal, etc.

[0006] In synchronous memory devices, such as synchronous DRAM (SDRAM), CA signals are provided to the memory device in synchronization with an external clock signal that can be provided by a processor. Various internal clock signals are generated within the memory device from the external clock signal and used to synchronize command and data signals to ensure proper operation of the memory device. That is, based on various CA signals, various internal clock signals are generated and used within the memory device to complete various operations within the memory device, such as read commands and write commands. For read commands, some internal circuitry and internal clock signals can not be needed in certain modes of operation. For example, an internal data strobe signal that can otherwise be generated can not be needed at all times during all modes of operation. In these instances, if the internal clock signal is generated but not used, power consumption can be unnecessarily increased. Embodiments of the present disclosure can relate to techniques for controlling data strobe signals during read operations to reduce power consumption during certain modes of operation. SUMMARY

[0007] One aspect of the present application provides an apparatus comprising: a data strobe (DQS) state control circuit configured to set at least one control signal to an active state at least partially in response to a read clock signal being supplied to control logic of the DQS state control circuit, the DQS state control circuit further configured to maintain the at least one control signal in the active state after the read clock signal has been suspended from being supplied to the control logic of the DQS state control circuit; and an output buffer circuit configured to receive the at least one control signal and the read clock signal, the output buffer circuit further configured to activate to drive a data strobe (DQS) terminal in response at least in part to the read clock signal based at least in part on the active state of the at least one control signal such that the output buffer circuit continues to drive the DQS terminal after the read clock signal has been suspended from being supplied to the control logic of the DQS state control circuit.

[0008] Another aspect of the present application provides an apparatus comprising: an output buffer circuit configured to selectively pass a read clock signal to an output terminal; and control logic configured to selectively receive the read clock signal and: place the output buffer circuit in an active state during a first period; maintain the output buffer circuit in the active state during a second period; and place the output buffer circuit in an inactive state during a third period; wherein when in the active state, the output buffer circuit is configured to allow the read clock signal to pass to the output terminal; wherein the control logic is configured to place the output buffer circuit in the active state or the inactive state in response at least to the read clock signal; and wherein the control logic is prevented from receiving the read clock signal during at least a portion of the second period.

[0009] Another aspect of the present application provides an apparatus comprising: an output buffer circuit configured to provide a data strobe (DQS) signal to an output terminal in response to a read clock signal; and control logic configured to selectively receive the read clock signal and: place the output buffer circuit in an active state during a first period; maintain the output buffer circuit in the active state during a second period; and place the output buffer circuit in an inactive state during a third period; wherein when in the active state, the output buffer circuit is configured to provide the DQS signal to the output terminal; wherein the control logic is configured to place the output buffer circuit in the active state or the inactive state in response at least to the read clock signal; and wherein the control logic is prevented from receiving the read clock signal during at least a portion of the second period.

[0010] Another aspect of the present application provides a method comprising: receiving a read clock signal from a read clock generator at an output buffer circuit; placing the output buffer circuit in an active state during a first period in response to an activation signal from control logic, wherein the activation signal is responsive to the read clock signal; maintaining the output buffer circuit in the active state during a second period; placing the output buffer circuit in an inactive state during a third period in response to a deactivation signal from the control logic, wherein the deactivation signal is responsive to the read clock signal; passing a data strobe (DQS) signal from the output buffer circuit to an output in response to the read clock signal when the output buffer circuit is in the active state; and preventing the control logic from receiving the read clock signal during at least a portion of the second period.

[0011] Another aspect of the present application provides an apparatus comprising: a clock generator; and a data strobe (DQS) generator, wherein the DQS generator further comprises: a DQS state control; and an output buffer circuit; wherein the clock generator provides a read clock signal to the DQS generator, and wherein the DQS state control circuit selectively receives the read clock signal; wherein the DQS state control circuit selectively provides an activation signal to the output buffer circuit in response to at least the read clock signal, and wherein the output buffer circuit selectively provides a DQS signal to an output in response to at least the read clock signal and the activation signal. BRIEF DESCRIPTION OF DRAWINGS

[0012] Various aspects of the application can be better understood after a reading of the following detailed description with reference to the drawings, wherein:

[0013] Figure 1 is a block diagram of a memory device according to an embodiment of the present application;

[0014] Figure 2 is a block diagram of a portion of a memory device of Figure 1 including a read data strobe (DQS) generator according to an embodiment of the present application;

[0015] Figure 3 is a timing diagram of signals for operating a read DQS generator of Figure 2 during a non-burst read operation according to an embodiment of the present application;

[0016] Figure 4 and 5 taken together is a timing diagram of signals for operating a read DQS generator of Figure 2 during a burst read operation according to an embodiment of the present application;

[0017] Figure 6 It is according to another embodiment of the present invention that includes a read DQS generator. Figure 1 A block diagram of a portion of a memory device; and

[0018] Figure 7 This is an embodiment of the invention used for operation during non-burst read operations. Figure 6 The timing diagram for reading the signals from the DQS generator. Detailed Implementation

[0019] One or more specific embodiments will be described below. To provide a brief description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it should be understood that this development work may be complex and time-consuming, but will still be routine work of design, manufacture, and production for those skilled in the art who will benefit from this invention.

[0020] When describing the elements of various embodiments of the present invention, the articles “a,” “an,” and “the” are intended to indicate the presence of one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and indicate that additional elements besides those listed may be present. Furthermore, it should be understood that references to “an embodiment” or “an embodiment” of the invention are not intended to be construed as excluding the presence of additional embodiments that are also incorporated into the listed features.

[0021] Typically, a computing system may include electronic devices that transmit information via electrical signals during operation. For example, the electronic devices in a computing system may include a processor communicatively coupled to memory. In this way, the processor can communicate with memory by issuing command and / or address (CA) signals to retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor. The CA signals facilitate access operations to an array of memory cells contained in the memory. For the purposes of this invention, the CA signal should be understood to represent (a number of) command signals, (a number of) address signals, or (a number of) command signals and (a number of) address signals.

[0022] Random access memory (RAM) devices, such as those that can be used in electronic devices to provide data processing and / or storage, can provide direct availability of addressable data stored in the memory circuits of the devices in response to a CA signal. Certain RAM devices, such as synchronous dynamic RAM (SDRAM) devices, for example, can have a plurality of memory banks, each memory bank having a number of addressable memory elements therein. A gated data bus can be used in combination with certain strobe signals to provide read and write access to the addressable memory elements. A data strobe signal (e.g., DQS) can include a programmable preamble portion, a data readout period, and a postamble portion. The programmable preamble portion can provide a programmable timing window for the receiving device to enable data capture circuitry when a known / valid level is present on the strobe signal, thereby avoiding false triggering of the data capture circuitry. After the programmable preamble portion and during the data readout period, the DQS will toggle between high and low transitions along with the clock signal to transfer data. The time after the last transition is referred to as the postamble portion. As described further below, as used herein, a "data readout period" refers to the amount of time (i.e., number of clock cycles) taken to transfer (i.e., read) data associated with a single read operation or command (RD), and will depend on a number of factors such as memory type and burst length (BL).

[0023] For read operations, the DQS signals can be synchronized with an internal clock signal (e.g., Read CLK) generated from the external clock signal(s) (e.g., CLK and / or CLKF). It should be appreciated that each read command (RD) includes a specific burst length (BL) that allows a certain number of bits to be read in response to each read command (RD). For example, if the burst length (BL) is equal to 16, then 16 data bits will be sequentially read out in response to a single read command. For double data rate (DDR) SDRAM devices, 16 bits will be read out in 8 clock cycles (8-tCK). Based on the timing of consecutive read commands, the memory device can operate in a "single read" (or "non-burst read") mode or a "consecutive burst read" (or "burst read") mode. If consecutive read commands are received with a time interval that is greater than the time taken to capture data equivalent to one BL (i.e., the data readout period), then the read commands will be "non-burst read operations." Conversely, if consecutive read commands are received as consecutive read commands with a time interval that is less than or equal to the time taken to capture data equivalent to one BL (i.e., the data readout period), then the read commands will be "burst read operations." For example, for a DDR SDRAM device with a BL equal to 16, if consecutive read commands are received with a time interval that is greater than 8-tCK, then the second command will be treated as a non-burst read operation. If consecutive read commands are received with a time interval that is less than or equal to 8-tCK, then the second command will be treated as a burst read operation.

[0024] Generally, a read DQS generator can be provided within the DQS circuit of a memory device. The read DQS generator includes control logic configured to provide control signals to drivers to drive the output of the DQS pin or terminal in response to an internal Read CLK signal. However, depending on the timing of consecutive read commands (i.e., whether the read operations are burst or non-burst operations), certain internal clock signal states and the circuitry that generates those signals can not be necessary. As provided herein, the read DQS generator can include a gate circuit configured to switchably provide the internal Read CLK signal to the control logic such that the drivers configured to drive the DQS terminal are disabled during the burst read operation mode. By disabling portions of the read DQS generator during burst read operations, as described further below, unnecessary switching and signal generation can be avoided, and thus power savings can be advantageously implemented in the memory device.

[0025] Turning now to the drawings, Figure 1is a simplified block diagram illustrating certain features of a memory device 10, for example, included in a device, electronic apparatus, or semiconductor apparatus. In some embodiments, the memory device 10 can be disposed in a host device (not illustrated) (physically integrated into the host device or connected to the host device), or otherwise coupled to a host device. The host device can include any of a desktop computer, a laptop computer, a pager, a cellular telephone, a personal organizer, a portable audio player, a control circuit, a camera, etc. The host device can also be a network node, such as a router, a server, and / or a client (e.g., one of the aforementioned types of computers). Alternatively, the host device may, for example, be another type of electronic apparatus, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. It should be noted that the terminology used to describe these various examples of systems, as well as many other terms used herein, can share some reference objects and thus, should not be narrowly construed according to other listed items.

[0026] Accordingly, the host device can be a processor-based device that can include a processor, such as a microprocessor, that controls the system functions and the processing of requests in the host device and the memory device 10. Moreover, any host processor can comprise multiple processors that share system control. The host processor can be coupled directly or indirectly to additional system elements of the host device, such that the host processor controls operations of the host device by executing instructions that can be stored within the host device or external to the host device.

[0027] In some embodiments, the electronic apparatuses can include DDR5 (Double Data Rate Type 5) SDRAM (Synchronous Dynamic Random Access Memory) integrated on a semiconductor chip, LPDDR4 (Low Power Double Data Rate Type 4) DRAM (Dynamic Random Access Memory) integrated on a single semiconductor chip, etc. Each electronic apparatus is provided with a memory device 10 coupled to external terminals. It should be understood that these external terminals can be bond pads, inputs, pins, etc., but are referred to as pads or terminals for ease of discussion herein. The memory device 10 can facilitate read and / or write operations based at least in part on CA signals and / or external clock signals (CLK and CLKF) and an external clock enable (CKE) signal supplied from a processing core of the electronic apparatus or an external host device.

[0028] CA signals and external clock signals can be supplied to CA pads or terminals 12 and clock (e.g., CLK, CLKF, and CKE) pads or terminals 14 of the electronic device from a controller or host processor, for example, via CA buses and clock buses or any suitable communication coupling. The CA signals and external clock signals are supplied to the memory device 10, thereby facilitating access operations with respect to the array of memory cells included in the memory device 10. Additionally, the memory device 10 can receive additional signals from the host processor / controller, such as a chip select (CS) signal, and these signals can be individually supplied to one or more memory devices 10 of the electronic device. As depicted, the memory device 10 receives a chip select (CS) signal at chip select (CS) pads or terminals 16. The chip select (CS) signal can activate the memory device 10 for memory operations. The CS signal is transmitted from the CS pads 16 to a chip select (CS) input circuit 17. The CS input circuit 17 includes circuitry to enable the CA input circuit 38 to allow the CA signals to be transmitted to the memory device 10.

[0029] In response to the receipt of the CA signals, memory device data (DQ) can be read from or written to the memory device 10 at data pads or terminals 18 via the communication coupling. In some embodiments, such as in the case of read-only memory (ROM) based electronic devices, the memory device 10 can not allow both read and write actions.

[0030] The memory device 10 can include one or more memory cell arrays 20 (or banks, BANK-0 through BANK-7), each of which can include word lines (WL), bit lines (BL), and bar bit lines (BLB) arranged in a grid pattern, respectively. In the illustrated memory cell array 20, each memory cell includes an access device 22, such as a transistor, and a storage device 24, such as a capacitor. It will be appreciated that many other types of memory cell arrays can be utilized. A row decoder / driver 26 can select a word line, while a column decoder / driver 28 can select a bit line and bar bit line. Bit lines (BL) and bar bit lines (BLB) can be paired and coupled to sense amplifiers 30 (SA) of the memory cell array 20. The sense amplifiers 30 can amplify a voltage difference generated between the bit line BL and BLB. The sense amplifiers 30 can also supply read data to complementary local input / output lines (LIOT / B) based at least in part on the voltage difference generated between the bit line BL and BLB, where the local input / output lines can represent a pair of lines (e.g., a normal line and an inverted line). The read data supplied to the local input / output lines can be transferred to complementary main input / output lines (MIOT / B) via a switch circuit (TG) 32. The read data on the main input / output lines can be converted to a single-ended signal and transmitted to a data (DQ) input / output circuit 34 via a read / write amplifier 36 (RW AMP) for translating electrical signal values (e.g., voltage levels) between values interpretable at the pads and values interpretable by the internal memory cell array 20.

[0031] As previously described, the memory device 10 can include CA pads 12, clock (e.g., CLK, CLKF, and CKE) pads 14, data (DQ) pads 18, and one or more chip select (CS) pads 16 to receive external command, address, clock, select, and data signals. It will be appreciated that the memory device 10 may, for example, also include one or more voltage pads to receive various voltages (e.g., VDD corresponding to a logic high voltage value and VSS corresponding to a logic low voltage value). It will be appreciated that several other voltage signals can also be provided to different input pads to power / control various other portions of the memory device 10. The voltages can be provided to a power circuit of the memory device (not shown) that can generate various internal voltage potentials based at least in part on a power supply potential (e.g., VDD). The internal potentials can be transmitted to the row decoder 26, the sense amplifiers 30, etc. to facilitate operation of the memory device 10. Further, the voltages can be provided to a power-on detector to determine whether an electrical signal (e.g., current) is flowing to the voltage pads of the memory device. In response to this determination, the memory device 10 can change operation, for example, it can be used to reset its own circuitry in preparation for a next memory operation.

[0032] CA signals are received at the CA pads 12 and can be transmitted to the CA input circuit 38. The memory device 10 can include any suitable number of CA pads 12, and as depicted, the memory device 10 includes (m+1) CA pads 12 (i.e., CA0 - CAm). As previously described, the CA signals can include address signals and command signals. The address signals can be transmitted to the address decoder 40 and the command signals can be transmitted to the command decoder 42. The address decoder 40 can supply row addresses to the row decoder / drivers 26 and column addresses to the column decoder / drivers 28. The command decoder 42 can generate internal commands by decoding the command signals, and can transmit the internal commands to various circuits in the memory device 10. For example, the command decoder 42 can generate active signals, read signals, write signals, etc. to transmit to various circuits in the memory device.

[0033] In response to outputs from the command decoder 42, a clock input circuit and an internal clock generator, referred to herein as clock generator 44, can enable and / or disable a variety of control signals to operate the memory device 10 circuits, e.g., mode registers, delay circuits, reset control circuits, column decoder / drivers 28, and row decoder / drivers 26, to perform operations, e.g., reset operations, read operations, and / or write operations, in accordance with the internal commands. For example, in response to an activate command, the command decoder 42 and clock generator 44 can operate to enable word lines in response to row addresses transmitted to the memory device 10. The CA input circuit 38, address decoder 40, command decoder 42, column decoder / drivers 28, and row decoder / drivers 26 can constitute CA control circuits and can access the memory cell array 20.

[0034] Further, the command decoder 42 can provide various internal commands to various other portions of the memory device 10. In particular with respect to read operations, the command decoder 42 can output a decoded read command (RDC) signal and various read clock enable signals, e.g., RClk_EN1 and RClk_EN2 to facilitate read operations, as will be further described below.

[0035] An external clock signal can be transmitted to the memory device 10 at the clock pad 14. The external clock signal CLK and the external clock signal CLKF can be complementary signals to one another (e.g., CLKF is an inversion of CLK), and both can be supplied to the clock generator 44. The clock generator 44 can generate one or more internal clock signals, such as a latch clock signal (not shown) used as a timing signal that defines the operation of one or more latching circuits of the memory device 10. The clock generator 44 can also generate various other internal clock signals, such as a phase controller internal clock signal. In some embodiments, the clock generator 44 can include clock distribution circuitry and / or a delay-locked loop (DLL) circuitry, where data associated with the data input / output (I / O) circuitry 34 is used to determine the output timing of read data (DQ). As depicted, the clock used to clock the read / write data (DQ) at the DQ I / O circuitry 34 is a data strobe (DQS) signal, which can be accessed at a data strobe (DQS) pad or terminal 48. As will be described in more detail below, the DQS signal is generated by the DQS circuitry 50, which is described in more detail below. Figure 1 In more detail, the clock generator 44 can also generate an internal clock signal (INTCLK) that can be used to synchronize various operations within the memory device 10, such as read and write operations.

[0036] The memory device also includes data strobe (DQS) circuitry 50 having a DQS signal generator therein. In particular with respect to read commands, the DQS circuitry 50 includes a read DQS generator 52. As will be described in more detail below, the read DQS generator 52 receives a decoded internal read command (RDC) signal and an RClk_EN2 signal from the command decoder 42. In addition, the read DQS generator 52 also receives an internal read clock signal (READ CLK) from the clock generator 44. The functions of these signals and associated circuitry will be described in more detail below. Figure 2

[0037] Reference is now made to Figure 2 , which illustrates Figure 1 ​Fig. 2 is a schematic block diagram of a portion of the memory device 10 including an embodiment of a read DQS generator 52 of the DQS circuit 50 and portions of the command decoder 42 and clock generator 44 related to the read portion of the DQS circuit 50. In the illustrated embodiment, the read DQS generator 52 includes a DQS OB (output buffer) pull-up driver 60 and a DQS OB (output buffer) pull-down driver 62. The DQS OB pull-up driver 60 is controlled by a State_PU signal. An active level of the State_PU signal enables the DQS OB pull-up driver 60 such that the DQS OB pull-up driver 60 drives the DQS terminal 48 to a high level in response to a high level of an internal read clock (Read_Clk) signal and stops driving the DQS terminal 48 in response to a low level of the Read_Clk signal. Conversely, an inactive level of the State_PU signal disables the DQS OB pull-up driver 60. In a similar manner, an active level of a State_PD signal enables the DQS OB pull-down driver 62 such that the DQS OB pull-down driver 62 drives the DQS terminal 48 to a low level in response to a low level of the internal Read_Clk signal and stops driving the DQS terminal 48 in response to a high level of the internal Read_Clk signal. An inactive level of the State_PD signal disables the DQS OB pull-down driver 62.

[0038] As illustrated, when both the State_PU signal and the State_PD signal are inactive (i.e., each of the DQS OB pull-up driver 60 and the DQS OB pull-down driver 62 is disabled), the DQS terminal 48 enters a high impedance (Hi-Z) state. The Hi-Z state refers to a floating state or tri-state in which a signal is not driven to a defined logic level. On the other hand, when both the State_PU and the State_PD are at active levels, the DQS OB pull-up driver 60 and the DQS OB pull-down driver 62 switch the DQS terminal 48 to provide a Read_DQS signal at the DQS terminal 48. Further, the combination of the levels of the State_PU signal and the State_PD signal provide a read preamble condition and a read postamble condition typically defined therebetween. By changing the combination of the levels of the State_PU signal and the State_PD signal, the read preamble condition and the read postamble condition can be controlled. For example, during a data readout period, DQ output buffers in the DQ I / O circuit 34 Figure 1 ) drive the DQ terminals 18 to provide (i.e., read out) data to an external device of the DDR memory device 10, such as a memory controller, at a double data rate in response to each of the edges of the Read_DQS signal at the DQS terminal 48.

[0039] An internal read clock signal Read CLK is provided by a read clock generator 64 (read clock generator) in a clock generator 44 (clock generator) and is generated from the external CLK signal. The read clock generator 64 is activated in response to a valid level of a (first) read clock enable (RClk_EN1) signal. The RClk_EN1 signal is provided to the read clock generator 64 by read control logic 66 in the command decoder 42 that handles a read command. That is, when a read command is supplied to (e.g., at the CA terminals) and decoded by the command decoder 42, the read control logic 66 changes the RClk_EN1 signal from an inactive level to an active level so that the read clock generator 64 begins to provide the internal Read CLK signal to the read DQS generator 52. The read control logic 66 further changes a decoded read command signal (RDC) to an active level to activate control logic 68 in DQS state control circuit 70 of the read DQS generator 52. For example, by changing the RDC signal to an active level, the control logic 68 is configured to control respective levels of State_PU and State_PD signals in response to an output (Clk_DQSCL) of a gate circuit, e.g., an AND gate 72.

[0040] The AND gate 72 receives the internal Read CLK signal from the read clock generator 64 and a second read clock enable signal (RClk_EN2) from the read control logic 66. Thus, the "on" or "off state of the gate circuit, here the AND gate 72, is controlled by RClk_EN2 that either passes or prevents the internal Read CLK signal from the read clock generator 64 through the gate circuit 72. That is, the AND gate 72 is configured to selectively allow or prevent the Read CLK signal to be received by the control logic 68 (as CLK_DQSCL) based on the state or logic level of the RClk_EN2 signal to ultimately enable or disable the drivers (DQS OB pull-up 60 and DQS OB pull-down 62) to drive the DQS terminals 48 via the Read_DQS signal. The logic level of the RClk_EN2 signal is controlled by the read control logic 66 in response to a particular data read mode, e.g., a "non-burst" read operation mode and a "burst" read operation mode described in detail above and discussed below with reference to the timing diagrams of Figures 3 to 5

[0041] Now turning to Figure 3 ​illustrates timing diagrams indicating non-burst read operations. As previously described, and as used herein, a "non-burst read operation" is performed when consecutive read commands are received at a time interval greater than the time taken to capture data equivalent to one burst length (BL). In the illustrated example of a DDR memory, the burst length is equal to 16, and thus 16 data bits will be sequentially read out in response to a single read command (e.g., RD1 and RD2). For a double data rate (DDR) SDRAM device, 16 bits will be read out in 8 clock cycles (8-tCK). It will be appreciated that because the internal Read CLK signal is generated from the external CLK signal, each clock cycle will have a clock period equal to 1-tCK. As shown from the timing diagrams, the time interval between consecutive read commands RD1 and RD2 is greater than 8-tCK, and thus the read operations are non-burst read operations. Figure 3 As is clear, the two consecutive read commands RD1 and RD2 are issued or asserted at a time interval greater than 8-tCK and thus are non-burst read operations. Although the examples provided relate to a DDR memory device operating at a read burst length of 16, one skilled in the art will appreciate that other types of memory and burst lengths will provide different timing of non-burst read operations and burst read operations. Figure 3 As is clear, the two consecutive read commands RD1 and RD2 are issued or asserted at a time interval greater than 8-tCK and thus are non-burst read operations. Although the examples provided relate to a DDR memory device operating at a read burst length of 16, one skilled in the art will appreciate that other types of memory and burst lengths will provide different timing of non-burst read operations and burst read operations.

[0042] As previously described, in a non-burst read operation, the respective levels of the control signals RClk_EN1, RDC, and RClk_EN2 cause the control logic 68 of the DQS state control circuit 70 to continue to receive the internal Read CLK throughout the period of each data read operation (e.g., RD1 and RD2). In other words, the control logic 68 of the DQS state control circuit 70 continues to receive Read CLK (via AND gate 72) during the data readout period (e.g., data readout period 80) in response to RD1. It will be understood that the length of the data readout period 80 is determined by the type of memory device 10 and the burst length (BL) associated with a single read command (e.g., RD1 or RD2). In the illustrated embodiment employing a DDR memory device 10 and BL = 16, the data readout period 80 is equal to 8-tCK.

[0043] Furthermore, by changing the combination of levels of the State_PU signal and the State_PD signal (e.g., read preamble 82 and read postamble 84) associated with RD1, the read preamble condition and the read postamble condition can be controlled. Thus, a transition of the State_PU signal from high to low, in conjunction with a transition of the State_PD signal from low to high, will trigger the end of the preamble 82 and the start of the data readout period 80. Similarly, a transition of the State_PU signal from low to high, in conjunction with a transition of the State_PD signal from high to low at the end of the data readout period 80, will trigger the postamble 84. As shown from the timing diagrams, the State_PU signal and the State_PD signal are asserted at a time interval greater than 8-tCK and thus are non-burst read operations. Figure 3As explained in the foregoing, the periods of the pre- and post- sync codes 82 and 84 and the control of the levels of the State_PU and State_PD signals during such periods are performed in response to (or in synchronization with) the Read CLK signal. In other words, the control logic 68 of the DQS state control circuit 70 uses the Read CLK signal to control the DQS signals of the pre- and post- sync codes 82 and 84. On the other hand, each of the State_PU and State_PD signals is maintained at the active level during the data readout period 80.

[0044] Turning now to the Figure 4 and 5 illustrate timing diagrams indicative of a burst read operation. As previously described, and as used herein, a burst read operation is performed when consecutive read commands are received in a time interval equal to the time taken to capture data equivalent to one burst length (BL) (i.e., a data readout period). In the illustrated example of the DDR memory device 10 operating with a read burst length equal to 16, a burst read operation will occur when two or more read commands are issued or asserted consecutively in a time interval equal to 8-tCK. In the illustrated example, the burst read operation is performed in response to the read commands RD4, RD5, and RD6 being issued consecutively in a time interval equal to 8-tCK after the read command RD3. Figure 4 and 5 In

[0045] Referring first to Figure 4 and again to Figure 2 , after the read command RD4 (i.e., RD4 is received at time period 90, which is equal to the data readout period, which here is 8-tCK) following the read command RD3 indicative of a burst read mode, the read control logic 66 determines that the read command RD4 is issued at a time equal to the data readout period. In response to the read command RD4 being received at a time equal to the data readout period, the read control logic 66 asserts the RClk_EN2 signal at the end of the data readout period 92, as indicated at time 96. In response to the RClk_EN2 signal being asserted, the gate circuit (e.g., AND gate 72) is thus "opened" to allow the internal Read CLK to pass to the control logic 68 of the DQS state control circuit 70. As illustrated, and in contrast to the burst read operation illustrated in Figure 3In contrast to the non-burst mode of operation illustrated in the middle, the read control logic 66 maintains the RDC signal at the active level because the device is operating in the burst read mode. Thus, the control logic 68 of the DQS state control circuit 70 maintains the State_PU signal and the State_PD signal at the respective active levels (L and H) so that the read_DQS signal is continued so as to provide data read out based on the read command RD4. That is, the data read out period 96 in response to the read command RD4 starts immediately after the data read out period 92 because RD4 is a burst read operation.

[0046] With reference to Figure 4 and 5 the same situation occurs with respect to the data read out based on the read commands RD5 and RD6. That is, because the time period 98 between the read commands RD4 and RD5 is equal to the associated data read out period (here, 8-tCK), the burst read mode of operation will continue as described above with respect to the signals associated with the read command RD4 following the read command RD3. Thus, the data read out in response to the read command RD5 during the data read out period 100 starts immediately after the data read out period 96 because RD5 is a burst read operation. Similarly, the time period 102 between the read commands RD5 and RD6 is equal to the associated data read out period (here, 8-tCK), and thus, the burst read mode of operation will continue and the data read out in response to the read command RD6 during the data read out period 104 starts immediately after the data read out period 100 because RD6 is a burst read operation.

[0047] As Figure 5As shown in the middle, after the read command RD6, no further read commands are issued within the data read period (here, 8-tCK) and thus, the burst read operation will terminate with the data read out during the data read period 104 based on the read command RD6. Termination of the burst read operation can be signaled by the issuance of any other command, such as a write command or another read command. Thus, after about half of the data (about 8 bits) has been provided at the DQ terminals 48 during the data read period 104 based on the read command RD6, the read control logic 66 transitions the RClk_EN2 signal to the high (H) level, as indicated at time 106. In response, the gate circuit 72 thus "opens" to restore the control logic 68 that passes the Read CLK signal to the DQS state control circuit 70, so that the control logic 68 is ready to perform the post-read preamble operation 108. Subsequently, the read control logic 66 transitions the RDC signal to the inactive level (L) to signal the control logic 68 of the DQS state control circuit 70 to provide the post-read preamble signal 108 after the data read out during the data read period 104 based on the read command RD6. Finally, the read control logic 66 transitions RClk_ENl to the inactive level (L) to deactivate the read clock generator 64 so that the internal Read CLK signal (and Clk_DQSCL) provided by the read clock generator 64 is stopped.

[0048] Thus, when one or more consecutive read commands are received within the length of a data read period (e.g., 8-tCK in the above example), the gate circuit, such as AND gate 72, will be closed. For example, referring again to Figure 4 and 5 , the AND gate 72 will be closed, thereby preventing the control logic 68 of the DQS state control circuit 70 from receiving the Read CLK signal, as indicated by the inactive state of the Clk_DQSCL signal starting at time 94. When the control logic 68 does not receive the Read CLK signal, it maintains each of the State_PU and State_PD signals at the active level. Thus, the drivers (i.e., DQS OB pull-up 60 and DQS OB pull-up 62) continue to operate to toggle the read DQS signal, resulting in the continuous read out of data DQ during the consecutive data read periods (e.g., 96, 100, and 104) without performing preamble and postamble operations for the associated read commands until other than a burst read operation is detected. By eliminating the internal toggling and control by the DQS state control 70 during a read burst, current and power savings can be achieved.

[0049] Referring now to Figure 6 and 7 , another embodiment of the relevant portions of the memory device 10 and associated timing diagrams are described. In particular,Figure 6 Another schematic block diagram of the read DQS generator 52 in the DQS circuit 50 and the corresponding portions of the command decoder 42 and clock generator 44 associated with the read portion of the DQS circuit 50. Figure 6 The embodiment of Figure 2 differs from the embodiment of In the illustrated embodiment, when the BL information sent to the read control logic 66 is at a high (H) level (which indicates BL = 16), the read control logic 66 is configured to perform a burst read operation. In one embodiment, the read control logic 66 is configured to perform a burst read operation in which 16 data bits are output from each DQ terminal 18 (DQ0-DQ15) in sequence, in synchronization with the read DQS signal at the DQS terminal 48. In other words, the read control logic 66 is configured to perform a burst read operation in which 16 data bits are output from each DQ terminal 18 (DQ0-DQ15) in sequence, in synchronization with the read DQS signal at the DQS terminal 48, and in which the read DQS signal at the DQS terminal 48 is asserted for 16 clock cycles.

[0050] In the illustrated embodiment, when the BL information sent to the read control logic 66 is at a high (H) level (which indicates BL = 16), the read control logic 66 is configured to perform a burst read operation. In one embodiment, the read control logic 66 is configured to perform a burst read operation in which 16 data bits are output from each DQ terminal 18 (DQ0-DQ15) in sequence, in synchronization with the read DQS signal at the DQS terminal 48. In other words, the read control logic 66 is configured to perform a burst read operation in which 16 data bits are output from each DQ terminal 18 (DQ0-DQ15) in sequence, in synchronization with the read DQS signal at the DQS terminal 48, and in which the read DQS signal at the DQS terminal 48 is asserted for 16 clock cycles. Figure 6 This embodiment of Figure 3 performs the same operations as previously described with respect to Figure 6 In other words, the embodiment of Figure 6 is capable of supporting both non-burst read operations and burst read operations. Moreover, according to the embodiment illustrated in Figure 7 , when the BL information sent to the read control logic 66 is at a low (L) level indicating BL = 32, a non-burst operation is performed as shown in Figure 7 As will be apparent in BL = 32, since 32 data bits are output from each DQ terminal 18 (DQ0-DQ15) in sequence in synchronization with the read DQS signal at the DQS terminal 48, the read DQS signal at the DQS terminal 48 is asserted for 32 clock cycles. Figure 1 Figure 7The level of RClk_EN2 is transitioned (e.g., from high to low) after the preamble process shown in FIG. 12 to stop the supply of the Read CLK signal from the read clock generator 64 to the control logic 68 of the DQS state control circuit 70 (i.e., by turning off the AND gate 72) to further reduce power consumption. That is, in response to the transition 112 of the RClk_EN2 signal, the Clk_DQSCL signal will remain inactive for a time period 114 during which the control logic 68 does not require the Read CLK signal. The time period 114 ends when RClk_EN2 transitions high again (time 116) and the control logic 68 receives the Read CLK signal again for the postamble process. As also indicated, a second data readout period 118 is illustrated after the second read command RD2 and preamble process are received. It should be noted that the burst read operation at BL = 32 can be performed in the same manner as discussed with reference to Figure 4 and 5 It should be noted that the partial stoppage of the delivery of the Read CLK to the control logic 68 during the data readout period can also be applied to the case of BL = 16 in order to also reduce power consumption.

[0051] It will be appreciated that during the burst read operation, Figure 6 Embodiments of the application can operate in the same manner as previously described with reference to the embodiments of the application in Figure 4 and 5 Figure 2 However, when the burst length (BL) is 32, the data readout period will be equal to 16-tCK (rather than 8-tCK for BL = 16). Thus, when a read command follows the immediately preceding read command at a distance of 16-tCK or less, the consecutive read commands will trigger the burst read operation mode. Thus, while the operation of the read DQS generator 52 will remain the same, the amount of time between the read commands that will trigger the burst operation mode and thus the suppression of the Read CLK signal to the control logic 68 will vary depending on the burst length.

[0052] While the application can be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the application is not intended to be limited to the particular

[0053] ​The technology presented and claimed herein is to be considered to have been invented in the year 2016. The technology presented and claimed herein is to be considered to have been invented by the inventors named in the patent. The technology presented and claimed herein is to be considered to have been invented in the United States of America. The technology presented and claimed herein is to be considered to have been invented in the city of San Diego, California, United States of America. The technology presented and claimed herein is to be considered to have been invented in the county of San Diego, California, United States of America. The technology presented and claimed herein is to be considered to have been invented in the state of California, United States of America. The technology presented and claimed herein is to be considered to have been invented in the country of the United States of America. The technology presented and claimed herein is to be considered to have been invented in the region of North America. The technology presented and claimed herein is to be considered to have been invented in the continent of North America. The technology presented and claimed herein is to be considered to have been invented in the hemisphere of the Northern Hemisphere. The technology presented and claimed herein is to be considered to have been invented in the Southern Hemisphere. The technology presented and claimed herein is to be considered to have been invented in the Eastern Hemisphere. The technology presented and claimed herein is to be considered to have been invented in the Western Hemisphere. The technology presented and claimed herein is to be considered to have been invented in the Eastern Hemisphere. The technology presented and claimed herein is to be considered to have been invented in the

Claims

1. A memory device comprising: A data strobe DQS state control circuit is configured to set at least one control signal to an active state in at least part of response to the control logic of supplying a read clock signal to the DQS state control circuit, and the DQS state control circuit is further configured to maintain the at least one control signal in the active state after the control logic of suspending the supply of the read clock signal to the DQS state control circuit has been suspended. and An output buffer circuit is configured to receive the at least one control signal and the read clock signal, and the output buffer circuit is further configured to be activated at least in part based on the active state of the at least one control signal to drive the data strobe DQS terminal at least in part in response to the read clock signal, such that the output buffer circuit continues to drive the DQS terminal after the control logic of supplying the read clock signal to the DQS state control circuit has been suspended.

2. The memory device of claim 1, wherein the DQS state control circuitry includes a gate circuitry configured to receive the read clock signal and a read clock enable signal and to control the supply of the read clock signal to the control logic of the DQS state control circuitry in response to the state of the read clock enable signal.

3. The memory device of claim 2, wherein the control logic of the DQS state control circuit is configured to receive the output of the gate circuit and output the at least one control signal to the output buffer circuit.

4. The memory device according to claim 1, wherein the output buffer circuit includes a DQS output buffer pull-up driver and a DQS output buffer pull-down driver.

5. The memory device of claim 4, wherein the at least one control signal includes a first control signal and a second control signal, wherein the DQS output buffer pull-up driver is configured to receive the first control signal from the DQS state control circuit, and wherein the DQS output buffer pull-down driver is configured to receive the second control signal from the DQS state control circuit.

6. The memory device of claim 1, wherein the control logic of pausing the supply of the read clock signal to the DQS state control circuit in a non-burst read mode is paused.

7. The memory device of claim 1, wherein the control logic of pausing the supply of the read clock signal to the DQS state control circuit in burst read mode is paused.

8. The memory device of claim 1, wherein the read clock signal is supplied to the control logic of the DQS state control circuit in both non-burst read mode and burst read mode.

9. The memory device of claim 1, wherein the DQS state control circuit is further configured to maintain the at least one control signal in the active state after the control logic for supplying the read clock signal to the DQS state control circuit has been restored, such that the output buffer circuit continues to drive the DQS terminal after the control logic for supplying the read clock signal to the DQS state control circuit has been restored.

10. A memory device comprising: An output buffer circuit is configured to selectively pass the read clock signal to the output. as well as Control logic, configured to selectively receive the read clock signal, and: During the first cycle, the output buffer circuit is put into an active state; During the second cycle, the output buffer circuit is maintained in the active state; as well as During the third cycle, the output buffer circuit is disabled; When in the active state, the output buffer circuit is configured to allow the read clock signal to be transmitted to the output terminal; The control logic is configured to place the output buffer circuit in the active state or the inactive state, at least in response to the read clock signal. as well as This prevents the control logic from receiving the read clock signal during at least a portion of the second cycle.

11. The memory device of claim 10, wherein the second cycle occurs during burst read mode operation.

12. The memory device according to claim 11, The burst read mode operation is initiated in response to at least a first read command and a second read command issued sequentially, wherein the second read command follows the first read command; Wherein, when the output buffer circuit transmits the data strobe DQS signal to the output terminal based on the first read command, the control logic receives the read clock signal; and When the output buffer circuit transmits the read clock signal to the output terminal based on the second read command, the control logic does not receive the read clock signal.

13. The memory device of claim 10, further comprising: The decoded read command RDC signal received by the control logic, wherein: If the RDC signal changes from a first value to a second value, the control logic puts the output buffer circuit into the active state during the first cycle; If the RDC signal maintains the second value, the control logic maintains the output buffer circuit in the active state during the second cycle; and If the RDC signal changes from the second value to the first value, the control logic puts the output buffer circuit into the invalid state during the third cycle.

14. The memory device of claim 13, further comprising: Read control logic; and Mode register; The read control logic receives variable burst length (BL) information from the mode register, and the RDC signal responds to the variable burst length (BL) information.

15. The memory device according to claim 14, The device is configured to receive an enable signal from the read control logic in response to the variable burst length (BL) information; and The control logic is configured to receive the read clock signal in response to the enable signal.

16. The memory device of claim 15, further comprising: Gate circuits; The gate circuit receives the enable signal and the read clock signal; and The gate circuit, in response to the enable signal, transmits the read clock signal to the control logic.

17. The memory device according to claim 10, The device is configured to receive an enable signal; and The control logic is configured to receive the read clock signal in response to the enable signal.

18. The memory device of claim 10, comprising: Gate circuits; The gate circuits selectively provide the control logic clock signal Clk_DQSCL to the control logic.

19. The memory device of claim 10, wherein the output buffer circuit includes a data strobe DQS output buffer pull-up driver and a DQS output buffer pull-down driver.

20. A memory device comprising: An output buffer circuit is configured to provide a data strobe (DQS) signal to the output in response to a read clock signal; as well as Control logic, configured to selectively receive the read clock signal, and: During the first cycle, the output buffer circuit is put into an active state; During the second cycle, the output buffer circuit is maintained in the active state; as well as During the third cycle, the output buffer circuit is disabled; When in the active state, the output buffer circuit is configured to provide the DQS signal to the output terminal; The control logic is configured to place the output buffer circuit in the active or inactive state, at least in response to the read clock signal; and This prevents the control logic from receiving the read clock signal during at least a portion of the second cycle.

21. A method for controlling a data strobe signal during a read operation, comprising: The output buffer circuit receives the read clock signal from the read clock generator. In response to an activation signal from the control logic, the output buffer circuit is put into an active state during the first cycle, wherein the activation signal is in response to the read clock signal; The output buffer circuit is maintained in the active state during the second cycle; In response to a deactivation activation signal from the control logic, the output buffer circuit is deactivated during the third cycle, wherein the deactivation activation signal is responsive to the read clock signal; When the output buffer circuit is in the active state, in response to the read clock signal, the data strobe DQS signal is transmitted from the output buffer circuit to the output terminal. as well as The control logic is prevented from receiving the read clock signal during at least a portion of the second cycle.

22. The method of claim 21, further comprising: The read clock signal is received at the gate circuit; as well as The read clock signal is selectively provided to the control logic from the gate circuit.

23. The method of claim 22, further comprising: Receive an enable signal at the gate circuit; as well as In response to the enable signal, the read clock signal is provided from the gate circuit to the control logic.

24. The method of claim 23, wherein the state of the enable signal depends at least in part on the burst length BL.

25. The method of claim 21, further comprising: The control logic receives the decoded read command RDC signal, wherein If the RDC signal changes from a first value to a second value, the control logic puts the output buffer circuit into the active state during the first cycle; If the RDC signal maintains the second value, the control logic maintains the output buffer circuit in the active state during the second cycle; as well as If the RDC signal changes from the second value to the first value, the control logic puts the output buffer circuit into the invalid state during the third cycle.

26. The method of claim 25, wherein the burst length BL is associated with the RDC signal.

27. A memory device comprising: Clock generator; as well as A data strobing DQS generator, wherein the DQS generator further comprises: DQS state control circuit; and Output buffer circuit; The clock generator provides a read clock signal to the DQS generator, and the DQS state control circuit selectively receives the read clock signal. The DQS state control circuit selectively provides an activation signal to the output buffer circuit in response to at least the read clock signal, and The output buffer circuit selectively provides a DQS signal to the output terminal in response to at least the read clock signal and the activation signal.

28. The memory device of claim 27, further comprising: A command decoder is configured to selectively provide a decode read command (RDC) signal to the DQS state control circuit, wherein the DQS state control circuit provides an activation signal to the output buffer circuit in response to the RDC signal.

29. The memory device of claim 28, wherein when the RDC signal is enabled, the DQS state control circuit does not receive the read clock signal for at least a portion of the time.

30. The memory device of claim 29, wherein the command decoder is configured to selectively provide an enable signal to the DQS state control circuitry, wherein the DQS state control circuitry receives the read clock signal at least in response to the enable signal.

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