Write assist circuit

Abstract

The present invention discloses a write assist circuit, comprising: a delay circuit, having a first and a second output terminal, outputting a first and a second delay signal respectively; a negative voltage generating module, wherein the second delay signal is used to provide a positive input voltage for the negative voltage generating module, and the first delay signal provides a control signal for the negative voltage generating module; under the control of the first delay signal, the negative voltage generating module converts the second delay signal into a first negative voltage required for writing; at least the first delay time of the first delay signal has working voltage dependency, and as the working voltage increases, the first delay time will decrease, so that the negative voltage generating module switches between positive and negative voltages in advance, so as to avoid the first negative voltage being too low and generating electrical stress. The present invention can provide a negative voltage and prevent the negative voltage from being too low, thereby preventing the occurrence of extreme electrical stress, and can also avoid the use of a clamping circuit, thereby avoiding the leakage path generated by the clamping circuit, thereby improving energy efficiency.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a write assist circuit. Background Art

[0002] The storage unit of static random access memory (SRAM) includes a pair of interlocked CMOS inverters and corresponding selection tubes. The commonly used 6T type SRAM storage unit includes 6 MOS transistors, among which each CMOS inverter includes a pull-up tube (PU) composed of PMOS and a pull-down tube (PD) composed of NMOS; the two selection tubes are composed of NMOS, and PG is usually used to represent the selection tube. Figure 1 As shown, it is a circuit diagram of an existing 6T type SRAM storage unit 101; wherein PU1 and PD1 form a CMOS inverter, PU2 and PD2 form another CMOS inverter, two storage nodes are Q and QB, and the signals of nodes Q and QB are inverted. Nodes Q and QB are connected to a pair of bit lines BL and BLB through selection tubes PG1 and PG2, respectively, and the gates of selection tubes PG1 and PG2 are connected to word lines WL.

[0003] like Figure 2 As shown, it is a circuit diagram of an existing SRAM using a write assist circuit; in the storage array 102 of the SRAM, the storage cells 101 are arranged in a row and column structure, and the gates of the selection tubes PG1 and PG2 of the storage cells 101 in the same row are connected to the word line WL, so the two storage nodes Q and QB of the storage cells 101 in the same row are respectively connected to a pair of bit lines BL and BLB. Figure 2 m rows are shown in the figure, and each row word line corresponds to WL[0] to WL[m] respectively; n columns are shown, and each column bit line BL and BLB corresponds to BL[0] to BL[n] and BLB[0] to BLB[n] respectively.

[0004] During the writing process of each storage cell 101, a pair of mutually inverted data to be written will be added to a pair of bit lines BL and BLB, and then the word line WL selects the corresponding row, and then the data on the bit line will be written into the storage cell 101 corresponding to the row and column.

[0005] Depend on Figure 2 As shown, after the data signal Din is input to the write operation control module 104, the write operation control module 104 forms a pair of mutually inverted signals through two paths, that is, a pair of mutually inverted signals are formed at the output ends of the inverters 105a and 105b.

[0006] The mutually inverted signals output by the write operation control module 104 are input to the bit lines BL and BLB of the corresponding columns under the selection of the selection module 103 .

[0007] For the SRAM memory cell 101, there is a conflict between the beta ratio and the Idsat, i.e., the saturation leakage current, of the pull-up tube. The beta ratio is the ratio of the Idsat, i.e., the saturation leakage current, between the pull-down tube and the selection tube. Therefore, it is necessary to balance the read margin and the write margin of the SRAM memory cell 101.

[0008] As the process continues to develop, the size of the device continues to shrink proportionally, and FinFET will be used to form SRAM. FinFET can further increase the density of the SRAM storage unit 101, which will make the write margin worse. At this time, a write assist circuit is required in the FinFET SRAM to make it easier to write to the storage unit.

[0009] like Figure 2 , is a circuit diagram of an existing SRAM using a write assist circuit; the SRAM also includes a write assist circuit 201, the input end of the write assist circuit 201 is connected to the bit line control signal RBL, and the output end outputs a first negative voltage NVSS.

[0010] The first negative voltage NVSS is added to the ground terminals of the inverters 105a and 105b. Those skilled in the art should understand that the inverter has a pull-up tube and a pull-down tube, and according to the input signal, the output signal is either connected to a positive voltage through the pull-up tube or to ground through the pull-down tube. Figure 2 In the process, after the first negative voltage NVSS is connected to the ground terminal of the inverters 105a and 105b, if the pull-down tubes of the inverters 105a and 105b are turned on, the output terminals of the inverters 105a and 105b will be directly pulled down to the first negative voltage NVSS instead of being pulled down to the ground, so that a negative bit line voltage can be provided for one of the bit lines BL and BLB, while the other still has a positive bit line voltage, so that the voltage difference between the bit lines BL and BLB can be increased, thereby increasing the write margin and reducing the writing difficulty.

[0011] like Figure 3AAs shown, it is a circuit diagram of the first existing write assist circuit 301; the first existing write assist circuit 301 includes a delay path 302 and a delay path composed of multiple inverters 303; wherein, the delay path 302 can include a logic circuit and an inverter, and the input end is connected to the bit line control signal RBL, and can also be connected to the digital control signal TSEL[1:0], and the control signal TSEL[1:0] can adjust the delay time of the delay path 302. In the path of the inverter 303, a signal is taken out from the node EN_NBL and connected to the NMOS tube N301.

[0012] The first end of the capacitor C301 is connected to the output end of the last inverter 303, the second end of the capacitor C301 is connected to the drain of the NMOS transistor N301 and outputs the first negative voltage NVSS. The source of the NMOS transistor N301 is grounded.

[0013] When the bit line control signal RBL is at a high level, the NMOS tube N301 is turned on, the second end of the capacitor C301 is grounded, and the first end of the capacitor C301 is charged to a positive voltage; when the bit line control signal RBL is at a low level, the NMOS tube N301 is turned off, the second end of the capacitor C301 is not grounded, and the first end of the capacitor C301 is grounded, which causes the second end of the capacitor C301 to output a first negative voltage NVSS.

[0014] The disadvantage of the first type of existing write assist circuit 301 is that the value of the first negative voltage NVSS is easily pulled to a relatively large value, thereby generating electrical stress. During the high temperature operation life test (HTOL) process, the write assist circuit will generate an extremely high voltage (x1.8VDD), which will deteriorate the reliability test results. Once no additional reliability design (DFR) is inserted, it is difficult to balance between product yield and reliability.

[0015] like Figure 3B , which is a circuit diagram of the existing second type of write assist circuit 401; the existing second type of write assist circuit 401 includes a delay path composed of multiple inverters 402; in the path of the inverter 402, a signal is taken out from the node EN_NBL and connected to the NMOS tube N401.

[0016] The signal of the node ENB_NBL is inverted by an inverter 402 and then inverted by an NMOS to obtain a signal of the node NBL_FIRE.

[0017] A PMOS is also connected between the node NBL_FIRE and the working voltage, and a gate of the PMOS is connected to the clock signal CLKW.

[0018] A first end of the capacitor C401 is connected to the node NBL_FIRE, and a second end of the capacitor C401 is connected to the drain of the NMOS transistor N401 and outputs a first negative voltage NVSS.

[0019] A coupling voltage suppressing block 403 is connected between the node NBL_FIRE and the ground. The coupling voltage suppressing block 403 includes a plurality of diode-connected NMOSs, and the gate of the topmost NMOS is connected to the clock signal CLKW. The coupling voltage suppressing block 403 can suppress the maximum value of the first negative voltage NVSS, that is, the maximum value of the absolute value, to achieve the effect of voltage clamping, which can avoid Figure 3A The technical problem shown in the figure is that the first negative voltage NVSS generated by the first type of prior art write assist circuit 301 is pulled down too much.

[0020] but Figure 3B The coupling voltage suppression module 403 of the second conventional write assist circuit 401 may bring about a leakage path, which is not conducive to reducing energy efficiency. Summary of the invention

[0021] The technical problem to be solved by the present invention is to provide a write assist circuit that can provide a negative voltage and prevent the negative voltage from being too low, thereby preventing extreme electrical stress, while also avoiding the use of a clamping circuit and thus avoiding the leakage path generated by the clamping circuit, thereby improving energy efficiency.

[0022] In order to solve the above technical problems, the write assist circuit provided by the present invention comprises:

[0023] The delay circuit has an input end connected to a bit line control signal; the delay circuit has a first output end and a second output end, the first output end outputs a first delayed signal, and the second output end outputs a second delayed signal.

[0024] A negative pressure generating module, wherein the second delayed signal is used to provide a positive input voltage for the negative pressure generating module, and the first delayed signal provides a control signal for the negative pressure generating module.

[0025] Under the control of the first delay signal, the negative voltage generating module converts the second delay signal into a first negative voltage required for writing.

[0026] At least the first delay time of the first delay signal is dependent on the operating voltage, and as the operating voltage increases, the first delay time will become smaller. The reduction of the first delay time enables the negative voltage generating module to switch between positive and negative voltages in advance to avoid the first negative voltage being too low and generating electrical stress.

[0027] A further improvement is that the second delay time of the second delay signal also has operating voltage dependence, and the operating voltage dependence of the second delay time is the same as the operating voltage dependence of the first delay time.

[0028] A further improvement is that the delay circuit is divided into a first delay path, a second delay path and a third delay path.

[0029] An input terminal of the first delay path is connected to the bit line control signal, and an output terminal of the first delay path outputs an intermediate delay signal.

[0030] An input end of the second delay path is connected to the intermediate delayed signal, and an output end of the second delay path outputs the first delayed signal.

[0031] An input end of the third delay path is connected to the first delayed signal, and an output end of the third delay path outputs the second delayed signal.

[0032] The first delay path has an operating voltage-dependent circuit structure so that the delay time of the intermediate delay signal has operating voltage dependence, and the operating voltage dependence of the first delay time and the second delay time are both determined by the operating voltage dependence of the delay time of the intermediate delay signal.

[0033] A further improvement is that the first delay path is formed by connecting a plurality of first inverters.

[0034] A further improvement is that the operating voltage dependency circuit structure of the first delay path includes:

[0035] A first resistor is provided between the power input terminal of each first inverter and the operating voltage, the first resistor is a voltage-dependent resistor, and the first resistor reduces the RC delay time of the first inverter as the operating voltage increases;

[0036] Alternatively, a second resistor is provided between the ground terminal of each first inverter and the ground, the second resistor is a voltage-dependent resistor, and the second resistor reduces the RC delay time of the second inverter as the operating voltage increases.

[0037] A further improvement is that the first resistor is formed by connecting a first PMOS, the source of the first PMOS is connected to the working voltage, the drain of the first PMOS is connected to the power input terminal of the first inverter, and the gate of the first PMOS is grounded.

[0038] A further improvement is that the second resistor is formed by connecting the first NMOS, the source of the first NMOS is grounded, the drain of the first NMOS is connected to the ground terminal of the first inverter, and the gate of the first NMOS is connected to the operating voltage.

[0039] A further improvement is that the operating voltage dependency circuit structure of the first delay path includes:

[0040] A voltage dividing circuit, used for dividing the working voltage and obtaining a first voltage dividing signal;

[0041] a first logic circuit, wherein an input end of the first logic circuit is connected to the first voltage-divided signal, and an output end of the first logic circuit outputs a selection signal;

[0042] The first delay path is provided with a plurality of output ends or a plurality of short-circuit paths; the delay time of the intermediate delay signal outputted by each output end of the first delay path is different, and the delay time of the intermediate delay signal outputted by the corresponding output end in the on and off states of each short-circuit path of the first delay path is different;

[0043] The second selection circuit selects the output end or the short-circuit path on the first delay path according to the output selection signal, so that the delay time of the intermediate delay signal has working voltage dependence.

[0044] A further improvement is that the voltage divider circuit includes a series structure of a plurality of diode-connected MOS transistors.

[0045] A further improvement is that the MOS transistor connected to the diode tube in the voltage divider circuit is a second NMOS, and the gate and drain of the second NMOS tube are connected.

[0046] A further improvement is that a second PMOS is connected between the operating voltage and the series structure of each MOS transistor, and the gate of the second PMOS is connected to a clock signal.

[0047] A further improvement is that the second selection circuit includes a switch circuit composed of a first MOS switch tube.

[0048] A further improvement is that the second selection circuit adopts a multiplexer.

[0049] A further improvement is that the first negative voltage is output to a write operation control module of the SRAM;

[0050] The input end of the write operation control module is connected to the data signal to be written;

[0051] The write operation control module converts the first negative voltage into a bit line negative voltage required by the bit line according to the data signal.

[0052] A further improvement is that, in the memory cell array of the SRAM, each of the memory cells in the same column shares a pair of bit lines consisting of a complementary first bit line and a second bit line;

[0053] The write operation control module also converts the external positive voltage into a bit line positive voltage required by the bit line according to the data signal;

[0054] When writing to the memory cell, the bit line negative voltage and the bit line positive voltage, which are in opposite phases to each other, are transmitted to the corresponding first bit line and the second bit line according to the data signal.

[0055] A further improvement is that the negative pressure generating module includes a second MOS switch tube and a first capacitor;

[0056] The gate of the second MOS switch tube is connected to the first delay signal;

[0057] The first end of the first capacitor is connected to the second delayed signal;

[0058] The second end of the first capacitor outputs the first negative voltage;

[0059] The source and drain of the second MOS switch tube are connected between the second end of the first capacitor and the ground.

[0060] A further improvement is that the second MOS switch tube is NMOS.

[0061] The present invention sets at least a structure in the delay circuit of the write assist circuit that makes the first delay time of the first delay signal have working voltage dependence. In this way, when the working voltage increases, the first delay signal can control the negative voltage generating module in advance, so that the negative voltage generating module will release the accumulated negative charge to the bit line in advance. Since the negative voltage finally generated by the negative voltage generating module is related to the working voltage and the time of releasing the negative charge to the bit line, releasing the negative charge to the bit line in advance can prevent the first negative voltage from being too low, that is, prevent the absolute value of the first negative voltage from being too large, while ensuring that the working voltage meets the requirements, thereby avoiding the electrical stress caused by the first negative voltage being too low. Therefore, the present invention can provide a negative voltage and prevent the negative voltage from being too low, thereby preventing the occurrence of extreme electrical stress, thereby also achieving the goal of Design for Reliability (DFR).

[0062] In addition, the present invention does not need to use a clamping circuit to prevent the first negative voltage from being too low, so the present invention can also avoid using a clamping circuit and thus avoid the leakage path generated by the clamping circuit, thereby improving energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0064] Figure 1 It is a circuit diagram of an existing 6T-type SRAM storage cell;

[0065] Figure 2 is a circuit diagram of an existing SRAM using a write assist circuit;

[0066] Figure 3A It is a circuit diagram of the first existing write assist circuit;

[0067] Figure 3B is a circuit diagram of the second existing write assist circuit;

[0068] Figure 4 is a circuit diagram of a write assist circuit according to an embodiment of the present invention;

[0069] Figure 5 yes Figure 4 The waveform diagram of each signal in ;

[0070] Figure 6 is a circuit diagram of a first structure of a first delay path in a write auxiliary circuit according to an embodiment of the present invention;

[0071] Figure 7 is a circuit diagram of a second structure of a first delay path in a write auxiliary circuit according to an embodiment of the present invention;

[0072] Figure 8 It is a circuit diagram of a third structure of the first delay path in the write auxiliary circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0073] like Figure 4 , which is a circuit diagram of a write assist circuit 501 according to an embodiment of the present invention; the write assist circuit 501 according to an embodiment of the present invention comprises:

[0074] The delay circuit has an input end connected to a bit line control signal RBL; the delay circuit has a first output end and a second output end, the first output end outputs a first delayed signal, and the second output end outputs a second delayed signal.

[0075] A negative pressure generating module, wherein the second delayed signal is used to provide a positive input voltage for the negative pressure generating module, and the first delayed signal provides a control signal for the negative pressure generating module.

[0076] Under the control of the first delay signal, the negative voltage generating module converts the second delay signal into a first negative voltage NVSS required for writing.

[0077] At least the first delay time of the first delay signal is dependent on the operating voltage, and as the operating voltage increases, the first delay time will become smaller. The reduction of the first delay time enables the negative voltage generating module to switch between positive and negative voltages in advance to avoid the first negative voltage NVSS being too low and generating electrical stress.

[0078] In the embodiment of the present invention, the second delay time of the second delay signal also has operating voltage dependence, and the operating voltage dependence of the second delay time is the same as the operating voltage dependence of the first delay time.

[0079] The delay circuit is divided into a first delay path 502, a second delay path, and a third delay path.

[0080] An input end of the first delay path 502 is connected to the bit line control signal RBL, and an output end of the first delay path 502 outputs an intermediate delay signal.

[0081] An input end of the second delay path is connected to the intermediate delayed signal, and an output end of the second delay path outputs the first delayed signal.

[0082] An input end of the third delay path is connected to the first delayed signal, and an output end of the third delay path outputs the second delayed signal.

[0083] The first delay path 502 has an operating voltage-dependent circuit structure so that the delay time of the intermediate delay signal has operating voltage dependence, and the operating voltage dependence of the first delay time and the second delay time are both determined by the operating voltage dependence of the delay time of the intermediate delay signal.

[0084] exist Figure 4 In a corresponding embodiment, the first delay path 502 is formed by connecting a plurality of first inverters 503 .

[0085] The second delay path and the third delay path are also formed by connecting a plurality of first inverters 503 .

[0086] Figure 4 In the embodiment, the first output terminal of the delay circuit corresponds to the node EN_NBL. The second output terminal of the delay circuit corresponds to the output terminal of the last inverter 503.

[0087] The negative pressure generating module includes a second MOS switch tube N501 and a first capacitor C501;

[0088] A gate of the second MOS switch tube N501 is connected to the first delay signal.

[0089] A first end of the first capacitor C501 is connected to the second delayed signal.

[0090] The second end of the first capacitor C501 outputs the first negative voltage NVSS;

[0091] The source and drain of the second MOS switch tube N501 are connected between the second end of the first capacitor C501 and the ground. The second MOS switch tube N501 is an NMOS.

[0092] In some embodiments, the operating voltage dependency circuit structure of the first delay path 502 includes:

[0093] A first resistor is provided between the power input terminal of each first inverter 503 and the operating voltage. The first resistor is a voltage-dependent resistor. The first resistor reduces the RC delay time of the first inverter 503 as the operating voltage increases.

[0094] Alternatively, a second resistor is provided between the ground terminal of each first inverter 503 and the ground, and the second resistor is a voltage-dependent resistor. The second resistor reduces the RC delay time of the second inverter as the operating voltage increases.

[0095] like Figure 6 , is a circuit diagram of a first structure of a first delay path in a write assist circuit according to an embodiment of the present invention; in the first structure 502a, the first inverter is individually marked with a mark 503a. The first resistor is formed by connecting a first PMOS 504, the source of the first PMOS 504 is connected to the working voltage, the drain of the first PMOS 504 is connected to the power input terminal of the first inverter 503, and the gate of the first PMOS 504 is grounded.

[0096] The second resistor is formed by connecting the first NMOS 505 , the source of the first NMOS 505 is grounded, the drain of the first NMOS 505 is connected to the ground terminal of the first inverter 503 , and the gate of the first NMOS 505 is connected to the working voltage.

[0097] In some embodiments, the operating voltage dependency circuit structure of the first delay path 502 includes:

[0098] A voltage dividing circuit, used for dividing the working voltage and obtaining a first voltage dividing signal;

[0099] a first logic circuit, wherein an input end of the first logic circuit is connected to the first voltage-divided signal, and an output end of the first logic circuit outputs a selection signal;

[0100] The first delay path 502 is provided with a plurality of output terminals or a plurality of short-circuit paths; the delay time of the intermediate delay signal outputted by each output terminal of the first delay path 502 is different, and the delay time of the intermediate delay signal outputted by the corresponding output terminal in the on and off states of each short-circuit path of the first delay path 502 is different;

[0101] The second selection circuit selects the output end or the short-circuit path on the first delay path 502 according to the output selection signal, so that the delay time of the intermediate delay signal has working voltage dependence.

[0102] In some embodiments, Figure 7 The embodiment of the present invention shown in the figure writes the second structure 502b of the first delay path in the auxiliary circuit; in the second structure 502b, the voltage divider circuit 506 includes a series structure of multiple diode-connected MOS transistors. Preferably, the diode-connected MOS transistor in the voltage divider circuit is a second NMOS, and the gate and drain of the second NMOS are connected. A second PMOS is also connected between the operating voltage and the series structure of each MOS transistor, and the gate of the second PMOS is connected to the clock signal.

[0103] The second selection circuit includes a switch circuit 508 composed of a first MOS switch tube.

[0104] Figure 7 In the embodiment, the first logic circuit does not need to be set. The voltage-divided signal directly passes through the delay path 507 composed of two inverters and is connected to the gate of the first MOS switch tube of the switch circuit 508. When the first MOS switch of the switch circuit 508 is turned on, part of the first inverters 502b in the series path of the first inverters 502b of the first delay path will be short-circuited, thereby realizing the adjustment of the delay time of the intermediate delay signal.

[0105] In some embodiments, Figure 8 The embodiment of the present invention shown in FIG. 1 shows a third structure 502c of the first delay path in the write auxiliary circuit; in the third structure 502c, the second selection circuit uses a multiplexer 508a.

[0106] The voltage divider circuit 506a and Figure 7 The voltage divider circuit 506 in FIG. 5 is the same as that in FIG. 5 , but is separately labeled with a reference numeral 506a.

[0107] Figure 8 The first logic circuit 507a is also provided therein.

[0108] The first inverter 503c on the first delay path is connected to form a structure with multiple output terminals, each output terminal corresponding to a different delay.

[0109] The logical relationship between the input signal and the output signal of the first logic circuit 507a is shown in Table 1.

[0110] Table 1

[0111]

[0112] like Figure 2 As shown, the first negative voltage NVSS is output to the write operation control module 104 of the SRAM.

[0113] The input end of the write operation control module 104 is connected to the data signal Din to be written.

[0114] The write operation control module 104 converts the first negative voltage NVSS into a bit line negative voltage required by the bit line BL or BLB according to the data signal Din.

[0115] In the memory cell array of the SRAM, each of the memory cells in the same column shares a pair of bit lines consisting of a complementary first bit line BL and a second bit line BLB;

[0116] The write operation control module 104 also converts the external positive voltage into the bit line positive voltage required by the bit line according to the data signal Din;

[0117] When writing to the memory cell, the bit line negative voltage and the bit line positive voltage, which are in opposite phases to each other, are transmitted to the corresponding first bit line BL and second bit line BLB according to the data signal Din.

[0118] like Figure 5 As shown, Figure 4 The waveform diagram of each signal in ; Figure 5 The waveforms of three signal lines are included, namely the waveform of the bit line control signal RBL, the signal of the node EN_NBL and the first negative voltage NVSS.

[0119] In adopting Figure 3A When the first conventional write assist circuit is shown, the bit line control signal RBL passes through t d1 The signal of node EN_NBL is obtained by the delay. Figure 5 The falling edge of the bit line control signal RBL is shown in d1 Afterwards, the signal at the node EN_NBL will also generate a falling edge, which will cause the first negative voltage NVSS to generate a relatively large negative voltage value.

[0120] However, after adopting the write assist circuit of the embodiment of the present invention, when the operating voltage increases, the delay between the signal of the node EN_NBL and the bit line control signal RBL will be shortened to t d2 , Figure 5 The falling edge of the bit line control signal RBL is shown in d2 After that, the signal of node EN_NBL will also produce a falling edge. d1 and t d2 It can be seen from the value of the first negative voltage NVSS that t d2The value of the first negative voltage NVSS corresponding to the position will become smaller, and the difference between the two is marked with ΔV. Therefore, the embodiment of the present invention can reduce the value of the first negative voltage NVSS.

[0121] In the embodiment of the present invention, at least a structure is set in the delay circuit of the write assist circuit 501 so that the first delay time of the first delay signal has working voltage dependence. In this way, when the working voltage increases, the first delay signal can control the negative voltage generating module in advance, so that the negative voltage generating module will switch the positive and negative voltages in advance. The early switching of positive and negative voltages can prevent the first negative voltage NVSS from being too low while ensuring that the working voltage meets the requirements, thereby avoiding the electrical stress caused by the first negative voltage NVSS being too low. Therefore, the embodiment of the present invention can provide a negative voltage and prevent the negative voltage from being too low, thereby preventing the occurrence of extreme electrical stress, thereby achieving the reliability design goal.

[0122] In addition, the embodiment of the present invention does not need to use a clamping circuit to prevent the first negative voltage NVSS from being too low, so the embodiment of the present invention can also avoid using a clamping circuit and thus avoid the leakage path generated by the clamping circuit, thereby improving energy efficiency.

[0123] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A write assist circuit, characterized in that: include: A delay circuit, an input end of which is connected to a bit line control signal; The delay circuit has a first output terminal and a second output terminal, the first output terminal outputs a first delayed signal, and the second output terminal outputs a second delayed signal; A negative pressure generating module, wherein the second delayed signal is used to provide a positive input voltage for the negative pressure generating module, and the first delayed signal provides a control signal for the negative pressure generating module; Under the control of the first delay signal, the negative voltage generating module converts the second delay signal into a first negative voltage required for writing; At least the first delay time of the first delay signal is dependent on the operating voltage, and as the operating voltage increases, the first delay time will become smaller. The reduction of the first delay time enables the negative voltage generating module to switch between positive and negative voltages in advance to avoid the first negative voltage being too low and generating electrical stress.

2. The write assist circuit according to claim 1, wherein: The second delay time of the second delay signal also has operating voltage dependency, and the operating voltage dependency of the second delay time is the same as the operating voltage dependency of the first delay time.

3. The write assist circuit according to claim 2, wherein: The delay circuit is divided into a first delay path, a second delay path and a third delay path; An input end of the first delay path is connected to the bit line control signal, and an output end of the first delay path outputs an intermediate delay signal; An input end of the second delay path is connected to the intermediate delayed signal, and an output end of the second delay path outputs the first delayed signal; An input end of the third delay path is connected to the first delay signal, and an output end of the third delay path outputs the second delay signal; The first delay path has an operating voltage-dependent circuit structure so that the delay time of the intermediate delay signal has operating voltage dependence, and the operating voltage dependence of the first delay time and the second delay time are both determined by the operating voltage dependence of the delay time of the intermediate delay signal.

4. The write assist circuit according to claim 3, wherein: The first delay path is formed by connecting a plurality of first inverters.

5. The write assist circuit according to claim 4, wherein: The operating voltage dependency circuit structure of the first delay path includes: A first resistor is provided between the power input terminal of each first inverter and the operating voltage, the first resistor is a voltage-dependent resistor, and the first resistor reduces the RC delay time of the first inverter as the operating voltage increases; Alternatively, a second resistor is provided between the ground terminal of each first inverter and the ground, the second resistor is a voltage-dependent resistor, and the second resistor reduces the RC delay time of the first inverter as the operating voltage increases.

6. The write assist circuit according to claim 5, wherein: The first resistor is formed by connecting first PMOS, the source of the first PMOS is connected to the working voltage, the drain of the first PMOS is connected to the power input terminal of the first inverter, and the gate of the first PMOS is grounded.

7. The write assist circuit according to claim 5, wherein: The second resistor is formed by connecting first NMOS, the source of the first NMOS is grounded, the drain of the first NMOS is connected to the ground terminal of the first inverter, and the gate of the first NMOS is connected to the working voltage.

8. The write assist circuit according to claim 4 or 5, characterized in that: The operating voltage dependency circuit structure of the first delay path includes: A voltage dividing circuit, used for dividing the working voltage and obtaining a first voltage dividing signal; a first logic circuit, wherein an input end of the first logic circuit is connected to the first voltage-divided signal, and an output end of the first logic circuit outputs a selection signal; The first delay path is provided with a plurality of output ends or a plurality of short-circuit paths; the delay time of the intermediate delay signal outputted by each output end of the first delay path is different, and the delay time of the intermediate delay signal outputted by the corresponding output end in the on and off states of each short-circuit path of the first delay path is different; The second selection circuit selects the output end or the short-circuit path on the first delay path according to the output selection signal, so that the delay time of the intermediate delay signal has working voltage dependence.

9. The write assist circuit according to claim 8, wherein: The voltage divider circuit includes a series structure of a plurality of diode-connected MOS transistors.

10. The write assist circuit according to claim 9, wherein: The MOS transistor connected to the diode tube in the voltage divider circuit is a second NMOS, and the gate and drain of the second NMOS tube are connected.

11. The write assist circuit according to claim 10, wherein: A second PMOS is also connected between the operating voltage and the series structure of each of the MOS transistors, and a gate of the second PMOS is connected to a clock signal.

12. The write assist circuit according to claim 8, wherein: The second selection circuit includes a switch circuit composed of a first MOS switch tube.

13. The write assist circuit according to claim 12, wherein: The second selection circuit adopts a multiplexer.

14. The write assist circuit according to claim 1, wherein: The first negative voltage is output to a write operation control module of the SRAM; The input end of the write operation control module is connected to the data signal to be written; The write operation control module converts the first negative voltage into a bit line negative voltage required by the bit line according to the data signal.

15. The write assist circuit according to claim 14, wherein: In the memory cell array of the SRAM, each of the memory cells in the same column shares a pair of bit lines consisting of a complementary first bit line and a second bit line; The write operation control module also converts the external positive voltage into a bit line positive voltage required by the bit line according to the data signal; When writing to the memory cell, the bit line negative voltage and the bit line positive voltage, which are in opposite phases to each other, are transmitted to the corresponding first bit line and the second bit line according to the data signal.

16. The write assist circuit according to claim 1, wherein: The negative pressure generating module includes a second MOS switch tube and a first capacitor; The gate of the second MOS switch tube is connected to the first delay signal; The first end of the first capacitor is connected to the second delayed signal; The second end of the first capacitor outputs the first negative voltage; The source and drain of the second MOS switch tube are connected between the second end of the first capacitor and the ground.

17. The write assist circuit according to claim 16, wherein: The second MOS switch tube is NMOS.

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