Semiconductor packaging method

Abstract

The present application provides a semiconductor packaging method. The semiconductor packaging method includes: forming an encapsulation structure, the encapsulation structure including an encapsulation layer and at least one chip, the encapsulation layer being provided with at least one concave cavity, the at least one chip being disposed within the at least one concave cavity, the front surface of the chip being exposed from the encapsulation layer, and the front surface of the chip being provided with a plurality of solder pads; forming a rewiring structure on the encapsulation structure, the rewiring structure leading out the solder pads of the chip; and placing an insulating film layer having a hollow portion over the rewiring structure, with the surface of the rewiring structure facing away from the chip exposing the insulating film layer through the hollow portion.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method. Background Art

[0002] Common semiconductor packaging technologies, such as chip packaging technologies, mainly include the following process steps: for the process of processing the front side of the chip, the front side of the chip is first mounted on a carrier, hot pressing and plastic sealing are performed, the carrier is peeled off, and then a rewiring structure is formed on the front side of the chip. Thereafter, an insulating layer for protecting the rewiring structure is formed on the rewiring structure, and the insulating layer is exposed on the surface of the rewiring structure facing away from the chip.

[0003] In existing chip packaging technology, when forming an insulating layer on the rewiring structure, the insulating layer is initially formed to completely cover the rewiring structure. Subsequently, the insulating layer is polished to reduce its thickness, exposing the rewiring structure on the surface facing away from the chip. However, the polishing process is time-consuming and affects packaging efficiency. Summary of the Invention

[0004] The present invention provides a semiconductor packaging method. The semiconductor packaging method includes:

[0005] forming an encapsulation structure, the encapsulation structure comprising an encapsulation layer and at least one chip, the encapsulation layer being provided with at least one concave cavity, the at least one chip being disposed in the at least one concave cavity, the front surface of the chip being exposed from the encapsulation layer, and the front surface of the chip being provided with a plurality of solder pads;

[0006] forming a rewiring structure on the encapsulation structure, wherein the rewiring structure leads out the bonding pads of the chip;

[0007] An insulating film layer disposed in the at least one concave cavity is sheathed on the rewiring structure, and the insulating film layer is exposed through the hollow portion on a surface of the rewiring structure facing away from the chip.

[0008] In one embodiment, a height difference between a side of the redistribution structure facing away from the encapsulation structure and a side of the insulation film layer facing away from the encapsulation structure ranges from 0 to 40 μm.

[0009] In one embodiment, the rewiring structure includes multiple conductive structures, and the insulating film layer is provided with multiple hollow portions, which correspond one to one with the conductive structures, and the side of the conductive structure facing away from the chip is exposed through the corresponding hollow portions.

[0010] In one embodiment, the conductive structure includes a trace structure connected to the pad and a conductive protrusion located on a side of the trace structure facing away from the chip;

[0011] The inner surface of the hollow portion is provided with a step structure, the trace structure is located in the hollow portion and on a side of the step structure close to the chip, and the conductive protrusion is located in the hollow portion and surrounded by the step structure.

[0012] In one embodiment, the insulating film layer is made of a flexible material.

[0013] In one embodiment, before the insulating film layer provided with the hollow portion is covered on the rewiring structure, the semiconductor packaging method further comprises: preparing the insulating film layer;

[0014] The preparing of the insulating film layer comprises:

[0015] Providing an insulating material layer and a stamping die, wherein the stamping die is provided with a stamping portion, and the stamping portion has the same shape as the rewiring structure;

[0016] The insulating material layer is punched by using the punching part of the punching die to form the hollow portion on the insulating material layer to obtain the insulating film layer.

[0017] In one embodiment, before the insulating film layer provided with the hollow portion is covered on the rewiring structure, the semiconductor packaging method further comprises:

[0018] An optical positioning instrument is used to position the insulating film layer.

[0019] In one embodiment, forming the encapsulation structure comprises:

[0020] Mounting the chip on a carrier board with the front side of the chip facing the surface of the carrier board;

[0021] forming an encapsulation layer, wherein the encapsulation layer covers the carrier and encapsulates the chip;

[0022] The carrier plate is peeled off to obtain the encapsulation structure.

[0023] In one embodiment, the rewiring structure is in direct contact with the bonding pad of the chip; or,

[0024] Before forming the redistribution structure on the encapsulation structure, the semiconductor packaging method further includes:

[0025] At least one trace layer is formed on the encapsulation layer, and the redistribution structure is electrically connected to the bonding pad of the chip through the at least one trace layer.

[0026] In one embodiment, the size of the insulating film layer is larger than the size of the encapsulation structure, and the semiconductor packaging method further includes:

[0027] The edges of the insulating film layer are cut so that the orthographic projections of the insulating film layer after cutting on the encapsulation structure all fall on the encapsulation structure.

[0028] The main technical effects achieved by the embodiments of the present application are:

[0029] The semiconductor packaging method provided in the embodiment of the present application is to put a pre-prepared insulating film layer on the rewiring structure after the rewiring structure is formed, and the insulating film layer is exposed on the surface of the rewiring structure away from the chip, so there is no need to grind the insulating film layer, which can save the time for grinding the insulating film layer, improve the packaging efficiency, and reduce production costs; at the same time, it can avoid the problem of poor thickness uniformity of the insulating film layer caused by the grinding process, and can avoid grinding the conductive structure during grinding, which will damage the chip's solder pad due to the stress on the conductive structure, and help improve the quality of the packaged product. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

[0031] Figure 2 is a flow chart of forming an encapsulation structure provided by an exemplary embodiment of the present application;

[0032] Figure 3 is a structural schematic diagram of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0033] Figure 4 is a structural schematic diagram of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0034] Figure 5 is a schematic structural diagram of an encapsulation structure provided by an exemplary embodiment of the present application;

[0035] Figure 6 is a cross-sectional view of a third intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application;

[0036] Figure 7 is a cross-sectional view of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0037] Figure 8 is a cross-sectional view of an insulating film layer provided by an exemplary embodiment of the present application;

[0038] Figure 9 is a cross-sectional view of an insulating material layer provided by an exemplary embodiment of the present application;

[0039] Figure 10 is a cross-sectional view of a stamping die provided by an exemplary embodiment of the present application;

[0040] Figure 11 is a cross-sectional view of a semiconductor package structure provided by another exemplary embodiment of the present application. Specific embodiments

[0041] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0042] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0043] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0044] The following embodiments of the present application are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0045] The present invention provides a semiconductor packaging method. Figure 1 The semiconductor packaging method includes the following steps 110 to 130.

[0046] In step 110, an encapsulation structure is formed, which includes an encapsulation layer and at least one chip. The encapsulation layer is provided with at least one concave cavity, and the at least one chip is arranged in the at least one concave cavity. The front side of the chip is exposed to the encapsulation layer, and the front side of the chip is provided with multiple solder pads.

[0047] In step 120 , a rewiring structure is formed on the encapsulation structure, wherein the rewiring structure leads out the bonding pads of the chip.

[0048] In step 130 , an insulating film layer provided with a hollow portion is covered on the rewiring structure, and the insulating film layer is exposed through the hollow portion on a surface of the rewiring structure facing away from the chip.

[0049] In the semiconductor packaging method provided in the embodiment of the present application, the insulating film layer is prepared in advance, and the insulating film layer is put on the rewiring structure, and the insulating film layer is exposed on the surface of the rewiring structure facing away from the chip. Therefore, there is no need to grind the insulating film layer, which can save the time for grinding the insulating film layer, improve the packaging efficiency, and reduce production costs. At the same time, it can avoid the problem of poor thickness uniformity of the insulating film layer caused by the grinding process, and can avoid grinding the conductive structure during grinding, which can avoid damaging the chip's solder pads due to stress on the conductive structure, and help improve the quality of the packaged product.

[0050] The following is a detailed introduction to each step of the semiconductor packaging method provided in the embodiment of the present application.

[0051] In step 110, an encapsulation structure is formed, which includes an encapsulation layer and at least one chip. The encapsulation layer is provided with at least one concave cavity, and the at least one chip is arranged in the at least one concave cavity. The front side of the chip is exposed to the encapsulation layer, and the front side of the chip is provided with multiple solder pads.

[0052] In one embodiment, the concave cavities on the encapsulation layer may correspond to the chips one by one, and the chips are located in the corresponding concave cavities.

[0053] In one embodiment, see Figure 2 The step 110 of forming the encapsulation structure includes the following steps 111 to 113.

[0054] In step 111 , the chip is mounted on a carrier board, with the front side of the chip facing the surface of the carrier board.

[0055] Through step 111, the following can be obtained: Figure 3 The first intermediate structure is shown. Figure 3 In the embodiment shown, a plurality of chips 20 are mounted on the carrier 10. In other embodiments, the number of chips 20 mounted on the carrier 10 may be one.

[0056] In one embodiment, the carrier 10 includes a mounting area for mounting the chip 20. The shape of the mounting area is designed based on the layout of the chip 20 on the entire carrier 10 and can include a circular, rectangular, or other shape. The carrier may include multiple mounting areas.

[0057] In one embodiment, chip 20 can be obtained by cutting a silicon wafer. The silicon wafer has an active surface, and the active surface of the silicon wafer is provided with a bonding pad. The silicon wafer can be cut by mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer, the back surface of the silicon wafer opposite the active surface can be ground using a grinding device to achieve a specified thickness.

[0058] The bonding pads of chip 20 are formed by the conductive electrodes that lead from the chip's internal circuits to the chip's surface. Multiple bonding pads may be provided on the front of chip 20. The bonding pads are provided on the conductive electrodes of chip 20 to lead out the conductive electrodes of chip 20.

[0059] In one embodiment, the carrier plate 10 may be circular, rectangular, or other shapes. The carrier plate 10 may be made of an iron-nickel constant expansion alloy, or may be made of stainless steel, polymer, or the like.

[0060] In one embodiment, the chip 20 can be mounted on the carrier 10 via an adhesive layer, and the adhesive layer can be made of an easily peelable material so that the chip 20 can be peeled off from the carrier 10 later. For example, the adhesive layer can be made of a thermal separation material that can lose its viscosity by heating.

[0061] In one embodiment, before step 111 of mounting the chip on a carrier, the semiconductor packaging method further includes: forming a protection layer on the front surface of the chip.

[0062] In the subsequent step 112 of forming the encapsulation layer 30, since the encapsulation layer 30 requires high pressure molding during molding, the encapsulation material forming the encapsulation layer 30 during this process can easily penetrate between the carrier 10 and the chip 20. By forming a protective layer on the front surface of the chip 20, the protective layer can prevent the encapsulation material from penetrating the surface of the chip 20. Moreover, even if the encapsulation material penetrates the protective layer during the formation of the encapsulation layer 30, after the carrier 10 and the chip 20 are peeled off, the surface of the protective layer can be directly treated by chemical means or grinding without directly contacting the front surface of the chip 20, thereby avoiding damage to the solder pads on the front surface of the chip 20.

[0063] In step 112 , an encapsulation layer is formed, and the encapsulation layer covers the carrier and encapsulates the chip.

[0064] Through step 112, the following can be obtained: Figure 4 The second intermediate structure is shown.

[0065] See also Figure 4 The encapsulation layer 30 is formed on the chip 20 and the exposed carrier 10 to encapsulate the chip 20 to reconstruct a flat structure, so that after the carrier 10 is peeled off, rewiring and packaging can continue on the reconstructed flat structure.

[0066] In one embodiment, before forming the encapsulation layer 30, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the chip 20 and the carrier 10, so that the encapsulation layer 30 can be more closely connected to the chip 20 and the carrier 10 without delamination or cracking.

[0067] In one embodiment, the encapsulation layer 30 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0068] In one embodiment, the step 120 of forming the encapsulation layer may include the following steps:

[0069] First, an encapsulation structure is formed, which covers the carrier and encapsulates the chip. In this step, the thickness of the encapsulation structure is greater than the thickness of the chip 20, so that the encapsulation structure completely encapsulates the chip 20.

[0070] Then, the side of the encapsulation structure facing away from the carrier is thinned to obtain the encapsulation layer. In this step, the encapsulation structure can be thinned by a grinding process to a specified thickness.

[0071] In step 113 , the carrier is peeled off to obtain the encapsulated structure.

[0072] Through step 113, the following can be obtained: Figure 5 The encapsulated structure shown.

[0073] In one embodiment, the carrier 10 can be mechanically peeled directly from the encapsulation layer 30 and the chips 20. In another embodiment, if the chips 20 and the carrier 10 are bonded by an adhesive layer, and the adhesive layer is made of a thermally separable material, the adhesive layer can be heated to reduce its viscosity, thereby allowing the carrier 10 to be peeled off. After the carrier 10 is peeled off, the front surfaces of the chips 20 are exposed.

[0074] In one embodiment, when a protection layer is formed on the front surface of the at least one chip 20 , the protection layer is provided with openings for exposing the bonding pads on the front surface of each chip 20 .

[0075] In step 120 , a rewiring structure is formed on the encapsulation structure, wherein the rewiring structure leads out the bonding pads of the chip.

[0076] Through step 120, the following can be obtained: Figure 6 The third intermediate structure is shown.

[0077] In one embodiment, see Figure 6The rewiring structure 40 includes a plurality of conductive structures 41, each of which includes a trace structure 411 electrically connected to the bonding pads of the chip 20 and a conductive stud 412 located on a side of the trace structure 411 facing away from the chip 20. The trace structure 411 is electrically connected to the bonding pads of the chip 20, leading the bonding pads of the chip 20 out. The conductive stud 412 is provided to facilitate electrical connection to other components.

[0078] In one embodiment, when forming the rewiring structure, a trace structure 411 is first formed on the encapsulation structure, and then a conductive protrusion 412 is formed on the trace structure 411. In some embodiments, the trace structure 411 and the conductive protrusion 412 can be formed by metal sputtering, electrolytic plating, electroless plating, etc.

[0079] In step 130 , an insulating film layer provided with a hollow portion is covered on the rewiring structure, and the insulating film layer is exposed through the hollow portion on a surface of the rewiring structure facing away from the chip.

[0080] Through step 130, the following can be obtained: Figure 7 The insulating film layer 50 is used to protect the rewiring structure 40 and prevent the rewiring structure 40 from being damaged and affecting the electrical connection between the rewiring structure 40 and other components.

[0081] In one embodiment, the insulating film layer 50 may be one or more layers of insulating material. The material of the insulating film layer 50 may be a plastic film, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties. In one embodiment, an organic or inorganic filler may also be added to the insulating film layer material.

[0082] In the embodiment of the present application, the surface of the rewiring structure 40 facing away from the chip 20 is exposed to the insulating film layer 50. This means that the surface of the rewiring structure 40 facing away from the chip 20 is flush with the surface of the insulating film layer 50 facing away from the chip 20, or the distance between the surface of the rewiring structure 40 facing away from the chip 20 and the encapsulation structure is slightly greater than the distance between the surface of the insulating film layer 50 facing away from the chip 20 and the encapsulation structure. This facilitates electrical connection of the rewiring structure 40 to other components.

[0083] In one embodiment, the height difference between the side of the rewiring structure 40 facing away from the encapsulation structure and the side of the insulating film layer 50 facing away from the encapsulation structure ranges from 0 to 40 μm. This configuration can avoid a large height difference between the surface of the rewiring structure 40 facing away from the encapsulation structure and the surface of the insulating film layer 50 facing away from the encapsulation structure, which may cause the rewiring structure to break when other rewiring structures are subsequently formed on the insulating film layer, or cause the surface flatness of the resulting semiconductor package structure to be poor. In some embodiments, the height difference between the side of the rewiring structure 40 facing away from the encapsulation structure and the side of the insulating film layer 50 facing away from the encapsulation structure ranges from 0, 10 μm, 20 μm, 30 μm, 40 μm, etc.

[0084] In one embodiment, see Figure 8 The insulating film layer 50 is provided with a plurality of hollow portions 51, each of which corresponds to the conductive structure 41. The side of the conductive structure 41 facing away from the chip 20 is exposed through the corresponding hollow portion 51. In this way, each conductive structure 41 can be exposed through the corresponding hollow portion 51.

[0085] In one embodiment, the inner surface of the hollow portion 51 is provided with a step structure 511. The trace structure 411 is located within the hollow portion 51 and on a side of the step structure 511 close to the chip. The conductive protrusion 412 is located within the hollow portion 51 and surrounded by the step structure 511. The sidewalls of the trace structure 411 can conform to the inner surface of the hollow portion 51, and the sidewalls of the conductive protrusion 412 can conform to the wall of the step structure 511. Therefore, after the insulating film layer 50 is sheathed on the conductive structure 41, the insulating film layer 50 will not move relative to the conductive structure 41.

[0086] In some embodiments, in a direction parallel to the extension direction of the insulating film layer, the size of the trace structure 411 is larger than the size of the conductive boss 412, the size of the hollow portion 51 located on the side of the step structure 511 facing the chip 10 is larger than the size of the portion enclosed by the step structure 511, and the orthographic projection of the portion enclosed by the step structure 511 on the encapsulation structure completely falls within the orthographic projection of the portion located on the side of the step structure 511 facing the chip 10 on the encapsulation structure.

[0087] In one embodiment, the insulating film layer 50 is made of a flexible material. For example, the insulating film layer 50 may be an organic insulating material. By making the insulating film layer 50 a flexible material, the insulating film layer 50 has a certain degree of elasticity, and the hollow portion 51 of the insulating film layer 50 is more easily fitted onto the corresponding conductive structure 41.

[0088] In one embodiment, before step 130 of covering the insulating film layer provided with the hollow portion on the rewiring structure, the semiconductor packaging method further includes: preparing the insulating film layer.

[0089] In some embodiments, preparing the insulating film layer comprises the following steps:

[0090] First, an insulating material layer and a stamping die are provided. The stamping die is provided with a stamping portion, and the stamping portion has the same shape as the rewiring structure.

[0091] See also Figure 9 , the insulating material layer 60 has no hollowing, that is, the insulating material layer is a complete film layer. In some embodiments, when forming the insulating material layer, a carrier board can be provided, and the insulating material layer 60 can be formed on the carrier board by lamination, spin coating, printing, molding, or other suitable methods, and then the carrier board can be peeled off.

[0092] See also Figure 10 The stamping die 70 includes a main body 71 and a plurality of stamping parts 72 disposed on one side of the main body 71. The main body 71 may be plate-shaped. The plurality of stamping parts 72 correspond one-to-one to the plurality of conductive structures 41. The stamping parts 72 include a first stamping part 721 and a second stamping part 722 located on one side of the first stamping part 721. The first stamping part 721 may have the same shape and size as the trace structure 411, and the second stamping part 722 may have the same shape and size as the conductive protrusion 412. The first stamping part 721 is connected to the main body 71, and the second stamping part 722 is located on the side of the first stamping part 721 facing away from the main body 71.

[0093] Subsequently, the insulating material layer is punched using the punching part of the punching die to form the hollow portion on the insulating material layer, thereby obtaining the insulating film layer.

[0094] Through the above steps, we can get Figure 7 The insulating film layer shown.

[0095] When the insulating material layer 60 is punched by the punching part 72 of the punching die, some material of the insulating material layer will be lost, so the size of the hollow portion 51 formed on the insulating material layer 60 is slightly larger than the size of the conductive structure 41, so that the conductive structure 41 can be accommodated in the hollow portion 51.

[0096] In one embodiment, before step 130 of covering the insulating film layer having the hollow portion on the rewiring structure, the semiconductor packaging method further comprises: positioning the insulating film layer using an optical aligner.

[0097] By using an optical positioning device to position the insulating film layer 50, the hollow portion 51 of the insulating film layer 50 can be more accurately aligned with the corresponding conductive structure 41, thereby avoiding the problem that the insulating film layer 50 cannot be placed on the rewiring structure 40 due to inaccurate alignment between the hollow portion 51 of the insulating film layer 50 and the corresponding conductive structure 41.

[0098] Figure 7 In the semiconductor package structure shown, the rewiring structure 40 is in direct contact with the bonding pad of the chip 20. In other embodiments, before forming the rewiring structure on the encapsulation structure, the semiconductor package method further includes:

[0099] At least one trace layer is formed on the encapsulation layer, and the redistribution structure is electrically connected to the bonding pad of the chip through the at least one trace layer.

[0100] That is, at least one trace layer is formed between the rewiring structure 40 and the encapsulation structure. Each trace layer may be covered with an insulating film layer, and each trace layer may have conductive studs formed on the side facing away from the encapsulation structure, with the insulating film layer exposed on the surface of the conductive studs facing away from the encapsulation structure. The steps of forming the trace layer, the conductive studs, and covering the trace layer with the insulating film layer can be found in the descriptions of steps 120 and 130, and will not be further elaborated here.

[0101] See also Figure 11 A trace layer 81 and a conductive protrusion 82 located on the side of the trace layer 81 facing away from the encapsulation structure are formed between the rewiring structure 40 and the encapsulation structure. An insulating film layer 83 is provided on the trace layer 82 and the conductive protrusion 82. The surface of the conductive protrusion 82 facing away from the encapsulation structure is exposed through a hollow portion 831 on the insulating film layer 83 and is electrically connected to the conductive structure 41. Figure 11 Only one trace layer is formed between the rewiring structure 40 and the encapsulation structure as an example for illustration. In other embodiments, multiple trace layers may be formed between the rewiring structure 40 and the encapsulation structure.

[0102] By covering each trace layer with an insulating film layer and exposing the insulating film layer on the surface of the rewiring structure away from the chip, there is no need to grind the insulating film layer corresponding to each trace layer, which can save the time for grinding the insulating film layer, improve packaging efficiency, and reduce production costs; at the same time, it can avoid the problem of poor thickness uniformity of the insulating film layer caused by the grinding process, and can avoid grinding the conductive structure during grinding and applying stress to the conductive structure and then damaging the chip's solder pad, which helps to improve the quality of the packaged product.

[0103] In one embodiment, the size of the insulating film layer is larger than the size of the encapsulation structure, and the semiconductor packaging method further includes:

[0104] The edges of the insulating film layer are cut so that the orthographic projections of the insulating film layer after cutting on the encapsulation structure all fall on the encapsulation structure.

[0105] By cutting the edge of the insulating film layer, the edge of the insulating film layer can be prevented from exceeding the encapsulation structure, thereby making the appearance of the obtained semiconductor package structure more regular.

[0106] In one embodiment, the package structure includes two or more chips, and the semiconductor packaging method further includes: cutting the semiconductor package structure obtained in the above steps to obtain multiple sub-package structures, each sub-package structure including only one chip.

[0107] In some embodiments, the process of cutting the semiconductor package structure and the process of cutting the edge of the insulating film layer can be performed simultaneously.

[0108] It should be noted that the drawings provided in the embodiments of the present application are only for illustration and may differ from the actual structure. For example, the drawings do not illustrate the solder pads on the front of the chip, but in reality the solder pads on the front of the chip are electrically connected to the rewiring structure.

[0109] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0110] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0111] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor packaging method, characterized in that: include: forming an encapsulation structure, the encapsulation structure comprising an encapsulation layer and at least one chip, the encapsulation layer being provided with at least one concave cavity, the at least one chip being disposed in the at least one concave cavity, the front surface of the chip being exposed from the encapsulation layer, and the front surface of the chip being provided with a plurality of solder pads; forming a rewiring structure on the encapsulation structure, wherein the rewiring structure leads out the bonding pads of the chip; An insulating film layer provided with a hollow portion is placed on the rewiring structure, with the surface of the rewiring structure facing away from the chip exposing the insulating film layer through the hollow portion; the hollow portion penetrates the insulating film layer; the rewiring structure includes a plurality of conductive structures, a plurality of the hollow portions are provided on the insulating film layer, the hollow portions corresponding to the conductive structures one by one, and the side of the conductive structure facing away from the chip is exposed through the corresponding hollow portion; Before the insulating film layer provided with the hollow portion is covered on the rewiring structure, the semiconductor packaging method further comprises: preparing the insulating film layer; the preparing the insulating film layer comprises: Providing an insulating material layer and a stamping die, wherein the stamping die is provided with a stamping portion, and the stamping portion has the same shape as the rewiring structure; The insulating material layer is punched by using the punching part of the punching die to form the hollow portion on the insulating material layer to obtain the insulating film layer.

2. The semiconductor packaging method according to claim 1, wherein: A height difference between a side of the redistribution structure facing away from the encapsulation structure and a side of the insulation film layer facing away from the encapsulation structure ranges from 0 to 40 μm.

3. The semiconductor packaging method according to claim 1, wherein: The conductive structure includes a trace structure connected to the pad and a conductive protrusion located on a side of the trace structure away from the chip; The inner surface of the hollow portion is provided with a step structure, the trace structure is located in the hollow portion and on a side of the step structure close to the chip, and the conductive protrusion is located in the hollow portion and surrounded by the step structure.

4. The semiconductor packaging method according to claim 1, wherein: The insulating film layer is made of flexible material.

5. The semiconductor packaging method according to claim 1, wherein: Before the insulating film layer provided with the hollow portion is covered on the rewiring structure, the semiconductor packaging method further includes: An optical positioning instrument is used to position the insulating film layer.

6. The semiconductor packaging method according to claim 1, wherein: The forming of the encapsulation structure comprises: Mounting the chip on a carrier board with the front side of the chip facing the surface of the carrier board; forming an encapsulation layer, wherein the encapsulation layer covers the carrier and encapsulates the chip; The carrier plate is peeled off to obtain the encapsulation structure.

7. The semiconductor packaging method according to claim 1, wherein: The rewiring structure is in direct contact with the bonding pad of the chip; or, Before forming the redistribution structure on the encapsulation structure, the semiconductor packaging method further includes: At least one trace layer is formed on the encapsulation layer, and the redistribution structure is electrically connected to the bonding pad of the chip through the at least one trace layer.

8. The semiconductor packaging method according to claim 1, wherein: The size of the insulating film layer is larger than the size of the encapsulation structure, and the semiconductor packaging method further includes: The edges of the insulating film layer are cut so that the orthographic projections of the insulating film layer after cutting on the encapsulation structure all fall on the encapsulation structure.

Images