Air gap isolation structure

Abstract

The present disclosure relates to semiconductor structures, and more particularly to air gap isolation structures and methods for fabricating the same. The structure includes: a bulk substrate material; a first air gap isolation structure disposed within the bulk substrate material and having a first aspect ratio; and a second air gap isolation structure disposed within the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to air gap isolation structures and fabrication methods. Background Art

[0002] Radio frequency (RF) devices are used in many different types of communications applications. For example, RF devices are used in cellular phones, which have wireless communication components such as switches, MOSFETs, transistors, and diodes. Currently, there is an increasing demand for wireless communication components that offer higher performance and lower price points. For example, a significant portion of the manufacturing cost of RF switches is the cost of designing for extremely high linearity to achieve very low harmonic distortion and meet product specifications.

[0003] RF devices are typically fabricated on high-resistivity silicon wafers or substrates to achieve the required RF linearity. State-of-the-art trap-rich silicon-on-insulator (SOI) high-resistivity substrates offer excellent vertical isolation and linearity, but SOI wafers can represent up to 50% of the total manufacturing cost, as they can cost 5 to 10 times more than high-resistivity non-SOI substrates. That is, the total normalized manufacturing cost of an RF device formed on an SOI wafer might be 1.0, while the total normalized manufacturing cost of a similar device formed on a high-resistivity non-SOI bulk wafer might be 0.6. Devices built on bulk Si substrates are known to suffer from low linearity, harmonics, noise, and leakage current, any of which degrade device performance, necessitating the higher SOI wafer costs. Summary of the Invention

[0004] In one aspect of the present disclosure, a structure includes a bulk substrate material; a first air gap isolation structure located in the bulk substrate material and including a first aspect ratio; and a second air gap isolation structure located in the bulk substrate material and including a second aspect ratio different from the first aspect ratio.

[0005] In one aspect of the present disclosure, a structure includes: a bulk substrate material; at least one air gap isolation structure located in the bulk substrate material; a first insulator material located on all surfaces of the at least one air gap isolation structure; and a second insulator material plugging at least one opening in the first insulator material and sealing the at least one air gap isolation structure.

[0006] In one aspect of the present disclosure, a structure includes: a first air-gap isolation structure in a semiconductor material, located between active devices, the surface of the first air-gap isolation structure being lined with an insulator material, the insulator material including at least one entry point independent of other patterning of the semiconductor material; a second air-gap isolation structure in the semiconductor material, located between banks of the active devices, the surface of the second air-gap isolation structure being lined with an insulator material, the insulator material including multiple entry points independent of the other patterning of the semiconductor material; at least one pillar located in the second air-gap isolation structure; and a second insulator material plugging the at least one opening of the first air-gap isolation structure and the multiple openings of the second air-gap isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0008] Figure 1 Shown are, among other features, shallow trench isolation (STI) structures and corresponding fabrication processes according to aspects of the present disclosure.

[0009] Figure 2 An oxide liner within an STI structure and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0010] Figure 3 Shown are, among other features, an STI structure filled with material and a corresponding fabrication process according to aspects of the present disclosure.

[0011] Figure 4 A liner material over a material in an STI structure and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0012] Figure 5 Active and passive components and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0013] Figure 6 A masking material having openings that expose material of an STI structure and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0014] Figure 7 Shown are, among other features, trench-selective STI structures from which material has been removed and corresponding fabrication processes according to aspects of the present disclosure.

[0015] Figure 8An air gap isolation structure and corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure relates to semiconductor structures, and more particularly to air gap isolation structures and methods of manufacturing. The air gap isolation structure can be used for radio frequency (RF) FETs or NPNs, such as FET switches. In an embodiment, the air gap isolation structure can be defined by a shallow trench isolation (STI) structure (e.g., a trench) throughout the shallow trench isolation region. By using an STI structure, it is now possible to have a well-defined air gap isolation structure with a larger air-to-dimensional ratio (compared to known air gap structures), thereby improving RF isolation (e.g., lower capacitance). In addition, the methods and structures described herein reduce or eliminate the shallow trench isolation effect that can occur at the interface of the oxide and substrate material at the corners of the STI structure.

[0017] In one embodiment, the air gap isolation structure can be defined by an STI structure within the bulk substrate. In this way, the air gap can be extended throughout the shallow trench isolation region, thereby utilizing existing contact via films for pinch-off (e.g., using boron phosphosilicate (BPSG)). Furthermore, the aspect ratio of the STI structure can be varied.

[0018] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, typically, methods and tools are used to form structures having micron and nanometer dimensions. Methods (i.e., techniques) for manufacturing the structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on wafers and implemented in a film of material patterned on top of the wafer by a photolithographic process. In particular, the manufacture of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film with respect to the mask.

[0019] Figure 11 , and a corresponding fabrication process are shown. More specifically, structure 10 includes a substrate 12 comprised of a semiconductor material. In an embodiment, substrate 12 includes a bulk substrate comprised of any suitable semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. A plurality of pad films 14, 16 are formed on substrate 12. For example, pad films 14, 16 may be a pad oxide film and a pad nitride film formed on the pad oxide film. Pad films 14, 16 may be deposited by conventional deposition methods, such as chemical vapor deposition (CVD).

[0020] Still refer to Figure 1 , a plurality of STI structures (trenches) 18 are formed in the substrate 12 throughout the STI region (e.g., the STI levels of the structure). The plurality of STI trenches 18 can have various aspect ratios, depending on design parameters and the placement of the device on the substrate 12. For example, smaller STI trenches 18 can be placed between transistors in a single bank; while larger STI trenches 18 can be placed between the separated banks themselves. In an embodiment, the larger STI trenches 18 can have a diameter of 200 microns or more; however, other sizes are also contemplated herein. The plurality of STI trenches 18 can have different aspect ratios because they are formed by the STI formation process and are not limited by the pinch-off process used by conventional air gap formation processes, where conventional air gap formation processes require narrow trenches to form cavities that are all the same size.

[0021] A plurality of STI trenches 18 are formed by conventional photolithography and etching methods known to those skilled in the art. As described herein, the STI trenches 18 are formed within the STI region and can therefore be formed using the same process as any other STI structures formed in the substrate. For example, a resist formed on the liner film 16 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), is used to form one or more STI trenches 18 in the substrate 12 through the openings in the resist. The resist can then be removed by a conventional oxygen ashing process or other known stripping agents.

[0022] like Figure 2As shown, an oxide liner 20 can be formed on the exposed substrate 12 within the STI trench 18. In an embodiment, an oxidation process can be used to form the oxide liner 20 having a uniform thickness. The oxidation process can be a thermal oxidation that produces a thin layer of oxide (e.g., SiO2) on the exposed surface of the substrate 12. The oxide liner 20 can be sufficiently robust, for example, having a size and coverage that can withstand corrosion during subsequent etching processes with different chemistries as described herein. For example, the oxide liner 20 can have a thickness of approximately 50 nm; however, other sizes are contemplated herein.

[0023] exist Figure 3 In the embodiment, the STI trenches 18 are filled with polysilicon material 22. In an embodiment, the polysilicon material 22 can be formed on top of the oxide liner 20 by a deposition process. Any residual material on the liner film 16 outside the STI trenches 18 can be removed by a chemical mechanical polishing (CMP) process known in the art, and no further explanation is required to fully understand the present disclosure. A polysilicon recess can also be performed to recess the polysilicon material 22 below at least the surface of the liner film 16. In this recess process, the liner film 16 acts as a mask to protect the underlying material.

[0024] Figure 4 An oxide material 24 is shown above the polysilicon material 22, thereby forming the STI structures 18a, 18b. In an embodiment, the oxide material 24 can be formed by an oxidation process, such as thermal oxidation, which, in combination with the oxide liner 20, can completely encapsulate the polysilicon material 22 within the STI trenches to form the STI structures 18a, 18b. That is, the oxide material 24 and the oxide liner 20 line all surfaces of the polysilicon material 22. The oxide material 24 can be located above the top surface of the substrate 12 and be sufficiently robust, such as having a size and coverage that allows it to survive removal of the liner films 14, 16 and subsequent device fabrication processes (e.g., fabrication of FETs). For example, the thickness of the oxide material 24 can be greater than about 50 nm; however, other dimensions are contemplated herein.

[0025] Figure 5 1. The device formed on the substrate and the corresponding manufacturing process are shown, among other features. In particular, active device 26 is formed on the side of the filled and encapsulated STI structure 18a; while passive device 28 can be formed on the filled and encapsulated STI structure 18b. As an example, active device 26 can be a plurality of transistors 50, and passive device 28 can be a resistor. Polysilicon material 22 below passive device 28 can act as a shallow trench isolation structure, providing thermal ballast (e.g., thermal coupling) between the resistor and substrate 12.

[0026] Before forming the active devices 26 and the passive devices 28, the liner films 14 and 16 can be removed by conventional etching or CMP processes. Thereafter, the active devices 26 and the passive devices 28 can be formed by conventional CMOS processes. For example, the active device 26 can be formed using a conventional gate formation process, such as a gate-first process or a replacement gate process. Illustratively and as a non-limiting example, in a gate-first process, a conventional CMOS manufacturing process known in the art is used to deposit and pattern the gate dielectric material 26a and the polysilicon material 26b, so that the present disclosure can be fully understood without further explanation. The gate dielectric material 26a can be an oxide material or a high-k gate dielectric material, such as HfO2. Sidewall material 26c (e.g., nitride) can be formed on the patterned gate dielectric material 26a and polysilicon material 26b using a conventional deposition process and a subsequent anisotropic etching process. The passive device 28 can be manufactured using the polysilicon material 26b and the sidewall material 26c. Source and drain regions 28 d are formed on the sides of active device 26 using a conventional ion implantation process, or alternatively, raised source and drain regions are formed by a doping epitaxial process.

[0027] Still refer to Figure 5 , forming silicide contacts 30 on the active devices 26 (e.g., source and drain regions 26d and polysilicon material 26b). Those skilled in the art will appreciate that the silicidation process begins by depositing a thin layer of transition metal, such as nickel, cobalt, or titanium, on top of the fully formed and patterned device. After depositing the material, the structure can be heated to cause the transition metal to react with exposed silicon (or other semiconductor materials described herein) in the active regions of the semiconductor device (e.g., source and drain regions 26d and polysilicon material 26b), thereby forming low-resistance transition metal silicide contacts 30. After the reaction, any remaining transition metal can be removed by chemical etching, leaving silicide contacts in the active regions of the device.

[0028] exist Figure 6 , a masking material 32 may be formed over devices 26, 28, followed by an etching process to form openings 34 that expose the polysilicon material 22 in selected STI structures 18a. In an embodiment, the etching process forms openings in the oxide material 24 to expose the underlying polysilicon material 22. The etching process may be performed by conventional photolithography and etching processes known in the art and as already described herein. As further shown, a different number of openings 34 may be provided for each of the different STI structures 18a, depending on the size of the initial STI trenches. For example, multiple openings 34 may be provided in larger STI trenches, thereby allowing for easier and / or faster drainage (e.g., removal) of the polysilicon material in a subsequent etching process.

[0029] like Figure 7 As further shown, polysilicon material 22 can be removed from the STI structure to form air gap 36. Oxide material 24 and oxide liner 20 line or remain on all surfaces of air gap 36. Polysilicon material 22 can be removed through opening 34 using a dry chemistry (e.g., XeF2) or a wet chemistry (e.g., TMAH). In an embodiment, oxide liner 20 can be sufficiently strong to protect the underlying material of substrate 12 from corrosion during the removal of polysilicon material 22 using dry or wet chemistry. After removing polysilicon material 22 from within the STI structure (structure 18a), masking material 32 can be removed.

[0030] In an embodiment, some polysilicon material 22 may remain in the larger STI trenches to form pillar structures 38. Pillar structures 38 provide support for the air gaps so that they do not collapse. It will be appreciated by those skilled in the art that pillar structures 38 may be "hourglass" shaped, for example, due to the isotropic nature of the XeF2 etch chemistry; however, other shapes are contemplated, depending on the dimensions of the cavity itself, the etch chemistry, and the etch time, to name a few variables.

[0031] exist Figure 8 In the embodiment of the present invention, a barrier material 40 can be formed (e.g., deposited) on the structures (e.g., the opening 34 of the oxide material 24 and the devices 26, 28) by conventional deposition methods (e.g., a plasma-enhanced CVD process) to a thickness that ensures pinching off of the opening 34. In an embodiment, the barrier material 40 seals the air gap, forming air gap isolation structures 42, 42a having different aspect ratios (e.g., having different dimensions). In other embodiments, it is also contemplated that the barrier material 40 can line the air gap isolation structures 42, 42a above the oxide material 20 during the pinching off process for sealing the air gap isolation structures 42, 42a, as representatively shown in the air gap 42. The barrier material 40 can also be deposited directly on the oxide material 24 above the air gap isolation structures 42, 42a. The barrier material 40 can also be located above the active device 26 and the passive device 28 to provide protection during subsequent processing steps.

[0032] In an embodiment, the air gap isolation structures 42, 42a can have different dimensions because, in addition to using STI structures, there are no longer any restrictions on the aspect ratio used for pinch-off. As previously mentioned, the original STI trenches 18 do not need to have the same aspect ratio because they are formed together with other STI structures in the STI region, which is in contrast to conventional air gap formation processes where all require the same aspect ratio. Smaller air gap isolation structures 42 can be placed between transistors 26 in a single group 50; while larger air gap isolation structures 42a can be placed between separate groups 50 themselves.

[0033] An interlevel dielectric material 44 may be deposited over the device, with contacts 46 formed to contact, for example, the silicide of the source / drain regions 26d and the polysilicon material 26b. The interlevel dielectric material 44 may be a BPSG material or other known interlevel dielectric material, such as SiO2. The contacts 46 may be a metal or metal alloy material, preferably composed of tungsten. Conventional photolithography and etching processes may be performed through the interlevel dielectric material 44 to form trenches, followed by deposition of a conductive material within the trenches to form the contacts 46. Any residual material on the interlevel dielectric material 44 may be removed by a CMP process.

[0034] These structures can be utilized in system-on-chip (SoC) technology. Those skilled in the art will understand that an SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, the SoC consumes much less power and occupies a much smaller area than a multi-chip design with equivalent functionality. As a result, SoC is becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0035] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0036] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: bulk substrate material; a first air gap isolation structure located in the bulk substrate material and comprising a first aspect ratio and an opening located at an upper surface of the bulk substrate material; as well as a second air gap isolation structure located in the bulk substrate material and comprising a second aspect ratio different from the first aspect ratio and an opening located at the upper surface of the bulk substrate material; as well as A barrier material is located over the upper surface of the bulk substrate material and seals the opening at the upper surface of the first air gap isolation structure and the opening at the upper surface of the second air gap isolation structure. 2 . The semiconductor structure of claim 1 , wherein the first air-gap isolation structure and the second air-gap isolation structure comprise oxide materials lining all surfaces. 3 . The semiconductor structure of claim 2 , wherein the barrier material comprises a nitride material extending on the oxide material over the first and second air gap isolation structures. 4 . The semiconductor structure according to claim 1 , wherein the first air gap isolation structure and the second air gap isolation structure are located on the same level as a shallow trench isolation structure.

5. The semiconductor structure according to claim 4, wherein the shallow trench isolation structure comprises a trench lined with an oxide material and filled with a polysilicon material above the oxide material, and the oxide material is also located on all surfaces of the first air gap isolation structure and the second air gap isolation structure. The semiconductor structure according to claim 4 , further comprising a passive device located above the shallow trench isolation structure. 7 . The semiconductor structure according to claim 1 , wherein the second air-gap isolation structure has more openings than the first air-gap isolation structure.

8. The semiconductor structure of claim 1, wherein the first air-gap isolation structure comprises a plurality of air-gap isolation structures separating active devices in a single group of active devices, and the second air-gap isolation structure separates the groups of active devices. 9 . The semiconductor structure according to claim 1 , wherein the first air gap isolation structure and the second air gap isolation structure are located at sides of an active device, and the second air gap isolation structure is larger than the first air gap isolation structure.

10. The semiconductor structure of claim 1, wherein the first air-gap isolation structure and the second air-gap isolation structure comprise oxide materials on upper surfaces of the first air-gap isolation structure and the second air-gap isolation structure, wherein a second insulator material plugs at least one opening in the oxide materials.

11. A semiconductor structure comprising: bulk substrate material; at least one air gap isolation structure disposed in the bulk substrate material; a first insulator material disposed on all surfaces of the at least one air-gap isolation structure; as well as A second insulator material plugs the at least one opening in the first insulator material and seals the at least one air gap isolation structure, the second insulator material extending above the upper surface of the bulk substrate material.

12. The semiconductor structure of claim 11, wherein the first insulator material comprises an oxide material and the second insulator material comprises a nitride material, the nitride material extending over the oxide material on an upper surface of the at least one air gap isolation structure. 13 . The semiconductor structure according to claim 11 , wherein the at least one air gap isolation structure is located on the same level as a shallow trench isolation structure, the shallow trench isolation structure including a liner of the first insulator material and filled with a polysilicon material on the first insulator material.

14. The semiconductor structure of claim 13, wherein the at least one air gap isolation structure separates active devices in a single group of active devices, and passive devices are located above the shallow trench isolation structure. 15 . The semiconductor structure of claim 11 , wherein the at least one air gap isolation structure comprises a plurality of air gap isolation structures having various aspect ratios. 16 . The semiconductor structure according to claim 15 , wherein the plurality of air gap isolation structures include a first air gap structure of a first size and a second air gap structure of a second size larger than the first size, the second air gap structure further comprising a pillar structure made of polysilicon material. 17 . The semiconductor structure of claim 16 , wherein the second air-gap isolation structure has more openings than the first air-gap isolation structure, and each of the openings of the first insulator material is plugged by the second insulator material. 18 . The semiconductor structure according to claim 16 , wherein the first air gap isolation structure and the second air gap isolation structure are located on sides of an active device.

19. A method for manufacturing a semiconductor structure, comprising: forming at least one air gap isolation structure in a bulk substrate material; forming a first insulator material on all surfaces of the at least one air gap isolation structure; as well as A second insulator material is formed to plug the at least one opening in the first insulator material and seal the at least one air gap isolation structure, the second insulator material extending above the upper surface of the bulk substrate material.

20. The method of claim 19, wherein the first insulator material comprises an oxide material and the second insulator material comprises a nitride material, the nitride material extending over the oxide material on an upper surface of the at least one air gap isolation structure.

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