Semiconductor element and method for producing the same

Abstract

This disclosure provides a semiconductor device having an antifuse and a metal-insulator-metal (MIM) capacitor connected to a redistribution layer (RDL), and a method for fabricating the same. The semiconductor device includes a first conductive portion and a second conductive portion disposed on a semiconductor substrate. The semiconductor device also includes a passivation layer covering the first conductive portion and the second conductive portion. An antifuse is formed by the first conductive portion, the second conductive portion, and a portion of the passivation layer therebetween. The semiconductor device further includes a first metal-insulator-metal (MIM) capacitor and a first redistribution layer (RDL) disposed on the passivation layer. The first MIM capacitor and the first RDL are electrically connected to the first conductive portion, and a first metal layer of the first MIM capacitor is integrally formed with the first RDL.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. Official Application No. 17 / 107,035, filed November 30, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, it relates to a semiconductor device having an antifuse connected to a redistribution layer (RDL) and a metal-insulator-metal (MIM) capacitor, and a method for fabricating the same. Background Technology

[0003] Integrated circuit (IC) components typically have all interconnections pre-configured during manufacturing. However, due to the high development costs, long manufacturing times, and high tooling costs associated with forming such IC components, users often require circuits that can be configured or programmed in the field. These circuits are called programmable circuits, and they typically contain programmable links. Programmable links are electrical interconnections that users disconnect or create at selected electronic nodes after the IC component is manufactured and packaged, used to activate or deactivate the corresponding selected electronic nodes.

[0004] One type of programmable connection is the fuse structure. Programmable connections in an IC element are programmed to create an open circuit by blowing the fuse structure at selected intersections. The combination of blown and unblowed connections represents the bit pattern of data 1s and 0s that the user wants to store in the IC element. Another type of programmable connection is the anti-fuse structure. Unlike the programming mechanism that results in an open circuit in the case of a fuse structure, the programming mechanism in an anti-fuse structure creates a short circuit or a relatively low resistance connection.

[0005] In integrated circuit manufacturing, fuse and antifuse structures are widely used for fault tolerance. For example, fuse and antifuse structures can be placed within the circuit paths of semiconductor devices. However, the fabrication and integration of semiconductor devices involve many complex steps and operations. Integration within semiconductor devices is becoming increasingly complex. This increased complexity in semiconductor device fabrication and integration can lead to defects. Therefore, there is a continuous need to improve the structure and manufacturing processes of semiconductor devices to address defects and enhance performance.

[0006] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first conductive portion and a second conductive portion disposed on a semiconductor substrate. The semiconductor device also includes a passivation layer covering the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion, and a portion of the passivation layer therebetween form an anti-fuse. The semiconductor device further includes a first metal-insulator-metal (MIM) capacitor and a first redistribution layer (RDL) disposed on the passivation layer. The first MIM capacitor and the first RDL are electrically connected to the first conductive portion, and a first metal layer of the first MIM capacitor is integrally formed with the first RDL.

[0008] In some embodiments, the antifuse has an air gap located between the first conductive portion and the second conductive portion and surrounded by the passivation layer. In some embodiments, the semiconductor device further includes a first insulating layer covering the first metal layer and the first RDL, and a second metal layer disposed on the first insulating layer, wherein the first metal layer, the second metal layer, and a portion of the first insulating layer therebetween form the first MIM capacitor. In some embodiments, the first RDL is not covered by the second metal layer.

[0009] In some embodiments, the semiconductor device further includes a second metal-insulator-metal (MIM) capacitor and a second redistribution layer (RDL) disposed on the passivation layer, wherein the second MIM capacitor and the second RDL are electrically connected to the second conductive portion, and a third metal layer of the second MIM capacitor is integrally formed with the second RDL. In some embodiments, the semiconductor device further includes a second insulating layer covering the third metal layer and the second RDL, and a fourth metal layer disposed on the second insulating layer, wherein the third metal layer, the fourth metal layer, and a portion of the second insulating layer therebetween form the second MIM capacitor. In some embodiments, the semiconductor device further includes a dielectric layer covering the first MIM capacitor, wherein the second MIM capacitor and the second RDL are disposed on the dielectric layer.

[0010] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first conductive portion and a second conductive portion disposed on a semiconductor substrate, and a passivation layer covering the first conductive portion and the second conductive portion. The semiconductor device also includes a first conductive plug passing through the passivation layer and contacting the first conductive portion, and a second conductive plug passing through the passivation layer and contacting the second conductive portion. The semiconductor device further includes an antifuse disposed between the first conductive plug and the second conductive plug, and a first metal-insulator-metal (MIM) capacitor disposed on the first conductive plug. Furthermore, the semiconductor device includes a first redistribution layer (RDL) physically connected to a first metal layer of the first MIM capacitor. The first RDL is electrically connected to the first conductive portion through the first metal layer of the first MIM capacitor and the first conductive plug.

[0011] In some embodiments, the semiconductor device further includes a dielectric layer disposed on the passivation layer, wherein the antifuse has an air gap surrounded by the dielectric layer and the passivation layer, and the air gap extends between the first conductive portion and the second conductive portion. In some embodiments, a conductive wire is formed between the first conductive portion and the second conductive portion and passes through the passivation layer and the air gap after the antifuse is programmed. In some embodiments, the first MIM capacitor further includes a second metal layer disposed on the first metal layer, and a first insulating layer sandwiched between the first metal layer and the second metal layer, wherein the first insulating layer extends to cover the first RDL.

[0012] In some embodiments, the semiconductor device further includes a second metal-insulator-metal (MIM) capacitor disposed on the second conductive plug, and a second redistribution layer (RDL) physically connected to a third metal layer of the second MIM capacitor, wherein the second RDL is electrically connected to the second conductive portion through the third metal layer of the second MIM capacitor and the second conductive plug. In some embodiments, the second MIM capacitor further includes a fourth metal layer disposed on the third metal layer, and a second insulating layer sandwiched between the third metal layer and the fourth metal layer, wherein the second insulating layer extends to cover the second RDL. In some embodiments, at least a portion of the second RDL overlaps with at least a portion of the first MIM capacitor.

[0013] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first conductive portion and a second conductive portion on a semiconductor substrate, and depositing a passivation layer on the first conductive portion and the second conductive portion. An opening is formed on the passivation layer and between the first conductive portion and the second conductive portion. The method also includes depositing a first dielectric layer on the passivation layer. The first dielectric layer extends into the opening to form an air gap surrounded by the first dielectric layer and the passivation layer. The method further includes simultaneously forming a first metal layer and a first redistribution layer (RDL) on the first dielectric layer. The first metal layer and the first RDL form a continuous layer. Furthermore, the method includes forming a first insulating layer to cover the first metal layer and the first RDL, and forming a second metal layer on the first insulating layer. The first metal layer, the second metal layer, and a portion of the first insulating layer therebetween form a first metal-insulator-metal (MIM) capacitor, and the first RDL is electrically connected to the first conductive portion through the first MIM capacitor.

[0014] In some embodiments, the first conductive portion, the second conductive portion, a portion of the passivation layer therebetween, and the air gap form an antifuse. In some embodiments, the method further includes applying a programming voltage to the antifuse to form a conductive wire passing through the passivation layer and the air gap of the portion therebetween. In some embodiments, the method further includes forming a second dielectric layer on the first MIM capacitor, and simultaneously forming a third metal layer and a second redistribution layer (RDL) on the second dielectric layer. The third metal layer and the second RDL form a continuous layer.

[0015] In some embodiments, the method further includes forming a second insulating layer to cover the third metal layer and the second RDL, and forming a fourth metal layer on the second insulating layer, wherein the third metal layer, the fourth metal layer, and a portion of the second insulating layer therebetween form a second metal-insulator-metal (MIM) capacitor. In some embodiments, the second RDL is electrically connected to the second conductive portion through the second MIM capacitor.

[0016] This disclosure provides an embodiment of a semiconductor device and a method for fabricating the same. In some embodiments, the semiconductor device includes an antifuse, a metal-insulator-metal (MIM) capacitor, and a redistribution layer (RDL). In some embodiments, the antifuse is composed of a first conductive portion, a second conductive portion, and a portion of a passivation layer between the first and second conductive portions. Furthermore, the MIM capacitor and the RDL are disposed on and electrically connected to the first conductive portion, and a metal layer of the MIM capacitor is integrally formed with the RDL. This increases the integration density of the semiconductor device and reduces its overall size.

[0017] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0018] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of each feature may be arbitrarily enlarged or reduced.

[0019] Figure 1 Cross-sectional views of semiconductor elements according to some embodiments of this disclosure are shown.

[0020] Figure 2 Example Figure 1 A cross-sectional view of a semiconductor device after it has been programmed.

[0021] Figure 3 A flowchart illustrating a method for fabricating a semiconductor element according to some embodiments of this disclosure is provided.

[0022] Figure 4 This embodiment illustrates an intermediate stage cross-sectional view of forming a dielectric layer on a semiconductor substrate during the fabrication process of a semiconductor device, according to some embodiments of the present disclosure.

[0023] Figure 5 This disclosure illustrates a cross-sectional view of an intermediate stage during the fabrication of a semiconductor device, showing the formation of a conductive material on the dielectric layer.

[0024] Figure 6 The following is an example of an intermediate stage cross-sectional view illustrating some embodiments of this disclosure of etching the conductive material during the manufacturing process of a semiconductor device to form a conductive portion.

[0025] Figure 7 Examples of some embodiments of this disclosure illustrate the deposition of a passivation layer during the fabrication process of a semiconductor device to form an intermediate stage cross-sectional view covering the conductive portion.

[0026] Figure 8 This illustration shows an intermediate stage cross-sectional view of depositing a dielectric layer on top of a passivation layer during the fabrication process of a semiconductor device, according to some embodiments of this disclosure.

[0027] Figure 9 This disclosure illustrates an intermediate stage cross-sectional view of forming a conductive plug on the conductive portion during the fabrication process of a semiconductor device, according to some embodiments of the present disclosure.

[0028] Figure 10 The following is a cross-sectional view illustrating an intermediate stage during the fabrication of a semiconductor device, in which an opening-filled dielectric layer is formed over a conductive plug, according to some embodiments of this disclosure.

[0029] Figure 11 The following is a cross-sectional view of an intermediate stage during the fabrication of a semiconductor device, illustrating some embodiments of the present disclosure, in which a metal material is formed on the dielectric layer.

[0030] Figure 12 The following is a cross-sectional view illustrating an intermediate stage during the fabrication of a semiconductor device, as shown in some embodiments of this disclosure, where the metal material is etched to form a metal layer and a redistribution layer.

[0031] Figure 13 This embodiment illustrates a cross-sectional view of an intermediate stage during the fabrication of a semiconductor device, in which an insulating layer is formed over the metal layer and the redistribution layer.

[0032] Figure 14 This disclosure illustrates a cross-sectional view of an intermediate stage during the fabrication of a semiconductor device, showing the formation of a metallic material on an insulating layer.

[0033] Figure 15 This disclosure illustrates an intermediate stage cross-sectional view of etching the metal material during the fabrication process of a semiconductor device to form a metal layer over the insulating layer, illustrating some embodiments of the present disclosure.

[0034] Figure 16 This illustration shows an intermediate stage cross-sectional view of forming a conductive layer on one of the conductive plugs during the fabrication process of a semiconductor device, according to some embodiments of this disclosure.

[0035] Figure 17 This disclosure illustrates an intermediate stage cross-sectional view of forming a conductive plug on a conductive layer during the fabrication process of a semiconductor device, according to some embodiments of the present disclosure.

[0036] Figure 18 The following is a cross-sectional view illustrating an intermediate stage during the fabrication of a semiconductor device, in which an opening is formed on a conductive plug.

[0037] Figure 19 The following is a cross-sectional view illustrating an intermediate stage during the fabrication of a semiconductor device, where a metal material is formed on the dielectric layer and extends into the opening, according to some embodiments of this disclosure.

[0038] Figure 20The following is a cross-sectional view illustrating an intermediate stage during the fabrication of a semiconductor device, as shown in some embodiments of this disclosure, where the metal material is etched to form a metal layer and a redistribution layer.

[0039] Figure 21 This illustration shows an intermediate stage cross-sectional view of forming an insulating layer over the metal layer and the redistribution layer and forming a metallic material over the insulating layer during the fabrication process of a semiconductor device, according to some embodiments of this disclosure.

[0040] The reference numerals in the attached figures are explained as follows:

[0041] 10: Preparation method

[0042] 100: Semiconductor components

[0043] 101: Semiconductor substrate

[0044] 103: Conductive pad

[0045] 105: Dielectric layer

[0046] 107: Conductive plug

[0047] 109: Conductive materials

[0048] 109': Conductive structure

[0049] 109a: Conductive part

[0050] 109b: Conductive part

[0051] 111: Patterned Mask

[0052] 114: Opening

[0053] 114': Air gap

[0054] 117: Passivation layer

[0055] 119: Dielectric layer

[0056] 121: Conductive plug

[0057] 123: Conductive plug

[0058] 125: Dielectric layer

[0059] 128: Opening

[0060] 130: Opening

[0061] 133: Metallic Materials

[0062] 133a: Metal layer

[0063] 133b: Redistribution layer

[0064] 135: Patterned Mask

[0065] 137: Insulation layer

[0066] 137a: Part

[0067] 139: Metallic Materials

[0068] 139a: Metal layer

[0069] 141: Patterned Mask

[0070] 143: MIM capacitor

[0071] 145: Conductive layer

[0072] 151: Dielectric layer

[0073] 153: Conductive plug

[0074] 155: Dielectric layer

[0075] 158: Opening

[0076] 160: Opening

[0077] 163: Metallic Materials

[0078] 163a: Metal layer

[0079] 163b: Redistribution layer

[0080] 165: Patterned Mask

[0081] 167: Insulation layer

[0082] 167a: Partial

[0083] 169: Metallic Materials

[0084] 169a: Metal layer

[0085] 171: Patterned Mask

[0086] 173: MIM capacitor

[0087] 180: Anti-fuse

[0088] 185: Conductive wire

[0089] S11: Steps

[0090] S13: Steps

[0091] S15: Steps

[0092] S17: Steps

[0093] S19: Steps

[0094] S21: Steps Detailed Implementation

[0095] The following discloses various embodiments or examples of different components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to limit the relationship between the different embodiments and / or structures discussed.

[0096] Furthermore, spatial terms such as "below," "below," "lower," "above," "higher," and similar terms are used here to facilitate the description of the relationship between one element or component shown in the diagram and another. These spatial relation terms are used to cover different orientations of the element in use or operation, beyond the orientation depicted in the diagram. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial relation adjectives used therein can be interpreted in the same way.

[0097] Figure 1 Cross-sectional views of a semiconductor device 100 according to some embodiments of this disclosure are shown. Figure 1 As shown, the semiconductor element 100 includes a semiconductor substrate 101, a dielectric layer 105 disposed on the semiconductor substrate 101, a conductive pad 103 disposed in the semiconductor substrate 101, and a conductive plug 107 disposed in the dielectric layer 105. In some embodiments, the conductive plug 107 is directly located on the conductive pad 103 and is in physical contact with the conductive pad 103.

[0098] In some embodiments, the semiconductor element 100 includes a conductive structure 109' disposed on a dielectric layer 105, and the conductive structure 109' includes conductive portions 109a and 109b. Conductive portion 109b is also referred to herein as a first conductive portion, and conductive portion 109a is also referred to herein as a second conductive portion. In some embodiments, a passivation layer 117 covers conductive portions 109a and 109b, and a dielectric layer 119 is disposed on the passivation layer 117.

[0099] In some embodiments, the semiconductor element 100 includes conductive plugs 121 and 123 that pass through the dielectric layer 119 and the passivation layer 117, respectively, and physically contact conductive portions 109a and 109b. Conductive plug 123 is also referred to herein as a first conductive plug, and conductive plug 121 is also referred to herein as a second conductive plug. In some embodiments, an air gap 114' is formed between conductive plugs 121 and 123 and between conductive portions 109a and 109b. Specifically, the air gap 114' is surrounded by the passivation layer 117 and the dielectric layer 119. In some embodiments, conductive portions 109a and 109b, a portion of the passivation layer 117 between conductive portions 109a and 109b, and the air gap 114' form an antifuse 180.

[0100] Furthermore, the semiconductor element 100 includes a dielectric layer 125 disposed on a dielectric layer 119, a metal layer 133a and a redistribution layer (RDL) 133b disposed on the dielectric layer 125, an insulating layer 137 disposed on the metal layer 133a and the RDL 133b, and a metal layer 139a disposed on the insulating layer 137. In some embodiments, the metal layers 133a and 139a and a portion 137a of the insulating layer 137 disposed between the metal layers 133a and 139a form a metal-insulator-metal (MIM) capacitor 143. It should be noted that the metal layer 133a of the MIM capacitor 143 is integrally formed with the RDL 133b. In some embodiments, the metal layers 133a and the RDL 133b are physically connected to each other.

[0101] In some embodiments, the metal layer 133a and RDL 133b of the MIM capacitor 143 penetrate the dielectric layer 125, and the metal layer 133a physically contacts the conductive plug 123. In some embodiments, the RDL 133b is not covered by the metal layer 139a of the MIM capacitor 143. The MIM capacitor 143 is also referred to herein as a first MIM capacitor, and the RDL 133b is also referred to herein as a first RDL.

[0102] Furthermore, according to some embodiments, the semiconductor element 100 includes a conductive layer 145 that passes through the dielectric layer 125 and the insulating layer 137 and physically contacts the conductive plug 121. In some embodiments, the semiconductor element 100 includes a dielectric layer 151 disposed on the MIM capacitor 143 and a conductive plug 153 passing through the dielectric layer 151. In some embodiments, the dielectric layer 151 covers the MIM capacitor 143.

[0103] Reference Figure 1The semiconductor element 100 includes a dielectric layer 155 disposed on a dielectric layer 151, a metal layer 163a and an RDL 163b disposed on the dielectric layer 155, an insulating layer 167 disposed on the metal layer 163a and the RDL 163b, and a metal layer 169a disposed on the insulating layer 167. In some embodiments, the metal layers 163a and 169a and a portion 167a of the insulating layer 167 disposed between the metal layers 163a and 169a form a MIM capacitor 173. It should be noted that the metal layer 163a of the MIM capacitor 173 is integrally formed with the RDL 163b. In some embodiments, the metal layers 163a and the RDL 163b are physically connected to each other.

[0104] In some embodiments, the metal layer 163a and RDL 163b of the MIM capacitor 173 penetrate the dielectric layer 155, and the metal layer 163a physically contacts the conductive plug 153. In some embodiments, the RDL 163b is not covered by the metal layer 169a of the MIM capacitor 173. The MIM capacitor 173 is also referred to herein as a second MIM capacitor, and the RDL 163b is also referred to herein as a second RDL.

[0105] Figure 2 Example Figure 1 A cross-sectional view of the semiconductor device 100. See also... Figure 1 The antifuse 180 of the semiconductor element 100 is in a high-resistance state before being programmed. During programming, a programming voltage is applied between conductive portions 109a and 109b, and the passivation layer 117 portion and the air gap 114' between conductive portions 109a and 109b are broken down to form a conductive wire 185. Therefore, according to some embodiments, programming changes the antifuse 180 from a high-resistance state to a low-resistance state, such as... Figure 2 As shown.

[0106] Figure 3 The flowchart illustrates a method 10 for fabricating a semiconductor element 100 according to some embodiments of the present disclosure, and the fabrication method 10 includes steps S11, S13, S15, S17, S19, and S21. A detailed description is provided below in conjunction with the accompanying drawings. Figure 3 Steps S11 to S21.

[0107] Figures 4 to 21 This illustration shows an intermediate stage cross-sectional view during the manufacturing process of a semiconductor device 100 according to some embodiments of the present disclosure. (See also:) Figure 4 As shown, according to some embodiments, a semiconductor substrate 101 having a conductive pad 103 is provided, and a dielectric layer 105 is formed on the semiconductor substrate 101.

[0108] Semiconductor substrate 101 may be part of an integrated circuit (IC) chip, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0109] Depending on the IC manufacturing stage, the semiconductor substrate 101 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC components (e.g., doped regions, isolation components, gate components, source / drain components, interconnect components, other components, or combinations thereof). For example, a conductive pad 103 adjacent to the top surface of the semiconductor substrate 101 is electrically connected to a conductive layer in the semiconductor substrate 101. For clarity, the semiconductor substrate 101 has been simplified. It should be noted that additional components may be added to the semiconductor substrate 101, and some of the components described below may be replaced, modified, or removed in other embodiments.

[0110] Furthermore, the dielectric layer 105 comprises a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant (k value) of less than about 4. Examples of low-k dielectric materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride (SiCN), silicon oxynitride (SiOCN), fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), and polyimide. Furthermore, the fabrication technique for the dielectric layer 105 may include a deposition process. The deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or another applicable process.

[0111] According to some embodiments, such as Figure 5 As shown, after the dielectric layer 105 is formed, a conductive plug 107 is formed that passes through the dielectric layer 105 and physically contacts the conductive pad 103. In some embodiments, the conductive plug 107 comprises tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), a combination thereof, or another applicable metallic material.

[0112] The formation of the conductive plug 107 may include partially removing the dielectric layer 105 by an etching process to form an opening (not shown), and filling the opening with a conductive material (not shown) by a deposition process. The etching process may include a wet etching process, a dry etching process, or a combination thereof. The deposition process may include a CVD process, a PVD process, an ALD process, a metal-organic chemical vapor deposition (MOCVD) process, a sputtering process, an electroplating process, a combination thereof, or another applicable process. After the deposition process, a planarization process may be performed to remove excess conductive material above the dielectric layer 105. The planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, a combination thereof, or another applicable process.

[0113] Reference Figure 5According to some embodiments, a conductive material 109 is formed on a dielectric layer 105 and covers a conductive plug 107, and a patterned mask 111 is formed on the conductive material 109. Some materials used to form the conductive material 109 are similar to or the same as those used to form the conductive plug 107, and their details will not be repeated here. The fabrication techniques for the conductive material 109 may include deposition processes, such as CVD, PVD, ALD, MOCVD, sputtering, electroplating, or another applicable process.

[0114] Next, according to some embodiments, the conductive material 109 is etched to form a conductive structure 109' by using a patterned mask 111 as a mask, and the patterned mask 111 is removed after the conductive structure 109' is formed, such as... Figure 6 As shown. The etching process can be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, after the etching process, an opening 114 is formed to expose the dielectric layer 105 between the conductive portions 109a and 109b of the conductive structure 109'. The various steps are described in... Figure 3 The preparation method shown in Figure 10 is step S11.

[0115] According to some embodiments, after forming conductive portions 109a and 109b, a passivation layer 117 is deposited on the conductive portions 109a and 109b, such as Figure 7 As shown. In some embodiments, the passivation layer 117 covers the sidewalls and top surface of the conductive portions 109a and 109b. In some embodiments, the passivation layer 117 extends to cover the sidewalls and bottom surface of the opening 114.

[0116] Furthermore, the passivation layer 117 has a neck located at the top portion of the opening 114. In some embodiments, the passivation layer 117 comprises silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, another applicable material, or a combination thereof, and the fabrication technique of the passivation layer 117 includes CVD processes, plasma-enhanced chemical vapor deposition (PECVD) processes, or another applicable process. The various steps are described in... Figure 3 The preparation method shown in Figure 10 is step S13.

[0117] Subsequently, according to some embodiments, a dielectric layer 119 is formed on the passivation layer 117, such as Figure 8As shown. In some embodiments, the dielectric layer 119 extends to fill the upper portion of the opening 114, while the lower portion of the opening 114 is left unfilled, such that the remaining portion 114' of the opening (i.e., the air gap 114') is surrounded by the dielectric layer 119 and the passivation layer 117. Some of the materials and processes used to form the dielectric layer 119 are similar to or the same as those used to form the passivation layer 117, and their details will not be repeated here.

[0118] In some embodiments, conductive portions 109a and 109b, a portion of the passivation layer 117 between conductive portions 109a and 109b, and the air gap 114' form an antifuse 180 (e.g., Figure 1 (As shown). In some other embodiments, opening 114 is completely filled by dielectric layer 119. Therefore, air gap 114' is not formed. In these cases, portions of conductive portions 109a and 109b and a portion of passivation layer 117 between conductive portions 109a and 109b form an antifuse. The various steps are as follows: Figure 3 The preparation method shown in Figure 10 is step S15.

[0119] Then, according to some embodiments, a conductive plug 121 is formed on the conductive portion 109a, and a conductive plug 123 is formed on the conductive portion 109b, such as... Figure 9 As shown. In some embodiments, conductive plugs 121 and 123 pass through dielectric layer 119 and passivation layer 117 to physically contact conductive portions 109a and 109b. Some materials and processes used to form conductive plugs 121 and 123 are similar to or the same as those used to form conductive plug 107, and their details will not be repeated here.

[0120] According to some embodiments, after forming conductive plugs 121 and 123, a dielectric layer 125 is formed over dielectric layer 119, and dielectric layer 125 is partially removed by an etching process to form openings 128 and 130, as shown. Figure 10 As shown. In some embodiments, openings 128 and 130 expose conductive plug 123 and a portion of dielectric layer 119. Some of the materials and processes used to form dielectric layer 125 are similar to or the same as those used to form passivation layer 117, and their details will not be repeated here.

[0121] For example, a patterned mask (not shown) may be formed on dielectric layer 125, and an etching process may be performed on dielectric layer 125 using the patterned mask as a mask to form openings 128 and 130. The etching process may include a wet etching process, a dry etching process, or a combination thereof. After forming openings 128 and 130, the patterned mask may be removed.

[0122] According to some embodiments, a metal material 133 is then formed on the dielectric layer 125, and a patterned mask 135 is formed on the metal material 133, such as... Figure 11 As shown. In some embodiments, the metal material 133 covers the top surface of the dielectric layer 125 and extends to... Figure 10 In openings 128 and 130. Specifically, metal material 133 covers the sidewalls and bottom surfaces of openings 128 and 130. In some embodiments, metal material 133 physically contacts the exposed portions of conductive plug 123 and dielectric layer 119.

[0123] It should be noted that openings 128 and 130 are not completely filled with metallic material 133. In some embodiments, metallic material 133 is conformally deposited on... Figure 10 Above the structure, and the remaining portions of openings 128 and 130 are filled with a patterned mask 135. Some materials and processes used to form the metallic material 133 are the same as those used to form... Figure 5 The conductive material 109 is made of similar or identical materials and processes, and its details will not be repeated here. In some embodiments, the metallic material 133 includes titanium nitride (TiN).

[0124] Subsequently, according to some embodiments, the metal material 133 is etched to form metal layers 133a and RDL 133b by using a patterned mask 135 as a mask, and the patterned mask 135 is removed after the metal layers 133a and RDL 133b are formed. Figure 12 As shown. The etching process can be a wet etching process, a dry etching process, or a combination of the above. Each step is described in... Figure 3 The preparation method shown in Figure 10 is step S17.

[0125] In some embodiments, dashed lines indicating the boundary between metal layer 133a and RDL 133b are used to illustrate this disclosure. There is no obvious interface between metal layer 133a and RDL 133b. It should be noted that, according to some embodiments, metal layer 133a and RDL 133b comprise the same material and are formed simultaneously from the same material layer (i.e., metal material 133). In some embodiments, metal layer 133a and RDL 133b are integrally formed. In some embodiments, metal layer 133a is physically connected to RDL 133b. In some embodiments, metal layer 133a and RDL 133b form a continuous layer.

[0126] According to some embodiments, after forming metal layer 133a and RDL 133b, an insulating layer 137 is formed on metal layer 133a, RDL 133b, and dielectric layer 125, such as... Figure 13 As shown. In some embodiments, the insulating layer 137 is conformally deposited on... Figure 12Above the structure. It should be noted that, Figure 12 The openings 128 and 130 are not completely filled by the insulating layer 137.

[0127] In some embodiments, the insulating layer 137 includes a dielectric material, such as silicon dioxide (SiO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), or a combination thereof. The fabrication techniques for the insulating layer 137 may include CVD processes, PVD processes, ALD processes, spin coating processes, or another applicable process. The various steps are described in... Figure 3 The preparation method shown in Figure 10 is step S19.

[0128] Next, according to some embodiments, a metal material 139 is formed on the insulating layer 137, and a patterned mask 141 is formed on the metal material 139, such as... Figure 14 As shown. In some embodiments, the metal material 139 covers the top surface of the insulating layer 137 and extends to... Figure 13 The openings are at 128 and 130. It should be noted that... Figure 13 The openings 128 and 130 were not completely filled with the metal material 139.

[0129] In some embodiments, the metallic material 139 is conformally deposited on Figure 13 Above the structure, and the remaining portion of the opening 128 is filled with a patterned mask 141. Some materials and processes used to form the metallic material 139 are the same as those used to form... Figure 5 The conductive material 109 is made of similar or identical materials and processes, and its details will not be repeated here. In some embodiments, the metallic material 139 includes titanium nitride (TiN), low-stress silicon germanium (SiGe), or a combination thereof.

[0130] Subsequently, according to some embodiments, the metal material 139 is etched to form a metal layer 139a by using a patterned mask 141 as a mask, and the patterned mask 141 is removed after the metal layer 139a is formed, such as... Figure 15 As shown. The etching process can be a wet etching process, a dry etching process, or a combination thereof. After forming the metal layer 139a, the MIM capacitor 143 is obtained.

[0131] As described above, the MIM capacitor 143 includes a metal layer 133a, a metal layer 139a, and a portion 137a of an insulating layer 137 sandwiched between the metal layers 133a and 139a. The various steps are described in... Figure 3The fabrication method 10 shown is step S21. In some embodiments, RDL 133b is electrically connected to the conductive portion 109b via MIM capacitor 143 and conductive plug 123. Since the metal layer 133a of MIM capacitor 143 and RDL 133b form a complete continuous layer, manufacturing costs are reduced and the overall size of the component can be reduced.

[0132] In some other embodiments, RDL 133b is integrally formed with the metal layer 139a of the MIM capacitor 143, rather than being integrally formed with the metal layer 133a of the MIM capacitor 143. In these cases, RDL 133b is physically connected to the metal layer 139a, and the metal layer 133a does not extend below RDL 133b. That is, in these cases, RDL 133b and the metal layer 139a are formed as a continuous layer.

[0133] According to some embodiments, after the MIM capacitor 143 is formed, the conductive layer 145 is formed directly on the conductive plug 121 and makes physical contact with the conductive plug 121, such as... Figure 16 As shown. In some embodiments, the conductive layer 145 extends through the dielectric layer 125 and the insulating layer 137. Some materials used to form the conductive layer 145 are similar to or the same as those used to form the conductive plug 107, and their details will not be repeated here.

[0134] Next, according to some embodiments, a dielectric layer 151 is formed on the metal layer 139a, insulating layer 137, and conductive layer 145 of the MIM capacitor 143, and a conductive plug 153 is formed directly on the conductive layer 145 and in physical contact with the conductive layer 145, such as... Figure 17 As shown. In some embodiments, dielectric layer 151 covers MIM capacitor 143 and RDL 133b. In some embodiments, the top surface of conductive plug 153 is higher than the top surface of metal layer 139a of MIM capacitor 143.

[0135] In some embodiments, the dielectric layer 151 comprises silicon oxide, silicon nitride, silicon oxynitride, another applicable material, or a combination thereof. The fabrication techniques for the dielectric layer 151 may include CVD processes, PVD processes, spin-coating processes, or another applicable process. Furthermore, some materials and processes used to form the conductive plug 153 are similar to or the same as those used to form the conductive plug 107, and their details will not be repeated here.

[0136] According to some embodiments, after forming the conductive plug 153, a dielectric layer 155 is formed on top of the dielectric layer 151, and the dielectric layer 155 is partially removed by an etching process to form openings 158 and 160, as shown. Figure 18As shown. In some embodiments, openings 158 and 160 expose conductive plug 153 and a portion of dielectric layer 151. Some of the materials and processes used to form dielectric layer 155 are similar to or the same as those used to form passivation layer 117, and their details will not be repeated here.

[0137] For example, a patterned mask (not shown) may be formed on dielectric layer 155, and dielectric layer 155 may be etched to form openings 158 and 160 by using the patterned mask as a mask. The etching process may include a wet etching process, a dry etching process, or a combination thereof. After forming openings 158 and 160, the patterned mask may be removed.

[0138] Then, according to some embodiments, a metal material 163 is formed on the dielectric layer 155, and a patterned mask 165 is formed on the metal material 163, such as... Figure 19 As shown. In some embodiments, the metal material 163 covers the top surface of the dielectric layer 155 and extends to... Figure 18 In openings 158 and 160. Specifically, metal material 163 covers the sidewalls and bottom surfaces of openings 158 and 160. In some embodiments, metal material 163 physically contacts the exposed portions of conductive plug 153 and dielectric layer 151.

[0139] It should be noted that openings 158 and 160 are not completely filled with metallic material 163. In some embodiments, metallic material 163 is conformally deposited on... Figure 18 Above the structure, and the remaining portions of openings 158 and 160 are filled with a patterned mask 165. Some of the materials and processes used to form the metallic material 163 are the same as those used to form... Figure 11 The materials and processes of the metal material 133 are similar or the same, and their details will not be repeated here.

[0140] Next, according to some embodiments, the metal material 163 is etched to form metal layers 163a and RDL 163b by using a patterned mask 165 as a mask, and the patterned mask 165 is removed after the metal layers 163a and RDL 163b are formed. Figure 20 As shown. The etching process can be a wet etching process, a dry etching process, or a combination of the above.

[0141] Similar to Figure 12 The dashed line between metal layer 133a and RDL 133b uses Figure 20The dashed line indicating the boundary between metal layer 163a and RDL 163b is used to clarify this disclosure. There is no obvious interface between metal layer 163a and RDL 163b. It should be noted that, according to some embodiments, metal layer 163a and RDL 163b comprise the same material and are formed simultaneously from the same material layer (i.e., metal material 163). In some embodiments, metal layer 163a and RDL 163b are integrally formed. In some embodiments, metal layer 163a is physically connected to RDL 163b. In some embodiments, metal layer 163a and RDL 163b form a continuous layer.

[0142] According to some embodiments, after forming metal layers 163a and RDL 163b, insulating layer 167 and metal material 169 are sequentially formed. Figure 20 On top of the structure, a patterned mask 171 is formed on the metal material 169, such as Figure 21 As shown. In some embodiments, the insulating layer 137 and the metal material 169 are conformally deposited on... Figure 20 Above the structure. It should be noted that, Figure 20 Openings 158 and 160 are not completely filled by the insulating layer 167 and the metal material 169, and the remaining portion of opening 168 is filled by the patterned mask 171. Some materials and processes used to form the insulating layer 167 and the metal material 169 are respectively related to those used to form... Figure 13 Insulation layer 137 and Figure 14 The materials and processes of the metal material 139 are similar or the same, and their details will not be repeated here.

[0143] Rereference Figure 1 According to some embodiments, after forming the patterned mask 171, the metal material 169 is etched using the patterned mask 171 as a mask to form a metal layer 169a, and the patterned mask 171 is removed after forming the metal layer 169a. The etching process can be a wet etching process, a dry etching process, or a combination thereof. After forming the metal layer 169a, a MIM capacitor 173 is obtained.

[0144] As described above, the MIM capacitor 173 includes a metal layer 163a, a metal layer 169a, and a portion 167a of an insulating layer 167 sandwiched between the metal layers 163a and 169a. In some embodiments, an RDL 163b is electrically connected to the conductive portion 109a via the MIM capacitor 173, conductive plug 153, conductive layer 145, and conductive plug 121. Because the metal layer 163a and the RDL 163b of the MIM capacitor 173 form a continuous layer, manufacturing costs are reduced, and the overall size of the semiconductor device 100 can be minimized.

[0145] In some other embodiments, RDL 163b is integrally formed with the metal layer 169a of the MIM capacitor 173, rather than integrally formed with the metal layer 163a of the MIM capacitor 173. In these cases, RDL 163b is physically connected to the metal layer 169a, and the metal layer 163a does not extend below RDL 163b. That is, in these cases, RDL 163b and the metal layer 169a are formed as a continuous layer.

[0146] This disclosure provides embodiments of a semiconductor element 100. In some embodiments, the semiconductor element 100 includes an antifuse 180, a MIM capacitor 143 (first MIM capacitor), a MIM capacitor 173 (second MIM capacitor), an RDL 133b (first RDL), and an RDL 163b (second RDL). In some embodiments, the antifuse 180 is formed of a conductive portion 109b (first conductive portion), a conductive portion 109a (second conductive portion), and a portion of a passivation layer 117 between the conductive portions 109b and 109a. In some embodiments, the antifuse 180 includes an air gap 114' surrounded by a portion of the passivation layer 117 between the conductive portions 109b and 109a. Furthermore, the MIM capacitor 143 and the RDL 133b are disposed on and electrically connected to the conductive portion 109b, and the metal layer (e.g., metal layer 133a) of the MIM capacitor 143 is integrally formed with the RDL 133b. Furthermore, the MIM capacitor 173 and RDL 163b are disposed on and electrically connected to the conductive portion 109a, and the metal layer of the MIM capacitor 173 (e.g., metal layer 163a) is integrally formed with the RDL 163b. This increases the integration density of the semiconductor device 100 and reduces its overall size. Additionally, it reduces the manufacturing cost of the semiconductor device 100.

[0147] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first conductive portion and a second conductive portion disposed on a semiconductor substrate. The semiconductor device also includes a passivation layer covering the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion, and a portion of the passivation layer therebetween form an antifuse. The semiconductor device further includes a first metal-insulator-metal (MIM) capacitor and a first redistribution layer (RDL) disposed on the passivation layer. The first MIM capacitor and the first RDL are electrically connected to the first conductive portion, and a first metal layer of the first MIM capacitor is integrally formed with the first RDL.

[0148] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first conductive portion and a second conductive portion disposed on a semiconductor substrate, and a passivation layer covering the first conductive portion and the second conductive portion. The semiconductor device also includes a first conductive plug passing through the passivation layer and contacting the first conductive portion, and a second conductive plug passing through the passivation layer and contacting the second conductive portion. The semiconductor device further includes an antifuse disposed between the first conductive plug and the second conductive plug, and a first metal-insulator-metal (MIM) capacitor disposed on the first conductive plug. Furthermore, the semiconductor device includes a first redistribution layer (RDL) physically connected to a first metal layer of the first MIM capacitor. The first RDL is electrically connected to the first conductive portion through the first metal layer of the first MIM capacitor and the first conductive plug.

[0149] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first conductive portion and a second conductive portion on a semiconductor substrate, and depositing a passivation layer on the first conductive portion and the second conductive portion. An opening is formed on the passivation layer and between the first conductive portion and the second conductive portion. The method also includes depositing a first dielectric layer on the passivation layer. The first dielectric layer extends into the opening to form an air gap closed by the first dielectric layer and the passivation layer. The method further includes simultaneously forming a first metal layer and a first redistribution layer (RDL) on the first dielectric layer. The first metal layer and the first RDL form a continuous layer. Furthermore, the method includes forming a first insulating layer to cover the first metal layer and the first RDL, and forming a second metal layer on the first insulating layer. The first metal layer, the second metal layer, and a portion of the first insulating layer therebetween form a first metal-insulator-metal (MIM) capacitor, and the first RDL is electrically connected to the first conductive portion through the first MIM capacitor.

[0150] The embodiments disclosed herein have several advantages. By incorporating antifuse, metal-insulator-metal capacitors, and redistribution layers into a semiconductor device, the integration density of the semiconductor device can be increased, and the overall size of the semiconductor device can be reduced.

[0151] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0152] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, matter formations, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, matter formations, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, matter formations, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: a first conductive portion and a second conductive portion disposed over a semiconductor substrate; a passivation layer covering the first conductive portion and the second conductive portion, wherein the first conductive portion, the second conductive portion, and a portion of the passivation layer therebetween form an antifuse; a first metal-insulator-metal capacitor and a first redistribution layer disposed over the passivation layer, wherein the first metal-insulator-metal capacitor and the first redistribution layer are electrically connected to the first conductive portion, and a first metal layer of the first metal-insulator-metal capacitor is integrally formed with the first redistribution layer; and a second metal-insulator-metal capacitor and a second redistribution layer disposed over the passivation layer, wherein the second metal-insulator-metal capacitor and the second redistribution layer are electrically connected to the second conductive portion, and a third metal layer of the second metal-insulator-metal capacitor is integrally formed with the second redistribution layer.

2. The semiconductor device of claim 1, wherein the antifuse has an air gap between the first conductive portion and the second conductive portion and is surrounded by the passivation layer.

3. The semiconductor device of claim 1, further comprising: a first insulating layer covering the first metal layer and the first redistribution layer; and a second metal layer disposed over the first insulating layer, wherein the first metal layer, the second metal layer, and a portion of the first insulating layer therebetween form the first metal-insulator-metal capacitor.

4. The semiconductor device of claim 3, wherein the first redistribution layer is not covered by the second metal layer.

5. The semiconductor device of claim 1, further comprising: a second insulating layer covering the third metal layer and the second redistribution layer; and a fourth metal layer disposed over the second insulating layer, wherein the third metal layer, the fourth metal layer, and a portion of the second insulating layer therebetween form the second metal-insulator-metal capacitor.

6. The semiconductor device of claim 1, further comprising: a dielectric layer covering the first metal-insulator-metal capacitor, wherein the second metal-insulator-metal capacitor and the second redistribution layer are disposed over the dielectric layer.

7. A semiconductor device, comprising: a first conductive portion and a second conductive portion disposed over a semiconductor substrate; a passivation layer covering the first conductive portion and the second conductive portion; a first conductive plug through the passivation layer and contacting the first conductive portion; a second conductive plug through the passivation layer and contacting the second conductive portion; an antifuse disposed between the first conductive plug and the second conductive plug; a first metal-insulator-metal capacitor disposed over the first conductive plug; a first redistribution layer physically connected to a first metal layer of the first metal-insulator-metal capacitor, wherein the first redistribution layer is electrically connected to the first conductive portion through the first metal layer of the first metal-insulator-metal capacitor and the first conductive plug; and a second metal-insulator-metal capacitor disposed over the second conductive plug. ​ ​ a second metal-insulator-metal capacitor disposed over the second conductive plug; and a second redistribution layer physically connected to a third metal layer of the second metal-insulator-metal capacitor, wherein the second redistribution layer is electrically connected to the second conductive portion through the third metal layer of the second metal-insulator-metal capacitor and the second conductive plug.

8. The semiconductor element of claim 7, further comprising: a dielectric layer disposed over the passivation layer, wherein the antifuse has an air gap enclosed by the dielectric layer and the passivation layer, and the air gap extends between the first conductive portion and the second conductive portion.

9. The semiconductor element of claim 8, wherein a conductive filament is formed between the first conductive portion and the second conductive portion and passes through the passivation layer and the air gap after the antifuse is programmed.

10. The semiconductor element of claim 7, wherein the first metal-insulator-metal capacitor further comprises: a second metal layer disposed over the first metal layer; and a first insulating layer sandwiched between the first metal layer and the second metal layer, wherein the first insulating layer extends to cover the first redistribution layer.

11. The semiconductor element of claim 7, wherein the second metal-insulator-metal capacitor further comprises: a fourth metal layer disposed over the third metal layer; and a second insulating layer sandwiched between the third metal layer and the fourth metal layer, wherein the second insulating layer extends to cover the second redistribution layer.

12. The semiconductor element of claim 7, wherein at least a portion of the second redistribution layer overlaps at least a portion of the first metal-insulator-metal capacitor.

13. A method of fabricating a semiconductor element, comprising: forming a first conductive portion and a second conductive portion over a semiconductor substrate; depositing a passivation layer over the first conductive portion and the second conductive portion, wherein an opening is formed in the passivation layer between the first conductive portion and the second conductive portion; depositing a first dielectric layer over the passivation layer, wherein the first dielectric layer extends into the opening to form an air gap enclosed by the first dielectric layer and the passivation layer; simultaneously forming a first metal layer and a first redistribution layer over the first dielectric layer, wherein the first metal layer and the first redistribution layer form a continuous layer; forming a first insulating layer to cover the first metal layer and the first redistribution layer; and forming a second metal layer over the first insulating layer, wherein the first metal layer, the second metal layer, and a portion of the first insulating layer therebetween form a first metal-insulator-metal capacitor, and wherein the first redistribution layer is electrically connected to the first conductive portion through the first metal-insulator-metal capacitor; forming a second dielectric layer over the first metal-insulator-metal capacitor; and simultaneously forming a third metal layer and a second redistribution layer over the second dielectric layer, wherein the third metal layer and the second redistribution layer form a continuous layer, wherein the second redistribution layer is electrically connected to the second conductive portion through the second metal-insulator-metal capacitor.

14. The method of claim 13, wherein the first conductive portion, the second conductive portion, a portion of the passivation layer therebetween, and the air gap form an antifuse.

15. The method of claim 14, further comprising: applying a program voltage to the antifuse to form a conductive filament that passes through the portion of the passivation layer and the air gap.

16. The method of claim 13, further comprising: forming a second insulating layer to cover the third metal layer and the second redistribution layer; and forming a fourth metal layer over the second insulating layer, wherein the third metal layer, the fourth metal layer, and a portion of the second insulating layer therebetween form a second metal-insulator-metal capacitor. ​

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