RF amplifier package

Abstract

The invention relates to an RF amplifier package. The invention further relates to a semiconductor die comprising an RF power FET for use in such an amplifier package. According to the invention, the RF power FET comprises a second drain bond wire arranged between a gate bond wire and a first drain bond wire, the first drain bond wire being connected to an output of the RF amplifier package. A drain finger extends from the second drain bond wire towards the gate bond wire, and the drain finger extends towards the first drain bond wire. The second drain bond wire is connected to a DC blocking capacitor using bond wires. These bond wires form an inductance which resonates with an output capacitance of the RF power FET at or near the operating frequency of the RF amplifier package. By arranging the second drain bond wire between the gate bond wire and the first drain bond wire, the RF amplifier package can be operated at a higher frequency.

Description

Technical Field

[0001] This invention relates to radio frequency (RF) amplifier packages. The invention further relates to semiconductor dies used in such amplifier packages. Background Technology

[0002] Figure 1A and Figure 1B Schematic top and cross-sectional views of known RF amplifier packages are shown respectively, while Figure 1C Its equivalent circuit is shown.

[0003] A known amplifier package has an output terminal 1, an input terminal 2, and a conductive substrate 3. The output terminal 1 and input terminal 2 are separated from the substrate 3 by a ceramic ring 16. After the RF amplifier package is assembled on a printed circuit board (PCB), the substrate 3 is typically connected to the PCB's ground.

[0004] A semiconductor die 4 is disposed on a substrate 3. An RF power field-effect transistor 'FET' 5 is disposed on the die. The RF power FET 5 includes a first set of drain fingers 6 and gate fingers 7, which are electrically connected to a first drain bond 8 and a gate bond 9, respectively. For example, the RF power FET 5 may include a silicon-based laterally diffused metal-oxide-semiconductor 'LDMOS' transistor. The substrate 3 is typically electrically connected to the source of the RF power FET 5. Furthermore, a copper or copper-based substrate may be used as the substrate 3 to allow for adequate cooling of the RF power FET 5.

[0005] Known RF amplifier packages further include capacitors C1 and C2, which can be implemented on other semiconductor dies or provided as discrete components. Figure 1A and Figure 1B In the process, capacitors C1 and C2 are formed on semiconductor dies 10 and 11, respectively. Figure 1A and Figure 1B In the diagram, a bonding strip 11' connected to the first end of C2 is shown, while the second end of C2 (not shown) is grounded. Similarly, a bonding strip 10' connected to the first end of C1 is shown, while the second end of C1 (not shown) is grounded.

[0006] Multiple bonding wires 12 extend from input terminal 2 to the first terminal of capacitor C2. As described above, the second terminal of this capacitor is grounded. For example, the substrate material of semiconductor die 11 can be conductive to allow a low-ohm connection from the second terminal of C2 through the substrate of semiconductor die 11 to the substrate 3 on which semiconductor die 11 is mounted. It should be noted that substrate 3 is most commonly a conductive substrate electrically grounded during use. The multiple bonding wires 12 have a given inductance, which inductance in Figure 1CThe equivalent circuit shown is represented by inductor L1. Multiple additional bonding wires 13 extend from the first end of C2 to the gate bonding strip 9. These multiple bonding wires... Figure 1C The inductor L2 is represented in the middle.

[0007] Two sets of multiple bond lines extend from the first drain bond line 8. Figure 1C Multiple drain bonding lines 15, represented by inductor L4, extend from the first drain bonding strip 8 to the output terminal 1. Figure 1C Multiple first bonding lines 14, represented by inductor L3, extend from the first drain bonding strip 8 to the first end of capacitor C1.

[0008] The RF power FET 5 includes parasitic components that affect the behavior of the transistor. One of these components is the output capacitance, which can be represented by the capacitor Cds disposed between the drain and source terminals of the RF power FET 5, such as... Figure 1C As shown. When this parasitic capacitance is not considered, it has a strong impact on the gain, power, and efficiency of the power amplifier.

[0009] A known method to mitigate the performance impact of ds is to utilize inductors placed parallel to the ds. These components together should exhibit parallel resonance at or near the amplifier's operating frequency. This ensures that the combined impedance of the ds and inductors is high enough to no longer significantly degrade the amplifier's RF behavior.

[0010] exist Figure 1C In this circuit, the inductor, placed parallel to Cds, is formed by multiple first bond lines 14, namely L3. Capacitor C1 should be large enough to act as an RF short circuit at or near the operating frequency. More specifically, the series connection of L3 and C1 should act as an inductor at or near the operating frequency to allow resonance in parallel with Cds. In DC mode, C1 blocks the DC path to ground.

[0011] An RF amplifier package according to the preamble of claim 1 is known from EP 3 499 717 A1. Figure 2A and Figure 2B The diagram shows a schematic top view and a cross-sectional view of the package. By comparison... Figure 1A and Figure 2A It can be seen that in Figure 2A In the process, a second drain bonding strip 8' is provided. A first set of drain fingers 6 extends between the first drain bonding strip 8 and the second drain bonding strip 8'. Furthermore, a capacitor C1 is integrated on the semiconductor die 4. The first end 20 of the capacitor C1 is connected to the second drain bonding strip 8' using multiple first bonding wires 14. Figure 2A The equivalent circuit of the embodiment is similar to Figure 1B The equivalent circuit shown.

[0012] exist Figure 2A In this embodiment, the second drain bonding strip 8' differs from the drain bonding strip 8, with multiple first bonding lines 14 extending from the second drain bonding strip 8' and multiple drain bonding lines 15 extending from the drain bonding strip 8. Furthermore, because the second drain bonding strip 8' is offset more towards the input side of the semiconductor die 4, there is less overlap between the current loops associated with the multiple first bonding lines 14 and the current loops associated with the multiple drain bonding lines 15. This results in... Figure 1C The mutual inductance between L3 and L4 is relatively low. Therefore, this will improve the efficiency and output impedance of the power amplifier.

[0013] Despite the advantages of using a second drain bonding strip, the applicant found... Figure 2A The layout is not optimal for RF amplifier packages that operate at relatively high frequencies. Summary of the Invention

[0014] Therefore, the object of the present invention is to provide an RF amplifier package that improves high-frequency performance.

[0015] According to the present invention, this objective is achieved using the RF amplifier package according to claim 1, characterized in that the RF power FET further includes a second set of drain fingers, each drain finger in the second set extending in the region between the second drain bonding strip and the gate bonding strip, wherein each of the plurality of gate fingers is operatively coupled to a corresponding drain finger in the first set of drain fingers and the second set of drain fingers. By using the modified positioning of the second drain bonding strip, a shorter first bonding line can be used, thereby increasing the resonant frequencies of L3 and Cds and allowing the RF amplifier package to operate at higher frequencies.

[0016] and Figure 2A Compared to the embodiments shown, the RF power FET of the present invention includes at least two amplification segments, namely: a first segment and a second segment, the first segment corresponding to the portion of the first group of drain fingers and gate fingers arranged adjacent to those drain fingers, and the second segment corresponding to the portion of the second group of drain fingers and gate fingers arranged adjacent to those drain fingers.

[0017] Each drain finger in the first set of drain fingers is arranged to align with a corresponding drain finger in the second set of drain fingers to form a corresponding pair of aligned drain fingers. Furthermore, each of the plurality of gate fingers is operatively coupled to a corresponding pair of aligned drain fingers.

[0018] Each drain finger in the first group of drain fingers may be connected to the second drain bonding strip at or near the first edge of the second drain bonding strip, and / or each drain finger in the second group of drain fingers may be connected to the second drain bonding strip at or near the second edge of the second drain bonding strip opposite to the first edge. For example, a semiconductor die may include a stack of metal layers disposed on a semiconductor substrate, the stack comprising multiple metal layers, wherein the second drain bonding strip is formed in the uppermost metal layer of the metal layer stack relative to the semiconductor substrate, and wherein the drain fingers and gate fingers in the first and second groups of drain fingers are formed in one or more lower metal layers at least at the location of the second drain bonding strip. Each drain finger in the first and second groups of drain fingers may be connected to the second drain bonding strip through a corresponding via between the uppermost metal layer and the one or more lower metal layers. The via may be disposed at or near the edge of the second drain bonding strip. Furthermore, the second drain bonding strip may include a substantially rectangular base and a plurality of protrusions, with a plurality of first bonding lines bonded to the base, and the plurality of protrusions extending from the base in a direction parallel to the longitudinal direction of the gate fingers, wherein each corresponding via terminates in a corresponding protrusion among the plurality of protrusions.

[0019] The vias used to electrically connect the drain fingers in the first set of drain fingers and the drain fingers in the second set of drain fingers can transmit mechanical forces applied to the rectangular base of the second drain bond bar during wire bonding to the lower drain finger in the first set of drain fingers and the second set of drain fingers. Lateral separation between the vias and the location where the wire bonding force is applied is achieved by arranging the vias below the protrusion. The applicant has found that this improves the reliability of the RF amplifier package because the wire bonding process is less likely to damage the drain or gate fingers extending below the second drain bond bar.

[0020] In addition to the above, the plurality of protrusions may include a plurality of second protrusions, each of the plurality of second protrusions extending from the rectangular base toward the gate bonding strip, wherein each drain finger of the second set of drain fingers is connected between the finger and the corresponding second protrusion using a corresponding via. Alternatively, the plurality of protrusions may include a plurality of first protrusions, each of the plurality of first protrusions extending from the rectangular base toward the first drain bonding strip, wherein each drain finger of the first set of drain fingers is connected between the finger and the corresponding first protrusion using a corresponding via.

[0021] The RF power FET may further include a third set of drain fingers, wherein each drain finger in the first set of drain fingers is integrally connected to a corresponding drain finger in the second set of drain fingers via a corresponding drain finger in the third set of drain fingers, thereby forming corresponding continuous drain fingers extending in the same metal layer of the metal layer stack. In this embodiment, the drain fingers of the RF power FET may have substantially the same length as the gate fingers. Each drain finger may include a first segment corresponding to a drain finger in the first set of drain fingers, a third segment corresponding to a drain finger extending below the second drain bonding strip, and a second segment corresponding to a drain finger in the second set of drain fingers.

[0022] The RF power FET may further include a plurality of shields formed in at least one of the one or more underlying metal layers, each shield being associated with a corresponding gate finger and disposed at least below the second drain bond bar, between the second drain bond bar and the gate finger. The use of shields according to the invention is particularly advantageous because the second drain bond bar can be capacitively coupled to the gate finger extending below the second drain bond bar. Preferably, each gate finger has a first side and a second side, the second side opposite to the first side, wherein the plurality of shields includes a plurality of first shields and a plurality of second shields, each first shield being associated with a corresponding gate finger and disposed at least below the second drain bond bar, between the second drain bond bar and the first side of the gate finger, and each second shield being associated with a corresponding gate finger and disposed at least below the second drain bond bar, between the second drain bond bar and the second side of the gate finger. In a particular embodiment, the first and second shields corresponding to the same gate finger may be integrally connected.

[0023] Each drain finger in the first set of drain fingers can extend on a first active region formed in the substrate between the second drain bonding strip and the first drain bonding strip, and each drain finger in the second set of drain fingers can extend on a second active region formed in the substrate between the second drain bonding strip and the gate bonding strip. For each gate finger, the first and second active regions associated with that finger are preferably adjacent to each other to form a single continuous active region. Therefore, in this embodiment, the second drain bonding strip is arranged on the active region. However, the present invention does not exclude embodiments in which the second drain bonding strip is not arranged on the active region. In such embodiments, the first and second regions are not adjacent.

[0024] The RF amplifier package may further include: a second DC blocking capacitor having a first terminal and a second terminal grounded; and multiple second bonding wires connecting a second drain bonding strip to the first terminal of the second DC blocking capacitor. By using the combination of the first and second DC blocking capacitors, more bonding wires can be arranged in parallel, thereby reducing the parallel inductance reaching ground. In this way, the resonant frequency can even be further increased, at which the output capacitance is compensated. More specifically, the multiple first bonding wires and the first DC blocking capacitor are preferably used together as a parallel inductor at frequencies close to or within the operating frequency range, and if multiple second bonding wires are provided, the multiple second bonding wires and the second DC blocking capacitor are preferably used together as a parallel inductor at frequencies close to or within the operating frequency range, at which the parallel inductor resonates with the output capacitance.

[0025] The semiconductor die may include a first edge and a second edge disposed opposite to it, wherein the first edge of the semiconductor die is disposed between an input terminal and a gate bonding strip, and wherein the second edge of the semiconductor die is disposed between an output terminal and a first drain bonding strip. A first DC blocking capacitor may be disposed near one of the first and second edges. Additionally, a second DC blocking capacitor may be disposed near an edge of the first and second edges of the semiconductor die that is different from the edge near which the first DC blocking capacitor is located. Alternatively, at least one of the first and second DC blocking capacitors may be integrated onto the semiconductor die.

[0026] The RF power FET can be a silicon-based laterally diffused metal-oxide-semiconductor 'LDMOS' transistor or a gallium nitride-based FET. Furthermore, the operating frequency range can be between 100 MHz and 40 GHz, preferably between 500 MHz and 10 GHz.

[0027] According to a second aspect, the present invention further provides a semiconductor die configured to include the aforementioned semiconductor die in an RF amplifier package containing an RF power FET. Attached Figure Description

[0028] The invention will now be described in more detail with reference to the accompanying drawings, in which:

[0029] Figures 1A to 1C The top view, cross-sectional view, and equivalent circuit of a known RF amplifier package are shown respectively;

[0030] Figure 2A and Figure 2B Top view and cross-sectional view of another known RF amplifier package are shown respectively;

[0031] Figure 3A and Figure 3B A top view and a cross-sectional view of an embodiment of the RF amplifier package according to the present invention are shown respectively;

[0032] Figure 4A and Figure 4B A cross-sectional view of an embodiment of an RF amplifier package according to the present invention is shown, indicating the active region of the RF power FET;

[0033] Figure 5 A cross-sectional view of another embodiment of the RF amplifier package according to the present invention is shown;

[0034] Figure 6 A detailed top view of an embodiment of the second drain bonding strip according to the present invention is shown; and

[0035] Figures 7A to 7E It shows the relationship with Figure 6 A cross-sectional view of the layer stack corresponding to the embodiment. Detailed Implementation

[0036] Figure 3A A top view of an embodiment of the RF amplifier package according to the present invention is shown. Figure 3B The corresponding cross-sectional view is shown in the figure. Here, the same reference numerals as those used in the known RF amplifier packages shown in Figures 1 and 2 are used to denote the same or similar components.

[0037] It should be noted that this invention is not limited to a specific packaging technology. More specifically, although Figure 3A A ceramic ring 16 is shown for separating input terminal 2 and output terminal 1 from the conductive substrate 3; however, those skilled in the art will readily understand that the invention can also be applied to other packaging techniques. For example, the invention can be applied to molded leadframe packages. In such packages, a cured molding compound is used to separate the terminals 1 and 2, shaped as leads, from the substrate 3. The cross-section of such a package can be similar to... Figure 3B The cross-section differs in that the ceramic ring 16 can be replaced by a cured molding compound body. Furthermore, a cap can be arranged to provide an air cavity within the package. Alternatively, the cap can be formed during the molding process. In such packages, all electronic components are completely encapsulated by the cured molding compound. Additionally, instead of molded leadframe packages, the invention can also be applied to flat leadless packages, such as DFN or QFN. Furthermore, the substrate 3 can be in the form of a metal flange, metal die pads, or other thermally and / or electrically conductive media.

[0038] By comparison Figure 3A and Figure 2AIt can be clearly seen that, according to the present invention, the second drain bonding strip 8' is placed close to the first drain bonding strip 8. Furthermore, in addition to the first set of drain fingers 6 extending between the second drain bonding strip 8' and the first drain bonding strip 8, a second set of drain fingers 6' extending between the second drain bonding strip 8' and the gate bonding strip 9 is also provided. Figure 3A In this configuration, drain fingers 6 extend from one edge of the second drain bonding strip 8' toward the first drain bonding strip 8, while drain fingers 6' extend from the opposite edge of the second drain bonding strip 8 toward the gate bonding strip 9. More specifically, drain fingers 6' are connected to drain fingers 6 only via the second drain bonding strip 8'. Figure 3A In the middle, each gate finger 7 extends below the second drain bonding strip 8'.

[0039] By changing the position of the second drain bond 8', the required length of the bond line 14 can be adjusted for a given operating frequency range. For example, when the RF amplifier package is to operate at a relatively high frequency, the position of the second drain bond 8' must be designed to be closer to the first drain bond 8.

[0040] As will be combined later Figures 7A to 7D As can be seen, each drain finger 6 in the first group of drain fingers can also be connected to a corresponding drain finger 6' in the second group of drain fingers to form a single continuous drain finger. This single continuous drain finger passes under the second drain bonding strip 8'.

[0041] exist Figure 3A In this embodiment, a DC blocking capacitor C1 is integrated on the semiconductor die 4. The DC blocking capacitor C1 includes a first end connected to the bonding strip 20 or bonding pad and a grounded second end. The second end will be grounded during use. For example, the semiconductor substrate of the semiconductor die 4 may be conductive to allow grounding through this substrate and a conductive substrate 3, wherein the conductive substrate 3 is fixedly connected to a ground plane on a PCB on which the RF amplifier package is mounted.

[0042] Figure 4A and Figure 4B An example of an RF amplifier package according to the present invention is shown, indicating the active region. Here, Figure 4A This indicates that separate active regions 21 and 22 are formed on opposite sides of the second drain bonding strip 8'. In this embodiment, the drain finger 6' and the drain finger 6 can only be connected via the second drain bonding strip 8'. This is different from... Figure 4B The implementation methods differ, in Figure 4B In one embodiment, a continuous active region 23 is formed for each gate finger 7. In a later embodiment, drain fingers 6 and drain fingers 6' are interconnected using drain fingers 6"". This is in Figure 6 It is shown in more detail below.

[0043] Figure 5 A cross-sectional view of another embodiment of the RF amplifier package according to the present invention is shown. In this embodiment, another DC blocking capacitor C3 is arranged on the gate side of the semiconductor die 4. The capacitor C3 has a ground terminal and a non-ground terminal, wherein the non-ground terminal is connected to the bonding strip 20' or the bonding pad. The bonding wire 14' connects the non-ground terminal of the capacitor C3 to the second drain bonding strip 8'.

[0044] The combination of bond wire 14' and capacitor C3 forms a parallel LC network whose resonant frequency is significantly lower than the operating frequency range of the RF amplifier package. A similar consideration is made for the combination of bond wire 14 and capacitor C1. In other words, at the operating frequency, the RF power FET 5 sees its output capacitance Cds arranged in parallel with the inductance formed by bond wire 14 and the inductance formed by bond wire 14'. By using two parallel LC networks, a higher resonant frequency is achieved, allowing the RF amplifier package to operate at higher frequencies.

[0045] like Figure 5 As shown, bonding strip 20' is arranged between gate bonding strip 9 and bonding strip 11'. However, the present invention does not exclude embodiments in which bonding strip 20' is arranged between gate bonding strip 9 and second drain bonding strip 8'. In other embodiments, capacitor C3 is integrated on semiconductor die 11, either between input terminal 2 and bonding strip 11', or between bonding strip 11' and gate bonding strip 9. Furthermore, in this and other embodiments, C2 may be arranged on semiconductor die 4.

[0046] Figure 6 A detailed top view of an embodiment of the second bonding bar 8' is shown. Figures 7A to 7D A cross-sectional view of the layer stack corresponding to the second bonding strip 8' is shown. The construction of the second bonding strip 8' can be applied to... Figure 3A , Figure 4A , Figure 4B and Figure 5 The example shown.

[0047] like Figure 6 As shown, each drain finger 6' in the second set of drain fingers is arranged to be aligned with the corresponding drain finger 6 in the first set of drain fingers. Furthermore, the second drain bonding strip 8' includes a rectangular base 24, a first protrusion 24' extending from the rectangular base 24 toward the first drain bonding strip 8, and a second protrusion 24" extending from the rectangular base 24 toward the gate bonding strip 9.

[0048] Each first protrusion 24' connects to a corresponding drain finger 6 in the first set of drain fingers, and each second protrusion 24' connects to a corresponding drain finger 6' in the second set of drain fingers. These connections are implemented using metal-to-metal vias V. Furthermore, gate fingers 7 extend below the second drain bonding strip 8'.

[0049] Figure 6 Three dashed lines are shown, representing the lines along which the cross-sectional view was obtained. More specifically, Figure 7A Corresponding to line A, Figure 7B Corresponding to line B, Figure 7C and Figure 7D There are two possibilities for line C.

[0050] Figure 7A It shows the corresponding Figure 6 The cross-sectional view of line A in the diagram shows that five metal layers, M0-M4, are stacked on the semiconductor die 4, but the present invention is not limited to this number of layers.

[0051] The bottom metal layer M0 is used to connect to the intrinsic drain and gate contacts of the RF power FET 5. Figures 7A to 7D In this designation, the letter "d" indicates the intrinsic drain contact, the letter "g" indicates the intrinsic gate contact, and the letter "s" indicates the source region, which is typically grounded during operation. For example, the source region is connected to the conductive substrate 3 via a through-hole within the semiconductor die 4. Alternatively, the semiconductor substrate of the semiconductor die 4 may be conductive.

[0052] Figure 7A The intrinsic drain contact is shown connected below the second drain bonding strip 8' to a metal strip 26 on metal layers M1, M2, and M3. These strips bonded to the intrinsic drain contact... Figure 6 The drain finger 6” in the third group of drain fingers is commonly referred to as such. It should be noted that vias are used to connect the metal layers. These vias are spaced apart along the longitudinal direction of the gate finger 7. Therefore, these vias may not be shown in cross-sectional views taken at different locations below the second drain bonding strip 8’. This is for… Figures 7B to 7D The cross-sectional view in the diagram is also valid.

[0053] Figure 7A The intrinsic gate contact is also shown to be connected to metal layers M1 and M2. More specifically, a large stripe 27 is present on metal layer M2. This stripe is connected to a smaller stripe 28 on metal layer M1 at spaced-apart locations. Figure 7A The connector 29 between strip 28 on metal layer M1 and strip 27 on metal layer M2 is shown, while Figure 7BThe connector is not shown because the cross-sectional view is taken at a different location than the connector described above. Strip 27 on metal layer M2... Figure 6 It is referred to as gate finger 7.

[0054] Figure 7A Shielding fingers 25, 25' are further shown, which are connected to the source region using multiple vias (not shown) and lateral connectors (not shown) similar to connector 29. Shielding fingers 25, 25' limit the feedback capacitance between the second drain bonding strip 8' and the gate finger 7.

[0055] If available Figure 7B As seen in the image, the drain finger 6' is connected to the second protrusion 24" via a through-hole between metal layers M3 and M4. Furthermore, metal layers M3, M2, and M1 of the drain finger 6' are integrally connected to metal layers M3, M2, and M1 of the drain finger 6". Similarly, metal layers M3, M2, and M1 of the drain finger 6 are integrally connected to metal layers M3, M2, and M1 of the drain finger 6". Furthermore, as... Figure 7C As shown, outside the second drain bonding strip 8', the drain finger 6' (and drain finger 6) may also include tracks on the metal layer M4 for reducing the inductance and / or resistance of the drain finger 6'. This can also be applied to applications such as... Figure 7D The gate finger 7 is shown. Figure 7D It also indicates that, under these conditions, the shielding fingers 25, 25' are not applied to the outside of the second drain bonding strip 8'.

[0056] Figure 7E It shows along Figure 6 Two possible cross-sections are taken from line D in the diagram. Figure 7E In the top diagram, drain fingers 6, 6', and 6" extend within metal layers M0, M1, M2, and M3. As shown, these layers are interconnected using vias. Drain fingers 6 and 6' are connected to the first protrusion 24' and the second protrusion 24" respectively, which are implemented in metal layer M4. Figure 7E In the bottom diagram, drain fingers 6 and 6' are also implemented in the metal layer M4. In the latter case, the portion of the metal layer M4 of the drain fingers 6" is integrally formed with the second drain bonding strip 8'.

[0057] In the foregoing description, detailed embodiments of the invention have been used to illustrate the invention. However, the invention is not limited to these embodiments, and various modifications may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A radio frequency (RF) amplifier package, comprising: Input terminal (2); Output terminal (1); Substrate (3); The first DC blocking capacitor (C1) has a first terminal and a grounded second terminal; Semiconductor die (4) mounted on the substrate, the semiconductor die comprising: Semiconductor substrate; An RF power field-effect transistor FET (5) is integrated on the semiconductor substrate, the RF power FET having an output capacitance (Cds) and configured to operate within the operating frequency range; Gate bonding strip (9) is connected directly to the input terminal using multiple gate bonding wires or connected to the input terminal via an input impedance matching stage; The first drain bonding strip (8) is directly connected to the output terminal using multiple drain bonding wires or connected to the output terminal via an output impedance matching stage; The second drain bonding strip (8') is disposed between the gate bonding strip and the first drain bonding strip; Multiple first bonding lines (14) connect the second drain bonding strip to the first end of the first DC blocking capacitor; The RF power FET includes: A plurality of gate fingers (7) are electrically connected to the gate bonding strip and each of the plurality of gate fingers extends from the gate bonding strip toward the first drain bonding strip and extends below the second drain bonding strip; The first group of drain fingers (6) extends in the region between the second drain bonding strip and the first drain bonding strip. The RF power FET is characterized in that it further includes a second set of drain fingers (6'), each of the second set of drain fingers extending in the region between the second drain bonding bar and the gate bonding bar, wherein each of the plurality of gate fingers is operatively coupled to a corresponding drain finger in the first set of drain fingers and the second set of drain fingers; Wherein, the drain fingers in the first group of drain fingers are arranged to align with the corresponding drain fingers in the second group of drain fingers to form a plurality of pairs of aligned drain fingers, and wherein the gate fingers are operatively coupled to the plurality of pairs of aligned drain fingers.

2. The RF amplifier package according to claim 1, wherein, Each of the first set of drain fingers is connected to the second drain bonding strip at a first edge of the second drain bonding strip, and wherein each of the second set of drain fingers is connected to the second drain bonding strip at a second edge of the second drain bonding strip opposite to the first edge.

3. The RF amplifier package according to claim 2, wherein, The semiconductor die includes a stack of metal layers disposed on the semiconductor substrate, the stack of metal layers including a plurality of metal layers (M0, M1, M2, M3, M4), wherein the second drain bonding strip is formed in the uppermost metal layer (M4) of the metal layer stack relative to the semiconductor substrate, and wherein the drain fingers of the first set of drain fingers and the second set of drain fingers and the gate fingers are formed in one or more lower metal layers at least at the location of the second drain bonding strip, wherein each drain finger of the first set of drain fingers and the second set of drain fingers is connected to the second drain bonding strip through a corresponding via between the uppermost metal layer and the one or more lower metal layers, the via being disposed at the edge of the second drain bonding strip.

4. The RF amplifier package according to claim 3, wherein, The second drain bonding strip includes a substantially rectangular base (24) and a plurality of protrusions, the plurality of first bonding lines being bonded to the base, the plurality of protrusions extending from the base in a direction parallel to the longitudinal direction of the gate fingers, wherein each corresponding via terminates in a corresponding protrusion among the plurality of protrusions.

5. The RF amplifier package according to claim 4, wherein, The plurality of protrusions includes a plurality of second protrusions (24'), each of the plurality of second protrusions extending from the rectangular base toward the gate bonding strip, wherein each drain finger of the second set of drain fingers is connected between the drain finger and the corresponding second protrusion using a corresponding via, wherein the plurality of protrusions includes a plurality of first protrusions (24'), each of the plurality of first protrusions extending from the rectangular base toward the first drain bonding strip, wherein each drain finger of the first set of drain fingers is connected between the drain finger and the corresponding first protrusion using a corresponding via.

6. The RF amplifier package according to any one of claims 3 to 5, wherein, The RF power FET further includes a third set of drain fingers (6), wherein each drain finger in the first set of drain fingers is integrally connected to a corresponding drain finger in the second set of drain fingers via a corresponding drain finger in the third set of drain fingers, thereby forming corresponding continuous drain fingers extending in the same metal layer of the metal layer stack.

7. The RF amplifier package according to any one of claims 3 to 5, wherein, The RF power FET further includes a plurality of shields (25, 25') formed in at least one of the one or more underlying metal layers, each shield corresponding to a corresponding gate finger and disposed at least below the second drain bond bar and between the second drain bond bar and the gate finger.

8. The RF amplifier package according to claim 7, wherein, Each gate finger has a first side and a second side, the second side being opposite to the first side. The plurality of shields include a plurality of first shields (25) and a plurality of second shields (25'). Each first shield corresponds to a corresponding gate finger and is arranged at least below the second drain bonding strip and between the second drain bonding strip and the first side of the gate finger. Each second shield corresponds to a corresponding gate finger and is arranged at least below the second drain bonding strip and between the second drain bonding strip and the second side of the gate finger.

9. The RF amplifier package according to claim 8, wherein, The first and second shields corresponding to the same gate finger are integrally connected.

10. The RF amplifier package according to any one of claims 1 to 5, wherein, Each drain finger in the first set of drain fingers extends on a first active region, the first active region being formed in the substrate and located between the second drain bonding bar and the first drain bonding bar, and wherein each drain finger in the second set of drain fingers extends on a second active region, the second active region being formed in the substrate and located between the second drain bonding bar and the gate bonding bar; In this configuration, for each gate finger, a first active region and a second active region corresponding to the gate finger are adjacent to each other to form a single continuous active region.

11. The RF amplifier package according to any one of claims 1 to 5, further comprising: The second DC blocking capacitor (C3) has a first terminal and a grounded second terminal; Multiple second bonding lines (14') connect the second drain bonding strip to the first end of the second DC blocking capacitor.

12. The RF amplifier package according to any one of claims 1 to 5, wherein, The plurality of first bonding wires and the first DC blocking capacitor are used together as a parallel inductor at a frequency close to or within the operating frequency range, and the parallel inductor resonates with the output capacitor at the frequency.

13. The RF amplifier package according to claim 11, wherein, The plurality of first bonding wires and the first DC blocking capacitor, as well as the plurality of second bonding wires and the second DC blocking capacitor, together serve as a parallel inductor at a frequency close to or within the operating frequency range, and the parallel inductor resonates with the output capacitor at the frequency.

14. The RF amplifier package according to any one of claims 1 to 5, wherein, The semiconductor die includes a first edge and a second edge arranged opposite to each other, wherein the first edge of the semiconductor die is arranged between the input terminal and the gate bonding strip, and wherein the second edge of the semiconductor die is arranged between the output terminal and the first drain bonding strip; The first DC blocking capacitor is disposed at one of the first edge and the second edge.

15. The RF amplifier package according to claim 11, wherein, The semiconductor die includes a first edge and a second edge arranged opposite to each other, wherein the first edge of the semiconductor die is arranged between the input terminal and the gate bonding strip, and wherein the second edge of the semiconductor die is arranged between the output terminal and the first drain bonding strip; The first DC blocking capacitor is disposed at one of the first edge and the second edge; The second DC blocking capacitor is disposed at the edge of the first and second edges of the semiconductor die, at an edge different from the edge approaching the first DC blocking capacitor.

16. The RF amplifier package of claim 11, wherein, At least one of the first and second DC blocking capacitors is integrated on the semiconductor die; and / or Among them, the RF power FET is a silicon-based laterally diffused metal-oxide-semiconductor LDMOS transistor or a gallium nitride-based FET; and / or The operating frequency range is between 100MHz and 40GHz; and / or The substrate is a conductive substrate, and the conductive substrate is electrically connected to the source of the RF power FET.

17. The RF amplifier package of claim 16, wherein, The operating frequency range is between 500MHz and 10GHz.

18. A semiconductor die configured as a semiconductor die in an RF amplifier package according to any one of claims 1 to 17.

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