Memory

Abstract

The present invention provides a memory. A plurality of node contact windows are directly defined by using a bit line structure. Since the height of the node contact windows is relatively low and the aspect ratio is relatively small at this time, when forming a first electrical transmission layer in the node contact windows, the requirements for the formation process of the first electrical transmission layer are relatively small. After forming the first electrical transmission layer, a spacer pattern is formed. The adjacent spacer patterns are spaced apart by an opening, and the opening at least exposes a part of the top of the first electrical transmission layer. A second electrical transmission layer is formed in the opening. Since the height of the opening is relatively low and the aspect ratio is relatively small at this time, when forming the second electrical transmission layer in the opening, the requirements for the formation process of the second electrical transmission layer are also relatively small. Moreover, after electrically connecting the second electrical transmission layer and the first electrical transmission layer to form a node contact structure, no adverse impact will be caused to the memory in this step.

Description

[0001] This is a divisional application of the invention case with the application number "202010590205.5", the application date "June 24, 2020", and the application title "Memory and Method of Forming the Same". Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a memory. Background Art

[0003] A memory, such as a Dynamic Random Access Memory (DRAM), generally has a memory cell array including a plurality of memory cells arranged in an array. The memory also has a plurality of bit line structures, each bit line structure being electrically connected to a corresponding memory cell, and the memory further includes a capacitor structure for storing charges representing stored information, and the memory cell can be electrically connected to the capacitor structure through a node contact structure, thereby realizing the storage function of each memory cell.

[0004] Currently, the method for forming the memory includes: forming a stacked bit line conductive layer, a bit line masking layer, and a dielectric layer on a substrate and patterning them, with the remaining bit line conductive layer and bit line masking layer constituting the bit line structure, and the remaining dielectric layer constituting an insulating pattern, using the bit line structure and the insulating pattern to define a node contact window; then filling a conductive material in the node contact window, and the conductive material also extends the insulating pattern; finally, etching the conductive material to form a plurality of openings to space the conductive material into a plurality of node contact structures. The insulating pattern is used to protect the bit line structure when etching the conductive material to form the openings and prevent the bit line structure from being etched and damaged. However, at the same time, the insulating pattern will increase the height of the node contact window, resulting in an increase in the aspect ratio of the node contact window, thus increasing the difficulty of filling the conductive material in the node contact window and imposing extremely high requirements on the process for forming the conductive material; and when patterning the bit line conductive layer, the bit line masking layer, and the dielectric layer, due to the relatively thick stacked film layers, the etching difficulty is very high, and the requirements for the etching process are also extremely high. Summary of the Invention

[0005] The purpose of the present invention is to provide a memory, which reduces the process requirements during the preparation of the memory and does not have an adverse effect on the performance of the memory.

[0006] To achieve the above object, the present invention provides a method for forming a memory, including:

[0007] Providing a substrate on which a plurality of bit line structures are formed, and the bit line structures define a plurality of node contact windows;

[0008] Form a first electrical conduction layer in the node contact window, and the first electrical conduction layer at least fills the node contact window to a partial depth;

[0009] Form a spacer pattern on the bit line structure, the spacer pattern at least covers a partial top of the bit line structure, and there is an opening gap between adjacent spacer patterns, and the opening at least exposes a partial top of the first electrical conduction layer; and,

[0010] Form a second electrical conduction layer in the opening, and electrically connect the second electrical conduction layer to the first electrical conduction layer.

[0011] Optionally, form the opening while forming the spacer pattern, and the steps of forming the spacer pattern and the opening include:

[0012] Form a spacer material layer on the bit line structure, the spacer material layer covers the bit line structure and fills the remaining depth of the node contact window; and,

[0013] Etch the spacer material layer to form a plurality of the openings, and the remaining spacer material layer constitutes the spacer pattern.

[0014] Optionally, in a direction perpendicular to the depth direction, the position of the opening corresponds to the position of the node contact window; or, in a direction perpendicular to the depth direction, the position of the opening has an offset from the position of the node contact window, and the opening also laterally extends to expose a partial top of the bit line structure.

[0015] Optionally, the spacer material layer includes a buffer material layer and an insulating material layer, the buffer material layer covers the bit line structure and extends to cover the inner wall of the remaining depth of the node contact window, and the insulating material layer is located on the buffer material layer and fills the remaining depth of the node contact window;

[0016] The buffer material layer is an insulating material;

[0017] Or, the buffer material layer is a conductive material, and before forming the second electrical conduction layer after forming the opening, it further includes:

[0018] Form an insulating sidewall at least on the sidewall of the opening to electrically isolate the buffer material layer from the first electrical conduction layer and the second electrical conduction layer.

[0019] The present invention further provides a memory, including:

[0020] A substrate;

[0021] A plurality of bit line structures, located on the substrate and defining a plurality of node contact windows, and the bit line structure includes a bit line conductive layer and a bit line shielding layer covering the bit line conductive layer;

[0022] A first electrical conduction layer, located in the node contact window, and at least partially filling the node contact window in terms of depth;

[0023] A second electrical conduction layer, covering part of the top of the first electrical conduction layer and part of the top of the bit line shielding layer and electrically connected to the first electrical conduction layer; and,

[0024] A spacer pattern, covering the remaining top of the bit line shielding layer and the remaining top of the first electrical conduction layer to space adjacent second electrical conduction layers apart.

[0025] Optionally, the first electrical conduction layer completely fills the node contact window, wherein the bottom of the second electrical conduction layer is flush with the top of the bit line shielding layer.

[0026] Optionally, the spacer pattern includes an insulating material layer.

[0027] Optionally, the spacer pattern further includes a buffer material layer, and the buffer material layer is located between the insulating material layer and the first electrical conduction layer and between the insulating material layer and the bit line shielding layer.

[0028] Optionally, the material of the buffer material layer is a material having an etching selectivity ratio with respect to the bit line shielding layer.

[0029] Optionally, the material of the buffer material layer is a conductive material, and the memory further includes:

[0030] An insulating sidewall, at least covering the sidewalls of the spacer pattern to electrically isolate the buffer material layer from the first electrical conduction layer and the second electrical conduction layer.

[0031] The present invention further provides a memory, including:

[0032] A substrate;

[0033] A plurality of bit line structures, located on the substrate and defining a plurality of node contact windows, and the bit line structures include a bit line conductive layer and a bit line shielding layer covering the bit line conductive layer;

[0034] A first electrical conduction layer, located in the node contact window, and at least partially filling the node contact window in terms of depth;

[0035] A second electrical conduction layer, filling the remaining depth of the node contact window and extending upward, and the second electrical conduction layer is also electrically connected to the first electrical conduction layer;

[0036] A spacer pattern, covering the top of the bit line shielding layer to space adjacent second electrical conduction layers apart; and,

[0037] An insulating sidewall is at least located on the sidewalls of the spacer pattern to electrically isolate the spacer pattern from the first electrical transmission layer and the second electrical transmission layer.

[0038] Optionally, the spacer pattern includes a buffer material layer and an insulating material layer covering the buffer material layer, and the material of the buffer material layer is a conductive material having an etching selectivity ratio with the bit line shielding layer.

[0039] Optionally, the material of the buffer material layer is a conductive material.

[0040] Optionally, the buffer material layer also extends from the bit line shielding layer into the node contact window at the remaining depth, and the insulating sidewall is also located between the buffer material layer and the first electrical transmission layer.

[0041] The memory provided by the present invention has the following beneficial effects:

[0042] 1) A plurality of node contact windows are directly defined by using the bit line structure. Since the height of the node contact window is relatively low and the aspect ratio is relatively small at this time, when forming the first electrical transmission layer in the node contact window, the requirements for the formation process of the first electrical transmission layer are relatively small; after forming the first electrical transmission layer, the spacer pattern is formed, and the adjacent spacer patterns are spaced apart by an opening, and the opening at least exposes a part of the top of the first electrical transmission layer, and the second electrical transmission layer is formed in the opening. Since the height of the opening is relatively low and the aspect ratio is relatively small at this time, when forming the second electrical transmission layer in the opening, the requirements for the formation process of the second electrical transmission layer are also relatively small, and furthermore, after electrically connecting the second electrical transmission layer and the first electrical transmission layer to form a node contact structure, no adverse effect will be caused to the memory in this step;

[0043] 2) The second electrical transmission layer can extend to cover a part of the top of the bit line structure, and the top surface width of the second electrical transmission layer increases, so that the area of the capacitor structure formed on the second electrical transmission layer subsequently can also be increased, thereby improving the storage performance of the memory;

[0044] 3) The spacer pattern includes a buffer material layer and an insulating material layer covering the buffer material layer, and the buffer material layer can provide a buffering effect when etching to form an opening, thereby protecting the first electrical transmission layer and the bit line shielding layer from being over-etched;

[0045] 4) When the buffer material layer is a conductive material, the etching selectivity ratio between the buffer material layer and the bit line shielding layer can be increased, thereby better protecting the bit line structure. Description of the Drawings

[0046] Figure 1 It is a flowchart of a method for forming a memory provided in Embodiment 1 of the present invention;

[0047] Figure 2a This is a simplified layout of the memory provided by the first embodiment of the present invention. Figures 2b - 2g This is a schematic structural diagram corresponding to the corresponding steps of the method for forming the memory provided by the first embodiment of the present invention, where Figures 2b - 2f is Figure 2a a schematic cross-sectional view of the structure in along the aa' and bb' directions;

[0048] Figure 3a and Figure 3b are schematic structural diagrams of the memory provided by the second embodiment of the present invention;

[0049] Figures 4a - 4d are schematic structural diagrams of the memory provided by the third embodiment of the present invention;

[0050] Figure 5a and Figure 5b are schematic structural diagrams of the memory provided by the fourth embodiment of the present invention;

[0051] Among them, the reference numerals are:

[0052] 100 - Substrate; AA - Active region; SIT - Trench isolation structure; 500 - Node contact window; 510 - Opening; 610 - Insulating layer; 620 - Stacked material layer; 630 - Electrode groove;

[0053] WL - Word line structure;

[0054] BL - Bit line structure; 200a - First bit line conductive layer; 200b - Second bit line conductive layer; 200c - Third bit line conductive layer; 200d - Bit line masking layer; 200e - Spacer sidewall;

[0055] SC - Node contact structure; 300a - Conductive contact layer; 300b - First signal transmission layer; 300c - Second signal transmission layer; 300d - Conductive barrier layer;

[0056] 400 - Spacer pattern, 400a - Buffer material layer; 400b - Insulating material layer; 400c - Insulating sidewall. Detailed implementation manners

[0057] The following will describe the detailed implementation manners of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0058] Embodiment 1

[0059] Figure 1Schematic structural diagram of the method for forming a memory provided by an embodiment of the present invention. As Figure 1 shown, the method for forming the memory includes:

[0060] Step S100: Provide a substrate, on which a plurality of bit line structures are formed, and the bit line structures define a plurality of node contact windows;

[0061] Step S200: Form a first electrical transmission layer in the node contact windows, and the first electrical transmission layer at least fills part of the depth of the node contact windows;

[0062] Step S300: Form a spacer pattern on the bit line structures, the spacer pattern at least covers part of the top of the bit line structures, and there is an opening between adjacent spacer patterns, and the opening at least exposes part of the top of the first electrical transmission layer; and,

[0063] Step S400: Form a second electrical transmission layer in the opening, and electrically connect the second electrical transmission layer to the first electrical transmission layer.

[0064] Specifically, please refer to Figures 2a - 2g , which is the schematic structural diagram corresponding to the corresponding steps of the method for forming the memory provided by this embodiment. Among them, Figures 2b - 2g is Figure 2a the cross-sectional schematic diagram in the aa' direction and the bb' direction in Figures 2a - 2f . Hereinafter, the method for forming the memory provided by this embodiment will be described in detail with reference to

[0065] Refer to Figure 2a and Figure 2b shown, execute step S100, provide a substrate 100, in which a trench isolation structure STI is formed, and the trench isolation structure SIT defines a plurality of active regions AA extending along a first predetermined direction (Z direction).

[0066] Refer to Figure 2a and Figure 2b shown, form a word line structure WL in the substrate 100, the word line structure WL extends along a second predetermined direction (X direction), and passes through the corresponding active regions AA and the trench isolation structure STI. Optionally, the lateral width (width dimension perpendicular to the height direction) of the word line structure WL located in the active region AA is smaller than the lateral width of the word line structure WL located in the trench isolation structure STI; the bottom of the word line structure WL located in the active region AA is lower than the bottom of the word line structure WL located in the trench isolation structure STI.

[0067] The step of forming the word line structure WL may be as follows:

[0068] Form word line trenches (not shown) in the substrate 100 and the word line trenches extend along a second predetermined direction;

[0069] Form a gate dielectric layer on the substrate 100, the gate dielectric layer covering the inner walls of the word line trenches, and the gate dielectric layer can serve as an insulating layer for isolating the word lines and the active regions AA;

[0070] Then form a gate conductive layer in the word line trenches, the gate conductive layer being a film layer having conductivity, such as polysilicon or tungsten, etc. The gate conductive layer fills part of the depth of the word line trenches; specifically, for example, the height of the gate conductive layer in the word line trenches can be reduced by an etch-back process so that the top surface of the gate conductive layer is lower than the upper surface of the substrate. In this way, the lower part of the word line trenches is filled with the gate conductive layer, and the upper part of the word line trenches remains vacant;

[0071] Form a gate insulating layer on the gate conductive layer, the gate insulating layer covering the gate conductive layer 200b and completely filling the word line trenches, and the gate dielectric layer, the gate conductive layer, and the gate insulating layer together constitute the word line structure WL.

[0072] It should be noted that although the mask layer on the surface of the substrate 100 is not shown in the drawings of this embodiment, it should be recognized that during the process of etching the substrate 100 to form the word line trenches, a mask layer is usually formed on the surface of the substrate 100 to prevent the regions of the substrate 100 other than the corresponding trenches from being etched.

[0073] Continue to refer to Figure 2b As shown, the method for forming the memory further includes: forming source / drain regions in the substrate 100, the side edge boundaries of the source / drain regions extending to the side walls of the word line trenches near the top openings, and the bottom boundaries of the source / drain regions being lower than the top positions of the gate conductive layer, so that there is an overlapping region facing each other between the source / drain regions and the gate conductive layer, and in the overlapping region, the gate conductive layer and the source / drain regions are separated from each other by the gate dielectric layer.

[0074] Specifically, the source / drain regions include a first source / drain region and a second source / drain region, and the first source / drain region and the second source / drain region are respectively located on both sides of the word line structure WL. In this embodiment, the side edge boundary of the first source / drain region also extends to the side wall of the trench isolation structure STI.

[0075] It should be noted that in this embodiment, the source / drain regions are prepared after forming the word line trenches and the word line structure WL. However, in other embodiments, the source / drain regions can also be formed first, and then the word line trenches and the word line structure WL are prepared in sequence, which is not limited here.

[0076] Please refer to Figure 2a and Figure 2b As shown, a plurality of bit line structures BL are formed on the substrate 100. The bit line structures BL extend along a third predetermined direction (Y direction). A plurality of node contact windows 500 are defined on the substrate 100 by the plurality of bit line structures BL. The plurality of node contact windows 500 are aligned and arranged in multiple rows in both the second predetermined direction and the third predetermined direction. The node contact window 500 referred to in this embodiment refers to the area between adjacent bit line structures BL and under the top of the bit line structure BL. That is to say, the top of the node contact window 500 is flush with the top of the bit line structure BL.

[0077] Specifically, when forming the bit line structure BL, a bit line trench needs to be formed first. Since the bit line trench forms the bit line structure BL in subsequent steps, the bit line trench needs to extend along the third predetermined direction. A part of the bit line trench extends into the active region AA of the substrate 100 and is located between two word line structures WL in the active region AA, and the other part is located above the shallow trench isolation structure STI.

[0078] Then, a bit line structure BL is formed in the bit line trench. The bit line structure BL includes three stacked conductive material layers. Based on this, the formed bit line structure BL can include a first bit line conductive layer 200a, a second bit line conductive layer 200b, and a third bit line conductive layer 200c. Further, the bit line structure BL further includes a bit line masking layer 200d. The bit line masking layer 200d can be a patterned film layer and is formed above the three conductive material layers. In an alternative solution, for example, the patterned bit line masking layer 200d is used to perform a patterning process on the conductive material layers below it in sequence. In this embodiment, the method for forming the bit line structure BL further includes: forming spacer sidewalls 200e on the sidewalls of the first bit line conductive layer 200a, the second bit line conductive layer 200b, the third bit line conductive layer 200c, and the bit line masking layer 200d.

[0079] Please refer to Figure 2b As shown, further, after defining the node contact window 500, it further includes etching the bottom of the substrate 100 of the node contact window 500 to make at least part of the bottom of the node contact window 500 further extend into the active region of the substrate 100, so as to make the subsequent formed node contact structure have a better electrical connection effect with the active region AA.

[0080] Please refer to Figure 2cAs shown, step S200 is performed to form a conductive contact layer 300a in the node contact window 500, and the conductive contact layer 300a fills a partial depth of the node contact window 500. In this embodiment, the conductive contact layer 300a is filled in the node contact window 500 to be electrically connected to the active region exposed in the node contact window 500.

[0081] Please continue to refer to Figure 2c As shown, a first electrical transmission layer 300b is formed. The second conductive layer 300b covers the top of the conductive contact layer 300a and fills a partial depth of the node contact window 500. That is, in this embodiment, when the first electrical transmission layer 300b is formed, the first electrical transmission layer 300b is formed on the conductive contact layer 300a, and the first electrical transmission layer 300b does not fill the node contact window 500 completely. The top height of the first electrical transmission layer 300b is lower than the height of the opening of the node contact window 500.

[0082] Optionally, the method for forming the first electrical transmission layer 300b may be:

[0083] Form a first electrical transmission material layer, and the first electrical transmission material layer fills the node contact window 500 and extends to cover the top of the bit line structure BL;

[0084] Etch back the first electrical transmission material layer to remove the first electrical transmission material layer on the top of the bit line structure BL and remove a partial height of the first electrical transmission material layer in the node contact window 500. The remaining first electrical transmission material layer constitutes the first electrical transmission layer 300b.

[0085] It should be understood that the greater the aspect ratio of the node contact window 500, the higher the process requirements for preparing the first electrical transmission layer 300b to avoid air gaps in the first electrical transmission layer 300b, and thus avoid the influence of air gaps on the conductivity of the subsequently formed node contact structure. In this embodiment, the bit line structure BL is directly used to define the node contact window 500. At this time, no additional dielectric layer is formed on the top of the bit line structure BL, and the height of the node contact window 500 is small, so the process requirements for forming the first electrical transmission layer 300b are not strict.

[0086] Please refer to Figure 2c and Figure 2d, step S300 is performed to form a spacer material layer on the bit line structure BL. The spacer material layer covers the bit line structure BL and fills the node contact window 500 with the remaining depth. Specifically, the spacer material layer includes a buffer material layer 400a and an insulating material layer 400b. The buffer material layer 400a covers the bit line structure BL and extends to cover the inner wall of the node contact window 500 with the remaining depth. The insulating material layer 400b is located on the buffer material layer 400a and fills the node contact window 500 with the remaining depth.

[0087] In this embodiment, the thickness of the buffer material layer 400a is much smaller than the thickness of the insulating material layer 400b. Moreover, the buffer material layer 400a and the insulating material layer 400b are insulating materials with different materials. For example, the material of the buffer material layer 400a is silicon oxide, and the insulating material layer 400b is nitride. The materials of the buffer material layer 400a and the insulating material layer 400b have a large etching selectivity. However, it should not be limited to this. The buffer material layer 400a and the insulating material layer 400b can also be other insulating materials. For example, the material of the insulating material layer 400b can also be carbon-doped nitride (such as carbon-doped silicon nitride), and the material of the buffer material layer 400a can also be carbide (such as silicon carbide) or other oxides (such as tantalum oxide, titanium oxide), etc. The present invention is not limited.

[0088] Next, please refer to Figure 2e , the insulating material layer 400b and the buffer material layer 400a are etched to form a plurality of openings 510. The openings 510 penetrate through the spacer material layer to divide the spacer material layer into individual spacer patterns 400. Each spacer pattern 400 includes the insulating material layer 400b and the buffer material layer 400a.

[0089] In this embodiment, a dry etching process is used to etch the spacer material layer to form the opening 510. When etching the insulating material layer 400b, the thickness of the insulating material layer 400b above the bit line structure BL is smaller and will be etched first. While the thickness of the insulating material layer 400b on the first electrical transmission layer 300b is larger. When the insulating material layer 400b above the bit line structure BL is etched completely, there is still some remaining insulating material layer 400b on the first electrical transmission layer 300b and further etching is required. Further, since the etching selectivity between the buffer material layer 400a and the insulating material layer 400b is large (the etching rate of the insulating material layer 400b is greater than that of the buffer material layer 400a), at this time, the buffer material layer 400a can act as an anti-etching film layer to protect the bit line structure BL and prevent the bit line structure BL from being damaged. When the insulating material layer 400b on the first electrical transmission layer 300b is etched completely, the buffer material layer 400a can also protect the first electrical transmission layer 300b and prevent the first electrical transmission layer 300b from being damaged.

[0090] Finally, change the etching gas to etch and remove part of the buffer material layer 400a to form the opening 510. It can be understood that in order to avoid adverse effects on the bit line structure BL when etching and removing part of the buffer material layer 400a, the material of the buffer material layer 400a is different from that of the bit line shielding layer 200d, and the etching selectivity between the material of the buffer material layer 400a and the material of the bit line shielding layer 200d is large, so as to prevent damage to the bit line structure BL when removing the buffer material layer 400a.

[0091] As an alternative embodiment, the spacer material layer in this embodiment may only include the insulating material layer 400b, thus simplifying the etching process. At this time, without the buffering of the buffer material layer, the etching selectivity requirements for the materials of the insulating material layer 400b and the bit line shielding layer 200d are relatively high.

[0092] Please continue to refer to Figure 2b and Figure 2e, in a direction perpendicular to the depth direction, the position of the opening 510 is offset from the position of the node contact window 500, that is to say, the center line of the opening 510 does not coincide with the center line of the node contact window 500, but has a certain offset (in this embodiment, the opening 510 is offset to the right relative to the node contact window 500). From a top view, the planar shape of the opening 510 is honeycomb-shaped, so that the area can be saved and the device size can be reduced. In this way, part of the opening 510 is located above the first electrical transmission layer 300b, and part is located above the bit line structure BL, so that the opening 510 exposes the tops of both the first electrical transmission layer 300b and the bit line structure BL.

[0093] Please continue to refer to Figure 2e and Figure 2f , perform step S400, and sequentially form a conduction barrier layer 300d and a second electrical transmission layer 300c in the opening 510. The conduction barrier layer 300d covers the inner wall of the opening 510, and the second electrical transmission layer 300c covers the conduction barrier layer 300d and fills the opening 510. The second electrical transmission layer 300c is electrically connected to the first electrical transmission layer 300b through the conduction barrier layer 300d. The conductive contact layer 300a, the first electrical transmission layer 300b, the conduction barrier layer 300d, and the second electrical transmission layer 300c that are electrically connected constitute a node contact structure SC. Adjacent node contact structures SC are electrically isolated by the spacer pattern 400. Since the height of the opening 510 is relatively low, the process requirements for forming the second electrical transmission layer 300c are not very strict.

[0094] Furthermore, the second electrical transmission layer 300c is a planarized film layer, and the top of the spacer pattern 400 is flush with the top of the second electrical transmission layer 300c.

[0095] It can be understood that since the opening 510 also exposes the top of the bit line structure BL, it is equivalent to that the opening 510 is laterally widened above the bit line structure BL. After the second electrical transmission layer 300c is formed in the opening 510, a part of the second electrical transmission layer 300c covers the first electrical transmission layer 300b and is electrically connected to the first electrical transmission layer 300b, and the other part laterally extends to cover the bit line structure BL. In this way, the width of the top of the node contact structure SC is widened, the area of the capacitor structure formed subsequently on the node contact structure SC can be increased, and thus the storage performance of the memory is improved.

[0096] As an alternative embodiment, the opening 510 may also only expose the top of the first electrical transmission layer 300b without exposing the top of the bit line structure BL. In this way, the second electrical transmission layer 300c only covers the top of the first electrical transmission layer 300b without extending to cover the top of the bit line structure BL, and this will not be elaborated here.

[0097] It should be understood that compared with the prior art in which an insulating pattern is first formed on the bit line structure and the node contact window with a relatively large aspect ratio is jointly defined by the bit line structure and the insulating pattern, in this embodiment, the node contact window with a relatively low height is directly defined by the bit line structure first. At this time, the process requirements for forming the first electrical transmission layer 300b can be reduced; then the spacer pattern 400 is formed to increase the height of the bit line structure BL to facilitate the formation of the second electrical transmission layer 300c, and the height of the spacer pattern 400 is not extremely high, which can reduce the process requirements for forming the second electrical transmission layer 300c; further, when the bit line structure BL is formed, since there is only the stacked film layer of the bit line structure BL, the etching difficulty can also be reduced. Or it can also be understood that in this embodiment, the existing node contact window is separated into upper and lower parts by the spacer pattern 400, and the first electrical transmission layer 300b and the second electrical transmission layer 300c are filled in the node contact window step by step, and the first electrical transmission layer 300b and the second electrical transmission layer 300c are electrically connected to form the node contact structure SC, so as not to affect the performance of the memory, and the heights of the first electrical transmission layer 300b and the second electrical transmission layer 300c are low, which can reduce the requirements for the manufacturing process.

[0098] Optionally, please refer to Figure 2g , after forming the Figure 2f memory in, the method for forming the memory further includes a step of forming a capacitor structure. Specifically, an insulating layer 610 is first formed on the spacer pattern 400, the insulating layer 610 covers the spacer pattern 400, and the insulating layer 610 is a patterned film layer. The insulating layer 610 and the bit line shielding layer 200d may be made of the same material, such as silicon nitride, etc.

[0099] Then a stacked material layer 620 is formed on the insulating layer 610, the stacked material layer 620 covers the insulating layer 610, and the stacked material layer 620 is a patterned film layer. An electrode groove 630 is formed between adjacent stacked material layers 620, and the electrode groove 630 is used to form the cylindrical lower electrode of the capacitor structure in a subsequent step. The insulating layer 610 in this embodiment can be used as a mask layer for forming the stacked material layer 620. Figure 2a For Figure 2f the simplified layout of the memory in, where Figure 2f For Figure 2aSchematic cross-sectional view of the memory in the aa' and bb' directions.

[0100] As Figure 2a and Figure 2f shown, the memory includes a substrate 100 and a word line structure WL formed in the substrate 100. Among them, a plurality of active regions AA and trench isolation structures STI extending along a first predetermined direction (Z direction) are formed in the substrate 100, and the trench isolation structures STI separate adjacent active regions AA. Among them, the plurality of active regions AA are arranged in an array, and each active region AA is made independent of each other through the trench isolation structure STI, avoiding interference between the active regions AA.

[0101] Furthermore, a word line trench is also formed in the substrate 100, and the word line trench is used to accommodate the word line structure WL. Specifically, the word line trench extends along a second predetermined direction (X direction) to pass through the corresponding active region AA and trench isolation structure STI, and the word line trench has a portion located in the trench isolation structure STI and a portion located in the active region AA.

[0102] In this embodiment, the opening size of the word line trench located in the trench isolation structure STI is larger than the opening size of the word line trench located in the active region AA. Furthermore, the bottom position of the word line trench located in the trench isolation structure STI is also lower than the bottom position of the word line trench located in the active region AA.

[0103] As described above, the word line trench passes through the corresponding active region AA and trench isolation structure STI, so the word line structure WL also correspondingly passes through the active region AA and trench isolation structure STI. In this embodiment, the bottom position of the word line structure WL in the trench isolation structure STI is lower than the bottom position of the word line structure WL in the active region AA, and the top positions of the word line structure WL are at the same height. The word line structure WL is formed in the word line trench, so a channel region buried in the active region AA with a curved structure can be formed. Thus, compared with a linear channel region, the curved channel region can have a relatively large length, which can improve the short-channel effect of the transistor.

[0104] Continue to refer to Figure 2a and Figure 2f shown, the word line structure WL includes a gate dielectric layer, a gate conductive layer, and a gate insulating layer. Among them, the gate dielectric layer covers the inner wall of the word line trench, the gate conductive layer is located on the gate dielectric layer and fills a part of the depth of the word line trench, and the gate insulating layer is located on the gate conductive layer and fills the remaining depth of the word line trench.

[0105] Further, the active region AA is, for example, used to form a memory transistor. Source / drain regions may also be formed in the active region AA. The source / drain regions include a first source / drain region and a second source / drain region. The first source / drain region and the second source / drain region are respectively located on both sides of the word line structure WL to jointly form the memory transistor. It can be understood that the bottoms of the first source / drain region and the second source / drain region are lower than the top of the gate conductive layer, such that there is an overlapping region between the first source / drain region and the second source / drain region and the gate conductive layer.

[0106] Continuing to refer to Figure 2a and Figure 2f As shown, a plurality of bit line structures BL are formed on the substrate 100 and extend along a third predetermined direction (Y direction) to pass through corresponding active regions AA. Referring to Figure 2f As shown, the bit line structure BL includes a first bit line conductive layer 200a, a second bit line conductive layer 200b, and a third bit line conductive layer 200c stacked in sequence. Among them, the material of the first bit line conductive layer 200a includes, for example, doped polysilicon, the material of the second bit line conductive layer 200b includes, for example, titanium nitride, and the material of the third bit line conductive layer 200c includes, for example, tungsten.

[0107] Further, the bit line structure BL may further include a bit line masking layer 200d and a spacer sidewall 200e. Among them, the bit line masking layer 200d is formed above the bit line conductive layers stacked in sequence, and the spacer sidewall 200e covers at least the sidewalls of the bit line conductive layers stacked in sequence and the sidewalls of the bit line masking layer 200d.

[0108] The bit line structure BL has a portion located on the trench isolation structure STI and a portion located in the active region AA. That is to say, a part of the bit line structure BL is located on the substrate 100 and directly above the trench isolation structure STI; another part of the bit line structure BL extends from the substrate 100 into the active region AA and is located between adjacent word line structures WL.

[0109] The bit line structure BL defines a node contact window 500 for accommodating a node contact structure SC. Among them, at least part of the bottom of the node contact window 500 may further extend into the substrate 100. The defined plurality of node contact windows 500 are aligned and arranged in both the second predetermined direction and the third predetermined direction. The plurality of node contact windows 500 are, for example, arranged in an array to form a node contact window array. At this time, it can be considered that the plurality of node contact windows 500 are arranged in multiple rows in both the second predetermined direction and the third predetermined direction.

[0110] Continuing to refer to Figure 2b andFigure 2f As shown, the node contact structure SC includes a conductive contact layer 300a, and the conductive contact layer 300a fills a partial depth of the node contact window 500 to be electrically connected to the active region AA.

[0111] Furthermore, the node contact structure SC further includes a first electrical transmission layer 300b, a conduction barrier layer 300d, and a second electrical transmission layer 300c. The first electrical transmission layer 300b fills a partial depth of the node contact window 500 and is formed on the conductive contact layer 300a to be electrically connected to the conductive contact layer 300a. The conduction barrier layer 300d is formed on the first electrical transmission layer 300b and covers the inner wall of the remaining depth of the node contact window 500. The second electrical transmission layer 300c is formed on the conduction barrier layer 300d, fills the remaining depth of the node contact window 500, and extends upward to be higher than the node contact window 500.

[0112] The conduction barrier layer 300d is used to prevent the material diffusion of the second electrical transmission layer 300c, thereby increasing the reliability of the memory. Optionally, the conduction barrier layer 300d can be formed by a Ti / TiN stacked structure.

[0113] Of course, other conductive film layers such as metal silicide can also be formed between the first electrical transmission layer 300b and the conduction barrier layer 300d, and no further examples will be given here.

[0114] Moreover, in the direction perpendicular to the depth direction, the second electrical transmission layer 300c and the first electrical transmission layer 300b have an offset (offset to the right), such that the second electrical transmission layer 300c also laterally extends to cover a partial top of the bit line structure BL, so that the top width of the second electrical transmission layer 300c is increased, thereby increasing the area of the capacitor structure formed on the second electrical transmission layer 300c subsequently.

[0115] Continue to refer to Figure 2f As shown, adjacent second electrical transmission layers 300c are separated by a spacer pattern 400, and the spacer pattern 400 covers a partial top of the bit line structure BL and a partial top of the first electrical transmission layer 300b. That is to say, the spacer pattern 400 also fills the remaining depth of the node contact window 500 and extends upward to be higher than the node contact window 500, and the spacer pattern 400 also laterally extends to cover a partial top of the bit line structure BL.

[0116] Further, the sidewall of the spacer pattern 400 is in contact with the adjacent second electrical transmission layer 300c, and the spacer pattern 400 also electrically isolates the adjacent second electrical transmission layer 300c, thereby electrically isolating the adjacent node contact structure SC. As can be seen from Figure 2f in, the spacer pattern 400 and the second electrical transmission layer 300c are spaced apart and both are L-shaped, and the top of the spacer pattern 400 is flush with the top of the second electrical transmission layer 300c.

[0117] Continue to refer to Figure 2f shown, the spacer pattern 400 includes a stacked buffer material layer 400a and an insulating material layer 400b, and the insulating material layer 400b covers the buffer material layer 400a. In this embodiment, the materials of the insulating material layer 400b and the buffer material layer 400a are both insulating materials, and the material of the insulating material layer 400b has a large etching selectivity ratio with the material of the buffer material layer 400a, and the material of the buffer material layer 400a has a large etching selectivity ratio with the material of the bit line shielding layer 200d, so that the buffer material layer 400a can protect the first electrical transmission layer 300b and the bit line shielding layer 200d from being over-etched during the etching process, thereby better protecting the bit line structure BL and preventing the bit line structure BL from being damaged.

[0118] In this embodiment, the material of the buffer material layer 400a is silicon oxide, the material of the insulating material layer 400b is silicon nitride, and the material of the bit line shielding layer 200d can be other insulating materials different from silicon oxide and silicon nitride, but it should not be limited thereto.

[0119] As an alternative embodiment, the spacer pattern 400 may also only include the insulating material layer 400b, and this embodiment is not limited.

[0120] Embodiment 2

[0121] Figure 3a and Figure 3b are the schematic structural diagrams corresponding to the respective steps of the method for forming the memory provided in this embodiment. As shown in Figure 3a and Figure 3b shown, the difference from Embodiment 1 is that in this embodiment, when forming the opening 510, in the depth direction, the position of the opening 510 corresponds to the position of the node contact window. In this way, from a top view, the planar shape of the opening 510 is checkerboard-shaped.

[0122] Please continue to refer to Figure 3a, the center line of the opening 510 coincides with the center line of the node contact window within the allowable error range, so that the opening 510 only exposes the top of the first electrical transmission layer 300b. After the second electrical transmission layer 300c is formed in the opening 510, the second electrical transmission layer 300c fills the node contact window 500 with the remaining depth and extends upward, and the second electrical transmission layer 300c is restricted between adjacent bit line structures BL.

[0123] As Figure 3b shown, compared with the first embodiment, the positions of the first electrical transmission layer 300b and the second electrical transmission layer 300c of the memory formed by using the method for forming a memory provided in this embodiment correspond in the depth direction. That is, the second electrical transmission layer 300c entirely covers the top of the first electrical transmission layer 300b and does not extend to cover the top of the bit line structure BL, and the spacer pattern 400 entirely covers the top of the bit line structure BL and does not extend to cover the top of the electrical transmission layer 300c. Compared with the first embodiment, in this embodiment, there is no need to consider the material problems of the spacer pattern 400 and the bit line shielding layer 200d, and the selection range of the material of the spacer pattern 400 is wider.

[0124] Furthermore, as Figure 3b shown, in this embodiment, when the opening 510 is etched and formed, the buffer material layer 400a on the sidewall of the node contact window 500 is not removed, so that the buffer material layer 400a of the memory extends downward from the top of the bit line shielding layer 200d to cover a part of the sidewall of the bit line structure BL and stays above the first electrical transmission layer 300b. In this way, the lateral width of the second electrical transmission layer 300c will be slightly smaller than the lateral width of the first electrical transmission layer 300b, but it does not affect the implementation of the present invention.

[0125] As an alternative embodiment, when the opening 510 is etched and formed, the buffer material layer 400a on the sidewall of the node contact window 500 can also be completely removed, so that the buffer material layer 400a of the memory is only located on the top of the bit line structure BL. In this way, the lateral width of the second electrical transmission layer 300c will be equal to the lateral width of the first electrical transmission layer 300b, and the present invention is not limited.

[0126] Embodiment Three

[0127] Figures 4a - 4d is a schematic structural diagram corresponding to the corresponding steps of the method for forming a memory provided in this embodiment. As Figures 4a - 4dAs shown, the difference from the first and second embodiments is that in this embodiment, the material of the buffer material layer 400a is a conductive material, thereby increasing the etching selectivity ratio between the buffer material layer 400a and the bit line shielding layer 200d, so as to better protect the bit line structure BL.

[0128] Specifically, please refer to Figure 4a . When forming the opening 510, the opening 510 corresponds to the position of the node contact window. At this time, when etching to form the opening 510, the buffer material layer 400a on the side wall of the node contact window 500 is completely removed. Before forming the second electrical transmission layer 300c, an insulating sidewall 400c is formed on the side wall of the opening 510. The material of the insulating sidewall 400c is an insulating medium. Through the insulating sidewall 400c, the buffer material layer 400a can be electrically isolated from the first electrical transmission layer 300b and the second electrical transmission layer 300c, preventing adjacent node contact structures SC from being short-circuited.

[0129] As Figure 4b shown, compared with the second embodiment, in the memory formed by using the memory formation method provided in this embodiment, the buffer material layer 400a and the insulating material layer are stacked on the bit line structure BL in sequence. An insulating sidewall 400c is formed on the side wall of the opening 510. The insulating sidewall 400c electrically isolates the buffer material layer 400a from the first electrical transmission layer 300b and the buffer material layer 400a from the second electrical transmission layer 300c, preventing adjacent node contact structures SC from being short-circuited.

[0130] It should be understood that when etching to form the opening 510, the buffer material layer 400a on the side wall of the node contact window 500 is not removed, so that the buffer material layer 400a of the memory extends downward from the top of the bit line shielding layer 200d to cover a part of the side wall of the bit line structure BL and stays above the first electrical transmission layer 300b. In this way, before forming the insulating sidewall 400c, a part of the height of the first electrical transmission layer 300b needs to be removed. When forming the buffer material layer 400a, the buffer material layer 400a not only needs to cover the side wall of the opening 510, but also needs to be located between the buffer material layer 400a and the first electrical transmission layer 300b to completely electrically isolate the buffer material layer 400a from the first electrical transmission layer 300b and the buffer material layer 400a from the second electrical transmission layer 300c.

[0131] Please refer to Figure 4c, when forming the opening 510, the position of the opening 510 and the node contact window 500 has an offset in the direction perpendicular to the depth. At this time, after etching to form the opening 510, a part of the top of the bit line shielding layer 200d and a part of the top of the electrical transmission layer 300b are exposed. Then, before forming the second electrical transmission layer 300c, an insulating sidewall 400c is formed on the sidewall of the opening 510. The insulating sidewall 400c is made of an insulating medium, and through the insulating sidewall 400c, the buffer material layer 400a can be electrically isolated from the first electrical transmission layer 300b and the second electrical transmission layer 300c, preventing adjacent node contact structures SC from being short-circuited.

[0132] As Figure 4d shown, compared with the first embodiment, in the memory formed by using the method for forming a memory provided in this embodiment, the buffer material layer 400a and the insulating material layer 400b are sequentially stacked on a part of the top of the bit line structure BL and a part of the top of the first electrical transmission layer 300b. An insulating sidewall 400c is formed on the sidewall of the opening 510, and the insulating sidewall 400c covers the sidewall of the opening 510. That is to say, the left sidewall of the opening 510 is an integral body, and the insulating sidewall 400c covers the entire left sidewall of the opening 510, while the right sidewall of the opening 510 has a step, and the insulating sidewall 400c covers the stepped side surface of the right sidewall of the opening 510. However, it should be understood that in fact, the insulating sidewall 400c only needs to cover the sidewall of the insulating sidewall 400c to electrically isolate the buffer material layer 400a from the first electrical transmission layer 300b and the second electrical transmission layer 300d. The insulating sidewall 400c electrically isolates the buffer material layer 400a from the first electrical transmission layer 300b and the buffer material layer 400a from the second electrical transmission layer 300c, preventing adjacent node contact structures SC from being short-circuited.

[0133] In this embodiment, the material of the insulating sidewall 400c can be a conductive material such as silicon, germanium, undoped polysilicon, or doped polysilicon. In this way, the material of the insulating sidewall 400c not only has a large etching selectivity ratio with the bit line shielding layer 200d, but also has a large etching selectivity ratio with the material of the first electrical transmission layer 300b (usually a metal material), so that the first electrical transmission layer 300b and the bit line structure BL can be better protected in the etching step.

[0134] Embodiment 4

[0135] Figure 5a and Figure 5bThe structural schematic diagram corresponding to the corresponding steps of the method for forming the memory provided in this embodiment. As Figure 5b shown, the difference from the first embodiment, the second embodiment, and the third embodiment is that in this embodiment, the first electrical transmission layer 300b completely fills the node contact window 500.

[0136] Please continue to refer to Figure 5b , since the first electrical transmission layer 300b completely fills the node contact window 500, the top of the first electrical transmission layer 300b is flush with the top of the bit line structure BL (the top of the bit line masking layer 200d), so that the bottom of the spacer pattern 400 and the bottom of the second electrical transmission layer 300c are also flush with the top of the bit line structure BL. As can be seen from Figure 5b , both the spacer pattern 400 and the first electrical transmission layer 300b are rectangular.

[0137] Please continue to refer to Figure 5a and Figure 5b , in the process of forming the memory in this embodiment, the difference from the first embodiment, the second embodiment, and the third embodiment is that when filling the first electrical transmission layer 300b in the node contact window 500, the node contact window 500 is directly filled with a conductive material (a planarization process can be performed subsequently), so that the formed first electrical transmission layer 300b completely fills the node contact window 500. At this time, the top of the first electrical transmission layer 300b is flush with the top of the bit line structure BL. In this way, after forming the first electrical transmission layer 300b, the substrate surface is flat, which is beneficial to the formation of the subsequent second electrical transmission layer 300c.

[0138] In summary, the memory provided by the present invention directly uses the bit line structure to define a plurality of node contact windows. Since the height of the node contact windows is relatively low and the aspect ratio is small at this time, when forming the first electrical transmission layer in the node contact windows, the requirements for the formation process of the first electrical transmission layer are relatively small. After forming the first electrical transmission layer, an interlayer pattern is formed. The adjacent interlayer patterns are spaced apart by openings, and the openings at least expose part of the top of the first electrical transmission layer. A second electrical transmission layer is formed in the openings. Since the height of the openings is relatively low and the aspect ratio is small at this time, when forming the second electrical transmission layer in the openings, the requirements for the formation process of the second electrical transmission layer are also relatively small. Moreover, after electrically connecting the second electrical transmission layer and the first electrical transmission layer to form a node contact structure, no adverse impact will be caused to the memory in this step. The second electrical transmission layer can extend to cover part of the top of the bit line structure, and the top surface width of the second electrical transmission layer increases, so that the area of the capacitor structure formed on the second electrical transmission layer subsequently can also be increased, thereby improving the storage performance of the memory. The interlayer pattern includes a buffer material layer and an insulating material layer covering the buffer material layer. The buffer material layer can provide a buffering effect during the etching to form the openings, thereby protecting the first electrical transmission layer and the bit line shielding layer from being over-etched. When the buffer material layer is a conductive material, the etching selectivity between the buffer material layer and the bit line shielding layer can be increased, so as to better protect the bit line structure.

[0139] It should be noted that the embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0140] It should also be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

[0141] It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequence relationship, etc. between each component, element, step.

[0142] In addition, it should be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices and may include sub-steps and sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly dictates otherwise. Furthermore, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

[0143] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art within the scope of the technical solution of the present invention, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the disclosed technical solution and technical content of the present invention, all of which fall within the content of the technical solution of the present invention and are still within the protection scope of the present invention.

Claims

1. A memory, characterized in that, Comprising: A substrate; Multiple bit line structures located on the substrate and defining a plurality of node contact windows, the bit line structures including a bit line conductive layer and a bit line shielding layer covering the bit line conductive layer; A first electrical transmission layer located in the node contact windows, the first electrical transmission layer at least filling a partial depth of the node contact windows, and a top surface of the first electrical transmission layer being lower than a top surface of the bit line shielding layer; A second electrical transmission layer covering a partial top of the first electrical transmission layer and a partial top of the bit line shielding layer and being electrically connected to the first electrical transmission layer; And, A spacer pattern covering a remaining top of the bit line shielding layer and a remaining top of the first electrical transmission layer to space adjacent second electrical transmission layers; A bottom of the spacer pattern is in contact with a top of the first electrical transmission layer, the spacer pattern including a buffer material layer and an insulating material layer covering the buffer material layer, wherein side walls of the buffer material layer and the insulating material layer are in direct contact with side walls of the second electrical transmission layer.

2. The memory according to claim 1, wherein The first electrical transmission layer completely fills the node contact windows.

3. The memory according to claim 1, characterized in that, The top surface of the first electrical transmission layer is lower than a bottom surface of the bit line shielding layer.

4. The memory according to claim 1, characterized in that, The buffer material layer is located between the insulating material layer and the first electrical transmission layer.

5. The memory according to claim 1, characterized in that, The buffer material layer is located between the insulating material layer and the bit line shielding layer.

6. The memory according to claim 4 or 5, characterized in that, The material of the buffer material layer is a material having an etching selectivity ratio with the bit line shielding layer.

7. The memory according to claim 1, characterized in that, The memory further comprises: An insulating sidewall at least covering side walls of the spacer pattern.

8. The memory according to claim 7, wherein The insulating sidewall is in direct contact with the first electrical transmission layer.

9. The memory according to claim 7, wherein The bit line structure further comprises: A spacer sidewall located on side walls of the bit line conductive layer and the bit line shielding layer, and the spacer pattern further extends to cover side walls of the spacer sidewall.

10. A memory, characterized in that, Comprising: A substrate; Multiple bit line structures located on the substrate and defining a plurality of node contact windows, the bit line structures including a bit line conductive layer and a bit line shielding layer covering the bit line conductive layer; A first electrical transmission layer located in the node contact windows, the first electrical transmission layer at least filling a partial depth of the node contact windows; A second electrical transmission layer filling a remaining depth of the node contact windows and extending upward, and the second electrical transmission layer is also electrically connected to the first electrical transmission layer; A spacer pattern covering a top of the bit line shielding layer to space adjacent second electrical transmission layers, the spacer pattern including a buffer material layer and an insulating material layer covering the buffer material layer; And, An insulating sidewall at least located on side walls of the spacer pattern and in direct contact with side walls of the buffer material layer and the insulating material layer to electrically isolate the spacer pattern from the first electrical transmission layer and the second electrical transmission layer; A bottom of the spacer pattern is in contact with a top of the first electrical transmission layer.

11. The memory according to claim 10, wherein The material of the buffer material layer is a conductive material having an etching selectivity ratio with the bit line shielding layer.

12. The memory according to claim 11, wherein The insulating sidewall is also located between the buffer material layer and the first electrical transmission layer.

13. The memory according to claim 10, wherein The insulating sidewall is in direct contact with the first electrical transmission layer.

14. The memory according to claim 10, wherein The bit line structure further comprises: Spacer sidewalls are located on the sidewalls of the bit line conductive layer and the bit line shielding layer, and the spacer pattern further extends to cover the sidewalls of the spacer sidewalls.

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