Diode structure of a power semiconductor device

Abstract

This invention discloses a diode structure for a power semiconductor device. The power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal. The body includes: at least one diode structure configured to conduct load current between terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and a drift region and a field stop region of the same conductivity type. The cathode port includes a first port portion and a second port portion having opposite conductivity types. The transition between each of the second port portions and the field stop region forms a corresponding pn junction extending along a first lateral direction. The lateral separation distance between adjacent second port portions is smaller in the second group than in the first group.

Description

Technical Field

[0001] This specification relates to embodiments of power semiconductor devices having a diode structure and to embodiments of processing power semiconductor devices having a diode structure. Background Technology

[0002] Many functions of modern equipment in automotive, consumer goods, and industrial applications, such as converting electrical energy and driving electric motors, rely on power semiconductor devices. Examples include insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, which have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] Power semiconductor devices typically include a semiconductor body configured to conduct load current along a load current path between two load terminals of the device. For example, a power semiconductor device is a diode, or correspondingly includes a diode structure to allow the flow of load current in either the forward or reverse direction and to block voltage in the other direction.

[0004] Furthermore, power semiconductor devices can be controlled devices. For example, they can provide an on function to allow forward voltage to be blocked. Additionally, they can provide an off function to suppress the flow of load current in the forward direction.

[0005] For example, the load current path can be controlled by means of an insulating electrode, sometimes referred to as a gate electrode. For example, when a corresponding control signal is received from, for example, a driver unit, the control electrode can set the power semiconductor device to one of a conduction state (also referred to as an "on state") and a blocking state.

[0006] Power semiconductor devices should generally exhibit low losses. If a power semiconductor device includes transistor functionality, i.e., provides switching capability, then the total losses consist primarily of on-state losses and switching losses. To keep on-state losses low, the lifetime of charge carriers contributing to the load current should be relatively long, while to keep switching losses low, the lifetime should be relatively short. Summary of the Invention

[0007] According to an embodiment, a power semiconductor device includes a semiconductor body coupled to each of a first load terminal and a second load terminal. The semiconductor body includes a drift region with dopant of a first conductivity type; at least one diode structure configured to conduct load current between the terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and a field stop region with dopant of the first conductivity type at a higher dopant concentration than the drift region, wherein the field stop region is disposed between the cathode port and the drift region. The cathode port includes a first port portion with dopant of the first conductivity type and a second port portion with dopant of a second conductivity type complementary to the first conductivity type, the transition between each of the second port portions and the field stop region forming a corresponding pn junction, the pn junction extending along a first lateral direction, wherein the diffusion voltage of the corresponding pn junction in an extension direction perpendicular to the first lateral direction is greater than a lateral voltage drop that laterally overlaps with the lateral extension of the corresponding pn junction.

[0008] According to another embodiment, a power semiconductor device includes a semiconductor body coupled to each of a first load terminal and a second load terminal. The semiconductor body includes a drift region with dopant of a first conductivity type; at least one diode structure configured to conduct load current between the terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and a field stop region with dopant of the first conductivity type at a higher dopant concentration than the drift region, wherein the field stop region is disposed between the cathode port and the drift region. The cathode port includes a first port portion with dopant of the first conductivity type and a second port portion with dopant of a second conductivity type complementary to the first conductivity type, each of the second port portions forming a corresponding pn junction with the field stop region, the pn junction extending along a first lateral direction. The second load terminal exhibits a contact region facing the semiconductor body, and wherein, in the active region of the power semiconductor device, the percentage of the contact region laterally overlapping the second port portion is at most half the percentage of the contact region laterally overlapping the first port portion. The percentage share of the contact area that laterally overlaps with the second port portion increases along the direction from the diode structure of the power semiconductor device to the adjacent structure, which includes at least one of an edge structure and a transistor structure.

[0009] According to another embodiment, a method of processing a power semiconductor device includes providing a semiconductor body for coupling to each of a first load terminal and a second load terminal of the power semiconductor device, and forming in the semiconductor body: a drift region having a dopant of a first conductivity type; at least one diode structure configured to conduct load current between the terminals and including an anode port to be electrically connected to the first load terminal and a cathode port to be electrically connected to the second load terminal; and a field stop region having a dopant of the first conductivity type at a higher dopant concentration than the drift region, wherein the field stop region is disposed between the cathode port and the drift region. The method further includes forming a first port portion having a dopant of the first conductivity type and a second port portion having a dopant of a second conductivity type complementary to the first conductivity type in the cathode port, each of the second port portions forming a corresponding pn junction with the field stop region, the pn junction extending along a first lateral direction; and ensuring that a diffusion voltage of a corresponding pn junction in an extension direction perpendicular to the first lateral direction is greater than a lateral voltage drop that laterally overlaps with the lateral extension of the corresponding pn junction.

[0010] According to yet another embodiment, a method of processing a power semiconductor device includes providing a semiconductor body for coupling to each of a first load terminal and a second load terminal of the power semiconductor device, and forming in the semiconductor body: a drift region having a dopant of a first conductivity type; at least one diode structure configured to conduct load current between the terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and a field stop region having a dopant of the first conductivity type at a higher dopant concentration than the drift region, wherein the field stop region is disposed between the cathode port and the drift region. The method further includes forming a first port portion having a dopant of the first conductivity type and a second port portion having a dopant of a second conductivity type complementary to the first conductivity type in the cathode port, each of the second port portions forming a corresponding pn junction with the field stop region, the pn junction extending along a first lateral direction. The second load terminal exhibits a contact region facing the semiconductor body. The cathode port is formed such that: in the active region of the power semiconductor device, the percentage of the contact region that laterally overlaps with the second port portion is at most half the percentage of the contact region that laterally overlaps with the first port portion; and the percentage of the contact region that laterally overlaps with the second port portion increases along the direction from the diode structure of the power semiconductor device to the adjacent structure, the adjacent structure including at least one of the edge structure and the transistor structure.

[0011] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0012] The figures are not necessarily to scale; the focus is on illustrating the principles of the invention. Furthermore, similar reference numerals designate corresponding parts in each figure. In the figures:

[0013] Figure 1 The illustration schematically and exemplary shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0014] Figure 2 The illustration schematically and exemplary shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0015] Figure 3 The illustration schematically and exemplary shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0016] Figure 4 The illustration schematically and exemplary shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0017] Figure 5A This schematically and exemplaryly illustrates a portion of a horizontal cross-section of a power semiconductor device according to one or more embodiments;

[0018] Figure 5B -C Each schematic and exemplary illustration shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0019] Figure 6 The illustration schematically and exemplary depicts a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; and

[0020] Figure 7 The diagram illustrates, and exemplarily demonstrates, a dopant concentration distribution in a power semiconductor device according to one or more embodiments. Detailed Implementation

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document and illustrate, by way of illustration, specific embodiments in which the invention may be practiced.

[0022] In this regard, directional terms such as “top,” “bottom,” “below,” “front,” “back,” “rear,” “leading,” “behind,” “below,” “above,” etc., may be used in conjunction with reference to the orientation of the accompanying drawings being described. Because portions of the embodiments can be positioned in many different orientations, directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0023] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation and is not intended to limit the invention. For example, features illustrated or described as part of one embodiment can be used in other embodiments or used in combination with other embodiments to produce yet another embodiment. Such modifications and variations are intended to be included in the invention. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements or manufacturing steps have been designated in different drawings by the same reference numerals.

[0024] As used herein, the term "horizontal" is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This surface may be, for example, the surface of a semiconductor wafer or die. For example, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0025] As used herein, the term "vertical" is intended to describe an orientation that is substantially perpendicular to a horizontal surface (i.e., parallel to the normal direction of the surface of the semiconductor wafer). For example, the extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y, and therefore can represent a vertical direction.

[0026] In this specification, n-doping is referred to as the "first conductivity type," and p-doping is referred to as the "second conductivity type." Alternatively, the opposite doping relationship can be used, such that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0027] Additionally, within this specification, the term "dopant concentration" may refer to the average dopant concentration, or correspondingly, the average dopant concentration or sheet charge carrier concentration of a particular semiconductor region or area. Thus, for example, a description of a particular semiconductor region exhibiting a higher or lower dopant concentration compared to another semiconductor region may indicate that the average dopant concentrations of the various semiconductor regions are different from each other.

[0028] In the context of this specification, the terms "ohmic contact," "electrical contact," "ohmic connection," and "electrical connection" are intended to describe a low-ohmic electrical connection or low-ohmic current path existing between two regions, segments, areas, sections, or parts of a semiconductor device, or between different terminals of one or more devices, or between a section or part of a semiconductor device and a terminal, metallization, or electrode. Additionally, in the context of this specification, the term "contact" is intended to describe a direct physical connection existing between two elements of a respective semiconductor device; for example, the transition between two elements in contact with each other may not require another intermediate element.

[0029] Furthermore, in the context of this specification, the term "electrically insulated," unless otherwise specified, is used in its generally valid understanding and is therefore intended to describe two or more components positioned separately from each other, where there is no ohmic connection connecting those components. However, components that are electrically insulated from each other may still be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. For example, the two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, for example, by means of an insulator (e.g., a dielectric).

[0030] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices, such as power semiconductor diodes or power semiconductor transistors, arranged in a strip or pin configuration, which can be used within a power converter or power supply. Thus, in embodiments, the semiconductor devices are configured to carry load currents to be fed to a load and / or correspondingly provided by a power source. For example, the semiconductor devices may include one or more active power semiconductor cells, such as monolithically integrated diode cells, monolithically integrated transistor cells, monolithically integrated IGBT cells, monolithically integrated RC-IGBT cells, monolithically integrated MOS gate-controlled diode (MGD) cells, monolithically integrated MOSFET cells, and / or their derivatives. Such diode cells and / or such transistor cells may be integrated within a power semiconductor module. Multiple such cells may form a cell field arranged together with the active region of the power semiconductor device.

[0031] As used in this specification, the term "power semiconductor device" is intended to describe a semiconductor device on a single chip that has high voltage blocking and / or high current carrying capacity. In other words, such a power semiconductor device is intended for use with high currents, typically in the ampere range, such as up to tens or hundreds of amperes, and / or high voltages, typically above 15V, more typically 100V and above, such as up to at least 400V. For example, the processed semiconductor device described below may be a semiconductor device exhibiting a strip cell configuration or a pin cell configuration, and may be configured for use as a power component in low, medium, and / or high voltage applications.

[0032] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0033] Figure 1 and 2 Each schematic and exemplary illustration depicts a portion of a vertical cross-section of a power semiconductor device 1 according to some embodiments. In the following, reference will be made to... Figure 1 and Figure 2 Each of them.

[0034] The illustrated cross-section is parallel to the plane defined by the first lateral direction X and the extension direction Z. Each of the illustrated components of the power semiconductor device 1 may extend along the second lateral direction Y.

[0035] The power semiconductor device 1 includes a semiconductor body 10, such as based on silicon or silicon carbide. Other possible semiconductor materials are further mentioned below. The semiconductor body 10 is coupled to each of a first load terminal 11 and a second load terminal 12 of the power semiconductor device 1. For example, the first load terminal 11 includes a first metallization, and the second load terminal 12 may include a second metallization. The power semiconductor device 1 may be arranged vertically, according to which the semiconductor body 10 is sandwiched between the first load terminal 11 and the second load terminal 12. The first load terminal 11 may also form the front side of the device 1, and the second load terminal 12 may also form the back side of the device 1. Accordingly, the first metallization of the first load terminal 11 may be the front-side metallization, and the second metallization of the second load terminal 12 may be the back-side metallization. For example, the power semiconductor device receives and outputs load current by means of these terminals 11 and 12. Accordingly, at least one of these 11 and 12, such as the first load terminal 11, may include one or more bonding pads (not shown) for bonding, for example, to a plurality of bonding wires.

[0036] The semiconductor body 10 includes a drift region 100 of a dopant having a first conductivity type. For example, the drift region 100 is n- Doped region. Furthermore, the dopant concentration and total elongation of the drift region 100 along the elongation direction Z can substantially define the blocking capability of the power semiconductor device 1, such as the maximum blocking voltage. For example, the blocking voltage is greater than 500V, greater than 1kV, or even greater than 1.5kV.

[0037] In the semiconductor body 10, at least one diode structure may be provided, wherein the diode structure may be configured to conduct the load current between terminals 11 and 12. For example, the number of diode structures provided in the semiconductor body may be configured for a nominal load current of at least 10A, at least 50A, or even greater than 100A.

[0038] The diode structure may include an anode port 101 electrically connected to a first load terminal 11 and a cathode port 102 electrically connected to a second load terminal 12. For example, at least in the drift region, the load current flows substantially parallel to the extension direction Z.

[0039] For example, the anode port 101 is formed of a semiconductor region doped with a dopant of a second conductivity type and arranged to be in electrical contact with the first load terminal. For example, the anode port 101 is a p-doped region electrically connected to the first load terminal 11. The anode port 101 may be arranged between the first load terminal 11 and the drift region 100. Since the drift region 100 and the anode port 101 may be complementary in terms of dopant type, the transition between the drift region 100 and the anode port 101 may form a pn junction, wherein the pn junction may be configured to block the blocking voltage applied between terminals 11 and 12. In an embodiment, the anode port 101 may be formed of the same semiconductor region that also forms a so-called channel region (which is also referred to as a "body region"), wherein the channel region may form part of the transistor structure of the power semiconductor device 1. This alternative aspect will relate to the following: Figure 4 Exemplary embodiments are explained in more detail.

[0040] Cathode port 102 includes a semiconductor region electrically connected to a second load terminal and comprising a dopant of a first conductivity type, such as an n-doped region. Various aspects of this specification relate to certain configurations of cathode port 102.

[0041] Before describing the optional aspects of the cathode port 102, it should be understood that the semiconductor body 10 may also include a field stop region 105 comprising dopants of a first conductivity type. For example, the dopant concentration of the field stop region 105 may be at least 5 times, at least 20 times, or even more than 50 times that of the dopant concentration of the drift region 100. For example, the field stop region 105 is n... +Doped regions. Furthermore, the total extension of the drift region 100 in the extension direction Z can be at least twice the total extension of the field stop region 105 in the extension direction Z. The total extension of the field stop region 105 in the extension direction Z can be in the range of 1 to 200 μm, 3 to 80 μm, or 5 to 40 μm, and its dopant concentration can be at least 1*10⁻⁶. 14 cm -3 At least 8*10 14 cm -3 or even more than 2*10 15 cm -3 Of course, the spatial size and dopant concentration of the field stop region 105 can be selected based on the desired blocking voltage of the power semiconductor device 1. In an embodiment, the dopant concentration of the field stop region 105 can vary along the extension direction Z, which will be explained in further detail below.

[0042] A field stop region 105 may be arranged between the cathode port 102 and the drift region 100. In an embodiment, the cathode port 102 is coupled to the drift region 100 by means of the field stop region 105. Accordingly, according to an embodiment, the cathode port 102 is not directly coupled to the drift region 100, but rather the junction between these regions is formed by the field stop region 105. In other words, the cathode port 102 can be separated from the drift region 100 by means of the field stop region 105.

[0043] The cathode port 102 of the diode structure may include a first port portion 1021 having a dopant of a first conductivity type and a second port portion 1022 having a dopant of a second conductivity type complementary to the first conductivity type.

[0044] like Figure 1 As schematically and exemplary illustrated, port portions 1021 and 1022 may be arranged laterally and alternately adjacent to each other along a first lateral direction X, and arranged to make electrical contact with the second load terminal 12. Accordingly, electrical contact may be established between each of the first port portions 1021 and the second load terminal 12, and between each of the second port portions 1022 and the second load terminal 12. For example, each of the first port portions 1021 and the second port portions 1022 is arranged to contact the second load terminal 12. In addition, each of the first port portions 1021 and the second port portions 1022 may exhibit the same corresponding total extension in the extension direction Z.

[0045] For example, according to Figure 1 Each of the transitions between the first port portion 1021 and the second load terminal 12 and the second port portion 1022 and the second load terminal 12 forms a corresponding ohmic contact.

[0046] In another embodiment, such as Figure 2 As schematically and exemplary, only the first port portion 1021 is arranged to make electrical contact with the second load terminal 12, and the second port portion 1022 is isolated from the second load terminal 12 by means of the first port portion 1021. As illustrated, in this embodiment, the first port portion 1021 may in fact be formed by a continuous first port portion 1021, and such a continuous first port portion 1021 can spatially isolate the second port portion 1022 from the second load terminal 12. For example, thus, the second port portion 1022 may be electrically floating.

[0047] Regardless of the above... Figure 1 and Figure 2 The following applies to both spatial configurations of the second port portion 1022, whether the second port portion 1022 is arranged to be in electrical contact with the second load terminal 12 or to be spatially isolated from it by means of the first port portion 1021.

[0048] Regarding drift region 100, the first port portion 1021 may be doped with the same dopant type as drift region 100, i.e., type 1, and the second port portion 1022 may be doped with a dopant type complementary to the dopant type present in drift region 100, i.e., type 2. For example, the first port portion is n + The semiconductor region is doped, and the second port portion 1022 is a p-doped semiconductor region.

[0049] The dopant concentration of the first port region 1021—which includes dopants of a first conductivity type—can be between 1e18 and 5e20 cm⁻¹. -3 Within the range, or between 2e19 and 2e20cm -3 Within a certain range. For example, the dopant concentration of the first port region 1021 is at most one-hundredth of the dopant concentration of the field stop region 105. For example, the dopant of the first conductivity type includes at least one of phosphorus (P), sulfur (S), selenium (Se), and arsenic (As). To provide such a low dopant concentration, in the case of selenium as the dopant material, the dopant concentration may even be equal to approximately 5e17cm. -3 According to the embodiments, damage injection can be performed.

[0050] The dopant concentration of the second port region 1022—which includes dopants of a second conductivity type—can range from 1e16 to 5e20 cm⁻¹. -3 Within the range of 5e16 to 1e19cm -3 Within the range, or between 1e17 and 1e18 cm -3Within the range. For example, the dopant concentration of the second port region 1022 is at most one-half, at most one-fifth, or at most one-tenth of the dopant concentration of the first port region 1021.

[0051] In this embodiment, the cathode port 102 primarily contributes to the diode function via the first port portion 1021, and the second port portion 1022 can be used to achieve another function, which will be explained in more detail below. The difference in this function can have an impact on the spatial dimensions of the first port portion 1021 and the second port portion 1022, some examples of which will now be explained.

[0052] For example, regarding the diode structure, the second port portion 1022 constitutes a percentage of less than 50%, less than 20%, or even less than 5% of the total volume of the cathode port 102. According to embodiments, the higher the percentage share of the second port portion 1022, the greater the reduction in emitter efficiency. For example, the second port portion 1022 is configured to prevent the dynamic injection of charge carriers.

[0053] Additionally, each of the second port portions 1022 may exhibit one of the following: a strip structure whose total extension in the second lateral direction Y is at least a multiple of its total extension in the first lateral direction X, an island structure (e.g., having a circular, elliptical, or rectangular perimeter), and a comb structure.

[0054] In the embodiments, regarding, for example Figure 1 The second port portion 1022 can exhibit a smaller total extension in the first lateral direction X than the total extension of each of the first port portions 1021 along the first lateral direction. This factor can be equal to at least two, at least five, or at least ten; correspondingly, the corresponding first port portion 1021 can exhibit a width at least twice the width of the corresponding second port portion 1022. Regarding... Figure 2 In some embodiments, the factor can be even larger; that is, the continuous first port portion 1021 can exhibit a width that is at least ten times larger than the corresponding width of the second port portion 1022.

[0055] The width of the corresponding second port portion 1022 can be less than 20 μm; for example, the width is in the range of 0.1 μm to 20 μm, in the range of 1 μm to 10 μm, or in the range of 2 μm to 8 μm.

[0056] Additionally, the second load terminal 12 may exhibit a contact region 121 facing the semiconductor body 10, wherein, in the active region of the power semiconductor device 1 (see, for example...), Figure 5AIn reference numeral 17), the percentage share of the contact area 121 that laterally overlaps with the second port portion 1022 can be at most one-half, at most one-fifth, or at most one-tenth of the percentage share of the contact area 121 that laterally overlaps with the first port portion 1021.

[0057] Accordingly, based on the foregoing, it becomes clear that in the embodiments, at least in the active region of the power semiconductor device 1, the cathode port 102 may be primarily formed by one or more first port portions 1021, but also includes a second port portion 1022, which is complementary to the dopant type and may interrupt the first port portion 1021, as per [reference to previous description]. Figure 1 As in the embodiments described above, or by "attaching a tag (docket)" to the first port portion 1021 without interrupting it, as per [the relevant documentation]. Figure 2 As in the example implementation.

[0058] Now refer to Figure 5A The diagram schematically and exemplary illustrates a portion of a horizontal cross-section of a power semiconductor device 1 according to an embodiment. The power semiconductor device 1 may include an active region 17, which includes one or more diode structures 1-1, for example, as described above regarding... Figure 1 and Figure 2 The configuration is as described. In the active region 17, in addition to the one or more diode structures 1-1, one or more transistor structures 1-2 may be arranged, for example, adjacent to one of the diode structures 1-1, wherein each transistor structure 1-2 may exhibit an IGBT configuration. The number of transistor structures may also be configured to conduct, for example, the nominal load current of 10A, at least 50A, or even more than 100A.

[0059] Therefore, the active region 17 of the power semiconductor device 17 can be configured to conduct load current between the first load terminal 11 and the second load terminal 12. For example, the forward load current is conducted by the one or more transistor structures 1-2, and the reverse load current is conducted by the one or more diode structures 1-1.

[0060] The active region 17 may be surrounded by a termination structure 18, which may be terminated by an edge structure 19. The edge structure 19 may be formed substantially by an edge that can be produced by wafer dicing. For example, the termination structure 18 may not be configured to conduct load current, but rather to achieve another purpose, such as avoiding excessively high electric field peaks; therefore, the termination structure 18 may be a non-active region.

[0061] Exemplary aspects of transistor structures 1-2 are as follows: Figure 4 The diagram is schematic and exemplary, showing that... Figure 4A portion of the vertical cross-section is shown. Accordingly, transistor structure 1-2 may include emitter region 103, such as a back emitter, which may be electrically connected to the second load terminal 12 on one side and to the field stop region 105 on the other side. According to an embodiment, the field stop region 105 may be configured in a layered manner and may extend into each of diode structure 1-1 and transistor structure 1-2 without interruption.

[0062] For example, emitter region 103 includes a dopant of a second conductivity type, such as emitter region 103 being p. + Doped semiconductor region.

[0063] A control electrode 131 may be arranged near the first load terminal 11. For example, the control electrode 131 may laterally overlap with the emitter region 103 along a first lateral direction X. The control electrode 131 may be configured as a planar electrode or, as illustrated, as a trench electrode included in the trench 13. The control electrode 131 may be electrically insulated from the semiconductor body 10 by means of an insulator 132 (e.g., an oxide). Adjacent to the insulator 132, a source region 104 may be provided, which may include a dopant of a first conductivity type and may be electrically connected to the first load terminal 11. For example, the source region 104 is an n-type electrode arranged to contact the first load terminal 11. + Doped semiconductor region. The source region 104 can be isolated from the drift region 100 by a channel region (also referred to as the "body region"), which can be formed by the same semiconductor region that also forms the anode port 101 of the diode structure 1-1. For example, the channel region 101 that isolates the source region 104 from the drift region 100 is a p-doped region. The control electrode 131 can be configured to introduce an inversion channel in the channel region 101, for example, when a corresponding control signal is received, the control signal can be formed by a voltage applied between the first load terminal 11 and a control terminal (not shown) of the power semiconductor device 1 electrically connected to the control electrode 131.

[0064] For example, transistor structures 1-2 represent an IGBT configuration. Accordingly, transistor structures 1-2 can be formed in a common manner to provide IGBT functionality, and they can exhibit typical IGBT characteristics. As already mentioned above, aspects of this specification more precisely relate to certain configurations of the cathode port 102, some of which will now be clarified.

[0065] For example, in diode structure 1-1, such as... Figure 1 or Figure 2 As illustrated, the transition between each of the second port portions 1022 and the field stop region 105 forms a corresponding pn junction 1052 extending along the first lateral direction X. The total extension of the pn junction 1052 in the first lateral direction X may correspond to the width of the corresponding second port portion 1022.

[0066] Further reference Figure 3 Each of the pn junctions 1052 can exhibit a diffusion voltage VD parallel to the extension direction Z, which is perpendicular to the first lateral direction X. For example, in the case where the semiconductor body 10 is formed of Si, the diffusion voltage VD is in the range of 0.3V to 0.9V, 0.4V to 0.8V, or 0.5V to 0.7V, where the exact amount can depend on the dopant concentration of the corresponding second port portion 1022 and the field stop region 105 and on the temperature. In the case where the power semiconductor body 10 is formed of SiC, the diffusion voltage VD can be significantly larger.

[0067] According to an embodiment, the diffusion voltage VD of a corresponding one of the pn junctions 1052 is greater than the lateral voltage drop VL that laterally overlaps with the lateral extension of the corresponding pn junction 1052. In this embodiment, this effect—VD greater than VL—occurs during the nominal state of the power semiconductor device 1, for example, if the semiconductor body conducts a load current within the range of the nominal load current to which the power semiconductor pin is designed. In contrast, during overload conditions, for example, when the load current exceeds the nominal load current by a factor of two, the effect must not necessarily exist. Alternatively, if no load current is conducted, then obviously such a lateral voltage drop VL is substantially absent. This aspect is explained in more detail below.

[0068] For example, the lateral voltage drop VL is caused by a portion of the load current IL formed by charge carriers (e.g., electrons) of a first conductivity type. This load current IL can flow between the first load terminal 11 and the second load terminal 12 (i.e., generally parallel to the extension direction Z). However, the portion of the load current IL does not pass through the pn junction 1052, but instead bypasses the second port portion 1022. Thus, the lateral voltage drop VL can occur. For example, the lateral voltage drop VL occurs at a certain distance in the first lateral direction X, said distance being equal to 50% of the total extension in the first lateral direction X, for example, equal to 50% of the maximum extension in the first lateral direction X of the corresponding second port portion 1022. This 50% can be constituted by the distance between one of the lateral center and one of the lateral ends of the corresponding second port portion 1022. The same voltage drop, but with another polarity, can occur at another 50%. Accordingly, the sum of the voltage drops along the entire lateral extension of the second pn junction 1052 can be substantially equal to zero.

[0069] The difference in voltage between the diffusion voltage VD and the transverse voltage drop VL can be equal to at least 10mV, at least 20mV, or more than 50mV.

[0070] Accordingly, the embodiments described herein can be configured to satisfy the conditions listed in the following expressions:

[0071] (1) VL <VD

[0072] (2) VD - VL > 10 mV;

[0073] The magnitude of the transverse voltage drop VL can be proportional to the following physical quantities:

[0074] (3) VL ~ IL * R ~ IL *.5 XP * 1 / CC(Z) * 1 / ZN

[0075] In expression (3), IL can be a portion of the load current flowing along a distance equal to 50% of the total lateral extension XP of the second port portion 1022 in the first lateral direction X, and R can be an ohmic resistance effective along said distance. This resistance R can depend on the dopant concentration CC of the field stop region 105, where the dopant concentration of the field stop region can be a function of Z (CC = CC(Z)), and where R can also depend on the total extension ZN of the field stop region 105 in the extension direction Z. For an exemplary trajectory of the dopant concentration CC of the field stop region 105, refer to... Figure 7 Examples of implementations.

[0076] As becomes apparent from the above, the lateral voltage drop VL can depend on the total load current. In an embodiment, the power semiconductor device 1 is configured to satisfy the conditions listed in expressions (1) and (2), at least as long as the load current is equal to or less than the nominal load current to which the power semiconductor device 1 is designed, for example, as long as the power semiconductor device 1 operates within the nominal voltage and nominal current range to which it is designed. Of course, if the power semiconductor device 1 is in an overload state, where the load current significantly exceeds the nominal load current, for example due to a short circuit or device failure, the conditions according to equation (1) can no longer be satisfied, since the lateral voltage drop VL can increase in response to the increase in load current, while the diffusion voltage VD of the pn junction 1052 remains substantially unchanged, regardless of whether the semiconductor device 1 is in a nominal state or an overload state.

[0077] Figure 7 The diagram schematically and exemplary illustrates a dopant concentration distribution in a power semiconductor device 1 according to one or more embodiments, for example, a dopant of a first conductivity type along an extension direction Z (e.g., along a path passing through each of the drift region 100, the field stop region 105, and the second port portion 1022, for example, according to...). Figure 3 The embodiment shown in the figure is in any unit (arb. un.) (e.g., in cm). -3The concentration of dopant (CC) is shown. For example, near the 1052 pn junction, the dopant concentration in the field stop region exhibits a minimum, for example, at 1e14 cm⁻¹. -3 up to 5e14 cm -3 Within the range. Along the direction opposite to the extension direction Z, one or more local maxima LM1, LM2, LM3 of the dopant concentration in the field stop region 105 can be found. For example, the first local maximum LM1, i.e., the local maximum closest to the second port portion 1022, is at 5e14 cm⁻¹. -3 up to 8e15 cm -3 Within the range. If present, other local maxima LM2 and LM3 can exhibit dopant concentrations within the same range as LM1. Alternatively, local maxima LM2 and LM3 can exhibit dopant concentrations between the dopant concentration of local maximum LM1 and the minimum concentration near pn junction 1052. Furthermore, according to an embodiment, the distance d between pn junction 1052 and the first local maximum LM1 is equal to at least 0.5 μm, 1 μm, or at least 3 μm. For example, along said distance d, the dopant concentration in field stop region 105 is less than 5e14 cm⁻¹. -3 The existence of one or more local maxima allows for a reduction in resistance R, thereby keeping VL small. Additionally, regarding... Figure 3 By using the current path indicated by the dotted line, arranging the one or more local maxima LM1, LM2, LM3 at the minimum distance d relative to the second port portion allows the load current IL to change its direction from Z to X / -X in the field stop region 105 quite "early"; that is, according to the embodiment, most of the load current in the lateral direction is held at the minimum distance d relative to the second port portion 1022.

[0078] As explained above, the power semiconductor device 1 may include one or more transistor structures 1-2. Accordingly, the power semiconductor device 1 may be configured to operate in both a blocking state and an on state. For example, during the blocking state, the voltage applied between the first load terminal 11 and the second load terminal 12 can be blocked, and the flow of forward load current is suppressed. However, reverse load current can be conducted by the power semiconductor device via the one or more diode structures 1-1. When in the on state, forward load current can be conducted by the power semiconductor device in the direction opposite to the reverse current, for example, via the aforementioned number of transistor structures 1-2.

[0079] For example, the power semiconductor device 1 can thus exhibit an RC-IGBT configuration, which can be essentially formed by the one or more diode structures 1-1 and the one or more transistor structures 1-2.

[0080] In an embodiment, each of the second port portions 1022 may be configured to prevent the emission of charge carriers, such as charge carriers of a second conductivity type, toward the drift region 100 during the turn-off process in one or more transistor structures 1-2. For example, such functionality of the second port portions 1022 is maintained up to a threshold of the total load current, wherein, according to an embodiment, such a threshold may be equal to at least twice the nominal load current for which the power semiconductor device 1 is designed.

[0081] Additionally, the second port portion 1022 can be configured to drain charge carriers of a second conductivity type. Thus, the second port portion 1022 can be configured to reduce the emitter efficiency of the power semiconductor device 1, such as the emitter efficiency of the cathode port 102.

[0082] For example, if diode structure 1-1 is based on Figure 2 In an embodiment configured such that the dopant concentration and space size of the second port portion 1022 are selected such that the pn junction formed by the transition between the second port portion 1022 and the continuous first port portion 1021 does not avalanche during the turn-off operation in the transistor structure 1-2. For example, for this purpose, according to an embodiment, the dopant concentration of the second port portion 1022 can be maintained at 1*10 17 cm -3 the following.

[0083] As explained above, the cathode port 102 can primarily provide diode functionality via the first port portion 1021, and the second port portion 1022 can be used to achieve another function, such as that described in the preceding paragraphs. As further explained above, the difference in functionality can have an effect on the dopant concentration and / or spatial dimensions of the first port portion 1021 and the second port portion 1022. For example, the second load terminal 12 can exhibit the contact region 121 facing the semiconductor body 10, wherein in the active region 17 of the power semiconductor device 1, the percentage share of the contact region 121 laterally overlapping with the second port portion 1022 of the cathode port of the diode structure 1-1 can be at most half of the percentage share of the contact region 121 laterally overlapping with the first port portion 1021 of the cathode port of the diode structure 1-1.

[0084] In an embodiment, the percentage share of the contact region 121 that laterally overlaps with the second port portion 1022 may increase along the direction from the diode structure 1-1 of the power semiconductor device 1 to the adjacent structure, wherein the adjacent structure may include at least one of the edge structure 19 and the transistor structure 1-2. Accordingly, the increase in the percentage share may occur in a transition region disposed between the diode structure 1-1 and the adjacent structures 19 and / or 1-2. For example, refer to... Figure 5B The transition region is located in the termination structure 18 arranged between the diode structure 1-1 and the edge structure 19. Accordingly, the transition region can form a part of the termination structure 18. Figure 5C neutralization Figure 4 In the embodiment illustrated in the figure, the transition region 1-12 is located between the diode structure 1-1 and the transistor structure 1-2.

[0085] Additionally, according to an embodiment, the power semiconductor device 1 does not conduct load current in the transition regions 18 and / or 1-12. Instead, the transition regions 18 and / or 1-12 can be non-active regions; for example, the transition regions 18 and / or 1-12 can be considered decommissioned semiconductor regions. Therefore, it should be understood that the cathode port 102 can extend from the diode structure 1-1 into the transition regions 18 and / or 1-12, wherein, in an embodiment, in the portion of the cathode port 102 that is part of the diode structure 1-1, at least one of the two conditions explained above applies, namely, the lateral voltage drop VL is less than the diffusion voltage VD and / or the percentage share of the contact region 121 that laterally overlaps with the second port portion 1022 is at most half of the percentage share of the contact region 121 that laterally overlaps with the first port portion 1021, and wherein, in the portion of the cathode port 102 that is not part of the diode structure but part of the transition structure, the percentage share of the contact region 121 that laterally overlaps with the second port portion 1022 can be increased.

[0086] For example, the increase in the percentage share occurs in a step-like or gradual manner. The increase in the percentage share can be equal to a factor of at least two. For example, in the transition region, approximately 50% of the total volume of the cathode port can be constituted by the first port portion 1021, and another 50% of the total volume of the cathode port can be constituted by the second port portion 1022. A portion of the second port portion 1022 can be even greater than 50%, for example, at least 60%, at least 70%, or even greater than 80%. For example, the transition region 18 / 1-12 exhibits a total extension of at least 10 μm in the first lateral direction X. This total extension can be even greater than 50 μm, greater than 150 μm, or even greater than 250 μm. The total extension of the transition region 18 / 1-12 can also depend on the blocking voltage of the power semiconductor device, for example, on the thickness of the semiconductor body 10 in the extension direction. For example, the total extension of the transition region 18 / 1-12 can be equal to at least half, at least equal to, or at least twice the thickness of the semiconductor body 10. Additionally, in transition regions 18 / 1-12, port portions 1021 and 1022 may be arranged laterally and alternately adjacent to each other along the first lateral direction X, and arranged to make electrical contact with the second load terminal 12. For example, in transition regions 18 / 1-12, each of the first port portion 1021 and the second port portion 1022 may exhibit a corresponding total extension in the first lateral direction X of 10% of the thickness of the semiconductor body 10 in the extension direction Z, for example, less than 5 μm, less than 2 μm, or even less than 1 μm.

[0087] For example, according to an embodiment, due to the increase in the percentage share in the transition regions 18 / 1-12, the charge carrier plasma during the on-state period of the power semiconductor device 1 (i.e., during the conduction of the load current) can be significantly reduced in the transition region.

[0088] Reference Figure 4 In some embodiments, the power semiconductor device 1 may further include a control terminal, such as a gate pad (not shown), electrically connected to a control electrode 131. For example, the control terminal of the power semiconductor device 1 is configured to receive a control signal from, for example, a gate driver, wherein the control signal may consist of a voltage applied between the control terminal and the first load terminal 11. For example, the potential of the control terminal is transferred to the control electrode 131, thereby allowing the control electrode 131 to control operation in the transistor structures 1-2, such as switching operation. In some embodiments, the electrical connection between the control electrode 131 and the control terminal may at least include a contact rail (see...). Figure 6 Reference numeral 133 (as shown in the original text) can be arranged at least partially outside the semiconductor body 10. For example, contact rails can be arranged in the surface structure of the power semiconductor device 1. Figure 6In the schematically and exemplary embodiment illustrated, transition regions 18; 1-12, wherein the percentage of lateral overlap between contact region 121 and the second port portion 1022 increases, and also laterally overlaps with contact rail 133, which electrically connects the control terminal to the control electrode 131. This positioning of transition regions 18; 1-12 allows for reduced stress applied to contact rail 133 during switching operations of the power semiconductor device 1.

[0089] According to another embodiment, a method for processing a power semiconductor device is presented. The method may include the following processing steps: providing a semiconductor body 10 to be coupled to each of a first load terminal 11 and a second load terminal 12 of the power semiconductor device; and forming in the semiconductor body 10: a drift region 100 having a dopant of a first conductivity type; at least one diode structure configured to conduct load current between the terminals 11, 12 and including an anode port 101 electrically connected to the first load terminal 11 and a cathode port 102 electrically connected to the second load terminal 12; and a field stop region 105 having a dopant of the first conductivity type at a higher dopant concentration than the drift region 100, wherein the field stop region 105 is disposed between the cathode port 102 and the drift region 100. The method may further include forming a first port portion 1021 having a dopant of a first conductivity type and a second port portion 1022 having a dopant of a second conductivity type complementary to the first conductivity type in the cathode port 102, the transition between each of the second port portions 1022 and the field stop region 105 forming a corresponding pn junction 1052 extending along a first lateral direction X; and ensuring that a corresponding diffusion voltage VD of the pn junction 1052 in an extension direction Z perpendicular to the first lateral direction X is greater than a lateral voltage drop VL that laterally overlaps with the lateral extension of the corresponding pn junction 1052.

[0090] According to another embodiment, an additional method for processing a power semiconductor device is presented. This additional method may include the following processing steps: providing a semiconductor body 10 to be coupled to each of a first load terminal 11 and a second load terminal 12 of a power semiconductor device 1; forming in the semiconductor body 10: a drift region 100 having a dopant of a first conductivity type; at least one diode structure configured to conduct load current between the terminals 11, 12 and including an anode port 101 to be electrically connected to the first load terminal 11 and a cathode port 102 to be electrically connected to the second load terminal 12; and having a first dopant concentration higher than that of the drift region 100. A field stop region 105 of a dopant of a first conductivity type is disposed between a cathode port 102 and a drift region 100; in the cathode port 102, a first port portion 1021 having a dopant of a first conductivity type and a second port portion 1022 having a dopant of a second conductivity type complementary to the first conductivity type are formed, and the transition between each of the second port portions 1022 and the field stop region 105 forms a corresponding pn junction 1052 extending along a first lateral direction X, wherein a second load terminal 12 exhibits a contact region 121 facing the semiconductor body 10. For example, the cathode port 102 is formed such that in the active region 17 of the power semiconductor device 1, the percentage of the contact region 121 that laterally overlaps with the second port portion 1022 is at most half the percentage of the contact region 121 that laterally overlaps with the first port portion 1021; and the percentage of the contact region 121 that laterally overlaps with the second port portion 1022 increases in the direction from the diode structure 1-1 of the power semiconductor device 1 to the adjacent structure 1-2 (or 19), the adjacent structure including at least one of the edge structure 19 and the transistor structure 1-2.

[0091] Exemplary ways of implementing the methods presented above can correspond to embodiments of the power semiconductor device 1 described above. Referring so far to the foregoing, for example, the back side of the semiconductor body 10 can be processed to form the cathode port 102, for example by positioning, sizing, and doping the first port portion 1021 and the second port portion 1022, such that at least one of the conditions defined herein is satisfied.

[0092] For example, embodiments of the described method may include forming one or more local maxima LM1, LM2, LM3 of the dopant concentration of the field stop region 105 at a minimum distance d of 0.5 mm from the second port portion 1022, as per [reference to...]. Figure 7 This is listed in more detail. For example, this could include implementing proton injection.

[0093] The power semiconductor device 1 presented above can be a bipolar power semiconductor device 1, such as a power diode or an RC-IGBT. The presented diode structure can also be used to form the drain region of a MOSFET, wherein the body diode of the MOSFET serves as a freewheeling diode. Accordingly, the method presented above can involve processing at least one of a power diode, an RC-IGBT, and a MOSFET.

[0094] The embodiments disclosed above include the understanding that, for example, in bipolar power semiconductor devices, it is possible to control charge carrier plasma by means of reducing charge carrier lifetime. Such reduction can be achieved, for example, by means of injection, such as electron injection and injection of at least one of helium and platinum, and / or by means of diffusion (e.g., diffusion of platinum). As already mentioned in the description, in order to achieve low on-state losses in power semiconductor devices, the charge carrier lifetime should be relatively long, wherein, in order to achieve low switching losses in power semiconductor devices, the charge carrier lifetime should be relatively short. However, impurities provided in the semiconductor body to reduce charge carrier lifetime can act as charge carrier generators in the blocking state of the power semiconductor device. As a result, leakage current can increase, which may be undesirable, for example, with respect to diode structures configured for relatively high junction temperatures. According to the embodiments presented above, by providing a second port portion 1022, which serves as a portion of the cathode port 102 at certain locations, having certain spatial dimensions and a certain dopant concentration, an appropriate emitter efficiency that allows for both low switching losses and on-state losses can be achieved.

[0095] The preceding text explained embodiments of semiconductor device processing methods. For example, these semiconductor devices are based on silicon (Si). Accordingly, single-crystal semiconductor regions or layers, such as the semiconductor body 10, drift region 100, and other regions 101, 102, 1021, 1022, 103, 104, and 105 of the exemplary embodiments, can be single-crystal Si regions or Si layers. In other embodiments, polycrystalline or amorphous silicon may be employed.

[0096] However, it should be understood that the semiconductor body 10 and components, such as regions 100, 101, 102, 1021, 1022, 103, 104 and 105, can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, the following: elemental semiconductor materials such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials such as silicon carbide (SiC) or silicon-germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The semiconductor materials mentioned above are also referred to as "homogeneous junction semiconductor materials." Heterogeneous junction semiconductor materials are formed when two different semiconductor materials are combined. Examples of heterojunction semiconductor materials include, but are not limited to, the following: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs, and GaN materials are currently the primary materials used.

[0097] Spatial relative terms such as “below,” “below,” “lower,” “above,” and “higher” are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the corresponding devices in addition to those different from those depicted in the accompanying drawings. Furthermore, terms such as “first” and “second” are also used to describe various elements, regions, segments, etc., and are not intended to be limiting. Throughout this description, similar terms refer to similar elements.

[0098] As used herein, the terms “having,” “containing,” “including,” “comprising,” “showing,” etc., are open-ended terms that indicate the presence of the described element or feature but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0099] Given the above scope of variations and applications, it should be understood that the invention is not limited to the foregoing description, nor is it limited by the accompanying drawings. Instead, the invention is limited only by the appended claims and their legal equivalents.

Claims

1. A power semiconductor device, comprising: A semiconductor body is coupled to a first load terminal and a second load terminal, wherein the semiconductor body comprises: Drift region of a dopant having a first conductivity type; At least one diode structure is configured to conduct load current between first and second terminals and includes an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; A field stop region having a dopant of a first conductivity type with a higher dopant concentration than the drift region, the field stop region being arranged between the cathode port and the drift region; The active region and the termination region that laterally separates the active region from the lateral edge of the semiconductor body. The cathode port includes: A first port portion having a dopant of a first conductivity type and a second port portion having a dopant of a second conductivity type complementary to the first conductivity type, wherein the transition between each of the second port portions and the field stop region forms a corresponding pn junction extending along a first lateral direction; A first group of the first and second port portions is disposed in the active region, the first group comprising first port portions alternately arranged between the second port portions. A second group of the first and second port portions is disposed in the termination region, the second group comprising first port portions alternately arranged between the second port portions, and The lateral separation distance between adjacent second port portions in the second group is smaller in the second group than in the first group.

2. The power semiconductor device of claim 1, wherein the active region comprises one or more transistor structures, and wherein the termination region has no transistor structure.

3. The power semiconductor device of claim 2, wherein the first port portion is arranged to make electrical contact with the second load terminal, and wherein the second port portion is isolated from the second load terminal through the first port portion.

4. The power semiconductor device of claim 2, wherein the doping concentration of the second port portion is less than the doping concentration of each of the first port portions.

5. A power semiconductor device, comprising: The semiconductor body includes: Drift region of a dopant having a first conductivity type; A field stop region having a dopant of the first conductivity type with a higher dopant concentration than the drift region; and The active region and the termination region that laterally separates the active region from the lateral edge of the semiconductor body. The termination region includes: A first port portion having a dopant of a first conductivity type and a second port portion having a dopant of a second conductivity type complementary to the first conductivity type, wherein the transition between each of the second port portions and the field stop region forms a corresponding pn junction extending along a first lateral direction, wherein the diffusion voltage of the corresponding pn junction in the extension direction perpendicular to the first lateral direction is greater than the lateral voltage drop that laterally overlaps with the lateral extension of the corresponding pn junction.

6. The power semiconductor device of claim 5, wherein the active region comprises one or more transistor structures, and wherein the termination region has no transistor structure.

7. The power semiconductor device of claim 5, wherein the semiconductor body includes a cathode port coupled to a load electrode, and wherein the first port portion and the second port portion are disposed in the cathode port.

8. The power semiconductor device of claim 5, wherein the lateral voltage drop is caused by a portion of the load current formed by charge carriers of the first conductivity type.

9. The power semiconductor device of claim 5, wherein the lateral voltage drop occurs at a distance in the first lateral direction, the distance being equal to 50% of the total extension of the corresponding second port portion in the first lateral direction.

10. A power semiconductor device, comprising: A semiconductor body is coupled to a first load terminal and a second load terminal, wherein the semiconductor body comprises: Drift region of a dopant having a first conductivity type; Electrically connected to the anode port of the first load terminal; Electrically connected to the cathode port of the second load terminal; A field stop region having a dopant of a first conductivity type with a higher dopant concentration than the drift region, the field stop region being disposed between the cathode port and the drift region; and The transition region that laterally separates the transistor region from the diode region. The transistor region includes one or more active transistor devices. The diode region includes a diode structure. In the transition region and the diode region, the cathode port includes: A first port portion having a dopant of a first conductivity type and a second port portion having a dopant of a second conductivity type complementary to the first conductivity type, wherein the transition between each of the second port portions and the field stop region forms a corresponding pn junction extending along a first lateral direction; The lateral separation distance between adjacent second port portions in the second port portion is greater in the diode region than in the transition region.

11. The power semiconductor device of claim 10, further comprising an active region, the active region comprising one or more transistor structures, wherein the transition region and the diode region have no transistor structures.

12. The power semiconductor device of claim 10, wherein the transistor region includes a vertical transistor, the vertical transistor comprising: A gate trench extending through the anode port and into the drift region, the gate trench including a conductive gate electrode and a gate dielectric that insulates the gate electrode from the semiconductor body; and The source region is adjacent to the gate trench and is perpendicularly separated from the drift region through a portion of the anode region. The gate electrode is configured as a conductive channel between the source region and the drift region.

13. The power semiconductor device of claim 12, wherein the vertical transistor is configured as an insulated-gate bipolar transistor, the insulated-gate bipolar transistor is configured to conduct forward current between first and second load terminals, and wherein the diode structure is configured to conduct reverse current between the first and second load terminals.

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