Memory device and method of manufacturing the same

Abstract

The present invention discloses a memory device and a method for manufacturing the same. The memory device includes a device substrate, a lower electrode, a variable resistance layer, and an upper electrode. The lower electrode is disposed on the device substrate. The variable resistance layer is disposed on the lower electrode. The upper electrode is disposed on the variable resistance layer. The lower electrode is formed to have tensile stress, and the upper electrode is formed to have compressive stress.

Description

Technical Field

[0001] The present invention relates to a memory device and a method of manufacturing the same. Background Art

[0002] Many current electronic devices include electronic memories for storing data. Electronic memories include volatile memories and non-volatile memories. Volatile memories can only store data when powered on, while non-volatile memories can retain the data stored therein when powered off. Resistive random access memory (RRAM) is a promising non-volatile memory technology. RRAM has the advantages of a simple structure, small footprint, low switching voltage, and short switching time, and is compatible with complementary metal oxide semiconductor (CMOS) fabrication processes. Summary of the Invention

[0003] One aspect of the present invention provides a memory device, comprising: a device substrate; a lower electrode disposed on the device substrate; a variable resistance layer disposed on the lower electrode; and an upper electrode disposed on the variable resistance layer, wherein the lower electrode is formed to have tensile stress, and the upper electrode is formed to have compressive stress.

[0004] In some embodiments, the lower electrode and the upper electrode respectively provide stress fields towards the variable resistance layer.

[0005] In some embodiments, the variable resistance layer is subjected to compressive stress corresponding to the stress fields provided by the lower electrode and the upper electrode.

[0006] In some embodiments, the lower electrode and the upper electrode are formed of the same conductive material.

[0007] In some embodiments, the materials of the lower electrode and the upper electrode respectively include titanium nitride, tantalum nitride, tantalum, or a combination thereof.

[0008] In some embodiments, the memory device further comprises: a cover layer covering sidewalls of the lower electrode, the variable resistance layer, and the upper electrode, and formed to have compressive stress.

[0009] In some embodiments, the lower electrode, the upper electrode, and the cover layer respectively provide stress fields towards the variable resistance layer, and the variable resistance layer is subjected to compressive stress corresponding to the application of the stress fields.

[0010] In some embodiments, the capping layer is formed as a wall structure that laterally surrounds the lower electrode, the variable resistance layer, and the upper electrode.

[0011] In some embodiments, the capping layer laterally surrounds the lower electrode, the variable resistance layer, and the upper electrode, and further covers the top surface of the upper electrode.

[0012] In some embodiments, the material of the capping layer includes silicon nitride, aluminum nitride, or a combination thereof.

[0013] Another aspect of the present invention provides a memory device, including: a lower electrode having a first stress and an upper electrode having a second stress, formed in a back-end process structure located on a semiconductor substrate, wherein the upper electrode is located on the lower electrode and overlaps the lower electrode; and a variable resistance layer sandwiched between the lower electrode and the upper electrode, and generating compressive strain corresponding to the first stress of the lower electrode and the second stress of the upper electrode.

[0014] In some embodiments, the memory device further includes: a stress layer covering sidewalls of the upper electrode, the variable resistance layer, and the lower electrode, and formed to have a third stress.

[0015] In some embodiments, the variable resistance layer further generates compressive strain corresponding to the third stress of the stress layer.

[0016] Yet another aspect of the present invention provides a method for manufacturing a memory device, including: sequentially forming a lower electrode layer, a variable resistance material layer, an upper electrode layer, and a hard mask layer on a device substrate, wherein the lower electrode layer is formed to have tensile stress, and the upper electrode layer is formed to have compressive stress; patterning the hard mask layer to form a hard mask; removing some portions of the upper electrode layer, the variable resistance material layer, and the lower electrode layer by using the hard mask as a mask to respectively form an upper electrode, a variable resistance layer, and a lower electrode; and removing the hard mask.

[0017] In some embodiments, the lower electrode layer is formed by a physical vapor deposition process using a radio frequency alternating current power source and a direct current power source, and the upper electrode layer is formed by a physical vapor deposition process using a direct current power source.

[0018] In some embodiments, the method for manufacturing the memory device further includes: after removing the hard mask, forming a capping material layer covering exposed surfaces of the upper electrode, the variable resistance layer, and the lower electrode, wherein the capping material layer is formed to have compressive stress.

[0019] In some embodiments, the method of manufacturing the memory device further includes: after forming the capping material layer, performing an anisotropic etching process on the capping material layer to remove a portion of the capping material layer covering the top surface of the upper electrode.

[0020] In some embodiments, the capping layer does not undergo an ion implantation process.

[0021] In some embodiments, the capping material layer is formed by a chemical vapor deposition process using a radio frequency alternating current power source and a direct current power source.

[0022] In some embodiments, some portions of the upper electrode layer, the variable resistance material layer, and the lower electrode layer are removed by multiple anisotropic etching processes to respectively form the upper electrode, the variable resistance layer, and the lower electrode.

[0023] Based on the above, the memory integrated circuit of the present invention can be a resistive memory integrated circuit, and the variable resistance layer in the variable resistance device of the memory cell is subjected to a compressive stress (generating a compressive strain) due to the stress field generated by the surrounding film layers. Specifically, at least one of the upper electrode and the lower electrode above and below the variable resistance layer can be configured to generate a stress field toward the variable resistance layer, so that the variable resistance layer is subjected to a compressive stress (generating a compressive strain). In addition, the capping layer that at least covers the sidewalls of the variable resistance layer can also be selectively configured to generate a stress field pointing from the outside of the variable resistance layer inward to the variable resistance layer, so as to further increase the compressive stress (increase the generated compressive strain) borne by the variable resistance layer. The above-mentioned compressive stress / compressive strain is beneficial to forming a conductive channel in the variable resistance layer and truncating or eliminating the above-mentioned conductive channel in the variable resistance layer. In this way, the write and erase operations of the variable resistance device can be performed at a lower operating voltage. Furthermore, the write and erase operations can be performed in a shorter time. Therefore, the power consumption of the memory integrated circuit can be reduced, and the operating speed of the memory integrated circuit can be increased. Description of the Drawings

[0024] Figure 1A is an equivalent circuit diagram of a resistive memory integrated circuit according to some embodiments of the present invention;

[0025] Figure 1B is Figure 1A a schematic diagram of the memory cell shown;

[0026] Figure 1C is Figure 1A and Figure 1B a cross-sectional schematic diagram of the variable resistance device shown;

[0027] Figure 1D is Figure 1C a top view schematic diagram of the variable resistance device shown;

[0028] Figure 2 is a manufacturing flowchart for fabricating Figure 1C the variable resistor device shown;

[0029] Figures 3A to 3J are cross-sectional schematic views of intermediate structures at various stages during the above manufacturing process;

[0030] Figure 4 is a cross-sectional schematic view of a variable resistor device according to some embodiments of the present invention. Detailed Description of the Invention

[0031] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0032] Figure 1A is an equivalent circuit diagram of a resistive memory integrated circuit 10 according to some embodiments of the present invention. Figure 1B is Figure 1A a schematic view of the memory cell MC shown. Figure 1C is Figure 1A associated with Figure 1B a cross-sectional schematic view of the variable resistor device 100 shown. Figure 1D is Figure 1C a top view schematic of the variable resistor device 100 shown.

[0033] Please refer to Figure 1A, the memory integrated circuit 10 can be a resistive memory integrated circuit, or can be simply referred to as a resistive memory. The memory integrated circuit 10 includes a plurality of memory cells MC, or memory devices. The plurality of memory cells MC can be arranged in an array, and can have a plurality of rows extending in the X direction and a plurality of columns extending in the Y direction. Each memory cell MC includes a variable resistance device 100 and an access transistor 200 electrically connected to the variable resistance device 100. The variable resistance device 100 can be a two-terminal device. By controlling the bias voltage between the two terminals of the variable resistance device 100, the resistance state of the variable resistance device 100 can be converted. For example, the resistance between the two terminals of the variable resistance device 100 can be changed from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state. In this way, the variable resistance device 100 can be configured to store a high logic state and a low logic state. One terminal of each variable resistance device 100 can be electrically connected to the access transistor 200, and the other terminal can be electrically connected to a bit line BL. On the other hand, the access transistor 200 can be a three-terminal device, such as a field effect transistor (FET). The gate terminal of each access transistor 200 can be connected to a word line WL. In addition, one drain / source terminal of each access transistor 200 can be electrically connected to a variable resistance device 100, and the other drain / source terminal can be electrically connected to a source line SL. It can be seen from this that one terminal of each variable resistance device 100 can be electrically connected to a drain / source terminal of the corresponding access transistor 200, and the other terminal can be electrically connected to the corresponding bit line BL. In other words, the switch of each access transistor 200 can determine the potential of one terminal of the corresponding variable resistance device 100, thereby affecting the bias voltage between the two terminals of the corresponding variable resistance device 100. Therefore, each access transistor 200 can be used to control the access of the variable resistance device 100 electrically connected thereto. Figure 1A In Figure 1A , the word line WL and the source line SL shown extend in the X direction, and the bit line BL extends in the Y direction. However, those of ordinary skill in the art can change the configuration directions of the word line WL, the source line SL, and the bit line BL according to design and process requirements. The word line WL, the source line SL, and the bit line BL can extend in the X direction or the Y direction respectively, and the present invention is not limited to the configuration directions of these signal lines.

[0034] Please refer to Figure 1A and Figure 1B, the access transistors 200 of each memory cell MC can be formed on the surface region of a substrate 202. The substrate 202 can be a semiconductor chip or a semiconductor-on-insulator (SOI) chip. Each access transistor 200 can include a gate structure 204 disposed on the substrate 202. The gate structure 204 can include a gate electrode 206 and a gate dielectric layer 208 located between the gate electrode 206 and the substrate 202. The gate electrode 206 can be a part of the word line WL described with reference to Figure 1A . In some embodiments, the interface where the gate structure 204 contacts the substrate 202 is a substantially flat surface. In these embodiments, the access transistor 200 can be a planar type field effect transistor (planar type FET). In alternative embodiments, the surface of the substrate 202 can be patterned into fin structures, or multiple channel structures separated from each other in the vertical direction can be formed on the surface of the substrate 202. In these alternative embodiments, the gate structure 204 can be staggered with the above-mentioned fin structures or channel structures and cover multiple surfaces of the above-mentioned fin structures or channel structures, and the access transistor 200 can be referred to as a fin type field effect transistor (fin type FET, fin-FET) or a gate-all-around FET (GAAFET). In addition, each access transistor 200 further includes drain / source structures 210 and drain / source structures 212 disposed on opposite sides of the gate structure 204. In some embodiments, the drain / source structures 210 and the drain / source structures 212 are doped regions disposed in the surface region of the substrate 202. In other embodiments, the drain / source structures 210 and the drain / source structures 212 can also be epitaxial structures disposed in surface depressions of the substrate 202, or epitaxial structures disposed on the substrate 202.

[0035] In some embodiments, each memory cell MC further includes contact plugs CP respectively standing on the drain / source structure 210 and the drain / source structure 212, and includes a back-end-of-line (BEOL) structure 214 located on the contact plugs CP and electrically connected to the contact plugs CP. The BEOL structure 214 includes multiple metallization layers (for example, including metallization layer M1, metallization layer M2, metallization layer M3, and metallization layer M4), and includes vias located between vertically adjacent metallization layers and electrically connecting these metallization layers (for example, via V1 located between metallization layer M1 and metallization layer M2 and via V2 located between metallization layer M2 and metallization layer M3). In addition, the variable resistance device 100 can be embedded in the BEOL structure 214. The bottommost metallization layer (for example, metallization layer M1) can be electrically connected to the contact plug CP. In some embodiments, a part of the metal layer M1, the metal layer M2, and the via V1 can be electrically connected to a drain / source structure (for example, drain / source structure 210) of the access transistor 200 via a contact plug CP, and this part of the metal layer M2 can be the part of the source line SL described in Figure 1A On the other hand, another part of the metal layer M1, the metal layer M2, and the via V1, as well as the metal layer M3, the metal layer M4, and the via V2 can be electrically connected to another drain / source structure (for example, drain / source structure 212) of the access transistor 200 via another contact plug CP. In addition, the variable resistance device 100 can be disposed between the metallization layer M3 and the metallization layer M4 and electrically connected to the metallization layer M3 and the metallization layer M4. In this way, the variable resistance device 100 can be electrically connected to a drain / source structure (for example, drain / source structure 212) of the access transistor 200 via the underlying metallization layers and vias (for example, a part of the metallization layer M1, the metallization layer M2, and the via V1, and the via V2 and the metallization layer M3). At this time, the metallization layer M4 located above the variable resistance device 100 can be the part of the bit line BL described in Figure 1A However, those of ordinary skill in the art can set more or fewer metallization layers and vias according to process and / or design requirements, and can also adjust the setting position of the variable resistance device 100. The present invention is not limited to the number of layers of the BEOL structure 214 and the position of the variable resistance device 100.

[0036] Please refer to Figure 1B and Figure 1C, each variable resistor device 100 includes a variable resistance layer 102. In the initial state (unwritten state), the variable resistance layer 102 may exhibit insulating characteristics, i.e., a high resistance state. During a write operation, by adjusting the bias voltage between the upper and lower ends of the variable resistance layer 102, a conductive channel (not shown), or a conductive filament, can be formed in the variable resistance layer 102. This conductive channel can extend from the bottom surface of the variable resistance layer 102 to the top surface of the variable resistance layer 102. In this way, the resistance between the upper and lower ends of the variable resistance layer 102 is reduced, and the variable resistance layer 102 exhibits a low resistance state. On the other hand, during an erase operation, a reverse bias voltage (a bias voltage opposite to the bias voltage applied during the write operation) can be applied to the upper and lower ends of the variable resistance layer 102 to truncate or eliminate the previously formed conductive channel. In this way, the variable resistance layer 102 can again exhibit a high resistance state. The formation and truncation / elimination of the conductive channel may be related to the movement of oxygen vacancies in the variable resistance layer 102, and the bias voltage between the upper and lower ends of the variable resistance layer 102 can control the movement of oxygen vacancies. That is to say, the conductive channel may be formed due to the aggregation of oxygen vacancies. On the other hand, the conductive channel may be truncated or eliminated due to the dispersion of oxygen vacancies. In addition, the stress borne by the variable resistance layer 102 may also affect the movement of oxygen vacancies. In some embodiments, the variable resistance layer 102 bears compressive stress and generates compressive strain. In these embodiments, the compressive stress / compressive strain is beneficial to the movement of oxygen vacancies, so that the write operation and the erase operation can be performed by applying a lower voltage. In addition, this compressive stress / compressive strain can cause the conductive channel to be formed or truncated / eliminated in a shorter time, and can accelerate the write operation and the erase operation. The variable resistance layer 102 can be a single-layer or multi-layer structure, and the material of the variable resistance layer 102 can be, for example, including tantalum oxide, hafnium oxide, titanium oxide, the like or a combination thereof.

[0037] Each variable resistor device 100 further includes an upper electrode 104 and a lower electrode 106. The upper electrode 104 is located above the variable resistance layer 102, and the lower electrode 106 is located below the variable resistance layer 102. By controlling the voltages of the upper electrode 104 and the lower electrode 106, the bias voltages at the upper and lower ends of the variable resistance layer 102 can be adjusted to switch the resistance state of the variable resistance layer 102. Furthermore, the upper electrode 104 and / or the lower electrode 106 are configured to apply a stress field to the variable resistance layer 102 so that the variable resistance layer 102 is subjected to compressive stress (generating compressive strain). In this way, the voltages required for write operations and erase operations on the variable resistance layer 102 can be reduced. In some embodiments, the upper electrode 104 is formed to have compressive stress and applies a stress field SF104 from top to bottom to the variable resistance layer 102. This stress field SF104 can cause the variable resistance layer 102 to be subjected to compressive stress (generating compressive strain). For example, the compressive stress of the upper electrode 104 can be in the range of about -50 MPa to about -1000 MPa. On the other hand, in some embodiments, the lower electrode 106 is formed to have tensile stress and applies a stress field SF106 from bottom to top to the variable resistance layer 102. Similar to the stress field SF104, the stress field SF106 can also cause compressive stress / compressive strain in the variable resistance layer 102. For example, the tensile stress of the lower electrode 106 can be in the range of about 50 MPa to about 1000 MPa. In Figure 1C In the illustrated embodiment, the upper electrode 104 and the lower electrode 106 are configured to apply the stress field SF104 and the stress field SF106 toward the variable resistance layer 102. However, in an alternative embodiment, only one of the upper electrode 104 and the lower electrode 106 is configured to apply a stress field toward the variable resistance layer 102 (i.e., the stress field SF104 or the stress field SF106), and the other can be in a substantially stress-free state. For example, the stress-free described herein means that the absolute value of the stress in the film layer can be less than about 50 MPa. The upper electrode 104 and the lower electrode 106 can be respectively composed of a conductive material. For example, the conductive material can include titanium nitride, tantalum nitride, tantalum, the like or a combination thereof.

[0038] In some embodiments, each variable resistor device 100 further includes an interfacial layer 108. The interfacial layer 108 is disposed between the upper electrode 104 and the variable resistance layer 102. Alternatively, the upper electrode 104 and the interfacial layer 108 can be collectively referred to as a composite upper electrode. The interfacial layer 108 can be composed of an inert metal (such as ruthenium (Ru)) and can be used to prevent oxygen vacancies from being trapped at the interface between the upper electrode 104 and the variable resistance layer 102. The problem of the trapped oxygen vacancies may cause variations in the voltages used for write operations / erase operations.

[0039] Please refer to Figure 1C and Figure 1D , in some embodiments, each variable resistor device 100 further includes a capping layer 110. In some embodiments, the capping layer 110 is formed as a wall structure that laterally surrounds the stacked structure composed of the upper electrode 104, the variable resistor layer 102, and the lower electrode 106 (or the upper electrode 104, the interface layer 108, the variable resistor layer 102, and the lower electrode 106). In other words, the capping layer 110 can laterally contact the upper electrode 104, the variable resistor layer 102, and the lower electrode 106 (or laterally contact the upper electrode 104, the interface layer 108, the variable resistor layer 102, and the lower electrode 106). Furthermore, the capping layer 110 can be configured to apply a stress field toward the variable resistor layer 102, so that the variable resistor layer 102 bears additional compressive stress (generating additional compressive strain). In some embodiments, the capping layer 110 is formed with compressive stress, and applies a stress field SF110 that points from the periphery of the variable resistor layer 102 inward toward the variable resistor layer 102. Similar to the stress field SF104 and the stress field SF106, the stress field SF110 can also cause compressive stress / compressive strain in the variable resistor layer 102. In embodiments where the upper electrode 104, the lower electrode 106, and the capping layer 110 all apply stress fields (i.e., the stress field SF104, the stress field SF106, and the stress field SF110) toward the variable resistor layer 102, the variable resistor layer 102 can be regarded as being disposed in a stress cage, and the compressive stress / compressive strain borne by the variable resistor layer 102 can be maximized. In alternative embodiments, the capping layer 110 can also be formed in a stress-free state, and this stress-free state means that the absolute value of the stress in the capping layer 110 is less than about 50 MPa. The capping layer 110 can be composed of an insulating material. For example, this insulating material can include silicon nitride or aluminum nitride.

[0040] In some embodiments, each variable resistor device 100 further includes an upper vias 112 and a lower vias 114. The upper vias 112 can stand on the top surface of the upper electrode 104 and electrically connect the upper electrode 104 to the upper metallization layer (such as the metallization layer M4 described with reference to Figure 1B ). On the other hand, the lower vias 114 can be disposed below the lower electrode 106 and electrically connect the lower electrode 106 to the lower metallization layer (such as the metallization layer M3 described with reference to Figure 1B ). The upper vias 112 and the lower vias 114 can be composed of a conductor material. For example, this conductor material can include aluminum, copper, aluminum-copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, the like, or a combination thereof. Additionally, it should be noted that Figure 1D the upper vias 112 are omitted in the top view schematic diagram shown.

[0041] In some embodiments, each variable resistor device 100 is disposed in the dielectric layer stack 116. For example, the dielectric layer stack 116 may include a dielectric layer 118, a dielectric layer 120, and a dielectric layer 122. The dielectric layer 118 laterally surrounds the stacked structure composed of the upper electrode 104, the variable resistor layer 102, and the lower electrode 106 (or the upper electrode 104, the interface layer 108, the variable resistor layer 102, and the lower electrode 106). In embodiments where the capping layer 110 is provided to laterally surround this stacked structure, the dielectric layer 118 laterally contacts this stacked structure through the capping layer 110. On the other hand, the dielectric layer 120 and the dielectric layer 122 may be disposed above and below the dielectric layer 118, respectively. In embodiments where the upper vias 112 and the lower vias 114 are provided, the dielectric layer 120 may laterally surround the upper vias 112, and the dielectric layer 122 may laterally surround the lower vias 114. Each dielectric layer may be composed of a dielectric material. For example, this dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof.

[0042] As described above, the variable resistor layer 102 is subjected to compressive stress (generating compressive strain) due to the stress field generated by one or more of the upper electrode 104, the lower electrode 106, and the capping layer 110. This compressive stress / compressive strain may be beneficial for forming a conductive channel in the variable resistor layer 102 and truncating or eliminating the above-mentioned conductive channel in the variable resistor layer 102. In this way, write and erase operations can be performed at a lower operating voltage. Furthermore, write and erase operations can be performed in a shorter time. Therefore, the power consumption of the memory integrated circuit 10 can be reduced, and the operating speed of the memory integrated circuit 10 can be increased.

[0043] Figure 2 is for manufacturing according to some embodiments Figure 1C The manufacturing flow chart of the illustrated variable resistor device 100. Figures 3A to 3J is a cross-sectional schematic diagram of the intermediate structure at each stage during the above manufacturing process.

[0044] Please refer to Figure 2 and Figure 3A , perform step S200 to form the lower vias 114 in the device substrate 300. The topmost layer of the device substrate 300 may be the dielectric layer 122 as described with reference to Figure 1C Although not shown, the device substrate 300 may further include as described with reference to Figure 1BThe access transistor 200, conductive plug CP, and the lower part of the BEOL structure 214 (e.g., the part below the metallization layer M3) as described. In some embodiments, the lower vias 114 are formed by a damascene process. This damascene process may include forming a perforation in the dielectric layer 122 by a lithography process and an etching process (e.g., an anisotropic etching process), and forming the lower vias 114 in the perforation by a deposition process (e.g., a physical vapor deposition process), a plating process, or a combination thereof and a planarization process. For example, the planarization process may include a grinding process, an etching process, or a combination thereof.

[0045] Please refer to Figure 2 and Figure 3B , perform step S202 to form a lower electrode layer 302 on the device substrate 300. The lower electrode layer 302 may then be patterned to form the lower electrode 106 as described with reference to Figure 1C . In some embodiments, the lower electrode layer 302 is formed to have a tensile stress. In these embodiments, the lower electrode layer 302 may be formed by a physical vapor deposition process. In addition, this physical vapor deposition process may use a radio frequency alternating current power supply plus a direct current power supply. By adjusting the power of the radio frequency alternating current power supply, the direct current power supply, and / or other process parameters, the tensile stress value of the deposited lower electrode layer 302 can be adjusted.

[0046] Please refer to Figure 2 and Figure 3C , perform step S204 to form a variable resistance material layer 304 and an interface material layer 306 on the lower electrode layer 302. The variable resistance material layer 304 may be patterned in a subsequent step to form the variable resistance layer 102 as described with reference to Figure 1C , and the interface material layer 306 may be patterned in a subsequent step to form the interface layer 108 as described with reference to Figure 1C . In some embodiments, the variable resistance material layer 304 is a single-layer or multi-layer structure, and the variable resistance material layer 304 is formed by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or a combination thereof. In addition, in some embodiments, the interface material layer 306 is formed by a physical vapor deposition process or an atomic layer deposition process.

[0047] Please refer to Figure 2 and Figure 3D , perform step S206 to form an upper electrode layer 308 on the interface material layer 306. The upper electrode layer 308 may then be patterned to form as described with reference to Figure 1CThe upper electrode 104 described above. In some embodiments, the upper electrode layer 308 is formed to have compressive stress. In these embodiments, the upper electrode layer 308 can be formed by a physical vapor deposition process. In addition, this physical vapor deposition process can use a DC power supply and turn off the RF AC power supply. By adjusting the power of the DC power supply and / or other process parameters, the compressive stress value of the deposited upper electrode layer 308 can be adjusted.

[0048] Please refer to Figure 2 and Figure 3E , perform step S208 to form a hard mask 310 on the upper electrode layer 308. The hard mask 310 will be used as a mask in the subsequent etching process for patterning the upper electrode layer 308 to define the profile of the formed upper electrode 104. The material of the hard mask 310 can be, for example, silicon oxide. In addition, in some embodiments, the method of forming the hard mask 310 includes forming a hard mask layer on the upper electrode layer 308 by a deposition process (such as a chemical vapor deposition process), and then patterning this hard mask layer by a photolithography process and an etching process to form the hard mask 310.

[0049] Please refer to Figure 2 and Figure 3F , perform step S210 to pattern the upper electrode layer 308 using the hard mask 310 as a mask. At this time, the upper electrode layer 308 is patterned to form the upper electrode 104 as described in reference to Figure 1C . In some embodiments, some portions of the upper electrode layer 308 are removed by an etching process (such as an anisotropic etching process) to pattern the upper electrode layer 308 into the upper electrode 104. In this etching process, the interface material layer 306 can be used as an etch stop layer. In addition, after completing this etching process, the hard mask 310 can be removed. For example, the hard mask 310 can be removed by an isotropic etching process.

[0050] Please refer to Figure 2 and Figure 3G , perform step S212 to pattern the interface material layer 306, the variable resistance material layer 304, and the lower electrode layer 302 using the upper electrode 104 as a mask. At this time, the interface material layer 306, the variable resistance material layer 304, and the lower electrode layer 302 are respectively patterned to form as described in reference to Figure 1CThe described interface layer 108, variable resistance layer 102, and lower electrode 106. In some embodiments, some portions of the interface material layer 306, variable resistance material layer 304, and lower electrode layer 302 are removed by an etching process (e.g., an anisotropic etching process), and the interface material layer 306, variable resistance material layer 304, and lower electrode layer 302 are patterned into the interface layer 108, variable resistance layer 102, and lower electrode 106, respectively. In some embodiments, the exposed surface portion of the dielectric layer 122 is removed during the above etching process. In these embodiments, the exposed portion of the dielectric layer 122 may be recessed downward relative to the shielded portion.

[0051] Please refer to Figure 2 and Figure 3H , perform step S214 to form a conformally coated covering material layer 312 on the current structure. The covering material layer 312 can conformally cover the Figure 3G structure shown, and can then be patterned to form the covering layer 110 as described with reference to Figure 1C . In some embodiments, the covering material layer 312 is formed to have a compressive stress. In these embodiments, the covering material layer 312 can be formed by a chemical vapor deposition process. Additionally, this chemical vapor deposition process can use a radio frequency alternating current power source and a direct current power source. By adjusting the power of the radio frequency alternating current power source, direct current power source, and / or other process parameters, the compressive stress value of the deposited covering material layer 312 can be adjusted. In these embodiments, an ion implantation process may not be necessary for the covering material layer 312, so the upper electrode 104, interface layer 108, variable resistance layer 102, and lower electrode 106 covered by the covering material layer 312 can be avoided from being ion-damaged. However, in alternative embodiments, the internal stress of the covering material layer 312 can also be adjusted by an ion implantation process.

[0052] Please refer to Figure 2 and Figure 3I , perform step S216 to pattern the covering material layer 312 to form the covering layer 110 as described with reference to Figure 1C and Figure 1D . In some embodiments, some horizontally extending portions of the covering material layer 312 are removed by an anisotropic etching process. The longitudinally extending portions of the covering material layer 312 covering the sidewalls of the upper electrode 104, interface layer 108, variable resistance layer 102, and lower electrode 106 can be retained to form the covering layer 110 as described with reference to Figure 1C and Figure 1D . In these embodiments, it is possible to remove the exposed surface portion of the dielectric layer 122 so that this surface portion is recessed downward relative to the shielded portion.

[0053] Please refer to Figure 2 and Figure 3J, perform step S218 to form a dielectric layer 118 that laterally surrounds and covers the dielectric layer 110 on the device substrate 300. In some embodiments, the method of forming the dielectric layer 118 includes forming a dielectric material layer that comprehensively covers the structure shown by chemical vapor deposition (CVD) or other deposition processes, and removing the portions of the dielectric material layer located on the top surfaces of the upper electrode 104 and the covering layer 110 through a planarization process. The remaining portion of the dielectric material layer forms the dielectric layer 118, and at this time, the top surfaces of the upper electrode 104 and the covering layer 110 are exposed. For example, the planarization process may include a grinding process, an etching process, or a combination thereof. Figure 3I The dielectric material layer of the structure shown, and includes removing the portions of this dielectric material layer located on the top surfaces of the upper electrode 104 and the covering layer 110 through a planarization process. The remaining portion of the dielectric material layer forms the dielectric layer 118, and at this time, the top surfaces of the upper electrode 104 and the covering layer 110 are exposed. For example, the planarization process may include a grinding process, an etching process, or a combination thereof.

[0054] Please refer to Figure 2 and Figure 1C , perform step S220 to form a dielectric layer 120 and an upper via 112. In some embodiments, initially, a dielectric layer 120 that comprehensively coats the structure shown is formed through a deposition process (such as chemical vapor deposition), and then vias are formed in the dielectric layer 120 through a damascene process and upper vias 112 are formed in these vias. In these embodiments, the damascene process may include forming the above-mentioned vias in the dielectric layer 120 through photolithography and etching processes (such as anisotropic etching processes), and forming the upper vias 112 in these vias through a deposition process (such as physical vapor deposition), plating process, or a combination thereof, and a planarization process. For example, the planarization process may include a grinding process, an etching process, or a combination thereof. Figure 3J The dielectric layer 120 of the structure shown, and then vias are formed in the dielectric layer 120 through a damascene process and upper vias 112 are formed in these vias. In these embodiments, the damascene process may include forming the above-mentioned vias in the dielectric layer 120 through photolithography and etching processes (such as anisotropic etching processes), and forming the upper vias 112 in these vias through a deposition process (such as physical vapor deposition), plating process, or a combination thereof, and a planarization process. For example, the planarization process may include a grinding process, an etching process, or a combination thereof.

[0055] So far, the manufacturing of the variable resistance device 100 as shown in Figure 1C has been completed. In addition, further processes can be performed on the current structure to complete the BEOL structure 214 described with reference to Figure 1B .

[0056] Figure 4 is a cross-sectional schematic view of a variable resistance device 100a according to some embodiments of the present invention. Figure 4 The variable resistance device 100a shown is similar to the variable resistance device 100 shown in Figure 1C . Only the differences between the variable resistance devices 100 and 100a are described below, and the same or similar parts will not be repeated. In addition, similar device symbols represent similar devices (for example, the covering layer 110 shown in Figure 1C and the covering layer 110a shown in Figure 4 ).

[0057] Please refer to Figure 4, in some embodiments, the capping layer 110a having a compressive stress further covers the top surface of the upper electrode 104 and extends more substantially horizontally on the top surface of the dielectric layer 122. In this way, the capping layer 110a can provide a stress field SF110a pointing to the variable resistance layer 102 both in the transverse and longitudinal directions. Therefore, the variable resistance layer 102 can be subjected to a greater compressive stress (generating a greater compressive strain), and the operating voltage for performing write / erase operations on the variable resistance device 100a can be further reduced. In these embodiments, the top surface of the dielectric layer 118 can be substantially coplanar with the topmost surface of the capping layer 110a. In addition, the upper vias 112a can further pass through the portion of the capping layer 110a covering the top surface of the upper electrode 104 to establish an electrical connection with the upper electrode 104.

[0058] The manufacturing method of the variable resistance device 100a is similar to that of the variable resistance device 100 described with reference to Figure 2 and Figures 3A to 3I , Figure 1C The manufacturing method of the variable resistance device 100a can omit the steps described with reference to Figure 3I That is, the capping material layer 312 described with reference to Figure 3H may not be patterned, and the capping material layer 312 is the capping layer 110a described with reference to Figure 4 In addition, forming the perforations for accommodating the upper vias 112 not only passes through the dielectric layer 120, but can further pass through the capping layer 110a to expose the upper electrode 104.

[0059] In summary, the memory integrated circuit of the present invention can be a resistive memory integrated circuit, and the variable resistance layer in the variable resistance device of the storage unit is subjected to a compressive stress (generating a compressive strain) by the stress field generated by the surrounding film layers. Specifically, at least one of the upper electrode and the lower electrode above and below the variable resistance layer can be configured to generate a stress field toward the variable resistance layer, so that the variable resistance layer is subjected to a compressive stress (generating a compressive strain). In addition, the capping layer that at least covers the sidewalls of the variable resistance layer can also be selectively configured to generate a stress field pointing from the outside of the variable resistance layer inward to the variable resistance layer to further increase the compressive stress (increase the generated compressive strain) borne by the variable resistance layer. The above-mentioned compressive stress / compressive strain is beneficial to forming a conductive channel in the variable resistance layer and truncating or eliminating the above-mentioned conductive channel in the variable resistance layer. In this way, write and erase operations can be performed on the variable resistance device with a lower operating voltage. Furthermore, the write and erase operations can be performed in a shorter time. Therefore, the power consumption of the memory integrated circuit can be reduced, and the operating speed of the memory integrated circuit can be increased.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory device, characterized in that, Comprising: A device substrate; A lower electrode disposed on the device substrate; A variable resistance layer disposed on the lower electrode; And An upper electrode disposed on the variable resistance layer, Wherein the lower electrode is formed to have tensile stress, and the upper electrode is formed to have compressive stress, and the lower electrode and the upper electrode respectively provide stress fields toward the variable resistance layer, and Wherein the variable resistance layer bears compressive stress corresponding to the stress fields provided by the lower electrode and the upper electrode, and the bias voltage between the upper and lower ends of the variable resistance layer can control the movement of oxygen vacancies.

2. The memory device according to claim 1, wherein The lower electrode and the upper electrode are formed of the same conductive material.

3. The memory device according to claim 1, wherein, The materials of the lower electrode and the upper electrode respectively include titanium nitride, tantalum nitride, tantalum, or a combination thereof.

4. The memory device according to claim 1, wherein Further comprising: A cover layer covering the sidewalls of the lower electrode, the variable resistance layer, and the upper electrode, and formed to have compressive stress.

5. The memory device according to claim 4, wherein The lower electrode, the upper electrode, and the cover layer respectively provide stress fields toward the variable resistance layer, and the variable resistance layer bears compressive stress corresponding to the application of the stress fields.

6. The memory device according to claim 4, wherein The cover layer is formed into a wall structure that laterally surrounds the lower electrode, the variable resistance layer, and the upper electrode.

7. The memory device according to claim 4, wherein The cover layer laterally surrounds the lower electrode, the variable resistance layer, and the upper electrode, and further covers the top surface of the upper electrode.

8. The memory device according to claim 4, wherein, The material of the cover layer includes silicon nitride, aluminum nitride, or a combination thereof.

9. A memory device, characterized in that, Comprising: A lower electrode having a first stress and an upper electrode having a second stress, formed in a back-end process structure located on a semiconductor substrate, wherein the upper electrode is located on the lower electrode and overlaps the lower electrode; And A variable resistance layer sandwiched between the lower electrode and the upper electrode, and generating compressive strain corresponding to the first stress of the lower electrode and the second stress of the upper electrode, wherein the lower electrode and the upper electrode respectively provide stress fields toward the variable resistance layer, and the bias voltage between the upper and lower ends of the variable resistance layer can control the movement of oxygen vacancies.

10. The memory device according to claim 9, wherein Further comprising: A stress layer covering the sidewalls of the upper electrode, the variable resistance layer, and the lower electrode, and formed to have a third stress.

11. The memory device according to claim 10, wherein, The variable resistance layer further generates compressive strain corresponding to the third stress of the stress layer.

12. A method for manufacturing a memory device, characterized in that, Comprising: Sequentially forming a lower electrode layer, a variable resistance material layer, an upper electrode layer, and a hard mask layer on a device substrate, wherein the lower electrode layer is formed to have tensile stress, and the upper electrode layer is formed to have compressive stress; Patterning the hard mask layer to form a hard mask; Removing some parts of the upper electrode layer, the variable resistance material layer, and the lower electrode layer by using the hard mask as a mask to respectively form an upper electrode, a variable resistance layer, and a lower electrode; And Removing the hard mask, the lower electrode and the upper electrode respectively provide stress fields toward the variable resistance layer, and Wherein the variable resistance layer bears compressive stress corresponding to the stress fields provided by the lower electrode and the upper electrode, and the bias voltage between the upper and lower ends of the variable resistance layer can control the movement of oxygen vacancies.

13. The manufacturing method of the memory device according to claim 12, wherein, The lower electrode layer is formed by a physical vapor deposition process using a radio frequency alternating current power source and a direct current power source, and the upper electrode layer is formed by a physical vapor deposition process using a direct current power source.

14. The method for manufacturing a memory device according to claim 12, wherein, Further comprising: After removing the hard mask, a capping material layer covering the exposed surfaces of the upper electrode, the variable resistance layer, and the lower electrode is formed, wherein the capping material layer is formed to have a compressive stress.

15. The method of manufacturing a memory device according to claim 14, further comprising: After forming the capping material layer, an anisotropic etching process is performed on the capping material layer to remove a part of the capping material layer covering the top surface of the upper electrode.

16. The manufacturing method of the memory device according to claim 14, characterized in that, The capping material layer does not undergo an ion implantation process.

17. The method for manufacturing a memory device according to claim 14, wherein, The capping material layer is formed by a chemical vapor deposition process using a radio frequency alternating current power source and a direct current power source.

18. The manufacturing method of the memory device according to claim 12, characterized in that, Some portions of the upper electrode layer, the variable resistance material layer, and the lower electrode layer are removed by multiple anisotropic etching processes to respectively form the upper electrode, the variable resistance layer, and the lower electrode.

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