An ultra-low voltage start-up assist circuit for high performance power management

Abstract

The application discloses an ultra-low voltage starting auxiliary circuit for high-performance power management, which comprises a low-voltage starting auxiliary circuit for driving a P-type power tube and a low-voltage starting auxiliary circuit for driving an N-type power tube; the application utilizes the charge storage characteristics of a capacitor to generate two auxiliary voltages, and can drive the P-type power tube and the N-type power tube to make the output voltage rise so as to start various modules of a converter when the power supply voltage of a power management circuit is small, especially in a BOOST type DCDC converter requiring ultra-low voltage starting.

Description

Technical Field

[0001] This invention belongs to the field of power management, and specifically relates to an ultra-low voltage startup auxiliary circuit for high-performance power management, which is mainly used in Boost DC / DC converters that require low voltage startup. Background Technology

[0002] Ultra-low voltage startup auxiliary circuits for high-performance power management are startup circuits composed of a ring oscillator and a charge pump. When the power supply voltage is extremely low, the chip cannot start automatically and requires an auxiliary circuit to start. With the continuous development of portable devices that rely on lithium batteries for power supply, the limited capacity of lithium batteries restricts the application of portable devices, and the role of low-voltage startup circuits in power chips is becoming increasingly important. Ultra-low voltage startup auxiliary circuits for high-performance power management are used in integrated circuit chips due to their ease of implementation, high integration, and small chip area. Summary of the Invention

[0003] Based on the charge storage characteristics of capacitors, an ultra-low voltage startup auxiliary circuit for high-performance power management is designed. This circuit can generate a negative voltage and a multiplier voltage when the power supply voltage is very low, which are used to drive the P-type power transistor and the N-type power transistor respectively, thereby realizing the self-starting of the power management circuit.

[0004] The technical solution of this invention is implemented as follows:

[0005] An ultra-low voltage startup auxiliary circuit for high-performance power management comprises two circuits: one generates a negative voltage to drive a P-type power transistor MP0, and the other generates a multiplier voltage to drive an N-type power transistor MN0. The circuit generating the negative voltage to drive the P-type power transistor MP0 includes a low-voltage clock generation circuit and a negative voltage generation circuit. The low-voltage clock circuit consists of a first-stage inverter, inverters INV1 and INV2, a NAND gate NAND2_1, a final-stage inverter, resistor R1, capacitor C1, and a P-type MOSFET MP3. The first-stage inverter consists of P-type MOSFET MP1 and N-type MOSFET MN1, and the final-stage inverter consists of P-type MOSFET MP2 and N-type MOSFET MN2. The negative voltage generation circuit consists of N-type MOSFETs MN3 and MN4 and capacitor C2. The circuit generating the multiplier voltage to drive the N-type power transistor MN0 includes both a low-voltage clock generation circuit and a multiplier voltage generation circuit. The low-voltage clock circuit consists of a first-stage inverter, inverters INV3 and INV4, a NAND gate NAND2_2, a final-stage inverter, resistor R2, capacitor C3, and a P-type MOSFET MP4. The first-stage inverter is composed of a P-type MOSFET MP5 and an N-type MOSFET MN5, and the final-stage inverter is composed of a P-type MOSFET MP6 and an N-type MOSFET MN6. The voltage multiplication circuit consists of P-type MOSFETs MP7, MP8, MP9, and MP10, and capacitors C4, C5, and C6.

[0006] The auxiliary circuit for generating negative voltage to drive the P-type power transistor MP0 includes a low-voltage clock generation circuit and a negative voltage generation circuit. The low-voltage clock circuit consists of a first-stage inverter, inverter INV1, NAND gate NAND2_1, inverter INV2, a final-stage inverter, resistor R1, capacitor C1, and a P-type MOSFET MP3. The first-stage inverter is composed of a P-type MOSFET MP1 and an N-type MOSFET MN1. The gate of P-type MOSFET MP1 is connected to the gate of N-type MOSFET MN1, and the drain of MP1 is connected to the drain of MN1 and then to the input terminal of inverter INV1. The drain of P-type MOSFET MP3 is connected to the input terminal of inverter INV1, and the gate of P-type MOSFET MP3 is connected to the output terminal of inverter INV1. The output terminal of inverter INV1 is connected to terminal B of the two-input NAND gate NAND2_1, and terminal A is the circuit's enable signal EN_P. The output of the two-input NAND gate NAND2_1 is the clock signal CLKN_P, which is connected to the input of inverter INV2. The output of inverter INV2 is the clock signal CLK_P, which is connected to the gate of the P-type MOSFET MP2 and the gate of the N-type MOSFET MN2 in the last stage inverter. The drain of the gate of P-type MOSFET MP2 is connected to the drain of N-type MOSFET MN2, and then connected to resistor R1. The other end of resistor R1 is connected to capacitor C1, and then connected to the gate of the P-type MOSFET PM1 and the gate of the N-type MOSFET MN1 in the first stage inverter. The other end of capacitor C1 is grounded. The negative voltage generation circuit consists of N-type MOSFETs MN3 and MN4 and capacitor C2. The gate of N-type MOSFET MN3 is connected to the clock signal CLKN_P, and its drain is the output terminal PGATE. The source of N-type MOSFET MN3 is connected to the drain of N-type MOSFET MN4, and then connected to one end X of capacitor C2. The other end of capacitor C2 is connected to the clock output signal CLK_P. The gate of the N-type MOSFET MN4 is connected to the clock signal CLKN, and the source is grounded.

[0007] Assume the power supply voltage of SW is VDD. When the clock signal CLK_P is high, the N-type MOSFET MN4 is turned on, one end of capacitor C2 is grounded at point X, and the other end is connected to CLK_P when it is high (VDD). The total charge stored in the capacitor when it is fully charged is:

[0008] Q = C * VDD

[0009] Where C is the capacitance of capacitor C2, and VDD is the clock high-level voltage value.

[0010] When the clock signal CLKN_P is high, the N-type MOS transistor MN3 is turned on. Since the total charge on capacitor C2 remains unchanged, when one end of capacitor C2 is connected to CLK_P at a low level, the voltage at point X on the other end is -VDD. Therefore, the value of the output voltage PGATE is the voltage value at point X, which is -VDD.

[0011] The auxiliary circuit for generating a multiplier voltage to drive the N-type power transistor MN0 includes a low-voltage clock generation circuit and a multiplier voltage generation circuit. The low-voltage clock circuit consists of a first-stage inverter, inverter INV3, NAND gate NAND2_2, inverter INV4, a final-stage inverter, resistor R21, capacitor C3, and P-type MOSFET MP4. The first-stage inverter is composed of P-type MOSFET MP5 and N-type MOSFET MN5. The gate of P-type MOSFET MP5 is connected to the gate of N-type MOSFET MN5, and the drain of MP5 is connected to the drain of MN5 and then to the input terminal of inverter INV3. The drain of P-type MOSFET MP4 is connected to the input terminal of inverter INV2, and its gate is connected to the output terminal of inverter INV2. The output terminal of inverter INV2 is connected to terminal B of the two-input NAND gate NAND2_2, and terminal A is the circuit's enable signal EN_N. The output of the two-input NAND gate NAND2_2 is the clock signal CLKN_N, which is connected to the input of inverter INV4. The output of inverter INV4 is the clock signal CLK_N, which is connected to the gate of the P-type MOSFET MP6 and the gate of the N-type MOSFET MN6 in the last stage inverter. The drain of the P-type MOSFET MP6 is connected to the drain of the N-type MOSFET MN6, and then connected to resistor R2. The other end of resistor R2 is connected to capacitor C3, and then connected to the gate of the P-type MOSFET MP5 and the N-type MOSFET MN5 in the first stage inverter. The other end of capacitor C2 is grounded. The voltage multiplier circuit consists of N-type MOSFETs MP7, MP8, MP9, and MP10, and capacitors C4, C5, and C6. The gate of P-type MOSFET MN7 is connected to the clock signal CLKN_N, and its drain is connected to VOUT. The source of P-type MOSFET MN7 is connected to one end of capacitor C4, and also to the drain of P-type MOSFET MP8 and the gate of P-type MOSFET MP9. This point is Y1. The other end of capacitor C4 is connected to the clock signal CLKN_N. The gate of P-type MOSFET MP8 is connected to the clock signal CLK_N, and its source is connected to the drain of P-type MOSFET MP9. It is also connected to one end of capacitor C5 and the gate of P-type MOSFET MP10. This point is Y2. The drain of P-type MOSFET MP10 is connected to one end of capacitor C6. This point is Y3. The other end of capacitor C6 is connected to the clock signal CLKN_N. The source of P-type MOSFET MP10 is the output point NGATE.

[0012] Let the high voltage of the clock signal be VDD, and the power supply voltage of the power transistor be PVDD. Ideally, PVDD and VDD should have the same value, and the capacitance values ​​of capacitors C4, C5, and C6 should be identical. When the clock signal CLKN_N is low, CLK_N is high, the P-type MOSFET MP7 is turned on, one end of capacitor C4 is connected to CLKN_N and is low, and the other end at point Y1 is charged to the high level VDD. When the clock signal CLKN_N is high, CLK_N is low, the P-type MOSFET MP8 is turned on, the charge in capacitor C4 is discharged to capacitor C5, and the voltage at point Y2 is raised. In the next cycle, when CLKN_N is low, CLK_N is high, PVDD recharges capacitor C4. At this time, because capacitor C4 is discharging and its voltage at one end becomes low, the voltage at point Y1 decreases, the P-type MOSFET MP9 is turned on, and the charge on capacitor C5 is discharged to capacitor C6. This process repeats for several cycles, the voltage at point Y2 gradually decreases, and the voltage at point Y3 gradually increases until the P-type MOSFET MP10 is turned on, and the charge on capacitor C6 charges the parasitic capacitance on NGATE. Whenever CLKN_N is low, and CLK_N is high, PVDD charges capacitor C4, and capacitor C5 charges capacitor C6; when CLKN_N is high, and CLK_N is low, capacitor C4 charges capacitor C5, and capacitor C6 charges the NGATE parasitic capacitance, until the NGATE parasitic capacitance is charged and maintained at the highest value of 2*VDD.

[0013] This invention discloses an ultra-low voltage startup auxiliary circuit for high-performance power management. Utilizing the charge storage characteristics of capacitors, it generates a negative voltage and a multiplier voltage when the power supply voltage is extremely low. The negative voltage drives a P-type power transistor, and the multiplier voltage drives an N-type power transistor, thereby enabling the circuit to self-start even at extremely low power supply voltages. This further reduces the minimum operating voltage of low-voltage domain BOOST DC / DC converters. Attached Figure Description

[0014] Figure 1 It is a negative voltage generation circuit used to drive P-type MOSFETs.

[0015] Figure 2 It is a voltage multiplication circuit used to drive N-type MOSFETs. Detailed Implementation

[0016] Referring to the accompanying drawings, the present invention includes a circuit for generating a negative voltage to drive a P-type power transistor MP0 and a circuit for generating a multiplier voltage to drive an N-type power transistor MN0. The circuit for generating the negative voltage to drive the P-type power transistor MP0 includes a low-voltage clock generation circuit and a negative voltage generation circuit. The low-voltage clock circuit consists of a first-stage inverter, inverters INV1 and INV2, a NAND gate NAND2_1, a last-stage inverter, resistor R1, capacitor C1, and a P-type MOSFET MP3. The first-stage inverter consists of P-type MOSFET MP1 and N-type MOSFET MN1, and the last-stage inverter consists of P-type MOSFET MP2 and N-type MOSFET MN2. The negative voltage generation circuit consists of N-type MOSFETs MN3 and MN4 and capacitor C2. The circuit for generating the multiplier voltage to drive the N-type power transistor MN0 includes a low-voltage clock generation circuit and a multiplier voltage generation circuit. The low-voltage clock circuit consists of a first-stage inverter, inverters INV3 and INV4, a NAND gate NAND2_2, a final-stage inverter, resistor R2, capacitor C3, and a P-type MOSFET MP4. The first-stage inverter is composed of a P-type MOSFET MP5 and an N-type MOSFET MN5, and the final-stage inverter is composed of a P-type MOSFET MP6 and an N-type MOSFET MN6. The voltage multiplication circuit consists of P-type MOSFETs MP7, MP8, MP9, and MP10, and capacitors C4, C5, and C6. The negative voltage generation circuit for driving the P-type MOSFETs includes a low-voltage clock generation circuit and a negative voltage generation circuit. The low-voltage clock signal provides two inverted clock digital logic signals, CLKN_P and CLK_P. CLKN_P and CLK_P serve as input signals to the negative voltage generation circuit, together generating a negative voltage drive signal PGATE that can drive the P-type MOSFETs. Assume the power supply voltage of SW is VDD. When the clock signal CLK_P is high, the N-type MOSFET MN4 is turned on, one end of capacitor C2 (point X) is grounded, and the other end is connected to CLK_P at a high level (VDD). The total charge stored when the capacitor is fully charged is the product of VDD and the capacitance of capacitor C2. When the clock signal CLKN_P is high, the N-type MOSFET MN3 is turned on. Since the total charge on capacitor C2 remains constant, when one end of capacitor C2 is connected to CLK_P at a low level, the voltage at point X is -VDD. Therefore, the output voltage PGATE is the voltage at point X, which is -VDD, a negative voltage.

[0017] The voltage multiplier circuit for driving an N-type MOSFET includes a low-voltage clock generation circuit and a voltage multiplier generation circuit. The low-voltage clock signal provides two inverted clock digital logic signals, CLKN_N and CLK_N. CLKN_N and CLK_N serve as input signals to the voltage multiplier generation circuit, together generating a voltage multiplier drive signal NGATE that can drive the N-type MOSFET. Let the high voltage of the clock signal be VDD, and the power supply voltage of the power transistor be PVDD. Ideally, PVDD and VDD should have the same value, and the capacitance values ​​of capacitors C4, C5, and C6 should be identical. When the clock signal CLKN_N is low, CLK_N is high, the P-type MOSFET MP7 is turned on, one end of capacitor C4 is connected to CLKN_N and is low, and the other end at point Y1 is charged to the high level VDD. When the clock signal CLKN_N is high, CLK_N is low, the P-type MOSFET MP8 is turned on, the charge in capacitor C4 is discharged to capacitor C5, and the voltage at point Y2 is raised. In the next cycle, when CLKN_N is low, CLK_N is high, PVDD recharges capacitor C4. At this time, because capacitor C4 is discharging and its voltage at one end becomes low, the voltage at point Y1 decreases, the P-type MOSFET MP9 is turned on, and the charge on capacitor C5 is discharged to capacitor C6. This process repeats for several cycles, the voltage at point Y2 gradually decreases, and the voltage at point Y3 gradually increases until the P-type MOSFET MP10 is turned on, and the charge on capacitor C6 charges the parasitic capacitance on NGATE. Whenever CLKN_N is low, and CLK_N is high, PVDD charges capacitor C4, and capacitor C5 charges capacitor C6; when CLKN_N is high, and CLK_N is low, capacitor C4 charges capacitor C5, and capacitor C6 charges the NGATE parasitic capacitance, until the NGATE parasitic capacitance is charged and maintained at its highest value of 2*VDD, which is a multiplier of the power supply voltage VDD.

Claims

1. An ultra-low voltage startup auxiliary circuit for high-performance power management, the auxiliary circuit comprising two components: one generating a negative voltage to drive a P-type power transistor MP0, and the other generating a multiplier voltage to drive an N-type power transistor MN0. The circuit generating the negative voltage to drive MP0 includes a low-voltage clock generation circuit and a negative voltage generation circuit; the circuit generating the multiplier voltage to drive MN0 includes a low-voltage clock generation circuit and a multiplier voltage generation circuit. The circuit is characterized in that... The low-voltage clock generation circuit that generates negative voltage to drive MP0 consists of an inverter composed of P-type MOS transistor MP1 and N-type MOS transistor MN1, inverters INV1 and INV2, two-input NAND gate NAND2_1, an inverter composed of P-type MOS transistor MP2 and N-type MOS transistor MN2, resistor R1, capacitor C1, and P-type MOS transistor MP3. The gate of MP1 is connected to the gate of MN1 and to one end of capacitor C1 and one end of resistor R1. The other end of resistor R1 is connected to the drain of MP2 and the drain of MN2. The other end of capacitor C1 is grounded. The sources of MP1, MP3, and MP2 are connected to the external signal SW. The sources of MN1 and MN2 are grounded. The drains of MP1 and MN1 are connected to the input of inverter INV1 and the drain of MP3. The gate of MP3 is connected to the output of inverter INV1 and one input of NAND gate NAND2_1. The other input of NAND2_1 is the enable signal EN_P of the circuit. The output of NAND2_1 is the clock signal CLKN_P and is connected to the input of inverter INV2. The output of inverter INV2 is the clock signal CLK_P and is connected to the gate of MP2 and the gate of MN2. The negative voltage generating circuit consists of N-type MOSFETs MN3 and MN4 and capacitor C2. The gate of MN3 is connected to the clock signal CLKN_P, the drain of MN3 is the output terminal PGATE, the source of MN3 is connected to the drain of MN4 and one end of capacitor C2, i.e., node X, and the other end of capacitor C2 is connected to the clock signal CLK_P and the gate of MN4. The source of MN4 is grounded.

2. The ultra-low voltage startup auxiliary circuit for high-performance power management according to claim 1, characterized in that, Let the voltage of the external signal SW be VDD. When the clock signal CLK_P is high, MN4 is turned on, one end of capacitor C2 is grounded at point X, and the other end is connected to CLK_P at the high level VDD. The total charge stored when the capacitor is fully charged is: Q = C * VDD, where C is the capacitance of capacitor C2 and VDD is the high-level voltage value. When the clock signal CLKN_P is high, MN3 is turned on. Since the total charge on capacitor C2 remains unchanged, when CLK_P is low, the voltage at point X is -VDD. Therefore, the value of the output voltage PGATE is the voltage value at point X -VDD.

3. The ultra-low voltage startup auxiliary circuit for high-performance power management according to claim 1, characterized in that, The low-voltage clock generation circuit that generates the multiplier voltage to drive MN0 consists of an inverter composed of a P-type MOSFET MP5 and an N-type MOSFET MN5, inverters INV3 and INV4, a two-input NAND gate NAND2_2, an inverter composed of a P-type MOSFET MP6 and an N-type MOSFET MN6, resistor R2, capacitor C3, and P-type MOSFET MP4. The gate of MP5 is connected to the gate of MN5 and to one end of capacitor C3 and one end of resistor R2. The other end of resistor R2 is connected to the drain of MP6 and the drain of MN6. The other end of capacitor C3 is grounded. The sources of MP5, MP4, and MP6 are connected to the external signal VDD. The sources of MN5 and MN6 are grounded. The drains of MP5 and MN5 are connected to the input of inverter INV3 and the drain of MP4. The gate of MP4 is connected to the output of inverter INV3 and one input of NAND gate NAND2_2. The other input of NAND2_2 is the enable signal EN_N of the circuit. The output of NAND2_2 is the clock signal CLKN_N and is connected to the input of inverter INV4. The output of inverter INV4 is the clock signal CLK_N and is connected to the gate of MP6 and the gate of MN6. The voltage multiplication circuit consists of P-type MOSFETs MP7, MP8, MP9, and MP10, and capacitors C4, C5, and C6. The gate of MP7 is connected to the clock signal CLKN_N, the drain is connected to the external signal PVDD, and the source is connected to one end of capacitor C4, the drain of MP8, and the gate of MP9. This point is Y1. The other end of capacitor C4 is connected to the clock signal CLKN_N. The gate of MP8 is connected to the clock signal CLK_N. The source of MP8 is connected to the drain of MP9, one end of capacitor C5, and the gate of MP10. This point is Y2. The other end of capacitor C5 is connected to the clock signal CLK_N. The source of MP9 is connected to the drain of MP10 and one end of capacitor C6. This point is Y3. The other end of capacitor C6 is connected to the clock signal CLKN_N. The source of MP10 is the output point NGATE.

4. The ultra-low voltage startup auxiliary circuit for high-performance power management according to claim 3, characterized in that, it is provided that... The clock signal high-level voltage is VDD, and the power transistor supply voltage is PVDD. Ideally, PVDD and VDD have the same value, and the capacitance values ​​of capacitors C4, C5, and C6 are identical. When the clock signal CLKN_N is low, CLK_N is high, MP7 is turned on, and point Y1 is charged to the high level VDD. When the clock signal CLKN_N is high, CLK_N is low, MP8 is turned on, and the charge in capacitor C4 discharges to capacitor C5, raising the voltage at point Y2. In the next cycle, when CLKN_N is low, CLK_N is high, and PVDD recharges capacitor C4. At this time, because capacitor C4 is discharging and its voltage at one end becomes low, the voltage at point Y1 decreases, MP9 is turned on, and the charge in capacitor C5 discharges to capacitor C6. This process repeats for several cycles. The voltage at point Y2 gradually decreases, and the voltage at point Y3 gradually increases until MP10 is turned on. The charge on capacitor C6 charges the parasitic capacitance on NGATE. Whenever CLKN_N is low or high, PVDD charges capacitor C4, and capacitor C5 charges capacitor C6. When CLKN_N is high or low, capacitor C4 charges capacitor C5, and capacitor C6 charges the parasitic capacitance on NGATE, until the parasitic capacitance on NGATE is charged and maintained at the highest value of 2*VDD.

Images