Phase-locked loop based on PID control

Abstract

The present invention discloses a phase-locked loop based on PID control, comprising: a digital phase detector, used to obtain an input signal, and obtain a feedback signal according to an output signal of a numerically controlled oscillator, and obtain a phase difference between the input signal and the feedback signal; a PID controller, connected to the digital phase detector, used to calculate a first difference between the phase difference and a target value, and perform PID control on the first difference to obtain a frequency control word; a numerically controlled oscillator, respectively connected to the digital phase detector and the PID controller, used to obtain an output signal according to the frequency control word. The phase-locked loop based on PID control can improve locking speed and locking accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to a phase-locked loop based on PID (proportional-integral-derivative) control. Background Art

[0002] The phase-locked loop system is a closed-loop feedback control system in which the output signal tracks the input signal. When the output signal is in phase synchronization with the input signal, the phase-locked loop is in a "locked" state. The digital phase-locked loop not only absorbs the advantages of digital circuits such as high reliability and small size, but also solves the shortcomings of analog phase-locked loops such as DC zero drift, device saturation, and susceptibility to power supply and ambient temperature. In addition, it has the ability to process discrete sample values ​​in real time, and has become the development direction of phase-locked technology.

[0003] The phase-locked loop in the related technology is as follows Figure 1 As shown in FIG. 1 , the phase-locked loop (PLL) is mainly composed of three parts: DPD (Digital Phase Detector), DLF (Digital Loop Filter) and NCO (Numerically Controlled Oscillator). However, the phase-locked loop in the related art has problems such as narrow phase-locking range, slow locking speed and poor locking accuracy. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the purpose of the present invention is to propose a phase-locked loop based on PID control to improve the locking speed and locking accuracy of the phase-locked loop.

[0005] To achieve the above-mentioned purpose, an embodiment of the present invention proposes a phase-locked loop based on PID control, including: a digital phase detector, used to obtain an input signal, and obtain a feedback signal according to an output signal of a numerically controlled oscillator, and obtain a phase difference between the input signal and the feedback signal; a PID controller, connected to the digital phase detector, used to calculate a first difference between the phase difference and a target value, and perform PID control on the first difference to obtain a frequency control word; the numerically controlled oscillator, respectively connected to the digital phase detector and the PID controller, used to obtain the output signal according to the frequency control word.

[0006] In the PID-controlled phase-locked loop of the embodiment of the present invention, after the digital phase detector obtains the phase difference between the input signal and the feedback signal, a PID controller is used to calculate the first difference between the phase difference and the target value, and then PID control is performed on the first difference to obtain a frequency control word, so that the digitally controlled oscillator obtains an output signal according to the frequency control word, and the digital phase detector can obtain a feedback signal according to the output signal, thereby improving the locking speed and locking accuracy of the phase-locked loop.

[0007] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the structure of a phase-locked loop in the related art;

[0009] Figure 2 It is a schematic diagram of the structure of a phase-locked loop based on PID control according to an embodiment of the present invention;

[0010] Figure 3 It is a structural schematic diagram of a phase-locked loop based on PID control according to another embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following describes a PID-controlled phase-locked loop according to an embodiment of the present invention with reference to the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described with reference to the accompanying drawings are exemplary and should not be construed as limiting the present invention.

[0012] Figure 2 It is a schematic diagram of the structure of a phase-locked loop based on PID control according to an embodiment of the present invention.

[0013] like Figure 2 As shown, the phase-locked loop 10 based on PID control includes: a digital phase detector 100 , a PID controller 200 , and a digitally controlled oscillator 300 .

[0014] Specifically, the digital phase detector 100 is used to obtain an input signal, obtain a feedback signal according to the output signal of the numerically controlled oscillator 300, and obtain the phase difference between the input signal and the feedback signal; the PID controller 200 is connected to the digital phase detector 100, and is used to calculate a first difference between the phase difference and a target value, and perform PID control on the first difference to obtain a frequency control word; the numerically controlled oscillator 300 is respectively connected to the digital phase detector 100 and the PID controller 200, and is used to obtain an output signal according to the frequency control word.

[0015] Assume that the above input signal is U i (nT) = Ui sin[ω0nT+θ1(nT)], the feedback signal obtained according to the output signal of the digital controlled oscillator 300 is U OI = sin(ω0nT+θ2) and U OQ =cos(ω0nT+θ2), then after obtaining the input signal and the feedback signal, the digital phase detector 100 mixes the input signal and the feedback signal, and performs low-pass filtering to obtain the low-pass filtering result shown below:

[0016] U dI (nT) = LPF[Ui(nT)*U OI (nT)]=AU i U O sin[θ1(nT)-θ2(nT)],

[0017] U dQ (nT) = LPF[Ui(nT)*U OQ (nT)]=AU i U O cos[θ1(nT)-θ2(nT)].

[0018] Wherein, LPF represents a low-pass operator, A=1 / 2, Ui is the amplitude of the input signal, and U0 is the amplitude of the output signal of the digital controlled oscillator 300 .

[0019] After obtaining the above low-pass filtering result U dI (nT), U dQ (nT), the low-pass filtering result is solved by the inverse tangent function to obtain the phase difference between the input signal and the feedback signal Q(nT) = arctan[U dI (nT) / U dQ (nT)] = θ1(nT) - θ2(nT).

[0020] Therefore, through this phase detection method, higher phase detection accuracy can be achieved, avoiding noise pollution caused by zero-crossing detection of traditional phase detectors.

[0021] After obtaining the phase difference, the digital phase detector 100 inputs the phase difference to the PID controller 200. The PID controller 200 first obtains the target value set by the user, and then obtains the first difference between the target value and the phase difference, and then obtains the frequency control word through the following formula:

[0022] U(k)=K p e(k)+K I ∑ i＝0 e(i)+K D [e(k)-e(k-1)],

[0023] Among them, U(k) is the frequency control word of the kth cycle, e(k) is the first difference of the kth cycle, e(k-1) is the first difference of the k-1th cycle, K p is the proportional control coefficient, K I is the integral control coefficient, K D is the differential control coefficient, i = 0, 1, 2, ..., k. The above target value is 0, that is, the expectation of the above phase difference is 0.

[0024] After acquiring the frequency control word, the PID controller 200 outputs the frequency control word, the numerically controlled oscillator 300 receives the frequency control word, and obtains an output signal according to the frequency control word.

[0025] In one embodiment of the present invention, see Figure 3 The digital phase detector 100 includes a phase shift module 101, a frequency mixing module 102, a low-pass filter module 103, and an inverse tangent module 104. The PID controller 200 includes an error calculation module 201 and a PID calculation module 202. Figure 3 The low-pass filter module 103 in is a digital low-pass filter BW order.

[0026] Specifically, the phase shift module 101 is connected to the digitally controlled oscillator 300, and is used to phase shift the output signal to obtain a feedback signal; the mixing module 102 is connected to the phase shift module 101, and is used to obtain an input signal, and mix the input signal and the feedback signal to obtain a mixed signal; the low-pass filtering module 103 is connected to the mixing module 102, and is used to filter the mixed signal to filter out the sum frequency component in the mixed signal; the inverse tangent module 104 is connected to the low-pass filtering module 103, and is used to use the inverse tangent function to operate the filtered mixed signal to obtain a phase difference.

[0027] The error calculation module 201 is connected to the digital phase detector 100 and is used to obtain the target value and calculate the first difference between the target value and the phase difference; the PID calculation module 202 is connected to the error calculation module 201 and is used to perform PID control on the first difference to obtain a frequency control word.

[0028] After receiving the output signal, the phase shift module 101 performs phase shift on the output signal to obtain a feedback signal, so that the feedback signal includes the output signal and the phase-shifted output signal.

[0029] The mixing module 102 mixes the feedback signal with the input signal to obtain a mixed signal including a sum frequency component and a difference frequency component. The mixing module 102 may use a DSP (Digital Signal Processing) multiplier, such as a DSP multiplier inside an FPGA (Field Programmable Gate Array).

[0030] After receiving the mixed signal, the low-pass filter module 103 filters the mixed signal to remove the sum frequency component in the mixed signal. The low-pass filter module 103 is implemented by digital RC filtering, thereby avoiding the problem that the traditional Fir filter cannot filter very low frequency signals, so that the PID control-based phase-locked loop 10 in the present application can lock a wide range of sinusoidal signals or square wave signals. Among them, the transfer function of the first-order RC filter is:

[0031] Uo1 / Ui1=1 / (2*pi*RC*f)^2+1)^0.5,

[0032] Among them, Uo1 is the output of the first-order RC filter, Ui1 is the input of the first-order RC filter, RC is the time constant of the RC filter, and f is the frequency of the signal to be filtered.

[0033] Then the transfer function of the m-order cascade RC filter is:

[0034] Uom / Ui1=1 / ((2*pi*RC*f)^2+1)^(0.5*m),

[0035] Wherein, Uom is the output of the cascaded RC filter with order m.

[0036] Thus, a low-pass filter can be constructed based on the above transfer function. In the embodiment of the present invention, the low-pass filter used is preferably a cascaded RC filter with an order of 8, that is, m in the transfer function of the low-pass filter is 8, and the low-pass filter is constructed based on the transfer function. In practical applications, two multipliers and one adder can be used to implement the low-pass filter, and the multiplier and the adder can both use the FPGA, and the constructed low-pass filter module 103 is filtered by the following formula:

[0037]

[0038] Among them, X out is the filtered signal, X in is the signal before filtering, Ts is the signal sampling rate, n is the nth sampling point, τ N is the time constant of the low-pass filter module 103 .

[0039] Specifically, this formula refers to the specific way of performing digital operations, and the above transfer function is to calculate the corresponding relationship between the time constant and the cutoff frequency of RC filters of different orders. For example, if the cutoff frequency of a fourth-order RC filter needs to be XHz, the corresponding time constant can be obtained according to the corresponding relationship between the time constant and the cutoff frequency, and then the time constant can be substituted into the current

[0040] After the low-pass filter module 103 performs filtering, the inverse tangent module 104 performs inverse tangent calculation on the filtering result. The inverse tangent module 104 is implemented by an inverse tangent IP core or a cordic inverse tangent iteration algorithm, for example, in an FPGA.

[0041] It should be noted that the above-mentioned PID control-based phase-locked loop 10 further includes a carrier frequency estimator, which is used to estimate the frequency of the input signal to obtain a frequency estimation value.

[0042] Specifically, before the input signal is input to the digital phase detector 100 , it also needs to be input to the carrier frequency estimator first to obtain a frequency estimation value of the input signal, thereby achieving the bandwidth of the low-pass filter module 103 being obtained according to the frequency estimation value.

[0043] Moreover, the control coefficient used in the PID controller 200 can also be obtained according to the frequency estimation value. Specifically, due to the existence of the carrier frequency estimator, the subsequent PID controller 200 can adopt a segmented loop filter bandwidth, that is, obtain the above-mentioned frequency estimation value and obtain the frequency band corresponding to the frequency estimation value, so as to obtain the frequency band and the proportional control coefficient K according to the pre-calibrated frequency band. P , integral control coefficient K I and differential control coefficient K D The required control coefficient is obtained by the corresponding relationship between . Thus, the locking speed can be greatly reduced and the locking accuracy can be improved.

[0044] Further, after the PID controller 200 calculates the above U(k), it adds the above frequency estimation value to the frequency control word as the final frequency control word, and then inputs the final frequency control word into the digital control oscillator 300. Moreover, when the PID controller 200 calculates the above U(k), it is necessary to limit U(k) according to the frequency estimation value, and the size of the limit is a reasonable value obtained by calibrating in advance and reserving a margin. The digital control oscillator 300 can be implemented, for example, using the DDS IP core in FPGA.

[0045] The upper and lower limits of U(k) are determined by the accuracy of the carrier frequency estimator. The higher the accuracy of the carrier frequency estimator, the narrower the upper and lower limits of U(k), and the easier it is for the PID controller 200 to lock.

[0046] It should be noted that the digital phase detector 100, PID controller 200, numerically controlled oscillator 300 and carrier frequency estimator in the above-mentioned PID-controlled phase-locked loop 10 can all be implemented using FPGA, and the characteristics of FPGA parallel pipeline calculation are used for data calculation, that is, a pipeline is opened in the FPGA for the above-mentioned digital phase detector 100, PID controller 200, numerically controlled oscillator 300 and carrier frequency estimator, so that the above-mentioned digital phase detector 100, PID controller 200, numerically controlled oscillator 300 and carrier frequency estimator can all perform pipeline calculations, thereby further improving the operating efficiency.

[0047] In summary, the PID-controlled phase-locked loop of the embodiment of the present invention, after the digital phase detector obtains the phase difference between the input signal and the feedback signal, uses a PID controller to calculate the first difference between the phase difference and the target value, and then performs PID control on the first difference to obtain a frequency control word, so that the digital control oscillator obtains an output signal according to the frequency control word, and the digital phase detector can obtain a feedback signal according to the output signal, thereby improving the locking speed and locking accuracy of the phase-locked loop. Moreover, by knowing the frequency band to which the input signal belongs in advance, selecting the corresponding PID coefficient according to different frequency bands, and combining the accurate digital phase detector in the present invention, the locking speed of the phase-locked loop can still be guaranteed within a large measured range, and at the same time, the locking accuracy of the phase-locked loop can still be guaranteed.

[0048] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0049] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0050] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0051] In the description of this specification, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as a limitation on the present invention.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0053] In the description of this specification, unless otherwise specified, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0054] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0055] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A phase-locked loop based on PID control, characterized in that: include: A digital phase detector, used to obtain an input signal, obtain a feedback signal according to an output signal of a digitally controlled oscillator, and obtain a phase difference between the input signal and the feedback signal; A PID controller, connected to the digital phase detector, for calculating a first difference between the phase difference and a target value, and performing PID control on the first difference to obtain a frequency control word; The digital controlled oscillator is connected to the digital phase detector and the PID controller respectively, and is used to obtain the output signal according to the frequency control word; The PID controller comprises: an error calculation module, connected to the digital phase detector, for obtaining the target value and calculating the first difference between the target value and the phase difference; A PID calculation module, connected to the error calculation module, and configured to perform PID control on the first difference to obtain the frequency control word; The PID calculation module obtains the frequency control word through the following formula: U(k)=K p e(k)+K I ∑ i＝0 e(i)+K D [e(k)-e(k-1)], Among them, U(k) is the frequency control word of the kth cycle, e(k) is the first difference of the kth cycle, e(k-1) is the first difference of the k-1th cycle, K p is the proportional control coefficient, K I is the integral control coefficient, K D is the differential control coefficient, i=0, 1, 2,…, k.

2. The PID-controlled phase-locked loop according to claim 1, characterized in that: The digital phase detector comprises: A phase shift module, connected to the digitally controlled oscillator, and configured to phase shift the output signal to obtain the feedback signal; A mixing module, connected to the phase shift module, for acquiring the input signal, and mixing the input signal and the feedback signal to obtain a mixed signal; A low-pass filtering module, connected to the mixing module, and configured to filter the mixing signal to remove the sum frequency component in the mixing signal; The inverse tangent module is connected to the low-pass filter module and is used to use the inverse tangent function to calculate the filtered mixed signal to obtain the phase difference.

3. The PID-controlled phase-locked loop according to claim 2, characterized in that: The low-pass filter module is implemented by two multipliers and one adder.

4. The PID-controlled phase-locked loop according to claim 3, characterized in that: The low-pass filter module performs filtering by the following formula: Among them, X out is the filtered signal, X in is the signal before filtering, Ts is the signal sampling rate, n is the nth sampling point, τ N is the time constant of the low-pass filtering module.

5. The PID-controlled phase-locked loop according to claim 2, characterized in that: The frequency mixing module is implemented by a DSP multiplier, and the inverse tangent module is implemented by an inverse tangent IP core or a cordic inverse tangent iteration algorithm.

6. The phase-locked loop based on PID control according to claim 1, characterized in that: The target value is 0.

7. The phase-locked loop based on PID control according to claim 2, characterized in that: Also includes: The carrier frequency estimator is used to estimate the frequency of the input signal to obtain a frequency estimation value, and the bandwidth of the low-pass filter module is obtained according to the frequency estimation value.

8. The phase-locked loop based on PID control according to claim 7, characterized in that: The control coefficient used in the PID controller is obtained based on the frequency estimate value.

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